1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
38 #include "dwarf2-frame.h"
40 #include "prologue-value.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
47 #include "common/selftest.h"
49 #include "aarch64-tdep.h"
50 #include "aarch64-ravenscar-thread.h"
53 #include "elf/aarch64.h"
55 #include "common/vec.h"
58 #include "record-full.h"
59 #include "arch/aarch64-insn.h"
61 #include "opcode/aarch64.h"
64 #define submask(x) ((1L << ((x) + 1)) - 1)
65 #define bit(obj,st) (((obj) >> (st)) & 1)
66 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
68 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
70 #define HA_MAX_NUM_FLDS 4
72 /* All possible aarch64 target descriptors. */
73 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/];
75 /* The standard register names, and all the valid aliases for them. */
78 const char *const name
;
80 } aarch64_register_aliases
[] =
82 /* 64-bit register names. */
83 {"fp", AARCH64_FP_REGNUM
},
84 {"lr", AARCH64_LR_REGNUM
},
85 {"sp", AARCH64_SP_REGNUM
},
87 /* 32-bit register names. */
88 {"w0", AARCH64_X0_REGNUM
+ 0},
89 {"w1", AARCH64_X0_REGNUM
+ 1},
90 {"w2", AARCH64_X0_REGNUM
+ 2},
91 {"w3", AARCH64_X0_REGNUM
+ 3},
92 {"w4", AARCH64_X0_REGNUM
+ 4},
93 {"w5", AARCH64_X0_REGNUM
+ 5},
94 {"w6", AARCH64_X0_REGNUM
+ 6},
95 {"w7", AARCH64_X0_REGNUM
+ 7},
96 {"w8", AARCH64_X0_REGNUM
+ 8},
97 {"w9", AARCH64_X0_REGNUM
+ 9},
98 {"w10", AARCH64_X0_REGNUM
+ 10},
99 {"w11", AARCH64_X0_REGNUM
+ 11},
100 {"w12", AARCH64_X0_REGNUM
+ 12},
101 {"w13", AARCH64_X0_REGNUM
+ 13},
102 {"w14", AARCH64_X0_REGNUM
+ 14},
103 {"w15", AARCH64_X0_REGNUM
+ 15},
104 {"w16", AARCH64_X0_REGNUM
+ 16},
105 {"w17", AARCH64_X0_REGNUM
+ 17},
106 {"w18", AARCH64_X0_REGNUM
+ 18},
107 {"w19", AARCH64_X0_REGNUM
+ 19},
108 {"w20", AARCH64_X0_REGNUM
+ 20},
109 {"w21", AARCH64_X0_REGNUM
+ 21},
110 {"w22", AARCH64_X0_REGNUM
+ 22},
111 {"w23", AARCH64_X0_REGNUM
+ 23},
112 {"w24", AARCH64_X0_REGNUM
+ 24},
113 {"w25", AARCH64_X0_REGNUM
+ 25},
114 {"w26", AARCH64_X0_REGNUM
+ 26},
115 {"w27", AARCH64_X0_REGNUM
+ 27},
116 {"w28", AARCH64_X0_REGNUM
+ 28},
117 {"w29", AARCH64_X0_REGNUM
+ 29},
118 {"w30", AARCH64_X0_REGNUM
+ 30},
121 {"ip0", AARCH64_X0_REGNUM
+ 16},
122 {"ip1", AARCH64_X0_REGNUM
+ 17}
125 /* The required core 'R' registers. */
126 static const char *const aarch64_r_register_names
[] =
128 /* These registers must appear in consecutive RAW register number
129 order and they must begin with AARCH64_X0_REGNUM! */
130 "x0", "x1", "x2", "x3",
131 "x4", "x5", "x6", "x7",
132 "x8", "x9", "x10", "x11",
133 "x12", "x13", "x14", "x15",
134 "x16", "x17", "x18", "x19",
135 "x20", "x21", "x22", "x23",
136 "x24", "x25", "x26", "x27",
137 "x28", "x29", "x30", "sp",
141 /* The FP/SIMD 'V' registers. */
142 static const char *const aarch64_v_register_names
[] =
144 /* These registers must appear in consecutive RAW register number
145 order and they must begin with AARCH64_V0_REGNUM! */
146 "v0", "v1", "v2", "v3",
147 "v4", "v5", "v6", "v7",
148 "v8", "v9", "v10", "v11",
149 "v12", "v13", "v14", "v15",
150 "v16", "v17", "v18", "v19",
151 "v20", "v21", "v22", "v23",
152 "v24", "v25", "v26", "v27",
153 "v28", "v29", "v30", "v31",
158 /* The SVE 'Z' and 'P' registers. */
159 static const char *const aarch64_sve_register_names
[] =
161 /* These registers must appear in consecutive RAW register number
162 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
163 "z0", "z1", "z2", "z3",
164 "z4", "z5", "z6", "z7",
165 "z8", "z9", "z10", "z11",
166 "z12", "z13", "z14", "z15",
167 "z16", "z17", "z18", "z19",
168 "z20", "z21", "z22", "z23",
169 "z24", "z25", "z26", "z27",
170 "z28", "z29", "z30", "z31",
172 "p0", "p1", "p2", "p3",
173 "p4", "p5", "p6", "p7",
174 "p8", "p9", "p10", "p11",
175 "p12", "p13", "p14", "p15",
179 static const char *const aarch64_pauth_register_names
[] =
181 /* Authentication mask for data pointer. */
183 /* Authentication mask for code pointer. */
187 /* AArch64 prologue cache structure. */
188 struct aarch64_prologue_cache
190 /* The program counter at the start of the function. It is used to
191 identify this frame as a prologue frame. */
194 /* The program counter at the time this frame was created; i.e. where
195 this function was called from. It is used to identify this frame as a
199 /* The stack pointer at the time this frame was created; i.e. the
200 caller's stack pointer when this function was called. It is used
201 to identify this frame. */
204 /* Is the target available to read from? */
207 /* The frame base for this frame is just prev_sp - frame size.
208 FRAMESIZE is the distance from the frame pointer to the
209 initial stack pointer. */
212 /* The register used to hold the frame pointer for this frame. */
215 /* Saved register offsets. */
216 struct trad_frame_saved_reg
*saved_regs
;
220 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
221 struct cmd_list_element
*c
, const char *value
)
223 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
228 /* Abstract instruction reader. */
230 class abstract_instruction_reader
233 /* Read in one instruction. */
234 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
235 enum bfd_endian byte_order
) = 0;
238 /* Instruction reader from real target. */
240 class instruction_reader
: public abstract_instruction_reader
243 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
246 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
252 /* If address signing is enabled, mask off the signature bits from ADDR, using
253 the register values in THIS_FRAME. */
256 aarch64_frame_unmask_address (struct gdbarch_tdep
*tdep
,
257 struct frame_info
*this_frame
,
260 if (tdep
->has_pauth ()
261 && frame_unwind_register_unsigned (this_frame
,
262 tdep
->pauth_ra_state_regnum
))
264 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
265 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
266 addr
= addr
& ~cmask
;
272 /* Analyze a prologue, looking for a recognizable stack frame
273 and frame pointer. Scan until we encounter a store that could
274 clobber the stack frame unexpectedly, or an unknown instruction. */
277 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
278 CORE_ADDR start
, CORE_ADDR limit
,
279 struct aarch64_prologue_cache
*cache
,
280 abstract_instruction_reader
& reader
)
282 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
284 /* Track X registers and D registers in prologue. */
285 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
287 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
288 regs
[i
] = pv_register (i
, 0);
289 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
291 for (; start
< limit
; start
+= 4)
296 insn
= reader
.read (start
, 4, byte_order_for_code
);
298 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
301 if (inst
.opcode
->iclass
== addsub_imm
302 && (inst
.opcode
->op
== OP_ADD
303 || strcmp ("sub", inst
.opcode
->name
) == 0))
305 unsigned rd
= inst
.operands
[0].reg
.regno
;
306 unsigned rn
= inst
.operands
[1].reg
.regno
;
308 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
309 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
310 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
311 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
313 if (inst
.opcode
->op
== OP_ADD
)
315 regs
[rd
] = pv_add_constant (regs
[rn
],
316 inst
.operands
[2].imm
.value
);
320 regs
[rd
] = pv_add_constant (regs
[rn
],
321 -inst
.operands
[2].imm
.value
);
324 else if (inst
.opcode
->iclass
== pcreladdr
325 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
327 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
328 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
330 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
332 else if (inst
.opcode
->iclass
== branch_imm
)
334 /* Stop analysis on branch. */
337 else if (inst
.opcode
->iclass
== condbranch
)
339 /* Stop analysis on branch. */
342 else if (inst
.opcode
->iclass
== branch_reg
)
344 /* Stop analysis on branch. */
347 else if (inst
.opcode
->iclass
== compbranch
)
349 /* Stop analysis on branch. */
352 else if (inst
.opcode
->op
== OP_MOVZ
)
354 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
355 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
357 else if (inst
.opcode
->iclass
== log_shift
358 && strcmp (inst
.opcode
->name
, "orr") == 0)
360 unsigned rd
= inst
.operands
[0].reg
.regno
;
361 unsigned rn
= inst
.operands
[1].reg
.regno
;
362 unsigned rm
= inst
.operands
[2].reg
.regno
;
364 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
365 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
366 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
368 if (inst
.operands
[2].shifter
.amount
== 0
369 && rn
== AARCH64_SP_REGNUM
)
375 debug_printf ("aarch64: prologue analysis gave up "
376 "addr=%s opcode=0x%x (orr x register)\n",
377 core_addr_to_string_nz (start
), insn
);
382 else if (inst
.opcode
->op
== OP_STUR
)
384 unsigned rt
= inst
.operands
[0].reg
.regno
;
385 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
387 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
389 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
390 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
391 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
392 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
394 stack
.store (pv_add_constant (regs
[rn
],
395 inst
.operands
[1].addr
.offset
.imm
),
396 is64
? 8 : 4, regs
[rt
]);
398 else if ((inst
.opcode
->iclass
== ldstpair_off
399 || (inst
.opcode
->iclass
== ldstpair_indexed
400 && inst
.operands
[2].addr
.preind
))
401 && strcmp ("stp", inst
.opcode
->name
) == 0)
403 /* STP with addressing mode Pre-indexed and Base register. */
406 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
407 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
409 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
410 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
411 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
412 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
413 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
414 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
416 /* If recording this store would invalidate the store area
417 (perhaps because rn is not known) then we should abandon
418 further prologue analysis. */
419 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
422 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
425 rt1
= inst
.operands
[0].reg
.regno
;
426 rt2
= inst
.operands
[1].reg
.regno
;
427 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
429 /* Only bottom 64-bit of each V register (D register) need
431 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
432 rt1
+= AARCH64_X_REGISTER_COUNT
;
433 rt2
+= AARCH64_X_REGISTER_COUNT
;
436 stack
.store (pv_add_constant (regs
[rn
], imm
), 8,
438 stack
.store (pv_add_constant (regs
[rn
], imm
+ 8), 8,
441 if (inst
.operands
[2].addr
.writeback
)
442 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
445 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
446 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
447 && (inst
.opcode
->op
== OP_STR_POS
448 || inst
.opcode
->op
== OP_STRF_POS
)))
449 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
450 && strcmp ("str", inst
.opcode
->name
) == 0)
452 /* STR (immediate) */
453 unsigned int rt
= inst
.operands
[0].reg
.regno
;
454 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
455 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
457 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
458 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
459 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
461 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
463 /* Only bottom 64-bit of each V register (D register) need
465 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
466 rt
+= AARCH64_X_REGISTER_COUNT
;
469 stack
.store (pv_add_constant (regs
[rn
], imm
),
470 is64
? 8 : 4, regs
[rt
]);
471 if (inst
.operands
[1].addr
.writeback
)
472 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
474 else if (inst
.opcode
->iclass
== testbranch
)
476 /* Stop analysis on branch. */
479 else if (inst
.opcode
->iclass
== ic_system
)
481 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
482 int ra_state_val
= 0;
484 if (insn
== 0xd503233f /* paciasp. */
485 || insn
== 0xd503237f /* pacibsp. */)
487 /* Return addresses are mangled. */
490 else if (insn
== 0xd50323bf /* autiasp. */
491 || insn
== 0xd50323ff /* autibsp. */)
493 /* Return addresses are not mangled. */
499 debug_printf ("aarch64: prologue analysis gave up addr=%s"
500 " opcode=0x%x (iclass)\n",
501 core_addr_to_string_nz (start
), insn
);
505 if (tdep
->has_pauth () && cache
!= nullptr)
506 trad_frame_set_value (cache
->saved_regs
,
507 tdep
->pauth_ra_state_regnum
,
514 debug_printf ("aarch64: prologue analysis gave up addr=%s"
516 core_addr_to_string_nz (start
), insn
);
525 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
527 /* Frame pointer is fp. Frame size is constant. */
528 cache
->framereg
= AARCH64_FP_REGNUM
;
529 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
531 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
533 /* Try the stack pointer. */
534 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
535 cache
->framereg
= AARCH64_SP_REGNUM
;
539 /* We're just out of luck. We don't know where the frame is. */
540 cache
->framereg
= -1;
541 cache
->framesize
= 0;
544 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
548 if (stack
.find_reg (gdbarch
, i
, &offset
))
549 cache
->saved_regs
[i
].addr
= offset
;
552 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
554 int regnum
= gdbarch_num_regs (gdbarch
);
557 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
559 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
566 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
567 CORE_ADDR start
, CORE_ADDR limit
,
568 struct aarch64_prologue_cache
*cache
)
570 instruction_reader reader
;
572 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
578 namespace selftests
{
580 /* Instruction reader from manually cooked instruction sequences. */
582 class instruction_reader_test
: public abstract_instruction_reader
585 template<size_t SIZE
>
586 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
587 : m_insns (insns
), m_insns_size (SIZE
)
590 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
593 SELF_CHECK (len
== 4);
594 SELF_CHECK (memaddr
% 4 == 0);
595 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
597 return m_insns
[memaddr
/ 4];
601 const uint32_t *m_insns
;
606 aarch64_analyze_prologue_test (void)
608 struct gdbarch_info info
;
610 gdbarch_info_init (&info
);
611 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
613 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
614 SELF_CHECK (gdbarch
!= NULL
);
616 struct aarch64_prologue_cache cache
;
617 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
621 /* Test the simple prologue in which frame pointer is used. */
623 static const uint32_t insns
[] = {
624 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
625 0x910003fd, /* mov x29, sp */
626 0x97ffffe6, /* bl 0x400580 */
628 instruction_reader_test
reader (insns
);
630 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
631 SELF_CHECK (end
== 4 * 2);
633 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
634 SELF_CHECK (cache
.framesize
== 272);
636 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
638 if (i
== AARCH64_FP_REGNUM
)
639 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
640 else if (i
== AARCH64_LR_REGNUM
)
641 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
643 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
646 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
648 int regnum
= gdbarch_num_regs (gdbarch
);
650 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
655 /* Test a prologue in which STR is used and frame pointer is not
658 static const uint32_t insns
[] = {
659 0xf81d0ff3, /* str x19, [sp, #-48]! */
660 0xb9002fe0, /* str w0, [sp, #44] */
661 0xf90013e1, /* str x1, [sp, #32]*/
662 0xfd000fe0, /* str d0, [sp, #24] */
663 0xaa0203f3, /* mov x19, x2 */
664 0xf94013e0, /* ldr x0, [sp, #32] */
666 instruction_reader_test
reader (insns
);
668 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
669 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
671 SELF_CHECK (end
== 4 * 5);
673 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
674 SELF_CHECK (cache
.framesize
== 48);
676 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
679 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
681 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
683 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
686 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
688 int regnum
= gdbarch_num_regs (gdbarch
);
691 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
694 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
699 /* Test a prologue in which there is a return address signing instruction. */
700 if (tdep
->has_pauth ())
702 static const uint32_t insns
[] = {
703 0xd503233f, /* paciasp */
704 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
705 0x910003fd, /* mov x29, sp */
706 0xf801c3f3, /* str x19, [sp, #28] */
707 0xb9401fa0, /* ldr x19, [x29, #28] */
709 instruction_reader_test
reader (insns
);
711 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
712 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
715 SELF_CHECK (end
== 4 * 4);
716 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
717 SELF_CHECK (cache
.framesize
== 48);
719 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
722 SELF_CHECK (cache
.saved_regs
[i
].addr
== -20);
723 else if (i
== AARCH64_FP_REGNUM
)
724 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
725 else if (i
== AARCH64_LR_REGNUM
)
726 SELF_CHECK (cache
.saved_regs
[i
].addr
== -40);
728 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
731 if (tdep
->has_pauth ())
733 SELF_CHECK (trad_frame_value_p (cache
.saved_regs
,
734 tdep
->pauth_ra_state_regnum
));
735 SELF_CHECK (cache
.saved_regs
[tdep
->pauth_ra_state_regnum
].addr
== 1);
739 } // namespace selftests
740 #endif /* GDB_SELF_TEST */
742 /* Implement the "skip_prologue" gdbarch method. */
745 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
747 CORE_ADDR func_addr
, limit_pc
;
749 /* See if we can determine the end of the prologue via the symbol
750 table. If so, then return either PC, or the PC after the
751 prologue, whichever is greater. */
752 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
754 CORE_ADDR post_prologue_pc
755 = skip_prologue_using_sal (gdbarch
, func_addr
);
757 if (post_prologue_pc
!= 0)
758 return std::max (pc
, post_prologue_pc
);
761 /* Can't determine prologue from the symbol table, need to examine
764 /* Find an upper limit on the function prologue using the debug
765 information. If the debug information could not be used to
766 provide that bound, then use an arbitrary large number as the
768 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
770 limit_pc
= pc
+ 128; /* Magic. */
772 /* Try disassembling prologue. */
773 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
776 /* Scan the function prologue for THIS_FRAME and populate the prologue
780 aarch64_scan_prologue (struct frame_info
*this_frame
,
781 struct aarch64_prologue_cache
*cache
)
783 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
784 CORE_ADDR prologue_start
;
785 CORE_ADDR prologue_end
;
786 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
787 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
789 cache
->prev_pc
= prev_pc
;
791 /* Assume we do not find a frame. */
792 cache
->framereg
= -1;
793 cache
->framesize
= 0;
795 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
798 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
802 /* No line info so use the current PC. */
803 prologue_end
= prev_pc
;
805 else if (sal
.end
< prologue_end
)
807 /* The next line begins after the function end. */
808 prologue_end
= sal
.end
;
811 prologue_end
= std::min (prologue_end
, prev_pc
);
812 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
818 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
822 cache
->framereg
= AARCH64_FP_REGNUM
;
823 cache
->framesize
= 16;
824 cache
->saved_regs
[29].addr
= 0;
825 cache
->saved_regs
[30].addr
= 8;
829 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
830 function may throw an exception if the inferior's registers or memory is
834 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
835 struct aarch64_prologue_cache
*cache
)
837 CORE_ADDR unwound_fp
;
840 aarch64_scan_prologue (this_frame
, cache
);
842 if (cache
->framereg
== -1)
845 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
849 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
851 /* Calculate actual addresses of saved registers using offsets
852 determined by aarch64_analyze_prologue. */
853 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
854 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
855 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
857 cache
->func
= get_frame_func (this_frame
);
859 cache
->available_p
= 1;
862 /* Allocate and fill in *THIS_CACHE with information about the prologue of
863 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
864 Return a pointer to the current aarch64_prologue_cache in
867 static struct aarch64_prologue_cache
*
868 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
870 struct aarch64_prologue_cache
*cache
;
872 if (*this_cache
!= NULL
)
873 return (struct aarch64_prologue_cache
*) *this_cache
;
875 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
876 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
881 aarch64_make_prologue_cache_1 (this_frame
, cache
);
883 catch (const gdb_exception_error
&ex
)
885 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
892 /* Implement the "stop_reason" frame_unwind method. */
894 static enum unwind_stop_reason
895 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
898 struct aarch64_prologue_cache
*cache
899 = aarch64_make_prologue_cache (this_frame
, this_cache
);
901 if (!cache
->available_p
)
902 return UNWIND_UNAVAILABLE
;
904 /* Halt the backtrace at "_start". */
905 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
906 return UNWIND_OUTERMOST
;
908 /* We've hit a wall, stop. */
909 if (cache
->prev_sp
== 0)
910 return UNWIND_OUTERMOST
;
912 return UNWIND_NO_REASON
;
915 /* Our frame ID for a normal frame is the current function's starting
916 PC and the caller's SP when we were called. */
919 aarch64_prologue_this_id (struct frame_info
*this_frame
,
920 void **this_cache
, struct frame_id
*this_id
)
922 struct aarch64_prologue_cache
*cache
923 = aarch64_make_prologue_cache (this_frame
, this_cache
);
925 if (!cache
->available_p
)
926 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
928 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
931 /* Implement the "prev_register" frame_unwind method. */
933 static struct value
*
934 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
935 void **this_cache
, int prev_regnum
)
937 struct aarch64_prologue_cache
*cache
938 = aarch64_make_prologue_cache (this_frame
, this_cache
);
940 /* If we are asked to unwind the PC, then we need to return the LR
941 instead. The prologue may save PC, but it will point into this
942 frame's prologue, not the next frame's resume location. */
943 if (prev_regnum
== AARCH64_PC_REGNUM
)
946 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
947 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
949 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
951 if (tdep
->has_pauth ()
952 && trad_frame_value_p (cache
->saved_regs
,
953 tdep
->pauth_ra_state_regnum
))
954 lr
= aarch64_frame_unmask_address (tdep
, this_frame
, lr
);
956 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
959 /* SP is generally not saved to the stack, but this frame is
960 identified by the next frame's stack pointer at the time of the
961 call. The value was already reconstructed into PREV_SP. */
974 if (prev_regnum
== AARCH64_SP_REGNUM
)
975 return frame_unwind_got_constant (this_frame
, prev_regnum
,
978 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
982 /* AArch64 prologue unwinder. */
983 struct frame_unwind aarch64_prologue_unwind
=
986 aarch64_prologue_frame_unwind_stop_reason
,
987 aarch64_prologue_this_id
,
988 aarch64_prologue_prev_register
,
990 default_frame_sniffer
993 /* Allocate and fill in *THIS_CACHE with information about the prologue of
994 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
995 Return a pointer to the current aarch64_prologue_cache in
998 static struct aarch64_prologue_cache
*
999 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
1001 struct aarch64_prologue_cache
*cache
;
1003 if (*this_cache
!= NULL
)
1004 return (struct aarch64_prologue_cache
*) *this_cache
;
1006 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1007 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1008 *this_cache
= cache
;
1012 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1014 cache
->prev_pc
= get_frame_pc (this_frame
);
1015 cache
->available_p
= 1;
1017 catch (const gdb_exception_error
&ex
)
1019 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1026 /* Implement the "stop_reason" frame_unwind method. */
1028 static enum unwind_stop_reason
1029 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1032 struct aarch64_prologue_cache
*cache
1033 = aarch64_make_stub_cache (this_frame
, this_cache
);
1035 if (!cache
->available_p
)
1036 return UNWIND_UNAVAILABLE
;
1038 return UNWIND_NO_REASON
;
1041 /* Our frame ID for a stub frame is the current SP and LR. */
1044 aarch64_stub_this_id (struct frame_info
*this_frame
,
1045 void **this_cache
, struct frame_id
*this_id
)
1047 struct aarch64_prologue_cache
*cache
1048 = aarch64_make_stub_cache (this_frame
, this_cache
);
1050 if (cache
->available_p
)
1051 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1053 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1056 /* Implement the "sniffer" frame_unwind method. */
1059 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1060 struct frame_info
*this_frame
,
1061 void **this_prologue_cache
)
1063 CORE_ADDR addr_in_block
;
1066 addr_in_block
= get_frame_address_in_block (this_frame
);
1067 if (in_plt_section (addr_in_block
)
1068 /* We also use the stub winder if the target memory is unreadable
1069 to avoid having the prologue unwinder trying to read it. */
1070 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1076 /* AArch64 stub unwinder. */
1077 struct frame_unwind aarch64_stub_unwind
=
1080 aarch64_stub_frame_unwind_stop_reason
,
1081 aarch64_stub_this_id
,
1082 aarch64_prologue_prev_register
,
1084 aarch64_stub_unwind_sniffer
1087 /* Return the frame base address of *THIS_FRAME. */
1090 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1092 struct aarch64_prologue_cache
*cache
1093 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1095 return cache
->prev_sp
- cache
->framesize
;
1098 /* AArch64 default frame base information. */
1099 struct frame_base aarch64_normal_base
=
1101 &aarch64_prologue_unwind
,
1102 aarch64_normal_frame_base
,
1103 aarch64_normal_frame_base
,
1104 aarch64_normal_frame_base
1107 /* Return the value of the REGNUM register in the previous frame of
1110 static struct value
*
1111 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1112 void **this_cache
, int regnum
)
1114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1119 case AARCH64_PC_REGNUM
:
1120 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1121 lr
= aarch64_frame_unmask_address (tdep
, this_frame
, lr
);
1122 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1125 internal_error (__FILE__
, __LINE__
,
1126 _("Unexpected register %d"), regnum
);
1130 static const unsigned char op_lit0
= DW_OP_lit0
;
1131 static const unsigned char op_lit1
= DW_OP_lit1
;
1133 /* Implement the "init_reg" dwarf2_frame_ops method. */
1136 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1137 struct dwarf2_frame_state_reg
*reg
,
1138 struct frame_info
*this_frame
)
1140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1144 case AARCH64_PC_REGNUM
:
1145 reg
->how
= DWARF2_FRAME_REG_FN
;
1146 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1149 case AARCH64_SP_REGNUM
:
1150 reg
->how
= DWARF2_FRAME_REG_CFA
;
1154 /* Init pauth registers. */
1155 if (tdep
->has_pauth ())
1157 if (regnum
== tdep
->pauth_ra_state_regnum
)
1159 /* Initialize RA_STATE to zero. */
1160 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1161 reg
->loc
.exp
.start
= &op_lit0
;
1162 reg
->loc
.exp
.len
= 1;
1165 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1166 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1168 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1174 /* Implement the execute_dwarf_cfa_vendor_op method. */
1177 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1178 struct dwarf2_frame_state
*fs
)
1180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1181 struct dwarf2_frame_state_reg
*ra_state
;
1183 if (tdep
->has_pauth () && op
== DW_CFA_AARCH64_negate_ra_state
)
1185 /* Allocate RA_STATE column if it's not allocated yet. */
1186 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1188 /* Toggle the status of RA_STATE between 0 and 1. */
1189 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1190 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1192 if (ra_state
->loc
.exp
.start
== nullptr
1193 || ra_state
->loc
.exp
.start
== &op_lit0
)
1194 ra_state
->loc
.exp
.start
= &op_lit1
;
1196 ra_state
->loc
.exp
.start
= &op_lit0
;
1198 ra_state
->loc
.exp
.len
= 1;
1206 /* When arguments must be pushed onto the stack, they go on in reverse
1207 order. The code below implements a FILO (stack) to do this. */
1211 /* Value to pass on stack. It can be NULL if this item is for stack
1213 const gdb_byte
*data
;
1215 /* Size in bytes of value to pass on stack. */
1219 DEF_VEC_O (stack_item_t
);
1221 /* Implement the gdbarch type alignment method, overrides the generic
1222 alignment algorithm for anything that is aarch64 specific. */
1225 aarch64_type_align (gdbarch
*gdbarch
, struct type
*t
)
1227 t
= check_typedef (t
);
1228 if (TYPE_CODE (t
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (t
))
1230 /* Use the natural alignment for vector types (the same for
1231 scalar type), but the maximum alignment is 128-bit. */
1232 if (TYPE_LENGTH (t
) > 16)
1235 return TYPE_LENGTH (t
);
1238 /* Allow the common code to calculate the alignment. */
1242 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1244 Return the number of register required, or -1 on failure.
1246 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1247 to the element, else fail if the type of this element does not match the
1251 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1252 struct type
**fundamental_type
)
1254 if (type
== nullptr)
1257 switch (TYPE_CODE (type
))
1260 if (TYPE_LENGTH (type
) > 16)
1263 if (*fundamental_type
== nullptr)
1264 *fundamental_type
= type
;
1265 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1266 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1271 case TYPE_CODE_COMPLEX
:
1273 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1274 if (TYPE_LENGTH (target_type
) > 16)
1277 if (*fundamental_type
== nullptr)
1278 *fundamental_type
= target_type
;
1279 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1280 || TYPE_CODE (target_type
) != TYPE_CODE (*fundamental_type
))
1286 case TYPE_CODE_ARRAY
:
1288 if (TYPE_VECTOR (type
))
1290 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1293 if (*fundamental_type
== nullptr)
1294 *fundamental_type
= type
;
1295 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1296 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1303 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1304 int count
= aapcs_is_vfp_call_or_return_candidate_1
1305 (target_type
, fundamental_type
);
1310 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1315 case TYPE_CODE_STRUCT
:
1316 case TYPE_CODE_UNION
:
1320 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1322 /* Ignore any static fields. */
1323 if (field_is_static (&TYPE_FIELD (type
, i
)))
1326 struct type
*member
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
1328 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1329 (member
, fundamental_type
);
1330 if (sub_count
== -1)
1335 /* Ensure there is no padding between the fields (allowing for empty
1336 zero length structs) */
1337 int ftype_length
= (*fundamental_type
== nullptr)
1338 ? 0 : TYPE_LENGTH (*fundamental_type
);
1339 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1352 /* Return true if an argument, whose type is described by TYPE, can be passed or
1353 returned in simd/fp registers, providing enough parameter passing registers
1354 are available. This is as described in the AAPCS64.
1356 Upon successful return, *COUNT returns the number of needed registers,
1357 *FUNDAMENTAL_TYPE contains the type of those registers.
1359 Candidate as per the AAPCS64 5.4.2.C is either a:
1362 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1363 all the members are floats and has at most 4 members.
1364 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1365 all the members are short vectors and has at most 4 members.
1368 Note that HFAs and HVAs can include nested structures and arrays. */
1371 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1372 struct type
**fundamental_type
)
1374 if (type
== nullptr)
1377 *fundamental_type
= nullptr;
1379 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1382 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1391 /* AArch64 function call information structure. */
1392 struct aarch64_call_info
1394 /* the current argument number. */
1397 /* The next general purpose register number, equivalent to NGRN as
1398 described in the AArch64 Procedure Call Standard. */
1401 /* The next SIMD and floating point register number, equivalent to
1402 NSRN as described in the AArch64 Procedure Call Standard. */
1405 /* The next stacked argument address, equivalent to NSAA as
1406 described in the AArch64 Procedure Call Standard. */
1409 /* Stack item vector. */
1410 VEC(stack_item_t
) *si
;
1413 /* Pass a value in a sequence of consecutive X registers. The caller
1414 is responsbile for ensuring sufficient registers are available. */
1417 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1418 struct aarch64_call_info
*info
, struct type
*type
,
1421 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1422 int len
= TYPE_LENGTH (type
);
1423 enum type_code typecode
= TYPE_CODE (type
);
1424 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1425 const bfd_byte
*buf
= value_contents (arg
);
1431 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1432 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1436 /* Adjust sub-word struct/union args when big-endian. */
1437 if (byte_order
== BFD_ENDIAN_BIG
1438 && partial_len
< X_REGISTER_SIZE
1439 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1440 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1444 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1445 gdbarch_register_name (gdbarch
, regnum
),
1446 phex (regval
, X_REGISTER_SIZE
));
1448 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1455 /* Attempt to marshall a value in a V register. Return 1 if
1456 successful, or 0 if insufficient registers are available. This
1457 function, unlike the equivalent pass_in_x() function does not
1458 handle arguments spread across multiple registers. */
1461 pass_in_v (struct gdbarch
*gdbarch
,
1462 struct regcache
*regcache
,
1463 struct aarch64_call_info
*info
,
1464 int len
, const bfd_byte
*buf
)
1468 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1469 /* Enough space for a full vector register. */
1470 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1471 gdb_assert (len
<= sizeof (reg
));
1476 memset (reg
, 0, sizeof (reg
));
1477 /* PCS C.1, the argument is allocated to the least significant
1478 bits of V register. */
1479 memcpy (reg
, buf
, len
);
1480 regcache
->cooked_write (regnum
, reg
);
1484 debug_printf ("arg %d in %s\n", info
->argnum
,
1485 gdbarch_register_name (gdbarch
, regnum
));
1493 /* Marshall an argument onto the stack. */
1496 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1499 const bfd_byte
*buf
= value_contents (arg
);
1500 int len
= TYPE_LENGTH (type
);
1506 align
= type_align (type
);
1508 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1509 Natural alignment of the argument's type. */
1510 align
= align_up (align
, 8);
1512 /* The AArch64 PCS requires at most doubleword alignment. */
1518 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1524 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1527 if (info
->nsaa
& (align
- 1))
1529 /* Push stack alignment padding. */
1530 int pad
= align
- (info
->nsaa
& (align
- 1));
1535 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1540 /* Marshall an argument into a sequence of one or more consecutive X
1541 registers or, if insufficient X registers are available then onto
1545 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1546 struct aarch64_call_info
*info
, struct type
*type
,
1549 int len
= TYPE_LENGTH (type
);
1550 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1552 /* PCS C.13 - Pass in registers if we have enough spare */
1553 if (info
->ngrn
+ nregs
<= 8)
1555 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1556 info
->ngrn
+= nregs
;
1561 pass_on_stack (info
, type
, arg
);
1565 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1566 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1567 registers. A return value of false is an error state as the value will have
1568 been partially passed to the stack. */
1570 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1571 struct aarch64_call_info
*info
, struct type
*arg_type
,
1574 switch (TYPE_CODE (arg_type
))
1577 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1578 value_contents (arg
));
1581 case TYPE_CODE_COMPLEX
:
1583 const bfd_byte
*buf
= value_contents (arg
);
1584 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1586 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1590 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1591 buf
+ TYPE_LENGTH (target_type
));
1594 case TYPE_CODE_ARRAY
:
1595 if (TYPE_VECTOR (arg_type
))
1596 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1597 value_contents (arg
));
1600 case TYPE_CODE_STRUCT
:
1601 case TYPE_CODE_UNION
:
1602 for (int i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
1604 /* Don't include static fields. */
1605 if (field_is_static (&TYPE_FIELD (arg_type
, i
)))
1608 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1609 struct type
*field_type
= check_typedef (value_type (field
));
1611 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1622 /* Implement the "push_dummy_call" gdbarch method. */
1625 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1626 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1628 struct value
**args
, CORE_ADDR sp
,
1629 function_call_return_method return_method
,
1630 CORE_ADDR struct_addr
)
1633 struct aarch64_call_info info
;
1635 memset (&info
, 0, sizeof (info
));
1637 /* We need to know what the type of the called function is in order
1638 to determine the number of named/anonymous arguments for the
1639 actual argument placement, and the return type in order to handle
1640 return value correctly.
1642 The generic code above us views the decision of return in memory
1643 or return in registers as a two stage processes. The language
1644 handler is consulted first and may decide to return in memory (eg
1645 class with copy constructor returned by value), this will cause
1646 the generic code to allocate space AND insert an initial leading
1649 If the language code does not decide to pass in memory then the
1650 target code is consulted.
1652 If the language code decides to pass in memory we want to move
1653 the pointer inserted as the initial argument from the argument
1654 list and into X8, the conventional AArch64 struct return pointer
1657 /* Set the return address. For the AArch64, the return breakpoint
1658 is always at BP_ADDR. */
1659 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1661 /* If we were given an initial argument for the return slot, lose it. */
1662 if (return_method
== return_method_hidden_param
)
1668 /* The struct_return pointer occupies X8. */
1669 if (return_method
!= return_method_normal
)
1673 debug_printf ("struct return in %s = 0x%s\n",
1674 gdbarch_register_name (gdbarch
,
1675 AARCH64_STRUCT_RETURN_REGNUM
),
1676 paddress (gdbarch
, struct_addr
));
1678 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1682 for (argnum
= 0; argnum
< nargs
; argnum
++)
1684 struct value
*arg
= args
[argnum
];
1685 struct type
*arg_type
, *fundamental_type
;
1688 arg_type
= check_typedef (value_type (arg
));
1689 len
= TYPE_LENGTH (arg_type
);
1691 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1692 if there are enough spare registers. */
1693 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1696 if (info
.nsrn
+ elements
<= 8)
1698 /* We know that we have sufficient registers available therefore
1699 this will never need to fallback to the stack. */
1700 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1702 gdb_assert_not_reached ("Failed to push args");
1707 pass_on_stack (&info
, arg_type
, arg
);
1712 switch (TYPE_CODE (arg_type
))
1715 case TYPE_CODE_BOOL
:
1716 case TYPE_CODE_CHAR
:
1717 case TYPE_CODE_RANGE
:
1718 case TYPE_CODE_ENUM
:
1721 /* Promote to 32 bit integer. */
1722 if (TYPE_UNSIGNED (arg_type
))
1723 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1725 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1726 arg
= value_cast (arg_type
, arg
);
1728 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1731 case TYPE_CODE_STRUCT
:
1732 case TYPE_CODE_ARRAY
:
1733 case TYPE_CODE_UNION
:
1736 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1737 invisible reference. */
1739 /* Allocate aligned storage. */
1740 sp
= align_down (sp
- len
, 16);
1742 /* Write the real data into the stack. */
1743 write_memory (sp
, value_contents (arg
), len
);
1745 /* Construct the indirection. */
1746 arg_type
= lookup_pointer_type (arg_type
);
1747 arg
= value_from_pointer (arg_type
, sp
);
1748 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1751 /* PCS C.15 / C.18 multiple values pass. */
1752 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1756 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1761 /* Make sure stack retains 16 byte alignment. */
1763 sp
-= 16 - (info
.nsaa
& 15);
1765 while (!VEC_empty (stack_item_t
, info
.si
))
1767 stack_item_t
*si
= VEC_last (stack_item_t
, info
.si
);
1770 if (si
->data
!= NULL
)
1771 write_memory (sp
, si
->data
, si
->len
);
1772 VEC_pop (stack_item_t
, info
.si
);
1775 VEC_free (stack_item_t
, info
.si
);
1777 /* Finally, update the SP register. */
1778 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1783 /* Implement the "frame_align" gdbarch method. */
1786 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1788 /* Align the stack to sixteen bytes. */
1789 return sp
& ~(CORE_ADDR
) 15;
1792 /* Return the type for an AdvSISD Q register. */
1794 static struct type
*
1795 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1799 if (tdep
->vnq_type
== NULL
)
1804 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1807 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1808 append_composite_type_field (t
, "u", elem
);
1810 elem
= builtin_type (gdbarch
)->builtin_int128
;
1811 append_composite_type_field (t
, "s", elem
);
1816 return tdep
->vnq_type
;
1819 /* Return the type for an AdvSISD D register. */
1821 static struct type
*
1822 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1824 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1826 if (tdep
->vnd_type
== NULL
)
1831 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1834 elem
= builtin_type (gdbarch
)->builtin_double
;
1835 append_composite_type_field (t
, "f", elem
);
1837 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1838 append_composite_type_field (t
, "u", elem
);
1840 elem
= builtin_type (gdbarch
)->builtin_int64
;
1841 append_composite_type_field (t
, "s", elem
);
1846 return tdep
->vnd_type
;
1849 /* Return the type for an AdvSISD S register. */
1851 static struct type
*
1852 aarch64_vns_type (struct gdbarch
*gdbarch
)
1854 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1856 if (tdep
->vns_type
== NULL
)
1861 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1864 elem
= builtin_type (gdbarch
)->builtin_float
;
1865 append_composite_type_field (t
, "f", elem
);
1867 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1868 append_composite_type_field (t
, "u", elem
);
1870 elem
= builtin_type (gdbarch
)->builtin_int32
;
1871 append_composite_type_field (t
, "s", elem
);
1876 return tdep
->vns_type
;
1879 /* Return the type for an AdvSISD H register. */
1881 static struct type
*
1882 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1884 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1886 if (tdep
->vnh_type
== NULL
)
1891 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1894 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1895 append_composite_type_field (t
, "u", elem
);
1897 elem
= builtin_type (gdbarch
)->builtin_int16
;
1898 append_composite_type_field (t
, "s", elem
);
1903 return tdep
->vnh_type
;
1906 /* Return the type for an AdvSISD B register. */
1908 static struct type
*
1909 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1911 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1913 if (tdep
->vnb_type
== NULL
)
1918 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1921 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1922 append_composite_type_field (t
, "u", elem
);
1924 elem
= builtin_type (gdbarch
)->builtin_int8
;
1925 append_composite_type_field (t
, "s", elem
);
1930 return tdep
->vnb_type
;
1933 /* Return the type for an AdvSISD V register. */
1935 static struct type
*
1936 aarch64_vnv_type (struct gdbarch
*gdbarch
)
1938 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1940 if (tdep
->vnv_type
== NULL
)
1942 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1943 slice from the non-pseudo vector registers. However NEON V registers
1944 are always vector registers, and need constructing as such. */
1945 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1947 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
1950 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1952 append_composite_type_field (sub
, "f",
1953 init_vector_type (bt
->builtin_double
, 2));
1954 append_composite_type_field (sub
, "u",
1955 init_vector_type (bt
->builtin_uint64
, 2));
1956 append_composite_type_field (sub
, "s",
1957 init_vector_type (bt
->builtin_int64
, 2));
1958 append_composite_type_field (t
, "d", sub
);
1960 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1962 append_composite_type_field (sub
, "f",
1963 init_vector_type (bt
->builtin_float
, 4));
1964 append_composite_type_field (sub
, "u",
1965 init_vector_type (bt
->builtin_uint32
, 4));
1966 append_composite_type_field (sub
, "s",
1967 init_vector_type (bt
->builtin_int32
, 4));
1968 append_composite_type_field (t
, "s", sub
);
1970 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1972 append_composite_type_field (sub
, "u",
1973 init_vector_type (bt
->builtin_uint16
, 8));
1974 append_composite_type_field (sub
, "s",
1975 init_vector_type (bt
->builtin_int16
, 8));
1976 append_composite_type_field (t
, "h", sub
);
1978 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1980 append_composite_type_field (sub
, "u",
1981 init_vector_type (bt
->builtin_uint8
, 16));
1982 append_composite_type_field (sub
, "s",
1983 init_vector_type (bt
->builtin_int8
, 16));
1984 append_composite_type_field (t
, "b", sub
);
1986 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1988 append_composite_type_field (sub
, "u",
1989 init_vector_type (bt
->builtin_uint128
, 1));
1990 append_composite_type_field (sub
, "s",
1991 init_vector_type (bt
->builtin_int128
, 1));
1992 append_composite_type_field (t
, "q", sub
);
1997 return tdep
->vnv_type
;
2000 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2003 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2005 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2007 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2008 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2010 if (reg
== AARCH64_DWARF_SP
)
2011 return AARCH64_SP_REGNUM
;
2013 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2014 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2016 if (reg
== AARCH64_DWARF_SVE_VG
)
2017 return AARCH64_SVE_VG_REGNUM
;
2019 if (reg
== AARCH64_DWARF_SVE_FFR
)
2020 return AARCH64_SVE_FFR_REGNUM
;
2022 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2023 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2025 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2026 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2028 if (tdep
->has_pauth ())
2030 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2031 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2033 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2034 return tdep
->pauth_ra_state_regnum
;
2040 /* Implement the "print_insn" gdbarch method. */
2043 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2045 info
->symbols
= NULL
;
2046 return default_print_insn (memaddr
, info
);
2049 /* AArch64 BRK software debug mode instruction.
2050 Note that AArch64 code is always little-endian.
2051 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2052 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2054 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2056 /* Extract from an array REGS containing the (raw) register state a
2057 function return value of type TYPE, and copy that, in virtual
2058 format, into VALBUF. */
2061 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2064 struct gdbarch
*gdbarch
= regs
->arch ();
2065 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2067 struct type
*fundamental_type
;
2069 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2072 int len
= TYPE_LENGTH (fundamental_type
);
2074 for (int i
= 0; i
< elements
; i
++)
2076 int regno
= AARCH64_V0_REGNUM
+ i
;
2077 /* Enough space for a full vector register. */
2078 gdb_byte buf
[register_size (gdbarch
, regno
)];
2079 gdb_assert (len
<= sizeof (buf
));
2083 debug_printf ("read HFA or HVA return value element %d from %s\n",
2085 gdbarch_register_name (gdbarch
, regno
));
2087 regs
->cooked_read (regno
, buf
);
2089 memcpy (valbuf
, buf
, len
);
2093 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2094 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2095 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2096 || TYPE_CODE (type
) == TYPE_CODE_PTR
2097 || TYPE_IS_REFERENCE (type
)
2098 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2100 /* If the type is a plain integer, then the access is
2101 straight-forward. Otherwise we have to play around a bit
2103 int len
= TYPE_LENGTH (type
);
2104 int regno
= AARCH64_X0_REGNUM
;
2109 /* By using store_unsigned_integer we avoid having to do
2110 anything special for small big-endian values. */
2111 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2112 store_unsigned_integer (valbuf
,
2113 (len
> X_REGISTER_SIZE
2114 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2115 len
-= X_REGISTER_SIZE
;
2116 valbuf
+= X_REGISTER_SIZE
;
2121 /* For a structure or union the behaviour is as if the value had
2122 been stored to word-aligned memory and then loaded into
2123 registers with 64-bit load instruction(s). */
2124 int len
= TYPE_LENGTH (type
);
2125 int regno
= AARCH64_X0_REGNUM
;
2126 bfd_byte buf
[X_REGISTER_SIZE
];
2130 regs
->cooked_read (regno
++, buf
);
2131 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2132 len
-= X_REGISTER_SIZE
;
2133 valbuf
+= X_REGISTER_SIZE
;
2139 /* Will a function return an aggregate type in memory or in a
2140 register? Return 0 if an aggregate type can be returned in a
2141 register, 1 if it must be returned in memory. */
2144 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2146 type
= check_typedef (type
);
2148 struct type
*fundamental_type
;
2150 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2153 /* v0-v7 are used to return values and one register is allocated
2154 for one member. However, HFA or HVA has at most four members. */
2158 if (TYPE_LENGTH (type
) > 16)
2160 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2161 invisible reference. */
2169 /* Write into appropriate registers a function return value of type
2170 TYPE, given in virtual format. */
2173 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2174 const gdb_byte
*valbuf
)
2176 struct gdbarch
*gdbarch
= regs
->arch ();
2177 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2179 struct type
*fundamental_type
;
2181 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2184 int len
= TYPE_LENGTH (fundamental_type
);
2186 for (int i
= 0; i
< elements
; i
++)
2188 int regno
= AARCH64_V0_REGNUM
+ i
;
2189 /* Enough space for a full vector register. */
2190 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2191 gdb_assert (len
<= sizeof (tmpbuf
));
2195 debug_printf ("write HFA or HVA return value element %d to %s\n",
2197 gdbarch_register_name (gdbarch
, regno
));
2200 memcpy (tmpbuf
, valbuf
,
2201 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2202 regs
->cooked_write (regno
, tmpbuf
);
2206 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2207 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2208 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2209 || TYPE_CODE (type
) == TYPE_CODE_PTR
2210 || TYPE_IS_REFERENCE (type
)
2211 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2213 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2215 /* Values of one word or less are zero/sign-extended and
2217 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2218 LONGEST val
= unpack_long (type
, valbuf
);
2220 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2221 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2225 /* Integral values greater than one word are stored in
2226 consecutive registers starting with r0. This will always
2227 be a multiple of the regiser size. */
2228 int len
= TYPE_LENGTH (type
);
2229 int regno
= AARCH64_X0_REGNUM
;
2233 regs
->cooked_write (regno
++, valbuf
);
2234 len
-= X_REGISTER_SIZE
;
2235 valbuf
+= X_REGISTER_SIZE
;
2241 /* For a structure or union the behaviour is as if the value had
2242 been stored to word-aligned memory and then loaded into
2243 registers with 64-bit load instruction(s). */
2244 int len
= TYPE_LENGTH (type
);
2245 int regno
= AARCH64_X0_REGNUM
;
2246 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2250 memcpy (tmpbuf
, valbuf
,
2251 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2252 regs
->cooked_write (regno
++, tmpbuf
);
2253 len
-= X_REGISTER_SIZE
;
2254 valbuf
+= X_REGISTER_SIZE
;
2259 /* Implement the "return_value" gdbarch method. */
2261 static enum return_value_convention
2262 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2263 struct type
*valtype
, struct regcache
*regcache
,
2264 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2267 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2268 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2269 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2271 if (aarch64_return_in_memory (gdbarch
, valtype
))
2274 debug_printf ("return value in memory\n");
2275 return RETURN_VALUE_STRUCT_CONVENTION
;
2280 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2283 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2286 debug_printf ("return value in registers\n");
2288 return RETURN_VALUE_REGISTER_CONVENTION
;
2291 /* Implement the "get_longjmp_target" gdbarch method. */
2294 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2297 gdb_byte buf
[X_REGISTER_SIZE
];
2298 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2300 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2302 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2304 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2308 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2312 /* Implement the "gen_return_address" gdbarch method. */
2315 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2316 struct agent_expr
*ax
, struct axs_value
*value
,
2319 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2320 value
->kind
= axs_lvalue_register
;
2321 value
->u
.reg
= AARCH64_LR_REGNUM
;
2325 /* Return the pseudo register name corresponding to register regnum. */
2328 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2330 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2332 static const char *const q_name
[] =
2334 "q0", "q1", "q2", "q3",
2335 "q4", "q5", "q6", "q7",
2336 "q8", "q9", "q10", "q11",
2337 "q12", "q13", "q14", "q15",
2338 "q16", "q17", "q18", "q19",
2339 "q20", "q21", "q22", "q23",
2340 "q24", "q25", "q26", "q27",
2341 "q28", "q29", "q30", "q31",
2344 static const char *const d_name
[] =
2346 "d0", "d1", "d2", "d3",
2347 "d4", "d5", "d6", "d7",
2348 "d8", "d9", "d10", "d11",
2349 "d12", "d13", "d14", "d15",
2350 "d16", "d17", "d18", "d19",
2351 "d20", "d21", "d22", "d23",
2352 "d24", "d25", "d26", "d27",
2353 "d28", "d29", "d30", "d31",
2356 static const char *const s_name
[] =
2358 "s0", "s1", "s2", "s3",
2359 "s4", "s5", "s6", "s7",
2360 "s8", "s9", "s10", "s11",
2361 "s12", "s13", "s14", "s15",
2362 "s16", "s17", "s18", "s19",
2363 "s20", "s21", "s22", "s23",
2364 "s24", "s25", "s26", "s27",
2365 "s28", "s29", "s30", "s31",
2368 static const char *const h_name
[] =
2370 "h0", "h1", "h2", "h3",
2371 "h4", "h5", "h6", "h7",
2372 "h8", "h9", "h10", "h11",
2373 "h12", "h13", "h14", "h15",
2374 "h16", "h17", "h18", "h19",
2375 "h20", "h21", "h22", "h23",
2376 "h24", "h25", "h26", "h27",
2377 "h28", "h29", "h30", "h31",
2380 static const char *const b_name
[] =
2382 "b0", "b1", "b2", "b3",
2383 "b4", "b5", "b6", "b7",
2384 "b8", "b9", "b10", "b11",
2385 "b12", "b13", "b14", "b15",
2386 "b16", "b17", "b18", "b19",
2387 "b20", "b21", "b22", "b23",
2388 "b24", "b25", "b26", "b27",
2389 "b28", "b29", "b30", "b31",
2392 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2394 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2395 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2397 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2398 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2400 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2401 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2403 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2404 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2406 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2407 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2409 if (tdep
->has_sve ())
2411 static const char *const sve_v_name
[] =
2413 "v0", "v1", "v2", "v3",
2414 "v4", "v5", "v6", "v7",
2415 "v8", "v9", "v10", "v11",
2416 "v12", "v13", "v14", "v15",
2417 "v16", "v17", "v18", "v19",
2418 "v20", "v21", "v22", "v23",
2419 "v24", "v25", "v26", "v27",
2420 "v28", "v29", "v30", "v31",
2423 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2424 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2425 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2428 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2429 prevents it from being read by methods such as
2430 mi_cmd_trace_frame_collected. */
2431 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2434 internal_error (__FILE__
, __LINE__
,
2435 _("aarch64_pseudo_register_name: bad register number %d"),
2439 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2441 static struct type
*
2442 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2444 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2446 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2448 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2449 return aarch64_vnq_type (gdbarch
);
2451 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2452 return aarch64_vnd_type (gdbarch
);
2454 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2455 return aarch64_vns_type (gdbarch
);
2457 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2458 return aarch64_vnh_type (gdbarch
);
2460 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2461 return aarch64_vnb_type (gdbarch
);
2463 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2464 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2465 return aarch64_vnv_type (gdbarch
);
2467 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2468 return builtin_type (gdbarch
)->builtin_uint64
;
2470 internal_error (__FILE__
, __LINE__
,
2471 _("aarch64_pseudo_register_type: bad register number %d"),
2475 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2478 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2479 struct reggroup
*group
)
2481 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2483 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2485 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2486 return group
== all_reggroup
|| group
== vector_reggroup
;
2487 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2488 return (group
== all_reggroup
|| group
== vector_reggroup
2489 || group
== float_reggroup
);
2490 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2491 return (group
== all_reggroup
|| group
== vector_reggroup
2492 || group
== float_reggroup
);
2493 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2494 return group
== all_reggroup
|| group
== vector_reggroup
;
2495 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2496 return group
== all_reggroup
|| group
== vector_reggroup
;
2497 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2498 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2499 return group
== all_reggroup
|| group
== vector_reggroup
;
2500 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2501 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2504 return group
== all_reggroup
;
2507 /* Helper for aarch64_pseudo_read_value. */
2509 static struct value
*
2510 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2511 readable_regcache
*regcache
, int regnum_offset
,
2512 int regsize
, struct value
*result_value
)
2514 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2516 /* Enough space for a full vector register. */
2517 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2518 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2520 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2521 mark_value_bytes_unavailable (result_value
, 0,
2522 TYPE_LENGTH (value_type (result_value
)));
2524 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2526 return result_value
;
2529 /* Implement the "pseudo_register_read_value" gdbarch method. */
2531 static struct value
*
2532 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2535 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2536 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2538 VALUE_LVAL (result_value
) = lval_register
;
2539 VALUE_REGNUM (result_value
) = regnum
;
2541 regnum
-= gdbarch_num_regs (gdbarch
);
2543 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2544 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2545 regnum
- AARCH64_Q0_REGNUM
,
2546 Q_REGISTER_SIZE
, result_value
);
2548 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2549 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2550 regnum
- AARCH64_D0_REGNUM
,
2551 D_REGISTER_SIZE
, result_value
);
2553 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2554 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2555 regnum
- AARCH64_S0_REGNUM
,
2556 S_REGISTER_SIZE
, result_value
);
2558 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2559 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2560 regnum
- AARCH64_H0_REGNUM
,
2561 H_REGISTER_SIZE
, result_value
);
2563 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2564 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2565 regnum
- AARCH64_B0_REGNUM
,
2566 B_REGISTER_SIZE
, result_value
);
2568 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2569 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2570 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2571 regnum
- AARCH64_SVE_V0_REGNUM
,
2572 V_REGISTER_SIZE
, result_value
);
2574 gdb_assert_not_reached ("regnum out of bound");
2577 /* Helper for aarch64_pseudo_write. */
2580 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2581 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2583 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2585 /* Enough space for a full vector register. */
2586 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2587 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2589 /* Ensure the register buffer is zero, we want gdb writes of the
2590 various 'scalar' pseudo registers to behavior like architectural
2591 writes, register width bytes are written the remainder are set to
2593 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2595 memcpy (reg_buf
, buf
, regsize
);
2596 regcache
->raw_write (v_regnum
, reg_buf
);
2599 /* Implement the "pseudo_register_write" gdbarch method. */
2602 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2603 int regnum
, const gdb_byte
*buf
)
2605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2606 regnum
-= gdbarch_num_regs (gdbarch
);
2608 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2609 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2610 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2613 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2614 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2615 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2618 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2619 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2620 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2623 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2624 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2625 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2628 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2629 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2630 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2633 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2634 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2635 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2636 regnum
- AARCH64_SVE_V0_REGNUM
,
2637 V_REGISTER_SIZE
, buf
);
2639 gdb_assert_not_reached ("regnum out of bound");
2642 /* Callback function for user_reg_add. */
2644 static struct value
*
2645 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2647 const int *reg_p
= (const int *) baton
;
2649 return value_of_register (*reg_p
, frame
);
2653 /* Implement the "software_single_step" gdbarch method, needed to
2654 single step through atomic sequences on AArch64. */
2656 static std::vector
<CORE_ADDR
>
2657 aarch64_software_single_step (struct regcache
*regcache
)
2659 struct gdbarch
*gdbarch
= regcache
->arch ();
2660 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2661 const int insn_size
= 4;
2662 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2663 CORE_ADDR pc
= regcache_read_pc (regcache
);
2664 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2666 CORE_ADDR closing_insn
= 0;
2667 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2668 byte_order_for_code
);
2671 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2672 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2675 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2678 /* Look for a Load Exclusive instruction which begins the sequence. */
2679 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2682 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2685 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2686 byte_order_for_code
);
2688 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2690 /* Check if the instruction is a conditional branch. */
2691 if (inst
.opcode
->iclass
== condbranch
)
2693 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2695 if (bc_insn_count
>= 1)
2698 /* It is, so we'll try to set a breakpoint at the destination. */
2699 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2705 /* Look for the Store Exclusive which closes the atomic sequence. */
2706 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2713 /* We didn't find a closing Store Exclusive instruction, fall back. */
2717 /* Insert breakpoint after the end of the atomic sequence. */
2718 breaks
[0] = loc
+ insn_size
;
2720 /* Check for duplicated breakpoints, and also check that the second
2721 breakpoint is not within the atomic sequence. */
2723 && (breaks
[1] == breaks
[0]
2724 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2725 last_breakpoint
= 0;
2727 std::vector
<CORE_ADDR
> next_pcs
;
2729 /* Insert the breakpoint at the end of the sequence, and one at the
2730 destination of the conditional branch, if it exists. */
2731 for (index
= 0; index
<= last_breakpoint
; index
++)
2732 next_pcs
.push_back (breaks
[index
]);
2737 struct aarch64_displaced_step_closure
: public displaced_step_closure
2739 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2740 is being displaced stepping. */
2743 /* PC adjustment offset after displaced stepping. */
2744 int32_t pc_adjust
= 0;
2747 /* Data when visiting instructions for displaced stepping. */
2749 struct aarch64_displaced_step_data
2751 struct aarch64_insn_data base
;
2753 /* The address where the instruction will be executed at. */
2755 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2756 uint32_t insn_buf
[DISPLACED_MODIFIED_INSNS
];
2757 /* Number of instructions in INSN_BUF. */
2758 unsigned insn_count
;
2759 /* Registers when doing displaced stepping. */
2760 struct regcache
*regs
;
2762 aarch64_displaced_step_closure
*dsc
;
2765 /* Implementation of aarch64_insn_visitor method "b". */
2768 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2769 struct aarch64_insn_data
*data
)
2771 struct aarch64_displaced_step_data
*dsd
2772 = (struct aarch64_displaced_step_data
*) data
;
2773 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2775 if (can_encode_int32 (new_offset
, 28))
2777 /* Emit B rather than BL, because executing BL on a new address
2778 will get the wrong address into LR. In order to avoid this,
2779 we emit B, and update LR if the instruction is BL. */
2780 emit_b (dsd
->insn_buf
, 0, new_offset
);
2786 emit_nop (dsd
->insn_buf
);
2788 dsd
->dsc
->pc_adjust
= offset
;
2794 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2795 data
->insn_addr
+ 4);
2799 /* Implementation of aarch64_insn_visitor method "b_cond". */
2802 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2803 struct aarch64_insn_data
*data
)
2805 struct aarch64_displaced_step_data
*dsd
2806 = (struct aarch64_displaced_step_data
*) data
;
2808 /* GDB has to fix up PC after displaced step this instruction
2809 differently according to the condition is true or false. Instead
2810 of checking COND against conditional flags, we can use
2811 the following instructions, and GDB can tell how to fix up PC
2812 according to the PC value.
2814 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2820 emit_bcond (dsd
->insn_buf
, cond
, 8);
2822 dsd
->dsc
->pc_adjust
= offset
;
2823 dsd
->insn_count
= 1;
2826 /* Dynamically allocate a new register. If we know the register
2827 statically, we should make it a global as above instead of using this
2830 static struct aarch64_register
2831 aarch64_register (unsigned num
, int is64
)
2833 return (struct aarch64_register
) { num
, is64
};
2836 /* Implementation of aarch64_insn_visitor method "cb". */
2839 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2840 const unsigned rn
, int is64
,
2841 struct aarch64_insn_data
*data
)
2843 struct aarch64_displaced_step_data
*dsd
2844 = (struct aarch64_displaced_step_data
*) data
;
2846 /* The offset is out of range for a compare and branch
2847 instruction. We can use the following instructions instead:
2849 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2854 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2855 dsd
->insn_count
= 1;
2857 dsd
->dsc
->pc_adjust
= offset
;
2860 /* Implementation of aarch64_insn_visitor method "tb". */
2863 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2864 const unsigned rt
, unsigned bit
,
2865 struct aarch64_insn_data
*data
)
2867 struct aarch64_displaced_step_data
*dsd
2868 = (struct aarch64_displaced_step_data
*) data
;
2870 /* The offset is out of range for a test bit and branch
2871 instruction We can use the following instructions instead:
2873 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2879 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2880 dsd
->insn_count
= 1;
2882 dsd
->dsc
->pc_adjust
= offset
;
2885 /* Implementation of aarch64_insn_visitor method "adr". */
2888 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2889 const int is_adrp
, struct aarch64_insn_data
*data
)
2891 struct aarch64_displaced_step_data
*dsd
2892 = (struct aarch64_displaced_step_data
*) data
;
2893 /* We know exactly the address the ADR{P,} instruction will compute.
2894 We can just write it to the destination register. */
2895 CORE_ADDR address
= data
->insn_addr
+ offset
;
2899 /* Clear the lower 12 bits of the offset to get the 4K page. */
2900 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2904 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2907 dsd
->dsc
->pc_adjust
= 4;
2908 emit_nop (dsd
->insn_buf
);
2909 dsd
->insn_count
= 1;
2912 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2915 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2916 const unsigned rt
, const int is64
,
2917 struct aarch64_insn_data
*data
)
2919 struct aarch64_displaced_step_data
*dsd
2920 = (struct aarch64_displaced_step_data
*) data
;
2921 CORE_ADDR address
= data
->insn_addr
+ offset
;
2922 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2924 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2928 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2929 aarch64_register (rt
, 1), zero
);
2931 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2932 aarch64_register (rt
, 1), zero
);
2934 dsd
->dsc
->pc_adjust
= 4;
2937 /* Implementation of aarch64_insn_visitor method "others". */
2940 aarch64_displaced_step_others (const uint32_t insn
,
2941 struct aarch64_insn_data
*data
)
2943 struct aarch64_displaced_step_data
*dsd
2944 = (struct aarch64_displaced_step_data
*) data
;
2946 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2947 dsd
->insn_count
= 1;
2949 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2952 dsd
->dsc
->pc_adjust
= 0;
2955 dsd
->dsc
->pc_adjust
= 4;
2958 static const struct aarch64_insn_visitor visitor
=
2960 aarch64_displaced_step_b
,
2961 aarch64_displaced_step_b_cond
,
2962 aarch64_displaced_step_cb
,
2963 aarch64_displaced_step_tb
,
2964 aarch64_displaced_step_adr
,
2965 aarch64_displaced_step_ldr_literal
,
2966 aarch64_displaced_step_others
,
2969 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2971 struct displaced_step_closure
*
2972 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
2973 CORE_ADDR from
, CORE_ADDR to
,
2974 struct regcache
*regs
)
2976 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2977 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
2978 struct aarch64_displaced_step_data dsd
;
2981 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2984 /* Look for a Load Exclusive instruction which begins the sequence. */
2985 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
2987 /* We can't displaced step atomic sequences. */
2991 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
2992 (new aarch64_displaced_step_closure
);
2993 dsd
.base
.insn_addr
= from
;
2996 dsd
.dsc
= dsc
.get ();
2998 aarch64_relocate_instruction (insn
, &visitor
,
2999 (struct aarch64_insn_data
*) &dsd
);
3000 gdb_assert (dsd
.insn_count
<= DISPLACED_MODIFIED_INSNS
);
3002 if (dsd
.insn_count
!= 0)
3006 /* Instruction can be relocated to scratch pad. Copy
3007 relocated instruction(s) there. */
3008 for (i
= 0; i
< dsd
.insn_count
; i
++)
3010 if (debug_displaced
)
3012 debug_printf ("displaced: writing insn ");
3013 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
3014 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
3016 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3017 (ULONGEST
) dsd
.insn_buf
[i
]);
3025 return dsc
.release ();
3028 /* Implement the "displaced_step_fixup" gdbarch method. */
3031 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3032 struct displaced_step_closure
*dsc_
,
3033 CORE_ADDR from
, CORE_ADDR to
,
3034 struct regcache
*regs
)
3036 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
3042 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3045 /* Condition is true. */
3047 else if (pc
- to
== 4)
3049 /* Condition is false. */
3053 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3056 if (dsc
->pc_adjust
!= 0)
3058 if (debug_displaced
)
3060 debug_printf ("displaced: fixup: set PC to %s:%d\n",
3061 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3063 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3064 from
+ dsc
->pc_adjust
);
3068 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3071 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
3072 struct displaced_step_closure
*closure
)
3077 /* Get the correct target description for the given VQ value.
3078 If VQ is zero then it is assumed SVE is not supported.
3079 (It is not possible to set VQ to zero on an SVE system). */
3082 aarch64_read_description (uint64_t vq
, bool pauth_p
)
3084 if (vq
> AARCH64_MAX_SVE_VQ
)
3085 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3086 AARCH64_MAX_SVE_VQ
);
3088 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
];
3092 tdesc
= aarch64_create_target_description (vq
, pauth_p
);
3093 tdesc_aarch64_list
[vq
][pauth_p
] = tdesc
;
3099 /* Return the VQ used when creating the target description TDESC. */
3102 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3104 const struct tdesc_feature
*feature_sve
;
3106 if (!tdesc_has_registers (tdesc
))
3109 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3111 if (feature_sve
== nullptr)
3114 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3115 aarch64_sve_register_names
[0]) / 8;
3116 return sve_vq_from_vl (vl
);
3119 /* Add all the expected register sets into GDBARCH. */
3122 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3124 reggroup_add (gdbarch
, general_reggroup
);
3125 reggroup_add (gdbarch
, float_reggroup
);
3126 reggroup_add (gdbarch
, system_reggroup
);
3127 reggroup_add (gdbarch
, vector_reggroup
);
3128 reggroup_add (gdbarch
, all_reggroup
);
3129 reggroup_add (gdbarch
, save_reggroup
);
3130 reggroup_add (gdbarch
, restore_reggroup
);
3133 /* Implement the "cannot_store_register" gdbarch method. */
3136 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3140 if (!tdep
->has_pauth ())
3143 /* Pointer authentication registers are read-only. */
3144 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3145 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3148 /* Initialize the current architecture based on INFO. If possible,
3149 re-use an architecture from ARCHES, which is a list of
3150 architectures already created during this debugging session.
3152 Called e.g. at program startup, when reading a core file, and when
3153 reading a binary file. */
3155 static struct gdbarch
*
3156 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3158 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3159 const struct tdesc_feature
*feature_pauth
;
3160 bool valid_p
= true;
3161 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3162 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3164 /* Use the vector length passed via the target info. Here -1 is used for no
3165 SVE, and 0 is unset. If unset then use the vector length from the existing
3168 if (info
.id
== (int *) -1)
3170 else if (info
.id
!= 0)
3171 vq
= (uint64_t) info
.id
;
3173 vq
= aarch64_get_tdesc_vq (info
.target_desc
);
3175 if (vq
> AARCH64_MAX_SVE_VQ
)
3176 internal_error (__FILE__
, __LINE__
, _("VQ out of bounds: %ld (max %d)"),
3177 vq
, AARCH64_MAX_SVE_VQ
);
3179 /* If there is already a candidate, use it. */
3180 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3181 best_arch
!= nullptr;
3182 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (best_arch
->gdbarch
);
3185 if (tdep
&& tdep
->vq
== vq
)
3186 return best_arch
->gdbarch
;
3189 /* Ensure we always have a target descriptor, and that it is for the given VQ
3191 const struct target_desc
*tdesc
= info
.target_desc
;
3192 if (!tdesc_has_registers (tdesc
) || vq
!= aarch64_get_tdesc_vq (tdesc
))
3193 tdesc
= aarch64_read_description (vq
, false);
3196 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3197 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3198 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3199 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3201 if (feature_core
== nullptr)
3204 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3206 /* Validate the description provides the mandatory core R registers
3207 and allocate their numbers. */
3208 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3209 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
3210 AARCH64_X0_REGNUM
+ i
,
3211 aarch64_r_register_names
[i
]);
3213 num_regs
= AARCH64_X0_REGNUM
+ i
;
3215 /* Add the V registers. */
3216 if (feature_fpu
!= nullptr)
3218 if (feature_sve
!= nullptr)
3219 error (_("Program contains both fpu and SVE features."));
3221 /* Validate the description provides the mandatory V registers
3222 and allocate their numbers. */
3223 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3224 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
3225 AARCH64_V0_REGNUM
+ i
,
3226 aarch64_v_register_names
[i
]);
3228 num_regs
= AARCH64_V0_REGNUM
+ i
;
3231 /* Add the SVE registers. */
3232 if (feature_sve
!= nullptr)
3234 /* Validate the description provides the mandatory SVE registers
3235 and allocate their numbers. */
3236 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3237 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
3238 AARCH64_SVE_Z0_REGNUM
+ i
,
3239 aarch64_sve_register_names
[i
]);
3241 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3242 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3245 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3247 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3248 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3249 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3250 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3251 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3254 /* Add the pauth registers. */
3255 if (feature_pauth
!= NULL
)
3257 first_pauth_regnum
= num_regs
;
3258 pauth_ra_state_offset
= num_pseudo_regs
;
3259 /* Validate the descriptor provides the mandatory PAUTH registers and
3260 allocate their numbers. */
3261 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3262 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
,
3263 first_pauth_regnum
+ i
,
3264 aarch64_pauth_register_names
[i
]);
3267 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3272 tdesc_data_cleanup (tdesc_data
);
3276 /* AArch64 code is always little-endian. */
3277 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3279 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
3280 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3282 /* This should be low enough for everything. */
3283 tdep
->lowest_pc
= 0x20;
3284 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3285 tdep
->jb_elt_size
= 8;
3287 tdep
->pauth_reg_base
= first_pauth_regnum
;
3288 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3289 : pauth_ra_state_offset
+ num_regs
;
3291 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3292 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3294 /* Advance PC across function entry code. */
3295 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3297 /* The stack grows downward. */
3298 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3300 /* Breakpoint manipulation. */
3301 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3302 aarch64_breakpoint::kind_from_pc
);
3303 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3304 aarch64_breakpoint::bp_from_kind
);
3305 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3306 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3308 /* Information about registers, etc. */
3309 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3310 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3311 set_gdbarch_num_regs (gdbarch
, num_regs
);
3313 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3314 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3315 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3316 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3317 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3318 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3319 aarch64_pseudo_register_reggroup_p
);
3320 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3323 set_gdbarch_short_bit (gdbarch
, 16);
3324 set_gdbarch_int_bit (gdbarch
, 32);
3325 set_gdbarch_float_bit (gdbarch
, 32);
3326 set_gdbarch_double_bit (gdbarch
, 64);
3327 set_gdbarch_long_double_bit (gdbarch
, 128);
3328 set_gdbarch_long_bit (gdbarch
, 64);
3329 set_gdbarch_long_long_bit (gdbarch
, 64);
3330 set_gdbarch_ptr_bit (gdbarch
, 64);
3331 set_gdbarch_char_signed (gdbarch
, 0);
3332 set_gdbarch_wchar_signed (gdbarch
, 0);
3333 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3334 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3335 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3336 set_gdbarch_type_align (gdbarch
, aarch64_type_align
);
3338 /* Internal <-> external register number maps. */
3339 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3341 /* Returning results. */
3342 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3345 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3347 /* Virtual tables. */
3348 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3350 /* Register architecture. */
3351 aarch64_add_reggroups (gdbarch
);
3353 /* Hook in the ABI-specific overrides, if they have been registered. */
3354 info
.target_desc
= tdesc
;
3355 info
.tdesc_data
= tdesc_data
;
3356 gdbarch_init_osabi (info
, gdbarch
);
3358 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3359 /* Register DWARF CFA vendor handler. */
3360 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3361 aarch64_execute_dwarf_cfa_vendor_op
);
3363 /* Add some default predicates. */
3364 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3365 dwarf2_append_unwinders (gdbarch
);
3366 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3368 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3370 /* Now we have tuned the configuration, set a few final things,
3371 based on what the OS ABI has told us. */
3373 if (tdep
->jb_pc
>= 0)
3374 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3376 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3378 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3380 /* Add standard register aliases. */
3381 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3382 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3383 value_of_aarch64_user_reg
,
3384 &aarch64_register_aliases
[i
].regnum
);
3386 register_aarch64_ravenscar_ops (gdbarch
);
3392 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3394 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3399 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3400 paddress (gdbarch
, tdep
->lowest_pc
));
3406 static void aarch64_process_record_test (void);
3411 _initialize_aarch64_tdep (void)
3413 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3416 /* Debug this file's internals. */
3417 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3418 Set AArch64 debugging."), _("\
3419 Show AArch64 debugging."), _("\
3420 When on, AArch64 specific debugging is enabled."),
3423 &setdebuglist
, &showdebuglist
);
3426 selftests::register_test ("aarch64-analyze-prologue",
3427 selftests::aarch64_analyze_prologue_test
);
3428 selftests::register_test ("aarch64-process-record",
3429 selftests::aarch64_process_record_test
);
3430 selftests::record_xml_tdesc ("aarch64.xml",
3431 aarch64_create_target_description (0, false));
3435 /* AArch64 process record-replay related structures, defines etc. */
3437 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3440 unsigned int reg_len = LENGTH; \
3443 REGS = XNEWVEC (uint32_t, reg_len); \
3444 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3449 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3452 unsigned int mem_len = LENGTH; \
3455 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3456 memcpy(&MEMS->len, &RECORD_BUF[0], \
3457 sizeof(struct aarch64_mem_r) * LENGTH); \
3462 /* AArch64 record/replay structures and enumerations. */
3464 struct aarch64_mem_r
3466 uint64_t len
; /* Record length. */
3467 uint64_t addr
; /* Memory address. */
3470 enum aarch64_record_result
3472 AARCH64_RECORD_SUCCESS
,
3473 AARCH64_RECORD_UNSUPPORTED
,
3474 AARCH64_RECORD_UNKNOWN
3477 typedef struct insn_decode_record_t
3479 struct gdbarch
*gdbarch
;
3480 struct regcache
*regcache
;
3481 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3482 uint32_t aarch64_insn
; /* Insn to be recorded. */
3483 uint32_t mem_rec_count
; /* Count of memory records. */
3484 uint32_t reg_rec_count
; /* Count of register records. */
3485 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3486 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3487 } insn_decode_record
;
3489 /* Record handler for data processing - register instructions. */
3492 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3494 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3495 uint32_t record_buf
[4];
3497 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3498 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3499 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3501 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3505 /* Logical (shifted register). */
3506 if (insn_bits24_27
== 0x0a)
3507 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3509 else if (insn_bits24_27
== 0x0b)
3510 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3512 return AARCH64_RECORD_UNKNOWN
;
3514 record_buf
[0] = reg_rd
;
3515 aarch64_insn_r
->reg_rec_count
= 1;
3517 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3521 if (insn_bits24_27
== 0x0b)
3523 /* Data-processing (3 source). */
3524 record_buf
[0] = reg_rd
;
3525 aarch64_insn_r
->reg_rec_count
= 1;
3527 else if (insn_bits24_27
== 0x0a)
3529 if (insn_bits21_23
== 0x00)
3531 /* Add/subtract (with carry). */
3532 record_buf
[0] = reg_rd
;
3533 aarch64_insn_r
->reg_rec_count
= 1;
3534 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3536 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3537 aarch64_insn_r
->reg_rec_count
= 2;
3540 else if (insn_bits21_23
== 0x02)
3542 /* Conditional compare (register) and conditional compare
3543 (immediate) instructions. */
3544 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3545 aarch64_insn_r
->reg_rec_count
= 1;
3547 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3549 /* CConditional select. */
3550 /* Data-processing (2 source). */
3551 /* Data-processing (1 source). */
3552 record_buf
[0] = reg_rd
;
3553 aarch64_insn_r
->reg_rec_count
= 1;
3556 return AARCH64_RECORD_UNKNOWN
;
3560 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3562 return AARCH64_RECORD_SUCCESS
;
3565 /* Record handler for data processing - immediate instructions. */
3568 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3570 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3571 uint32_t record_buf
[4];
3573 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3574 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3575 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3577 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3578 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3579 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3581 record_buf
[0] = reg_rd
;
3582 aarch64_insn_r
->reg_rec_count
= 1;
3584 else if (insn_bits24_27
== 0x01)
3586 /* Add/Subtract (immediate). */
3587 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3588 record_buf
[0] = reg_rd
;
3589 aarch64_insn_r
->reg_rec_count
= 1;
3591 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3593 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3595 /* Logical (immediate). */
3596 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3597 record_buf
[0] = reg_rd
;
3598 aarch64_insn_r
->reg_rec_count
= 1;
3600 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3603 return AARCH64_RECORD_UNKNOWN
;
3605 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3607 return AARCH64_RECORD_SUCCESS
;
3610 /* Record handler for branch, exception generation and system instructions. */
3613 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3615 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3616 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3617 uint32_t record_buf
[4];
3619 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3620 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3621 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3623 if (insn_bits28_31
== 0x0d)
3625 /* Exception generation instructions. */
3626 if (insn_bits24_27
== 0x04)
3628 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3629 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3630 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3632 ULONGEST svc_number
;
3634 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3636 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3640 return AARCH64_RECORD_UNSUPPORTED
;
3642 /* System instructions. */
3643 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3645 uint32_t reg_rt
, reg_crn
;
3647 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3648 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3650 /* Record rt in case of sysl and mrs instructions. */
3651 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3653 record_buf
[0] = reg_rt
;
3654 aarch64_insn_r
->reg_rec_count
= 1;
3656 /* Record cpsr for hint and msr(immediate) instructions. */
3657 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3659 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3660 aarch64_insn_r
->reg_rec_count
= 1;
3663 /* Unconditional branch (register). */
3664 else if((insn_bits24_27
& 0x0e) == 0x06)
3666 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3667 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3668 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3671 return AARCH64_RECORD_UNKNOWN
;
3673 /* Unconditional branch (immediate). */
3674 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3676 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3677 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3678 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3681 /* Compare & branch (immediate), Test & branch (immediate) and
3682 Conditional branch (immediate). */
3683 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3685 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3687 return AARCH64_RECORD_SUCCESS
;
3690 /* Record handler for advanced SIMD load and store instructions. */
3693 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3696 uint64_t addr_offset
= 0;
3697 uint32_t record_buf
[24];
3698 uint64_t record_buf_mem
[24];
3699 uint32_t reg_rn
, reg_rt
;
3700 uint32_t reg_index
= 0, mem_index
= 0;
3701 uint8_t opcode_bits
, size_bits
;
3703 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3704 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3705 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3706 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3707 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3710 debug_printf ("Process record: Advanced SIMD load/store\n");
3712 /* Load/store single structure. */
3713 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3715 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3716 scale
= opcode_bits
>> 2;
3717 selem
= ((opcode_bits
& 0x02) |
3718 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3722 if (size_bits
& 0x01)
3723 return AARCH64_RECORD_UNKNOWN
;
3726 if ((size_bits
>> 1) & 0x01)
3727 return AARCH64_RECORD_UNKNOWN
;
3728 if (size_bits
& 0x01)
3730 if (!((opcode_bits
>> 1) & 0x01))
3733 return AARCH64_RECORD_UNKNOWN
;
3737 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3744 return AARCH64_RECORD_UNKNOWN
;
3750 for (sindex
= 0; sindex
< selem
; sindex
++)
3752 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3753 reg_rt
= (reg_rt
+ 1) % 32;
3757 for (sindex
= 0; sindex
< selem
; sindex
++)
3759 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3760 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3763 record_buf_mem
[mem_index
++] = esize
/ 8;
3764 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3766 addr_offset
= addr_offset
+ (esize
/ 8);
3767 reg_rt
= (reg_rt
+ 1) % 32;
3771 /* Load/store multiple structure. */
3774 uint8_t selem
, esize
, rpt
, elements
;
3775 uint8_t eindex
, rindex
;
3777 esize
= 8 << size_bits
;
3778 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3779 elements
= 128 / esize
;
3781 elements
= 64 / esize
;
3783 switch (opcode_bits
)
3785 /*LD/ST4 (4 Registers). */
3790 /*LD/ST1 (4 Registers). */
3795 /*LD/ST3 (3 Registers). */
3800 /*LD/ST1 (3 Registers). */
3805 /*LD/ST1 (1 Register). */
3810 /*LD/ST2 (2 Registers). */
3815 /*LD/ST1 (2 Registers). */
3821 return AARCH64_RECORD_UNSUPPORTED
;
3824 for (rindex
= 0; rindex
< rpt
; rindex
++)
3825 for (eindex
= 0; eindex
< elements
; eindex
++)
3827 uint8_t reg_tt
, sindex
;
3828 reg_tt
= (reg_rt
+ rindex
) % 32;
3829 for (sindex
= 0; sindex
< selem
; sindex
++)
3831 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3832 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3835 record_buf_mem
[mem_index
++] = esize
/ 8;
3836 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3838 addr_offset
= addr_offset
+ (esize
/ 8);
3839 reg_tt
= (reg_tt
+ 1) % 32;
3844 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3845 record_buf
[reg_index
++] = reg_rn
;
3847 aarch64_insn_r
->reg_rec_count
= reg_index
;
3848 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3849 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3851 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3853 return AARCH64_RECORD_SUCCESS
;
3856 /* Record handler for load and store instructions. */
3859 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3861 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3862 uint8_t insn_bit23
, insn_bit21
;
3863 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3864 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3865 uint64_t datasize
, offset
;
3866 uint32_t record_buf
[8];
3867 uint64_t record_buf_mem
[8];
3870 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3871 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3872 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3873 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3874 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3875 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3876 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3877 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3878 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3879 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3880 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3882 /* Load/store exclusive. */
3883 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3886 debug_printf ("Process record: load/store exclusive\n");
3890 record_buf
[0] = reg_rt
;
3891 aarch64_insn_r
->reg_rec_count
= 1;
3894 record_buf
[1] = reg_rt2
;
3895 aarch64_insn_r
->reg_rec_count
= 2;
3901 datasize
= (8 << size_bits
) * 2;
3903 datasize
= (8 << size_bits
);
3904 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3906 record_buf_mem
[0] = datasize
/ 8;
3907 record_buf_mem
[1] = address
;
3908 aarch64_insn_r
->mem_rec_count
= 1;
3911 /* Save register rs. */
3912 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3913 aarch64_insn_r
->reg_rec_count
= 1;
3917 /* Load register (literal) instructions decoding. */
3918 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3921 debug_printf ("Process record: load register (literal)\n");
3923 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3925 record_buf
[0] = reg_rt
;
3926 aarch64_insn_r
->reg_rec_count
= 1;
3928 /* All types of load/store pair instructions decoding. */
3929 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3932 debug_printf ("Process record: load/store pair\n");
3938 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3939 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
3943 record_buf
[0] = reg_rt
;
3944 record_buf
[1] = reg_rt2
;
3946 aarch64_insn_r
->reg_rec_count
= 2;
3951 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
3953 size_bits
= size_bits
>> 1;
3954 datasize
= 8 << (2 + size_bits
);
3955 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
3956 offset
= offset
<< (2 + size_bits
);
3957 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3959 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
3961 if (imm7_off
& 0x40)
3962 address
= address
- offset
;
3964 address
= address
+ offset
;
3967 record_buf_mem
[0] = datasize
/ 8;
3968 record_buf_mem
[1] = address
;
3969 record_buf_mem
[2] = datasize
/ 8;
3970 record_buf_mem
[3] = address
+ (datasize
/ 8);
3971 aarch64_insn_r
->mem_rec_count
= 2;
3973 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3974 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3976 /* Load/store register (unsigned immediate) instructions. */
3977 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
3979 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3989 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
3991 /* PRFM (immediate) */
3992 return AARCH64_RECORD_SUCCESS
;
3994 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
3996 /* LDRSW (immediate) */
4010 debug_printf ("Process record: load/store (unsigned immediate):"
4011 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4017 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4018 datasize
= 8 << size_bits
;
4019 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4021 offset
= offset
<< size_bits
;
4022 address
= address
+ offset
;
4024 record_buf_mem
[0] = datasize
>> 3;
4025 record_buf_mem
[1] = address
;
4026 aarch64_insn_r
->mem_rec_count
= 1;
4031 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4033 record_buf
[0] = reg_rt
;
4034 aarch64_insn_r
->reg_rec_count
= 1;
4037 /* Load/store register (register offset) instructions. */
4038 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4039 && insn_bits10_11
== 0x02 && insn_bit21
)
4042 debug_printf ("Process record: load/store (register offset)\n");
4043 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4050 if (size_bits
!= 0x03)
4053 return AARCH64_RECORD_UNKNOWN
;
4057 ULONGEST reg_rm_val
;
4059 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4060 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4061 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4062 offset
= reg_rm_val
<< size_bits
;
4064 offset
= reg_rm_val
;
4065 datasize
= 8 << size_bits
;
4066 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4068 address
= address
+ offset
;
4069 record_buf_mem
[0] = datasize
>> 3;
4070 record_buf_mem
[1] = address
;
4071 aarch64_insn_r
->mem_rec_count
= 1;
4076 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4078 record_buf
[0] = reg_rt
;
4079 aarch64_insn_r
->reg_rec_count
= 1;
4082 /* Load/store register (immediate and unprivileged) instructions. */
4083 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4088 debug_printf ("Process record: load/store "
4089 "(immediate and unprivileged)\n");
4091 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4098 if (size_bits
!= 0x03)
4101 return AARCH64_RECORD_UNKNOWN
;
4106 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4107 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4108 datasize
= 8 << size_bits
;
4109 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4111 if (insn_bits10_11
!= 0x01)
4113 if (imm9_off
& 0x0100)
4114 address
= address
- offset
;
4116 address
= address
+ offset
;
4118 record_buf_mem
[0] = datasize
>> 3;
4119 record_buf_mem
[1] = address
;
4120 aarch64_insn_r
->mem_rec_count
= 1;
4125 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4127 record_buf
[0] = reg_rt
;
4128 aarch64_insn_r
->reg_rec_count
= 1;
4130 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4131 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4133 /* Advanced SIMD load/store instructions. */
4135 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4137 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4139 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4141 return AARCH64_RECORD_SUCCESS
;
4144 /* Record handler for data processing SIMD and floating point instructions. */
4147 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4149 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4150 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4151 uint8_t insn_bits11_14
;
4152 uint32_t record_buf
[2];
4154 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4155 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4156 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4157 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4158 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4159 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4160 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4161 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4162 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4165 debug_printf ("Process record: data processing SIMD/FP: ");
4167 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4169 /* Floating point - fixed point conversion instructions. */
4173 debug_printf ("FP - fixed point conversion");
4175 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4176 record_buf
[0] = reg_rd
;
4178 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4180 /* Floating point - conditional compare instructions. */
4181 else if (insn_bits10_11
== 0x01)
4184 debug_printf ("FP - conditional compare");
4186 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4188 /* Floating point - data processing (2-source) and
4189 conditional select instructions. */
4190 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4193 debug_printf ("FP - DP (2-source)");
4195 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4197 else if (insn_bits10_11
== 0x00)
4199 /* Floating point - immediate instructions. */
4200 if ((insn_bits12_15
& 0x01) == 0x01
4201 || (insn_bits12_15
& 0x07) == 0x04)
4204 debug_printf ("FP - immediate");
4205 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4207 /* Floating point - compare instructions. */
4208 else if ((insn_bits12_15
& 0x03) == 0x02)
4211 debug_printf ("FP - immediate");
4212 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4214 /* Floating point - integer conversions instructions. */
4215 else if (insn_bits12_15
== 0x00)
4217 /* Convert float to integer instruction. */
4218 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4221 debug_printf ("float to int conversion");
4223 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4225 /* Convert integer to float instruction. */
4226 else if ((opcode
>> 1) == 0x01 && !rmode
)
4229 debug_printf ("int to float conversion");
4231 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4233 /* Move float to integer instruction. */
4234 else if ((opcode
>> 1) == 0x03)
4237 debug_printf ("move float to int");
4239 if (!(opcode
& 0x01))
4240 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4242 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4245 return AARCH64_RECORD_UNKNOWN
;
4248 return AARCH64_RECORD_UNKNOWN
;
4251 return AARCH64_RECORD_UNKNOWN
;
4253 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4256 debug_printf ("SIMD copy");
4258 /* Advanced SIMD copy instructions. */
4259 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4260 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4261 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4263 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4264 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4266 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4269 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4271 /* All remaining floating point or advanced SIMD instructions. */
4275 debug_printf ("all remain");
4277 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4281 debug_printf ("\n");
4283 aarch64_insn_r
->reg_rec_count
++;
4284 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4285 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4287 return AARCH64_RECORD_SUCCESS
;
4290 /* Decodes insns type and invokes its record handler. */
4293 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4295 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4297 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4298 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4299 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4300 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4302 /* Data processing - immediate instructions. */
4303 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4304 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4306 /* Branch, exception generation and system instructions. */
4307 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4308 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4310 /* Load and store instructions. */
4311 if (!ins_bit25
&& ins_bit27
)
4312 return aarch64_record_load_store (aarch64_insn_r
);
4314 /* Data processing - register instructions. */
4315 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4316 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4318 /* Data processing - SIMD and floating point instructions. */
4319 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4320 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4322 return AARCH64_RECORD_UNSUPPORTED
;
4325 /* Cleans up local record registers and memory allocations. */
4328 deallocate_reg_mem (insn_decode_record
*record
)
4330 xfree (record
->aarch64_regs
);
4331 xfree (record
->aarch64_mems
);
4335 namespace selftests
{
4338 aarch64_process_record_test (void)
4340 struct gdbarch_info info
;
4343 gdbarch_info_init (&info
);
4344 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4346 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4347 SELF_CHECK (gdbarch
!= NULL
);
4349 insn_decode_record aarch64_record
;
4351 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4352 aarch64_record
.regcache
= NULL
;
4353 aarch64_record
.this_addr
= 0;
4354 aarch64_record
.gdbarch
= gdbarch
;
4356 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4357 aarch64_record
.aarch64_insn
= 0xf9800020;
4358 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4359 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4360 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4361 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4363 deallocate_reg_mem (&aarch64_record
);
4366 } // namespace selftests
4367 #endif /* GDB_SELF_TEST */
4369 /* Parse the current instruction and record the values of the registers and
4370 memory that will be changed in current instruction to record_arch_list
4371 return -1 if something is wrong. */
4374 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4375 CORE_ADDR insn_addr
)
4377 uint32_t rec_no
= 0;
4378 uint8_t insn_size
= 4;
4380 gdb_byte buf
[insn_size
];
4381 insn_decode_record aarch64_record
;
4383 memset (&buf
[0], 0, insn_size
);
4384 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4385 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4386 aarch64_record
.aarch64_insn
4387 = (uint32_t) extract_unsigned_integer (&buf
[0],
4389 gdbarch_byte_order (gdbarch
));
4390 aarch64_record
.regcache
= regcache
;
4391 aarch64_record
.this_addr
= insn_addr
;
4392 aarch64_record
.gdbarch
= gdbarch
;
4394 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4395 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4397 printf_unfiltered (_("Process record does not support instruction "
4398 "0x%0x at address %s.\n"),
4399 aarch64_record
.aarch64_insn
,
4400 paddress (gdbarch
, insn_addr
));
4406 /* Record registers. */
4407 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4409 /* Always record register CPSR. */
4410 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4411 AARCH64_CPSR_REGNUM
);
4412 if (aarch64_record
.aarch64_regs
)
4413 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4414 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4415 aarch64_record
.aarch64_regs
[rec_no
]))
4418 /* Record memories. */
4419 if (aarch64_record
.aarch64_mems
)
4420 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4421 if (record_full_arch_list_add_mem
4422 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4423 aarch64_record
.aarch64_mems
[rec_no
].len
))
4426 if (record_full_arch_list_add_end ())
4430 deallocate_reg_mem (&aarch64_record
);