gdb/arc-tdep.c

   1 /* ARC target-dependent stuff.
   2    Copyright (C) 1995, 1997 Free Software Foundation, Inc.
   3
   4 This file is part of GDB.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 #include "defs.h"
  21 #include "frame.h"
  22 #include "inferior.h"
  23 #include "gdbcore.h"
  24 #include "target.h"
  25 #include "floatformat.h"
  26 #include "symtab.h"
  27 #include "gdbcmd.h"
  28
  29 /* Current CPU, set with the "set cpu" command.  */
  30 static int arc_bfd_mach_type;
  31 char *arc_cpu_type;
  32 char *tmp_arc_cpu_type;
  33
  34 /* Table of cpu names.  */
  35 struct {
  36   char *name;
  37   int value;
  38 } arc_cpu_type_table[] = {
  39   { "base", bfd_mach_arc_base },
  40   { NULL, 0 }
  41 };
  42
  43 /* Used by simulator.  */
  44 int display_pipeline_p;
  45 int cpu_timer;
  46 /* This one must have the same type as used in the emulator.
  47    It's currently an enum so this should be ok for now.  */
  48 int debug_pipeline_p;
  49
  50 #define ARC_CALL_SAVED_REG(r) ((r) >= 16 && (r) < 24)
  51
  52 #define OPMASK  0xf8000000
  53
  54 /* Instruction field accessor macros.
  55    See the Programmer's Reference Manual.  */
  56 #define X_OP(i) (((i) >> 27) & 0x1f)
  57 #define X_A(i) (((i) >> 21) & 0x3f)
  58 #define X_B(i) (((i) >> 15) & 0x3f)
  59 #define X_C(i) (((i) >> 9) & 0x3f)
  60 #define X_D(i) ((((i) & 0x1ff) ^ 0x100) - 0x100)
  61 #define X_L(i) (((((i) >> 5) & 0x3ffffc) ^ 0x200000) - 0x200000)
  62 #define X_N(i) (((i) >> 5) & 3)
  63 #define X_Q(i) ((i) & 0x1f)
  64
  65 /* Return non-zero if X is a short immediate data indicator.  */
  66 #define SHIMM_P(x) ((x) == 61 || (x) == 63)
  67
  68 /* Return non-zero if X is a "long" (32 bit) immediate data indicator.  */
  69 #define LIMM_P(x) ((x) == 62)
  70
  71 /* Build a simple instruction.  */
  72 #define BUILD_INSN(op, a, b, c, d) \
  73   ((((op) & 31) << 27) \
  74    | (((a) & 63) << 21) \
  75    | (((b) & 63) << 15) \
  76    | (((c) & 63) << 9) \
  77    | ((d) & 511))
  78 \f
  79 /* Codestream stuff.  */
  80 static void codestream_read PARAMS ((unsigned int *, int));
  81 static void codestream_seek PARAMS ((CORE_ADDR));
  82 static unsigned int codestream_fill PARAMS ((int));
  83
  84 #define CODESTREAM_BUFSIZ 16
  85 static CORE_ADDR codestream_next_addr;
  86 static CORE_ADDR codestream_addr;
  87 static unsigned int codestream_buf[CODESTREAM_BUFSIZ];
  88 static int codestream_off;
  89 static int codestream_cnt;
  90
  91 #define codestream_tell() \
  92   (codestream_addr + codestream_off * sizeof (codestream_buf[0]))
  93 #define codestream_peek() \
  94   (codestream_cnt == 0 \
  95    ? codestream_fill (1) \
  96    : codestream_buf[codestream_off])
  97 #define codestream_get() \
  98   (codestream_cnt-- == 0 \
  99    ? codestream_fill (0) \
 100    : codestream_buf[codestream_off++])
 101
 102 static unsigned int
 103 codestream_fill (peek_flag)
 104     int peek_flag;
 105 {
 106   codestream_addr = codestream_next_addr;
 107   codestream_next_addr += CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]);
 108   codestream_off = 0;
 109   codestream_cnt = CODESTREAM_BUFSIZ;
 110   read_memory (codestream_addr, (char *) codestream_buf,
 111                CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]));
 112   /* FIXME: check return code?  */
 113
 114   /* Handle byte order differences.  */
 115   if (HOST_BYTE_ORDER != TARGET_BYTE_ORDER)
 116     {
 117       register unsigned int i, j, n = sizeof (codestream_buf[0]);
 118       register char tmp, *p;
 119       for (i = 0, p = (char *) codestream_buf; i < CODESTREAM_BUFSIZ;
 120            ++i, p += n)
 121         for (j = 0; j < n / 2; ++j)
 122           tmp = p[j], p[j] = p[n - 1 - j], p[n - 1 - j] = tmp;
 123     }
 124
 125   if (peek_flag)
 126     return codestream_peek ();
 127   else
 128     return codestream_get ();
 129 }
 130
 131 static void
 132 codestream_seek (place)
 133     CORE_ADDR place;
 134 {
 135   codestream_next_addr = place / CODESTREAM_BUFSIZ;
 136   codestream_next_addr *= CODESTREAM_BUFSIZ;
 137   codestream_cnt = 0;
 138   codestream_fill (1);
 139   while (codestream_tell () != place)
 140     codestream_get ();
 141 }
 142
 143 /* This function is currently unused but leave in for now.  */
 144
 145 static void
 146 codestream_read (buf, count)
 147      unsigned int *buf;
 148      int count;
 149 {
 150   unsigned int *p;
 151   int i;
 152   p = buf;
 153   for (i = 0; i < count; i++)
 154     *p++ = codestream_get ();
 155 }
 156 \f
 157 /* Set up prologue scanning and return the first insn.  */
 158
 159 static unsigned int
 160 setup_prologue_scan (pc)
 161      CORE_ADDR pc;
 162 {
 163   unsigned int insn;
 164
 165   codestream_seek (pc);
 166   insn = codestream_get ();
 167
 168   return insn;
 169 }
 170
 171 /*
 172  * Find & return amount a local space allocated, and advance codestream to
 173  * first register push (if any).
 174  * If entry sequence doesn't make sense, return -1, and leave
 175  * codestream pointer random.
 176  */
 177
 178 static long
 179 arc_get_frame_setup (pc)
 180      CORE_ADDR pc;
 181 {
 182   unsigned int insn;
 183   /* Size of frame or -1 if unrecognizable prologue.  */
 184   int frame_size = -1;
 185   /* An initial "sub sp,sp,N" may or may not be for a stdarg fn.  */
 186   int maybe_stdarg_decr = -1;
 187
 188   insn = setup_prologue_scan (pc);
 189
 190   /* The authority for what appears here is the home-grown ABI.
 191      The most recent version is 1.2.  */
 192
 193   /* First insn may be "sub sp,sp,N" if stdarg fn.  */
 194   if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 195       == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
 196     {
 197       maybe_stdarg_decr = X_D (insn);
 198       insn = codestream_get ();
 199     }
 200
 201   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st blink,[sp,4] */
 202       == BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
 203     {
 204       insn = codestream_get ();
 205       /* Frame may not be necessary, even though blink is saved.
 206          At least this is something we recognize.  */
 207       frame_size = 0;
 208     }
 209
 210   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))           /* st fp,[sp] */
 211       == BUILD_INSN (2, 0, SP_REGNUM, FP_REGNUM, 0))
 212     {
 213       insn = codestream_get ();
 214       if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 215                != BUILD_INSN (12, FP_REGNUM, SP_REGNUM, SP_REGNUM, 0))
 216         return -1;
 217
 218       /* Check for stack adjustment sub sp,sp,N.  */
 219       insn = codestream_peek ();
 220       if ((insn & BUILD_INSN (-1, -1, -1, 0, 0))
 221           == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, 0, 0))
 222         {
 223           if (LIMM_P (X_C (insn)))
 224             frame_size = codestream_get ();
 225           else if (SHIMM_P (X_C (insn)))
 226             frame_size = X_D (insn);
 227           else
 228             return -1;
 229           if (frame_size < 0)
 230             return -1;
 231
 232           codestream_get ();
 233
 234           /* This sequence is used to get the address of the return
 235              buffer for a function that returns a structure.  */
 236           insn = codestream_peek ();
 237           if (insn & OPMASK == 0x60000000)
 238             codestream_get ();
 239         }
 240       /* Frameless fn.  */
 241       else
 242         {
 243           frame_size = 0;
 244         }
 245     }
 246
 247   /* If we found a "sub sp,sp,N" and nothing else, it may or may not be a
 248      stdarg fn.  The stdarg decrement is not treated as part of the frame size,
 249      so we have a dilemma: what do we return?  For now, if we get a
 250      "sub sp,sp,N" and nothing else assume this isn't a stdarg fn.  One way
 251      to fix this completely would be to add a bit to the function descriptor
 252      that says the function is a stdarg function.  */
 253
 254   if (frame_size < 0 && maybe_stdarg_decr > 0)
 255     return maybe_stdarg_decr;
 256   return frame_size;
 257 }
 258
 259 /* Given a pc value, skip it forward past the function prologue by
 260    disassembling instructions that appear to be a prologue.
 261
 262    If FRAMELESS_P is set, we are only testing to see if the function
 263    is frameless.  If it is a frameless function, return PC unchanged.
 264    This allows a quicker answer.  */
 265
 266 CORE_ADDR
 267 skip_prologue (pc, frameless_p)
 268      CORE_ADDR pc;
 269      int frameless_p;
 270 {
 271   unsigned int insn;
 272   int i, frame_size;
 273
 274   if ((frame_size = arc_get_frame_setup (pc)) < 0)
 275     return (pc);
 276
 277   if (frameless_p)
 278     return frame_size == 0 ? pc : codestream_tell ();
 279
 280   /* Skip over register saves.  */
 281   for (i = 0; i < 8; i++)
 282     {
 283       insn = codestream_peek ();
 284       if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
 285           != BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
 286         break; /* not st insn */
 287       if (! ARC_CALL_SAVED_REG (X_C (insn)))
 288         break;
 289       codestream_get ();
 290     }
 291
 292   return codestream_tell ();
 293 }
 294
 295 /* Return the return address for a frame.
 296    This is used to implement FRAME_SAVED_PC.
 297    This is taken from frameless_look_for_prologue.  */
 298
 299 CORE_ADDR
 300 arc_frame_saved_pc (frame)
 301      struct frame_info *frame;
 302 {
 303   CORE_ADDR func_start;
 304   unsigned int insn;
 305
 306   func_start = get_pc_function_start (frame->pc) + FUNCTION_START_OFFSET;
 307   if (func_start == 0)
 308     {
 309       /* Best guess.  */
 310       return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
 311     }
 312
 313   /* The authority for what appears here is the home-grown ABI.
 314      The most recent version is 1.2.  */
 315
 316   insn = setup_prologue_scan (func_start);
 317
 318   /* First insn may be "sub sp,sp,N" if stdarg fn.  */
 319   if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 320       == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
 321     insn = codestream_get ();
 322
 323   /* If the next insn is "st blink,[sp,4]" we can get blink from there.
 324      Otherwise this is a leaf function and we can use blink.  Note that
 325      this still allows for the case where a leaf function saves/clobbers/
 326      restores blink.  */
 327
 328   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st blink,[sp,4] */
 329       != BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
 330     return ARC_PC_TO_REAL_ADDRESS (read_register (BLINK_REGNUM));
 331   else
 332     return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
 333 }
 334
 335 /*
 336  * Parse the first few instructions of the function to see
 337  * what registers were stored.
 338  *
 339  * The startup sequence can be at the start of the function.
 340  * 'st blink,[sp+4], st fp,[sp], mov fp,sp'
 341  *
 342  * Local space is allocated just below by sub sp,sp,nnn.
 343  * Next, the registers used by this function are stored (as offsets from sp).
 344  */
 345
 346 void
 347 frame_find_saved_regs (fip, fsrp)
 348      struct frame_info *fip;
 349      struct frame_saved_regs *fsrp;
 350 {
 351   long locals;
 352   unsigned int insn;
 353   CORE_ADDR dummy_bottom;
 354   CORE_ADDR adr;
 355   int i, regnum, offset;
 356
 357   memset (fsrp, 0, sizeof *fsrp);
 358
 359   /* If frame is the end of a dummy, compute where the beginning would be.  */
 360   dummy_bottom = fip->frame - 4 - REGISTER_BYTES - CALL_DUMMY_LENGTH;
 361
 362   /* Check if the PC is in the stack, in a dummy frame.  */
 363   if (dummy_bottom <= fip->pc && fip->pc <= fip->frame)
 364     {
 365       /* all regs were saved by push_call_dummy () */
 366       adr = fip->frame;
 367       for (i = 0; i < NUM_REGS; i++)
 368         {
 369           adr -= REGISTER_RAW_SIZE (i);
 370           fsrp->regs[i] = adr;
 371         }
 372       return;
 373     }
 374
 375   locals = arc_get_frame_setup (get_pc_function_start (fip->pc));
 376
 377   if (locals >= 0)
 378     {
 379       /* Set `adr' to the value of `sp'.  */
 380       adr = fip->frame - locals;
 381       for (i = 0; i < 8; i++)
 382         {
 383           insn = codestream_get ();
 384           if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
 385                != BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
 386             break;
 387           regnum = X_C (insn);
 388           offset = X_D (insn);
 389           fsrp->regs[regnum] = adr + offset;
 390         }
 391     }
 392
 393   fsrp->regs[PC_REGNUM] = fip->frame + 4;
 394   fsrp->regs[FP_REGNUM] = fip->frame;
 395 }
 396
 397 void
 398 push_dummy_frame ()
 399 {
 400   CORE_ADDR sp = read_register (SP_REGNUM);
 401   int regnum;
 402   char regbuf[MAX_REGISTER_RAW_SIZE];
 403
 404   read_register_gen (PC_REGNUM, regbuf);
 405   write_memory (sp+4, regbuf, REGISTER_SIZE);
 406   read_register_gen (FP_REGNUM, regbuf);
 407   write_memory (sp, regbuf, REGISTER_SIZE);
 408   write_register (FP_REGNUM, sp);
 409   for (regnum = 0; regnum < NUM_REGS; regnum++)
 410     {
 411       read_register_gen (regnum, regbuf);
 412       sp = push_bytes (sp, regbuf, REGISTER_RAW_SIZE (regnum));
 413     }
 414   sp += (2*REGISTER_SIZE);
 415   write_register (SP_REGNUM, sp);
 416 }
 417
 418 void
 419 pop_frame ()
 420 {
 421   struct frame_info *frame = get_current_frame ();
 422   CORE_ADDR fp;
 423   int regnum;
 424   struct frame_saved_regs fsr;
 425   char regbuf[MAX_REGISTER_RAW_SIZE];
 426
 427   fp = FRAME_FP (frame);
 428   get_frame_saved_regs (frame, &fsr);
 429   for (regnum = 0; regnum < NUM_REGS; regnum++)
 430     {
 431       CORE_ADDR adr;
 432       adr = fsr.regs[regnum];
 433       if (adr)
 434         {
 435           read_memory (adr, regbuf, REGISTER_RAW_SIZE (regnum));
 436           write_register_bytes (REGISTER_BYTE (regnum), regbuf,
 437                                 REGISTER_RAW_SIZE (regnum));
 438         }
 439     }
 440   write_register (FP_REGNUM, read_memory_integer (fp, 4));
 441   write_register (PC_REGNUM, read_memory_integer (fp + 4, 4));
 442   write_register (SP_REGNUM, fp + 8);
 443   flush_cached_frames ();
 444 }
 445 \f
 446 /* Simulate single-step.  */
 447
 448 typedef enum
 449 {
 450   NORMAL4, /* a normal 4 byte insn */
 451   NORMAL8, /* a normal 8 byte insn */
 452   BRANCH4, /* a 4 byte branch insn, including ones without delay slots */
 453   BRANCH8, /* an 8 byte branch insn, including ones with delay slots */
 454 } insn_type;
 455
 456 /* Return the type of INSN and store in TARGET the destination address of a
 457    branch if this is one.  */
 458 /* ??? Need to verify all cases are properly handled.  */
 459
 460 static insn_type
 461 get_insn_type (insn, pc, target)
 462      unsigned long insn;
 463      CORE_ADDR pc, *target;
 464 {
 465   unsigned long limm;
 466
 467   switch (insn >> 27)
 468     {
 469     case 0 : case 1 : case 2 : /* load/store insns */
 470       if (LIMM_P (X_A (insn))
 471           || LIMM_P (X_B (insn))
 472           || LIMM_P (X_C (insn)))
 473         return NORMAL8;
 474       return NORMAL4;
 475     case 4 : case 5 : case 6 : /* branch insns */
 476       *target = pc + 4 + X_L (insn);
 477       /* ??? It isn't clear that this is always the right answer.
 478          The problem occurs when the next insn is an 8 byte insn.  If the
 479          branch is conditional there's no worry as there shouldn't be an 8
 480          byte insn following.  The programmer may be cheating if s/he knows
 481          the branch will never be taken, but we don't deal with that.
 482          Note that the programmer is also allowed to play games by putting
 483          an insn with long immediate data in the delay slot and then duplicate
 484          the long immediate data at the branch target.  Ugh!  */
 485       if (X_N (insn) == 0)
 486         return BRANCH4;
 487       return BRANCH8;
 488     case 7 : /* jump insns */
 489       if (LIMM_P (X_B (insn)))
 490         {
 491           limm = read_memory_integer (pc + 4, 4);
 492           *target = ARC_PC_TO_REAL_ADDRESS (limm);
 493           return BRANCH8;
 494         }
 495       if (SHIMM_P (X_B (insn)))
 496         *target = ARC_PC_TO_REAL_ADDRESS (X_D (insn));
 497       else
 498         *target = ARC_PC_TO_REAL_ADDRESS (read_register (X_B (insn)));
 499       if (X_Q (insn) == 0 && X_N (insn) == 0)
 500         return BRANCH4;
 501       return BRANCH8;
 502     default : /* arithmetic insns, etc. */
 503       if (LIMM_P (X_A (insn))
 504           || LIMM_P (X_B (insn))
 505           || LIMM_P (X_C (insn)))
 506         return NORMAL8;
 507       return NORMAL4;
 508     }
 509 }
 510
 511 /* single_step() is called just before we want to resume the inferior, if we
 512    want to single-step it but there is no hardware or kernel single-step
 513    support.  We find all the possible targets of the coming instruction and
 514    breakpoint them.
 515
 516    single_step is also called just after the inferior stops.  If we had
 517    set up a simulated single-step, we undo our damage.  */
 518
 519 void
 520 arc_software_single_step (ignore, insert_breakpoints_p)
 521      enum target_signal ignore; /* sig but we don't need it */
 522      int insert_breakpoints_p;
 523 {
 524   static CORE_ADDR next_pc, target;
 525   static int brktrg_p;
 526   typedef char binsn_quantum[BREAKPOINT_MAX];
 527   static binsn_quantum break_mem[2];
 528
 529   if (insert_breakpoints_p)
 530     {
 531       insn_type type;
 532       CORE_ADDR pc;
 533       unsigned long insn;
 534
 535       pc = read_register (PC_REGNUM);
 536       insn = read_memory_integer (pc, 4);
 537       type = get_insn_type (insn, pc, &target);
 538
 539       /* Always set a breakpoint for the insn after the branch.  */
 540       next_pc = pc + ((type == NORMAL8 || type == BRANCH8) ? 8 : 4);
 541       target_insert_breakpoint (next_pc, break_mem[0]);
 542
 543       brktrg_p = 0;
 544
 545       if ((type == BRANCH4 || type == BRANCH8)
 546           /* Watch out for branches to the following location.
 547              We just stored a breakpoint there and another call to
 548              target_insert_breakpoint will think the real insn is the
 549              breakpoint we just stored there.  */
 550           && target != next_pc)
 551         {
 552           brktrg_p = 1;
 553           target_insert_breakpoint (target, break_mem[1]);
 554         }
 555
 556     }
 557   else
 558     {
 559       /* Remove breakpoints.  */
 560       target_remove_breakpoint (next_pc, break_mem[0]);
 561
 562       if (brktrg_p)
 563         target_remove_breakpoint (target, break_mem[1]);
 564
 565       /* Fix the pc.  */
 566       stop_pc -= DECR_PC_AFTER_BREAK;
 567       write_pc (stop_pc);
 568     }
 569 }
 570 \f
 571 #ifdef GET_LONGJMP_TARGET
 572 /* Figure out where the longjmp will land.  Slurp the args out of the stack.
 573    We expect the first arg to be a pointer to the jmp_buf structure from which
 574    we extract the pc (JB_PC) that we will land at.  The pc is copied into PC.
 575    This routine returns true on success. */
 576
 577 int
 578 get_longjmp_target(pc)
 579      CORE_ADDR *pc;
 580 {
 581   char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
 582   CORE_ADDR sp, jb_addr;
 583
 584   sp = read_register (SP_REGNUM);
 585
 586   if (target_read_memory (sp + SP_ARG0, /* Offset of first arg on stack */
 587                           buf,
 588                           TARGET_PTR_BIT / TARGET_CHAR_BIT))
 589     return 0;
 590
 591   jb_addr = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
 592
 593   if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
 594                           TARGET_PTR_BIT / TARGET_CHAR_BIT))
 595     return 0;
 596
 597   *pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
 598
 599   return 1;
 600 }
 601 #endif /* GET_LONGJMP_TARGET */
 602 \f
 603 /* Disassemble one instruction.  */
 604
 605 static int
 606 arc_print_insn (vma, info)
 607      bfd_vma vma;
 608      disassemble_info *info;
 609 {
 610   static int current_mach;
 611   static int current_endian;
 612   static disassembler_ftype current_disasm;
 613
 614   if (current_disasm == NULL
 615       || arc_bfd_mach_type != current_mach
 616       || TARGET_BYTE_ORDER != current_endian)
 617     {
 618       current_mach = arc_bfd_mach_type;
 619       current_endian = TARGET_BYTE_ORDER;
 620       current_disasm = arc_get_disassembler (current_mach,
 621                                              current_endian == BIG_ENDIAN);
 622     }
 623
 624   return (*current_disasm) (vma, info);
 625 }
 626 \f
 627 /* Command to set cpu type.  */
 628
 629 void
 630 arc_set_cpu_type_command (args, from_tty)
 631      char *args;
 632      int from_tty;
 633 {
 634   int i;
 635
 636   if (tmp_arc_cpu_type == NULL || *tmp_arc_cpu_type == '\0')
 637     {
 638       printf_unfiltered ("The known ARC cpu types are as follows:\n");
 639       for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
 640         printf_unfiltered ("%s\n", arc_cpu_type_table[i].name);
 641
 642       /* Restore the value.  */
 643       tmp_arc_cpu_type = strsave (arc_cpu_type);
 644
 645       return;
 646     }
 647
 648   if (!arc_set_cpu_type (tmp_arc_cpu_type))
 649     {
 650       error ("Unknown cpu type `%s'.", tmp_arc_cpu_type);
 651       /* Restore its value.  */
 652       tmp_arc_cpu_type = strsave (arc_cpu_type);
 653     }
 654 }
 655
 656 static void
 657 arc_show_cpu_type_command (args, from_tty)
 658      char *args;
 659      int from_tty;
 660 {
 661 }
 662
 663 /* Modify the actual cpu type.
 664    Result is a boolean indicating success.  */
 665
 666 int
 667 arc_set_cpu_type (str)
 668      char *str;
 669 {
 670   int i, j;
 671
 672   if (str == NULL)
 673     return 0;
 674
 675   for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
 676     {
 677       if (strcasecmp (str, arc_cpu_type_table[i].name) == 0)
 678         {
 679           arc_cpu_type = str;
 680           arc_bfd_mach_type = arc_cpu_type_table[i].value;
 681           return 1;
 682         }
 683     }
 684
 685   return 0;
 686 }
 687 \f
 688 void
 689 _initialize_arc_tdep ()
 690 {
 691   struct cmd_list_element *c;
 692
 693   c = add_set_cmd ("cpu", class_support, var_string_noescape,
 694                    (char *) &tmp_arc_cpu_type,
 695                    "Set the type of ARC cpu in use.\n\
 696 This command has two purposes.  In a multi-cpu system it lets one\n\
 697 change the cpu being debugged.  It also gives one access to\n\
 698 cpu-type-specific registers and recognize cpu-type-specific instructions.\
 699 ",
 700                    &setlist);
 701   c->function.cfunc = arc_set_cpu_type_command;
 702   c = add_show_from_set (c, &showlist);
 703   c->function.cfunc = arc_show_cpu_type_command;
 704
 705   /* We have to use strsave here because the `set' command frees it before
 706      setting a new value.  */
 707   tmp_arc_cpu_type = strsave (DEFAULT_ARC_CPU_TYPE);
 708   arc_set_cpu_type (tmp_arc_cpu_type);
 709
 710   c = add_set_cmd ("displaypipeline", class_support, var_zinteger,
 711                    (char *) &display_pipeline_p,
 712                    "Set pipeline display (simulator only).\n\
 713 When enabled, the state of the pipeline after each cycle is displayed.",
 714                    &setlist);
 715   c = add_show_from_set (c, &showlist);
 716
 717   c = add_set_cmd ("debugpipeline", class_support, var_zinteger,
 718                    (char *) &debug_pipeline_p,
 719                    "Set pipeline debug display (simulator only).\n\
 720 When enabled, debugging information about the pipeline is displayed.",
 721                    &setlist);
 722   c = add_show_from_set (c, &showlist);
 723
 724   c = add_set_cmd ("cputimer", class_support, var_zinteger,
 725                    (char *) &cpu_timer,
 726                    "Set maximum cycle count (simulator only).\n\
 727 Control will return to gdb if the timer expires.\n\
 728 A negative value disables the timer.",
 729                    &setlist);
 730   c = add_show_from_set (c, &showlist);
 731
 732   tm_print_insn = arc_print_insn;
 733 }