gdb/gdbserver/linux-crisv32-low.c

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
   3    2007 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20    Boston, MA 02110-1301, USA.  */
  21
  22 #include "server.h"
  23 #include "linux-low.h"
  24 #include <sys/ptrace.h>
  25
  26 /* CRISv32 */
  27 #define cris_num_regs 49
  28
  29 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
  30    without any significant gain).  */
  31
  32 /* Locations need to match <include/asm/arch/ptrace.h>.  */
  33 static int cris_regmap[] = {
  34   1*4, 2*4, 3*4, 4*4,
  35   5*4, 6*4, 7*4, 8*4,
  36   9*4, 10*4, 11*4, 12*4,
  37   13*4, 14*4, 24*4, 15*4,
  38
  39   -1, -1, -1, 16*4,
  40   -1, 22*4, 23*4, 17*4,
  41   -1, -1, 21*4, 20*4,
  42   -1, 19*4, -1, 18*4,
  43
  44   25*4,
  45
  46   26*4, -1,   -1,   29*4,
  47   30*4, 31*4, 32*4, 33*4,
  48   34*4, 35*4, 36*4, 37*4,
  49   38*4, 39*4, 40*4, -1
  50
  51 };
  52
  53 extern int debug_threads;
  54
  55 static CORE_ADDR
  56 cris_get_pc (void)
  57 {
  58   unsigned long pc;
  59   collect_register_by_name ("pc", &pc);
  60   if (debug_threads)
  61     fprintf (stderr, "stop pc is %08lx\n", pc);
  62   return pc;
  63 }
  64
  65 static void
  66 cris_set_pc (CORE_ADDR pc)
  67 {
  68   unsigned long newpc = pc;
  69   supply_register_by_name ("pc", &newpc);
  70 }
  71
  72 static const unsigned short cris_breakpoint = 0xe938;
  73 #define cris_breakpoint_len 2
  74
  75 static int
  76 cris_breakpoint_at (CORE_ADDR where)
  77 {
  78   unsigned short insn;
  79
  80   (*the_target->read_memory) (where, (unsigned char *) &insn,
  81                               cris_breakpoint_len);
  82   if (insn == cris_breakpoint)
  83     return 1;
  84
  85   /* If necessary, recognize more trap instructions here.  GDB only uses the
  86      one.  */
  87   return 0;
  88 }
  89
  90 /* We only place breakpoints in empty marker functions, and thread locking
  91    is outside of the function.  So rather than importing software single-step,
  92    we can just run until exit.  */
  93
  94 /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP
  95    for CRISv32.  Without it, td_ta_event_getmsg in thread_db_create_event
  96    will fail when debugging multi-threaded applications.  */
  97
  98 static CORE_ADDR
  99 cris_reinsert_addr (void)
 100 {
 101   unsigned long pc;
 102   collect_register_by_name ("srp", &pc);
 103   return pc;
 104 }
 105
 106 static void
 107 cris_write_data_breakpoint (int bp, unsigned long start, unsigned long end)
 108 {
 109   switch (bp)
 110     {
 111     case 0:
 112       supply_register_by_name ("s3", &start);
 113       supply_register_by_name ("s4", &end);
 114       break;
 115     case 1:
 116       supply_register_by_name ("s5", &start);
 117       supply_register_by_name ("s6", &end);
 118       break;
 119     case 2:
 120       supply_register_by_name ("s7", &start);
 121       supply_register_by_name ("s8", &end);
 122       break;
 123     case 3:
 124       supply_register_by_name ("s9", &start);
 125       supply_register_by_name ("s10", &end);
 126       break;
 127     case 4:
 128       supply_register_by_name ("s11", &start);
 129       supply_register_by_name ("s12", &end);
 130       break;
 131     case 5:
 132       supply_register_by_name ("s13", &start);
 133       supply_register_by_name ("s14", &end);
 134       break;
 135     }
 136 }
 137
 138 static int
 139 cris_insert_watchpoint (char type, CORE_ADDR addr, int len)
 140 {
 141   int bp;
 142   unsigned long bp_ctrl;
 143   unsigned long start, end;
 144   unsigned long ccs;
 145
 146   /* Breakpoint/watchpoint types (GDB terminology):
 147      0 = memory breakpoint for instructions
 148      (not supported; done via memory write instead)
 149      1 = hardware breakpoint for instructions (not supported)
 150      2 = write watchpoint (supported)
 151      3 = read watchpoint (supported)
 152      4 = access watchpoint (supported).  */
 153
 154   if (type < '2' || type > '4')
 155     {
 156       /* Unsupported.  */
 157       return 1;
 158     }
 159
 160   /* Read watchpoints are set as access watchpoints, because of GDB's
 161      inability to deal with pure read watchpoints.  */
 162   if (type == '3')
 163     type = '4';
 164
 165   /* Get the configuration register.  */
 166   collect_register_by_name ("s0", &bp_ctrl);
 167
 168   /* The watchpoint allocation scheme is the simplest possible.
 169      For example, if a region is watched for read and
 170      a write watch is requested, a new watchpoint will
 171      be used.  Also, if a watch for a region that is already
 172      covered by one or more existing watchpoints, a new
 173      watchpoint will be used.  */
 174
 175   /* First, find a free data watchpoint.  */
 176   for (bp = 0; bp < 6; bp++)
 177     {
 178       /* Each data watchpoint's control registers occupy 2 bits
 179          (hence the 3), starting at bit 2 for D0 (hence the 2)
 180          with 4 bits between for each watchpoint (yes, the 4).  */
 181       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 182         break;
 183     }
 184
 185   if (bp > 5)
 186     {
 187       /* We're out of watchpoints.  */
 188       return -1;
 189     }
 190
 191   /* Configure the control register first.  */
 192   if (type == '3' || type == '4')
 193     {
 194       /* Trigger on read.  */
 195       bp_ctrl |= (1 << (2 + bp * 4));
 196     }
 197   if (type == '2' || type == '4')
 198     {
 199       /* Trigger on write.  */
 200       bp_ctrl |= (2 << (2 + bp * 4));
 201     }
 202
 203   /* Setup the configuration register.  */
 204   supply_register_by_name ("s0", &bp_ctrl);
 205
 206   /* Setup the range.  */
 207   start = addr;
 208   end = addr + len - 1;
 209
 210   /* Configure the watchpoint register.  */
 211   cris_write_data_breakpoint (bp, start, end);
 212
 213   collect_register_by_name ("ccs", &ccs);
 214   /* Set the S1 flag to enable watchpoints.  */
 215   ccs |= (1 << 19);
 216   supply_register_by_name ("ccs", &ccs);
 217
 218   return 0;
 219 }
 220
 221 static int
 222 cris_remove_watchpoint (char type, CORE_ADDR addr, int len)
 223 {
 224   int bp;
 225   unsigned long bp_ctrl;
 226   unsigned long start, end;
 227
 228   /* Breakpoint/watchpoint types:
 229      0 = memory breakpoint for instructions
 230      (not supported; done via memory write instead)
 231      1 = hardware breakpoint for instructions (not supported)
 232      2 = write watchpoint (supported)
 233      3 = read watchpoint (supported)
 234      4 = access watchpoint (supported).  */
 235   if (type < '2' || type > '4')
 236     return -1;
 237
 238   /* Read watchpoints are set as access watchpoints, because of GDB's
 239      inability to deal with pure read watchpoints.  */
 240   if (type == '3')
 241     type = '4';
 242
 243   /* Get the configuration register.  */
 244   collect_register_by_name ("s0", &bp_ctrl);
 245
 246   /* Try to find a watchpoint that is configured for the
 247      specified range, then check that read/write also matches.  */
 248
 249   /* Ugly pointer arithmetic, since I cannot rely on a
 250      single switch (addr) as there may be several watchpoints with
 251      the same start address for example.  */
 252
 253   unsigned long bp_d_regs[12];
 254
 255   /* Get all range registers to simplify search.  */
 256   collect_register_by_name ("s3", &bp_d_regs[0]);
 257   collect_register_by_name ("s4", &bp_d_regs[1]);
 258   collect_register_by_name ("s5", &bp_d_regs[2]);
 259   collect_register_by_name ("s6", &bp_d_regs[3]);
 260   collect_register_by_name ("s7", &bp_d_regs[4]);
 261   collect_register_by_name ("s8", &bp_d_regs[5]);
 262   collect_register_by_name ("s9", &bp_d_regs[6]);
 263   collect_register_by_name ("s10", &bp_d_regs[7]);
 264   collect_register_by_name ("s11", &bp_d_regs[8]);
 265   collect_register_by_name ("s12", &bp_d_regs[9]);
 266   collect_register_by_name ("s13", &bp_d_regs[10]);
 267   collect_register_by_name ("s14", &bp_d_regs[11]);
 268
 269   for (bp = 0; bp < 6; bp++)
 270     {
 271       if (bp_d_regs[bp * 2] == addr
 272           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 273         /* Matching range.  */
 274         int bitpos = 2 + bp * 4;
 275         int rw_bits;
 276
 277         /* Read/write bits for this BP.  */
 278         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 279
 280         if ((type == '3' && rw_bits == 0x1)
 281             || (type == '2' && rw_bits == 0x2)
 282             || (type == '4' && rw_bits == 0x3))
 283           {
 284             /* Read/write matched.  */
 285             break;
 286           }
 287       }
 288     }
 289
 290   if (bp > 5)
 291     {
 292       /* No watchpoint matched.  */
 293       return -1;
 294     }
 295
 296   /* Found a matching watchpoint.  Now, deconfigure it by
 297      both disabling read/write in bp_ctrl and zeroing its
 298      start/end addresses.  */
 299   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 300   /* Setup the configuration register.  */
 301   supply_register_by_name ("s0", &bp_ctrl);
 302
 303   start = end = 0;
 304   /* Configure the watchpoint register.  */
 305   cris_write_data_breakpoint (bp, start, end);
 306
 307   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 308   return 0;
 309 }
 310
 311 static int
 312 cris_stopped_by_watchpoint (void)
 313 {
 314   unsigned long exs;
 315
 316   collect_register_by_name ("exs", &exs);
 317
 318   return (((exs & 0xff00) >> 8) == 0xc);
 319 }
 320
 321 static CORE_ADDR
 322 cris_stopped_data_address (void)
 323 {
 324   unsigned long eda;
 325
 326   collect_register_by_name ("eda", &eda);
 327
 328   /* FIXME: Possibly adjust to match watched range.  */
 329   return eda;
 330 }
 331
 332 static void
 333 cris_fill_gregset (void *buf)
 334 {
 335   int i;
 336
 337   for (i = 0; i < cris_num_regs; i++)
 338     {
 339       if (cris_regmap[i] != -1)
 340         collect_register (i, ((char *) buf) + cris_regmap[i]);
 341     }
 342 }
 343
 344 static void
 345 cris_store_gregset (const void *buf)
 346 {
 347   int i;
 348
 349   for (i = 0; i < cris_num_regs; i++)
 350     {
 351       if (cris_regmap[i] != -1)
 352         supply_register (i, ((char *) buf) + cris_regmap[i]);
 353     }
 354 }
 355
 356 typedef unsigned long elf_gregset_t[cris_num_regs];
 357
 358 struct regset_info target_regsets[] = {
 359   { PTRACE_GETREGS, PTRACE_SETREGS, sizeof (elf_gregset_t),
 360     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 361   { 0, 0, -1, -1, NULL, NULL }
 362 };
 363
 364 struct linux_target_ops the_low_target = {
 365   -1,
 366   NULL,
 367   NULL,
 368   NULL,
 369   cris_get_pc,
 370   cris_set_pc,
 371   (const unsigned char *) &cris_breakpoint,
 372   cris_breakpoint_len,
 373   cris_reinsert_addr,
 374   0,
 375   cris_breakpoint_at,
 376   cris_insert_watchpoint,
 377   cris_remove_watchpoint,
 378   cris_stopped_by_watchpoint,
 379   cris_stopped_data_address,
 380 };