1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 /* Some MIPS boards don't support floating point, so we permit the
40 user to turn it off. */
44 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
45 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
46 MIPS_FPU_NONE
/* No floating point. */
49 #ifndef MIPS_DEFAULT_FPU_TYPE
50 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
52 static int mips_fpu_type_auto
= 1;
53 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
54 #define MIPS_FPU_TYPE mips_fpu_type
57 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
59 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
60 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
63 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
66 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
68 static void mips_print_register
PARAMS ((int, int));
70 static mips_extra_func_info_t
71 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
73 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
75 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
77 void mips_set_processor_type_command
PARAMS ((char *, int));
79 int mips_set_processor_type
PARAMS ((char *));
81 static void mips_show_processor_type_command
PARAMS ((char *, int));
83 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
84 struct cmd_list_element
*));
86 static mips_extra_func_info_t
87 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
89 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
90 mips_extra_func_info_t proc_desc
));
92 /* This value is the model of MIPS in use. It is derived from the value
93 of the PrID register. */
95 char *mips_processor_type
;
97 char *tmp_mips_processor_type
;
99 /* A set of original names, to be used when restoring back to generic
100 registers from a specific set. */
102 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
104 /* Names of IDT R3041 registers. */
106 char *mips_r3041_reg_names
[] = {
107 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
108 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
109 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
110 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
111 "sr", "lo", "hi", "bad", "cause","pc",
112 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
113 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
114 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
115 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
116 "fsr", "fir", "fp", "",
117 "", "", "bus", "ccfg", "", "", "", "",
118 "", "", "port", "cmp", "", "", "epc", "prid",
121 /* Names of IDT R3051 registers. */
123 char *mips_r3051_reg_names
[] = {
124 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
125 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
126 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
127 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
128 "sr", "lo", "hi", "bad", "cause","pc",
129 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
130 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
131 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
132 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
133 "fsr", "fir", "fp", "",
134 "inx", "rand", "elo", "", "ctxt", "", "", "",
135 "", "", "ehi", "", "", "", "epc", "prid",
138 /* Names of IDT R3081 registers. */
140 char *mips_r3081_reg_names
[] = {
141 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
142 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
143 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
144 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
145 "sr", "lo", "hi", "bad", "cause","pc",
146 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
147 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
148 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
149 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
150 "fsr", "fir", "fp", "",
151 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
152 "", "", "ehi", "", "", "", "epc", "prid",
155 /* Names of LSI 33k registers. */
157 char *mips_lsi33k_reg_names
[] = {
158 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
159 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
160 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
161 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
162 "epc", "hi", "lo", "sr", "cause","badvaddr",
163 "dcic", "bpc", "bda", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
165 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
168 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
175 } mips_processor_type_table
[] = {
176 { "generic", mips_generic_reg_names
},
177 { "r3041", mips_r3041_reg_names
},
178 { "r3051", mips_r3051_reg_names
},
179 { "r3071", mips_r3081_reg_names
},
180 { "r3081", mips_r3081_reg_names
},
181 { "lsi33k", mips_lsi33k_reg_names
},
185 /* Table to translate MIPS16 register field to actual register number. */
186 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
188 /* Heuristic_proc_start may hunt through the text section for a long
189 time across a 2400 baud serial line. Allows the user to limit this
192 static unsigned int heuristic_fence_post
= 0;
194 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
195 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
196 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
197 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
198 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
199 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
200 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
201 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
202 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
203 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
204 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
205 #define _PROC_MAGIC_ 0x0F0F0F0F
206 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
207 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
209 struct linked_proc_info
211 struct mips_extra_func_info info
;
212 struct linked_proc_info
*next
;
213 } *linked_proc_desc_table
= NULL
;
216 /* Should the upper word of 64-bit addresses be zeroed? */
217 static int mask_address_p
= 1;
219 /* Should call_function allocate stack space for a struct return? */
221 mips_use_struct_convention (gcc_p
, type
)
226 return (TYPE_LENGTH (type
) > 2 * MIPS_REGSIZE
);
228 return 1; /* Structures are returned by ref in extra arg0 */
231 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
234 pc_is_mips16 (bfd_vma memaddr
)
236 struct minimal_symbol
*sym
;
238 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
239 if (IS_MIPS16_ADDR (memaddr
))
242 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
243 the high bit of the info field. Use this to decide if the function is
244 MIPS16 or normal MIPS. */
245 sym
= lookup_minimal_symbol_by_pc (memaddr
);
247 return MSYMBOL_IS_SPECIAL (sym
);
253 /* This returns the PC of the first inst after the prologue. If we can't
254 find the prologue, then return 0. */
257 after_prologue (pc
, proc_desc
)
259 mips_extra_func_info_t proc_desc
;
261 struct symtab_and_line sal
;
262 CORE_ADDR func_addr
, func_end
;
265 proc_desc
= find_proc_desc (pc
, NULL
);
269 /* If function is frameless, then we need to do it the hard way. I
270 strongly suspect that frameless always means prologueless... */
271 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
272 && PROC_FRAME_OFFSET (proc_desc
) == 0)
276 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
277 return 0; /* Unknown */
279 sal
= find_pc_line (func_addr
, 0);
281 if (sal
.end
< func_end
)
284 /* The line after the prologue is after the end of the function. In this
285 case, tell the caller to find the prologue the hard way. */
290 /* Decode a MIPS32 instruction that saves a register in the stack, and
291 set the appropriate bit in the general register mask or float register mask
292 to indicate which register is saved. This is a helper function
293 for mips_find_saved_regs. */
296 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
298 unsigned long *gen_mask
;
299 unsigned long *float_mask
;
303 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
304 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
305 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
307 /* It might be possible to use the instruction to
308 find the offset, rather than the code below which
309 is based on things being in a certain order in the
310 frame, but figuring out what the instruction's offset
311 is relative to might be a little tricky. */
312 reg
= (inst
& 0x001f0000) >> 16;
313 *gen_mask
|= (1 << reg
);
315 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
316 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
317 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
320 reg
= ((inst
& 0x001f0000) >> 16);
321 *float_mask
|= (1 << reg
);
325 /* Decode a MIPS16 instruction that saves a register in the stack, and
326 set the appropriate bit in the general register or float register mask
327 to indicate which register is saved. This is a helper function
328 for mips_find_saved_regs. */
331 mips16_decode_reg_save (inst
, gen_mask
)
333 unsigned long *gen_mask
;
335 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
337 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
338 *gen_mask
|= (1 << reg
);
340 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
342 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
343 *gen_mask
|= (1 << reg
);
345 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
346 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
347 *gen_mask
|= (1 << RA_REGNUM
);
351 /* Fetch and return instruction from the specified location. If the PC
352 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
355 mips_fetch_instruction (addr
)
358 char buf
[MIPS_INSTLEN
];
362 if (pc_is_mips16 (addr
))
364 instlen
= MIPS16_INSTLEN
;
365 addr
= UNMAKE_MIPS16_ADDR (addr
);
368 instlen
= MIPS_INSTLEN
;
369 status
= read_memory_nobpt (addr
, buf
, instlen
);
371 memory_error (status
, addr
);
372 return extract_unsigned_integer (buf
, instlen
);
376 /* These the fields of 32 bit mips instructions */
377 #define mips32_op(x) (x >> 25)
378 #define itype_op(x) (x >> 25)
379 #define itype_rs(x) ((x >> 21)& 0x1f)
380 #define itype_rt(x) ((x >> 16) & 0x1f)
381 #define itype_immediate(x) ( x & 0xffff)
383 #define jtype_op(x) (x >> 25)
384 #define jtype_target(x) ( x & 0x03fffff)
386 #define rtype_op(x) (x >>25)
387 #define rtype_rs(x) ((x>>21) & 0x1f)
388 #define rtype_rt(x) ((x>>16) & 0x1f)
389 #define rtype_rd(x) ((x>>11) & 0x1f)
390 #define rtype_shamt(x) ((x>>6) & 0x1f)
391 #define rtype_funct(x) (x & 0x3f )
394 mips32_relative_offset(unsigned long inst
)
396 x
= itype_immediate(inst
) ;
397 if (x
& 0x8000) /* sign bit set */
399 x
|= 0xffff0000 ; /* sign extension */
405 /* Determine whate to set a single step breakpoint while considering
408 mips32_next_pc(CORE_ADDR pc
)
412 inst
= mips_fetch_instruction(pc
) ;
413 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
414 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
415 { op
= ((inst
>> 25) & 0x03) ;
418 case 0 : goto equal_branch
; /* BEQL */
419 case 1 : goto neq_branch
; /* BNEZ */
420 case 2 : goto less_branch
; /* BLEZ */
421 case 3 : goto greater_branch
; /* BGTZ */
425 else pc
+= 4 ; /* Not a branch, next instruction is easy */
428 { /* This gets way messy */
430 /* Further subdivide into SPECIAL, REGIMM and other */
431 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
433 case 0 : /* SPECIAL */
434 op
= rtype_funct(inst
) ;
439 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
444 break ; /* end special */
445 case 1 : /* REGIMM */
447 op
= jtype_op(inst
) ; /* branch condition */
448 switch (jtype_op(inst
))
452 case 16 : /* BLTZALL */
453 case 18 : /* BLTZALL */
455 if (read_register(itype_rs(inst
)) < 0)
456 pc
+= mips32_relative_offset(inst
) + 4 ;
457 else pc
+= 8 ; /* after the delay slot */
461 case 17 : /* BGEZAL */
462 case 19 : /* BGEZALL */
463 greater_equal_branch
:
464 if (read_register(itype_rs(inst
)) >= 0)
465 pc
+= mips32_relative_offset(inst
) + 4 ;
466 else pc
+= 8 ; /* after the delay slot */
468 /* All of the other intructions in the REGIMM catagory */
472 break ; /* end REGIMM */
475 { unsigned long reg
;
476 reg
= jtype_target(inst
) << 2 ;
477 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
478 /* Whats this mysterious 0xf000000 adjustment ??? */
481 /* FIXME case JALX :*/
482 { unsigned long reg
;
483 reg
= jtype_target(inst
) << 2 ;
484 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
485 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
487 break ; /* The new PC will be alternate mode */
488 case 4 : /* BEQ , BEQL */
490 if (read_register(itype_rs(inst
)) ==
491 read_register(itype_rt(inst
)))
492 pc
+= mips32_relative_offset(inst
) + 4 ;
495 case 5 : /* BNE , BNEL */
497 if (read_register(itype_rs(inst
)) !=
498 read_register(itype_rs(inst
)))
499 pc
+= mips32_relative_offset(inst
) + 4 ;
502 case 6 : /* BLEZ , BLEZL */
504 if (read_register(itype_rs(inst
) <= 0))
505 pc
+= mips32_relative_offset(inst
) + 4 ;
509 greater_branch
: /* BGTZ BGTZL */
510 if (read_register(itype_rs(inst
) > 0))
511 pc
+= mips32_relative_offset(inst
) + 4 ;
518 } /* mips32_next_pc */
520 /* Decoding the next place to set a breakpoint is irregular for the
521 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
522 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
523 We dont want to set a single step instruction on the extend instruction
527 /* Lots of mips16 instruction formats */
528 /* Predicting jumps requires itype,ritype,i8type
529 and their extensions extItype,extritype,extI8type
531 enum mips16_inst_fmts
533 itype
, /* 0 immediate 5,10 */
534 ritype
, /* 1 5,3,8 */
535 rrtype
, /* 2 5,3,3,5 */
536 rritype
, /* 3 5,3,3,5 */
537 rrrtype
, /* 4 5,3,3,3,2 */
538 rriatype
, /* 5 5,3,3,1,4 */
539 shifttype
, /* 6 5,3,3,3,2 */
540 i8type
, /* 7 5,3,8 */
541 i8movtype
, /* 8 5,3,3,5 */
542 i8mov32rtype
, /* 9 5,3,5,3 */
543 i64type
, /* 10 5,3,8 */
544 ri64type
, /* 11 5,3,3,5 */
545 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
546 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
547 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
548 extRRItype
, /* 15 5,5,5,5,3,3,5 */
549 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
550 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
551 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
552 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
553 extRi64type
, /* 20 5,6,5,5,3,3,5 */
554 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
556 /* I am heaping all the fields of the formats into one structure and then,
557 only the fields which are involved in instruction extension */
560 unsigned short inst
;
561 enum mips16_inst_fmts fmt
;
562 unsigned long offset
;
563 unsigned int regx
; /* Function in i8 type */
569 static void print_unpack(char * comment
,
570 struct upk_mips16
* u
)
572 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
573 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
576 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
577 format for the bits which make up the immediatate extension.
580 extended_offset(unsigned long extension
)
582 unsigned long value
;
583 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
585 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
587 value
|= extension
& 0x01f ; /* extract 4:0 */
591 /* Only call this function if you know that this is an extendable
592 instruction, It wont malfunction, but why make excess remote memory references?
593 If the immediate operands get sign extended or somthing, do it after
594 the extension is performed.
596 /* FIXME: Every one of these cases needs to worry about sign extension
597 when the offset is to be used in relative addressing */
600 static unsigned short fetch_mips_16(CORE_ADDR pc
)
603 pc
&= 0xfffffffe ; /* clear the low order bit */
604 target_read_memory(pc
,buf
,2) ;
605 return extract_unsigned_integer(buf
,2) ;
609 unpack_mips16(CORE_ADDR pc
,
610 struct upk_mips16
* upk
)
613 unsigned long extension
;
615 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
616 /* Decrement to previous address and loose the 16bit mode flag */
617 /* return if the instruction was extendable, but not actually extended */
618 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
619 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
624 unsigned long value
;
626 { value
= extended_offset(extension
) ;
627 value
= value
<< 11 ; /* rom for the original value */
628 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
631 { value
= upk
->inst
& 0x7ff ;
632 /* FIXME : Consider sign extension */
634 upk
->offset
= value
;
639 { /* A register identifier and an offset */
640 /* Most of the fields are the same as I type but the
641 immediate value is of a different length */
642 unsigned long value
;
645 value
= extended_offset(extension
) ;
646 value
= value
<< 8 ; /* from the original instruction */
647 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
648 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
649 if (value
& 0x4000) /* test the sign bit , bit 26 */
650 { value
&= ~ 0x3fff ; /* remove the sign bit */
655 value
= upk
->inst
& 0xff ; /* 8 bits */
656 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
657 /* FIXME: Do sign extension , this format needs it */
658 if (value
& 0x80) /* THIS CONFUSES ME */
659 { value
&= 0xef ; /* remove the sign bit */
664 upk
->offset
= value
;
669 unsigned long value
;
670 unsigned short nexthalf
;
671 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
672 value
= value
<< 16 ;
673 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
675 upk
->offset
= value
;
679 printf_filtered("Decoding unimplemented instruction format type\n") ;
682 /* print_unpack("UPK",upk) ; */
686 #define mips16_op(x) (x >> 11)
688 /* This is a map of the opcodes which ae known to perform branches */
689 static unsigned char map16
[32] =
696 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
698 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
704 static struct upk_mips16 upk
;
706 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
710 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
711 inst
= fetch_mips_16(pc
) ;
713 op
= mips16_op(upk
.inst
) ;
719 case 2 : /* Branch */
721 unpack_mips16(pc
,&upk
) ;
723 offset
= upk
.offset
;
728 pc
+= (offset
<< 1) + 2 ;
731 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
733 unpack_mips16(pc
,&upk
) ;
734 pc
= add_offset_16(pc
,upk
.offset
) ;
735 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
736 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
741 unpack_mips16(pc
,&upk
) ;
742 reg
= read_register(upk
.regx
) ;
744 pc
+= (upk
.offset
<< 1) + 2 ;
749 unpack_mips16(pc
,&upk
) ;
750 reg
= read_register(upk
.regx
) ;
752 pc
+= (upk
.offset
<< 1) + 2 ;
755 case 12 : /* I8 Formats btez btnez */
757 unpack_mips16(pc
,&upk
) ;
758 /* upk.regx contains the opcode */
759 reg
= read_register(24) ; /* Test register is 24 */
760 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
761 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
762 /* pc = add_offset_16(pc,upk.offset) ; */
763 pc
+= (upk
.offset
<< 1) + 2 ;
766 case 29 : /* RR Formats JR, JALR, JALR-RA */
768 op
= upk
.inst
& 0x1f ;
771 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
772 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
775 case 0 : reg
= upk
.regx
; break ;
776 case 1 : reg
= 31 ; break ; /* Function return instruction*/
777 case 2 : reg
= upk
.regx
; break ;
778 default: reg
= 31 ; break ; /* BOGUS Guess */
780 pc
= read_register(reg
) ;
784 case 30 : /* This is an extend instruction */
785 pc
+= 4 ; /* Dont be setting breakpints on the second half */
788 printf("Filtered - next PC probably incorrrect due to jump inst\n");
793 else pc
+= 2 ; /* just a good old instruction */
794 /* See if we CAN actually break on the next instruction */
795 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
797 } /* mips16_next_pc */
799 /* The mips_next_pc function supports single_tep when the remote target monitor or
800 stub is not developed enough to so a single_step.
801 It works by decoding the current instruction and predicting where a branch
802 will go. This isnt hard because all the data is available.
803 The MIPS32 and MIPS16 variants are quite different
805 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
808 /* inst = mips_fetch_instruction(pc) ; */
809 /* if (pc_is_mips16) <----- This is failing */
811 return mips16_next_pc(pc
) ;
812 else return mips32_next_pc(pc
) ;
815 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
819 mips_find_saved_regs (fci
)
820 struct frame_info
*fci
;
823 CORE_ADDR reg_position
;
824 /* r0 bit means kernel trap */
826 /* What registers have been saved? Bitmasks. */
827 unsigned long gen_mask
, float_mask
;
828 mips_extra_func_info_t proc_desc
;
831 frame_saved_regs_zalloc (fci
);
833 /* If it is the frame for sigtramp, the saved registers are located
834 in a sigcontext structure somewhere on the stack.
835 If the stack layout for sigtramp changes we might have to change these
836 constants and the companion fixup_sigtramp in mdebugread.c */
837 #ifndef SIGFRAME_BASE
838 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
839 above the sigtramp frame. */
840 #define SIGFRAME_BASE MIPS_REGSIZE
841 /* FIXME! Are these correct?? */
842 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
843 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
844 #define SIGFRAME_FPREGSAVE_OFF \
845 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
847 #ifndef SIGFRAME_REG_SIZE
848 /* FIXME! Is this correct?? */
849 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
851 if (fci
->signal_handler_caller
)
853 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
855 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
856 + ireg
* SIGFRAME_REG_SIZE
;
857 fci
->saved_regs
[ireg
] = reg_position
;
859 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
861 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
862 + ireg
* SIGFRAME_REG_SIZE
;
863 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
865 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
869 proc_desc
= fci
->proc_desc
;
870 if (proc_desc
== NULL
)
871 /* I'm not sure how/whether this can happen. Normally when we can't
872 find a proc_desc, we "synthesize" one using heuristic_proc_desc
873 and set the saved_regs right away. */
876 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
877 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
878 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
880 if (/* In any frame other than the innermost or a frame interrupted by
881 a signal, we assume that all registers have been saved.
882 This assumes that all register saves in a function happen before
883 the first function call. */
884 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
886 /* In a dummy frame we know exactly where things are saved. */
887 && !PROC_DESC_IS_DUMMY (proc_desc
)
889 /* Don't bother unless we are inside a function prologue. Outside the
890 prologue, we know where everything is. */
892 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
894 /* Not sure exactly what kernel_trap means, but if it means
895 the kernel saves the registers without a prologue doing it,
896 we better not examine the prologue to see whether registers
897 have been saved yet. */
900 /* We need to figure out whether the registers that the proc_desc
901 claims are saved have been saved yet. */
905 /* Bitmasks; set if we have found a save for the register. */
906 unsigned long gen_save_found
= 0;
907 unsigned long float_save_found
= 0;
910 /* If the address is odd, assume this is MIPS16 code. */
911 addr
= PROC_LOW_ADDR (proc_desc
);
912 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
914 /* Scan through this function's instructions preceding the current
915 PC, and look for those that save registers. */
916 while (addr
< fci
->pc
)
918 inst
= mips_fetch_instruction (addr
);
919 if (pc_is_mips16 (addr
))
920 mips16_decode_reg_save (inst
, &gen_save_found
);
922 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
925 gen_mask
= gen_save_found
;
926 float_mask
= float_save_found
;
929 /* Fill in the offsets for the registers which gen_mask says
931 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
932 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
933 if (gen_mask
& 0x80000000)
935 fci
->saved_regs
[ireg
] = reg_position
;
936 reg_position
-= MIPS_REGSIZE
;
939 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
940 of that normally used by gcc. Therefore, we have to fetch the first
941 instruction of the function, and if it's an entry instruction that
942 saves $s0 or $s1, correct their saved addresses. */
943 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
945 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
946 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
949 int sreg_count
= (inst
>> 6) & 3;
951 /* Check if the ra register was pushed on the stack. */
952 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
954 reg_position
-= MIPS_REGSIZE
;
956 /* Check if the s0 and s1 registers were pushed on the stack. */
957 for (reg
= 16; reg
< sreg_count
+16; reg
++)
959 fci
->saved_regs
[reg
] = reg_position
;
960 reg_position
-= MIPS_REGSIZE
;
965 /* Fill in the offsets for the registers which float_mask says
967 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
969 /* The freg_offset points to where the first *double* register
970 is saved. So skip to the high-order word. */
971 if (! GDB_TARGET_IS_MIPS64
)
972 reg_position
+= MIPS_REGSIZE
;
974 /* Fill in the offsets for the float registers which float_mask says
976 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
977 if (float_mask
& 0x80000000)
979 fci
->saved_regs
[FP0_REGNUM
+ireg
] = reg_position
;
980 reg_position
-= MIPS_REGSIZE
;
983 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
987 read_next_frame_reg(fi
, regno
)
988 struct frame_info
*fi
;
991 for (; fi
; fi
= fi
->next
)
993 /* We have to get the saved sp from the sigcontext
994 if it is a signal handler frame. */
995 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
999 if (fi
->saved_regs
== NULL
)
1000 mips_find_saved_regs (fi
);
1001 if (fi
->saved_regs
[regno
])
1002 return read_memory_integer(fi
->saved_regs
[regno
], MIPS_REGSIZE
);
1005 return read_register (regno
);
1008 /* mips_addr_bits_remove - remove useless address bits */
1011 mips_addr_bits_remove (addr
)
1014 #if GDB_TARGET_IS_MIPS64
1015 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
)0xffffffff))
1017 /* This hack is a work-around for existing boards using PMON,
1018 the simulator, and any other 64-bit targets that doesn't have
1019 true 64-bit addressing. On these targets, the upper 32 bits
1020 of addresses are ignored by the hardware. Thus, the PC or SP
1021 are likely to have been sign extended to all 1s by instruction
1022 sequences that load 32-bit addresses. For example, a typical
1023 piece of code that loads an address is this:
1024 lui $r2, <upper 16 bits>
1025 ori $r2, <lower 16 bits>
1026 But the lui sign-extends the value such that the upper 32 bits
1027 may be all 1s. The workaround is simply to mask off these bits.
1028 In the future, gcc may be changed to support true 64-bit
1029 addressing, and this masking will have to be disabled. */
1030 addr
&= (CORE_ADDR
)0xffffffff;
1033 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1034 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1035 So we still have to mask off useless bits from addresses. */
1036 addr
&= (CORE_ADDR
)0xffffffff;
1043 mips_init_frame_pc_first (fromleaf
, prev
)
1045 struct frame_info
*prev
;
1049 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1050 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1051 tmp
= mips_skip_stub (pc
);
1052 prev
->pc
= tmp
? tmp
: pc
;
1057 mips_frame_saved_pc(frame
)
1058 struct frame_info
*frame
;
1061 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1062 /* We have to get the saved pc from the sigcontext
1063 if it is a signal handler frame. */
1064 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1065 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1067 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1068 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
1070 saved_pc
= read_next_frame_reg(frame
, pcreg
);
1072 return ADDR_BITS_REMOVE (saved_pc
);
1075 static struct mips_extra_func_info temp_proc_desc
;
1076 static struct frame_saved_regs temp_saved_regs
;
1078 /* Set a register's saved stack address in temp_saved_regs. If an address
1079 has already been set for this register, do nothing; this way we will
1080 only recognize the first save of a given register in a function prologue.
1081 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1084 set_reg_offset (regno
, offset
)
1088 if (temp_saved_regs
.regs
[regno
] == 0)
1089 temp_saved_regs
.regs
[regno
] = offset
;
1093 /* Test whether the PC points to the return instruction at the
1094 end of a function. */
1097 mips_about_to_return (pc
)
1100 if (pc_is_mips16 (pc
))
1101 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1102 generates a "jr $ra"; other times it generates code to load
1103 the return address from the stack to an accessible register (such
1104 as $a3), then a "jr" using that register. This second case
1105 is almost impossible to distinguish from an indirect jump
1106 used for switch statements, so we don't even try. */
1107 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1109 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1113 /* This fencepost looks highly suspicious to me. Removing it also
1114 seems suspicious as it could affect remote debugging across serial
1118 heuristic_proc_start (pc
)
1126 pc
= ADDR_BITS_REMOVE (pc
);
1128 fence
= start_pc
- heuristic_fence_post
;
1129 if (start_pc
== 0) return 0;
1131 if (heuristic_fence_post
== UINT_MAX
1132 || fence
< VM_MIN_ADDRESS
)
1133 fence
= VM_MIN_ADDRESS
;
1135 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1137 /* search back for previous return */
1138 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1139 if (start_pc
< fence
)
1141 /* It's not clear to me why we reach this point when
1142 stop_soon_quietly, but with this test, at least we
1143 don't print out warnings for every child forked (eg, on
1144 decstation). 22apr93 rich@cygnus.com. */
1145 if (!stop_soon_quietly
)
1147 static int blurb_printed
= 0;
1149 if (fence
== VM_MIN_ADDRESS
)
1150 warning("Hit beginning of text section without finding");
1152 warning("Hit heuristic-fence-post without finding");
1154 warning("enclosing function for address 0x%s", paddr_nz (pc
));
1158 This warning occurs if you are debugging a function without any symbols\n\
1159 (for example, in a stripped executable). In that case, you may wish to\n\
1160 increase the size of the search with the `set heuristic-fence-post' command.\n\
1162 Otherwise, you told GDB there was a function where there isn't one, or\n\
1163 (more likely) you have encountered a bug in GDB.\n");
1170 else if (pc_is_mips16 (start_pc
))
1172 unsigned short inst
;
1174 /* On MIPS16, any one of the following is likely to be the
1175 start of a function:
1179 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1180 inst
= mips_fetch_instruction (start_pc
);
1181 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1182 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1183 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1184 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1186 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1187 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1192 else if (mips_about_to_return (start_pc
))
1194 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1199 /* skip nops (usually 1) 0 - is this */
1200 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1201 start_pc
+= MIPS_INSTLEN
;
1206 /* Fetch the immediate value from a MIPS16 instruction.
1207 If the previous instruction was an EXTEND, use it to extend
1208 the upper bits of the immediate value. This is a helper function
1209 for mips16_heuristic_proc_desc. */
1212 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1213 unsigned short prev_inst
; /* previous instruction */
1214 unsigned short inst
; /* current instruction */
1215 int nbits
; /* number of bits in imm field */
1216 int scale
; /* scale factor to be applied to imm */
1217 int is_signed
; /* is the imm field signed? */
1221 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1223 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1224 if (offset
& 0x8000) /* check for negative extend */
1225 offset
= 0 - (0x10000 - (offset
& 0xffff));
1226 return offset
| (inst
& 0x1f);
1230 int max_imm
= 1 << nbits
;
1231 int mask
= max_imm
- 1;
1232 int sign_bit
= max_imm
>> 1;
1234 offset
= inst
& mask
;
1235 if (is_signed
&& (offset
& sign_bit
))
1236 offset
= 0 - (max_imm
- offset
);
1237 return offset
* scale
;
1242 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1243 stream from start_pc to limit_pc. */
1246 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1247 CORE_ADDR start_pc
, limit_pc
;
1248 struct frame_info
*next_frame
;
1252 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1253 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1254 unsigned inst
= 0; /* current instruction */
1255 unsigned entry_inst
= 0; /* the entry instruction */
1258 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1259 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1261 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1263 /* Save the previous instruction. If it's an EXTEND, we'll extract
1264 the immediate offset extension from it in mips16_get_imm. */
1267 /* Fetch and decode the instruction. */
1268 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1269 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1270 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1272 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1273 if (offset
< 0) /* negative stack adjustment? */
1274 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1276 /* Exit loop if a positive stack adjustment is found, which
1277 usually means that the stack cleanup code in the function
1278 epilogue is reached. */
1281 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1283 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1284 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1285 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1286 set_reg_offset (reg
, sp
+ offset
);
1288 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1290 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1291 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1292 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1293 set_reg_offset (reg
, sp
+ offset
);
1295 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1297 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1298 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1299 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1301 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1303 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1304 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1305 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1307 else if (inst
== 0x673d) /* move $s1, $sp */
1310 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1312 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1314 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1315 frame_addr
= sp
+ offset
;
1316 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1317 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1319 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1321 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1322 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1323 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1324 set_reg_offset (reg
, frame_addr
+ offset
);
1326 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1328 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1329 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1330 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1331 set_reg_offset (reg
, frame_addr
+ offset
);
1333 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1334 entry_inst
= inst
; /* save for later processing */
1335 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1336 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1339 /* The entry instruction is typically the first instruction in a function,
1340 and it stores registers at offsets relative to the value of the old SP
1341 (before the prologue). But the value of the sp parameter to this
1342 function is the new SP (after the prologue has been executed). So we
1343 can't calculate those offsets until we've seen the entire prologue,
1344 and can calculate what the old SP must have been. */
1345 if (entry_inst
!= 0)
1347 int areg_count
= (entry_inst
>> 8) & 7;
1348 int sreg_count
= (entry_inst
>> 6) & 3;
1350 /* The entry instruction always subtracts 32 from the SP. */
1351 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1353 /* Now we can calculate what the SP must have been at the
1354 start of the function prologue. */
1355 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1357 /* Check if a0-a3 were saved in the caller's argument save area. */
1358 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1360 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1361 set_reg_offset (reg
, sp
+ offset
);
1362 offset
+= MIPS_REGSIZE
;
1365 /* Check if the ra register was pushed on the stack. */
1367 if (entry_inst
& 0x20)
1369 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1370 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1371 offset
-= MIPS_REGSIZE
;
1374 /* Check if the s0 and s1 registers were pushed on the stack. */
1375 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1377 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1378 set_reg_offset (reg
, sp
+ offset
);
1379 offset
-= MIPS_REGSIZE
;
1385 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1386 CORE_ADDR start_pc
, limit_pc
;
1387 struct frame_info
*next_frame
;
1391 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1393 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1394 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1395 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1396 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1398 unsigned long inst
, high_word
, low_word
;
1401 /* Fetch the instruction. */
1402 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1404 /* Save some code by pre-extracting some useful fields. */
1405 high_word
= (inst
>> 16) & 0xffff;
1406 low_word
= inst
& 0xffff;
1407 reg
= high_word
& 0x1f;
1409 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1410 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1411 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1413 if (low_word
& 0x8000) /* negative stack adjustment? */
1414 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1416 /* Exit loop if a positive stack adjustment is found, which
1417 usually means that the stack cleanup code in the function
1418 epilogue is reached. */
1421 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1423 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1424 set_reg_offset (reg
, sp
+ low_word
);
1426 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1428 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1429 but the register size used is only 32 bits. Make the address
1430 for the saved register point to the lower 32 bits. */
1431 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1432 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1434 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1436 /* Old gcc frame, r30 is virtual frame pointer. */
1437 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1438 frame_addr
= sp
+ low_word
;
1439 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1441 unsigned alloca_adjust
;
1442 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1443 frame_addr
= read_next_frame_reg(next_frame
, 30);
1444 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1445 if (alloca_adjust
> 0)
1447 /* FP > SP + frame_size. This may be because
1448 * of an alloca or somethings similar.
1449 * Fix sp to "pre-alloca" value, and try again.
1451 sp
+= alloca_adjust
;
1456 /* move $30,$sp. With different versions of gas this will be either
1457 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1458 Accept any one of these. */
1459 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1461 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1462 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1464 unsigned alloca_adjust
;
1465 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1466 frame_addr
= read_next_frame_reg(next_frame
, 30);
1467 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1468 if (alloca_adjust
> 0)
1470 /* FP > SP + frame_size. This may be because
1471 * of an alloca or somethings similar.
1472 * Fix sp to "pre-alloca" value, and try again.
1474 sp
+= alloca_adjust
;
1479 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1481 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1482 set_reg_offset (reg
, frame_addr
+ low_word
);
1487 static mips_extra_func_info_t
1488 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1489 CORE_ADDR start_pc
, limit_pc
;
1490 struct frame_info
*next_frame
;
1492 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1494 if (start_pc
== 0) return NULL
;
1495 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1496 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1497 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1498 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1499 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1501 if (start_pc
+ 200 < limit_pc
)
1502 limit_pc
= start_pc
+ 200;
1503 if (pc_is_mips16 (start_pc
))
1504 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1506 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1507 return &temp_proc_desc
;
1510 static mips_extra_func_info_t
1511 non_heuristic_proc_desc (pc
, addrptr
)
1515 CORE_ADDR startaddr
;
1516 mips_extra_func_info_t proc_desc
;
1517 struct block
*b
= block_for_pc(pc
);
1520 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1522 *addrptr
= startaddr
;
1523 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1527 if (startaddr
> BLOCK_START (b
))
1528 /* This is the "pathological" case referred to in a comment in
1529 print_frame_info. It might be better to move this check into
1533 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1536 /* If we never found a PDR for this function in symbol reading, then
1537 examine prologues to find the information. */
1540 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1541 if (PROC_FRAME_REG (proc_desc
) == -1)
1551 static mips_extra_func_info_t
1552 find_proc_desc (pc
, next_frame
)
1554 struct frame_info
*next_frame
;
1556 mips_extra_func_info_t proc_desc
;
1557 CORE_ADDR startaddr
;
1559 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1563 /* IF this is the topmost frame AND
1564 * (this proc does not have debugging information OR
1565 * the PC is in the procedure prologue)
1566 * THEN create a "heuristic" proc_desc (by analyzing
1567 * the actual code) to replace the "official" proc_desc.
1569 if (next_frame
== NULL
)
1571 struct symtab_and_line val
;
1572 struct symbol
*proc_symbol
=
1573 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1577 val
= find_pc_line (BLOCK_START
1578 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1580 val
.pc
= val
.end
? val
.end
: pc
;
1582 if (!proc_symbol
|| pc
< val
.pc
)
1584 mips_extra_func_info_t found_heuristic
=
1585 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1587 if (found_heuristic
)
1588 proc_desc
= found_heuristic
;
1594 /* Is linked_proc_desc_table really necessary? It only seems to be used
1595 by procedure call dummys. However, the procedures being called ought
1596 to have their own proc_descs, and even if they don't,
1597 heuristic_proc_desc knows how to create them! */
1599 register struct linked_proc_info
*link
;
1601 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1602 if (PROC_LOW_ADDR(&link
->info
) <= pc
1603 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1607 startaddr
= heuristic_proc_start (pc
);
1610 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1616 get_frame_pointer(frame
, proc_desc
)
1617 struct frame_info
*frame
;
1618 mips_extra_func_info_t proc_desc
;
1620 return ADDR_BITS_REMOVE (
1621 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1622 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1625 mips_extra_func_info_t cached_proc_desc
;
1628 mips_frame_chain(frame
)
1629 struct frame_info
*frame
;
1631 mips_extra_func_info_t proc_desc
;
1633 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1635 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1638 /* Check if the PC is inside a call stub. If it is, fetch the
1639 PC of the caller of that stub. */
1640 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1643 /* Look up the procedure descriptor for this PC. */
1644 proc_desc
= find_proc_desc(saved_pc
, frame
);
1648 cached_proc_desc
= proc_desc
;
1650 /* If no frame pointer and frame size is zero, we must be at end
1651 of stack (or otherwise hosed). If we don't check frame size,
1652 we loop forever if we see a zero size frame. */
1653 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1654 && PROC_FRAME_OFFSET (proc_desc
) == 0
1655 /* The previous frame from a sigtramp frame might be frameless
1656 and have frame size zero. */
1657 && !frame
->signal_handler_caller
)
1660 return get_frame_pointer (frame
, proc_desc
);
1664 init_extra_frame_info(fci
)
1665 struct frame_info
*fci
;
1669 /* Use proc_desc calculated in frame_chain */
1670 mips_extra_func_info_t proc_desc
=
1671 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1673 fci
->saved_regs
= NULL
;
1675 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1678 /* Fixup frame-pointer - only needed for top frame */
1679 /* This may not be quite right, if proc has a real frame register.
1680 Get the value of the frame relative sp, procedure might have been
1681 interrupted by a signal at it's very start. */
1682 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1683 && !PROC_DESC_IS_DUMMY (proc_desc
))
1684 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1686 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1688 if (proc_desc
== &temp_proc_desc
)
1692 /* Do not set the saved registers for a sigtramp frame,
1693 mips_find_saved_registers will do that for us.
1694 We can't use fci->signal_handler_caller, it is not yet set. */
1695 find_pc_partial_function (fci
->pc
, &name
,
1696 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1697 if (!IN_SIGTRAMP (fci
->pc
, name
))
1699 fci
->saved_regs
= (CORE_ADDR
*)
1700 frame_obstack_alloc (SIZEOF_FRAME_SAVED_REGS
);
1701 memcpy (fci
->saved_regs
, temp_saved_regs
.regs
, SIZEOF_FRAME_SAVED_REGS
);
1702 fci
->saved_regs
[PC_REGNUM
]
1703 = fci
->saved_regs
[RA_REGNUM
];
1707 /* hack: if argument regs are saved, guess these contain args */
1708 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1709 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1711 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1713 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1720 /* MIPS stack frames are almost impenetrable. When execution stops,
1721 we basically have to look at symbol information for the function
1722 that we stopped in, which tells us *which* register (if any) is
1723 the base of the frame pointer, and what offset from that register
1724 the frame itself is at.
1726 This presents a problem when trying to examine a stack in memory
1727 (that isn't executing at the moment), using the "frame" command. We
1728 don't have a PC, nor do we have any registers except SP.
1730 This routine takes two arguments, SP and PC, and tries to make the
1731 cached frames look as if these two arguments defined a frame on the
1732 cache. This allows the rest of info frame to extract the important
1733 arguments without difficulty. */
1736 setup_arbitrary_frame (argc
, argv
)
1741 error ("MIPS frame specifications require two arguments: sp and pc");
1743 return create_new_frame (argv
[0], argv
[1]);
1747 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1749 * For n32 ABI, eight.
1750 * For all others, he same as the size of a general register.
1752 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1753 #define MIPS_NABI32 1
1754 #define STACK_ARGSIZE 8
1756 #define MIPS_NABI32 0
1757 #define STACK_ARGSIZE MIPS_REGSIZE
1761 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1766 CORE_ADDR struct_addr
;
1772 int stack_offset
= 0;
1774 /* Macros to round N up or down to the next A boundary; A must be
1776 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1777 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1779 /* First ensure that the stack and structure return address (if any)
1780 are properly aligned. The stack has to be at least 64-bit aligned
1781 even on 32-bit machines, because doubles must be 64-bit aligned.
1782 On at least one MIPS variant, stack frames need to be 128-bit
1783 aligned, so we round to this widest known alignment. */
1784 sp
= ROUND_DOWN (sp
, 16);
1785 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1787 /* Now make space on the stack for the args. We allocate more
1788 than necessary for EABI, because the first few arguments are
1789 passed in registers, but that's OK. */
1790 for (argnum
= 0; argnum
< nargs
; argnum
++)
1791 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1792 sp
-= ROUND_UP (len
, 16);
1794 /* Initialize the integer and float register pointers. */
1796 float_argreg
= FPA0_REGNUM
;
1798 /* the struct_return pointer occupies the first parameter-passing reg */
1800 write_register (argreg
++, struct_addr
);
1802 /* Now load as many as possible of the first arguments into
1803 registers, and push the rest onto the stack. Loop thru args
1804 from first to last. */
1805 for (argnum
= 0; argnum
< nargs
; argnum
++)
1808 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1809 value_ptr arg
= args
[argnum
];
1810 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1811 int len
= TYPE_LENGTH (arg_type
);
1812 enum type_code typecode
= TYPE_CODE (arg_type
);
1814 /* The EABI passes structures that do not fit in a register by
1815 reference. In all other cases, pass the structure by value. */
1816 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1817 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1819 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1820 typecode
= TYPE_CODE_PTR
;
1825 val
= (char *)VALUE_CONTENTS (arg
);
1827 /* 32-bit ABIs always start floating point arguments in an
1828 even-numbered floating point register. */
1829 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1830 && (float_argreg
& 1))
1833 /* Floating point arguments passed in registers have to be
1834 treated specially. On 32-bit architectures, doubles
1835 are passed in register pairs; the even register gets
1836 the low word, and the odd register gets the high word.
1837 On non-EABI processors, the first two floating point arguments are
1838 also copied to general registers, because MIPS16 functions
1839 don't use float registers for arguments. This duplication of
1840 arguments in general registers can't hurt non-MIPS16 functions
1841 because those registers are normally skipped. */
1842 if (typecode
== TYPE_CODE_FLT
1843 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1844 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
1846 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1848 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1849 unsigned long regval
;
1851 /* Write the low word of the double to the even register(s). */
1852 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1853 write_register (float_argreg
++, regval
);
1855 write_register (argreg
+1, regval
);
1857 /* Write the high word of the double to the odd register(s). */
1858 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1859 write_register (float_argreg
++, regval
);
1862 write_register (argreg
, regval
);
1869 /* This is a floating point value that fits entirely
1870 in a single register. */
1871 CORE_ADDR regval
= extract_address (val
, len
);
1872 write_register (float_argreg
++, regval
);
1875 write_register (argreg
, regval
);
1876 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1882 /* Copy the argument to general registers or the stack in
1883 register-sized pieces. Large arguments are split between
1884 registers and stack. */
1885 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1886 are treated specially: Irix cc passes them in registers
1887 where gcc sometimes puts them on the stack. For maximum
1888 compatibility, we will put them in both places. */
1890 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1891 (len
% MIPS_REGSIZE
!= 0));
1894 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1896 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1898 /* Write this portion of the argument to the stack. */
1899 /* Should shorter than int integer values be
1900 promoted to int before being stored? */
1902 int longword_offset
= 0;
1903 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1904 if (STACK_ARGSIZE
== 8 &&
1905 (typecode
== TYPE_CODE_INT
||
1906 typecode
== TYPE_CODE_PTR
||
1907 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1908 longword_offset
= STACK_ARGSIZE
- len
;
1909 else if ((typecode
== TYPE_CODE_STRUCT
||
1910 typecode
== TYPE_CODE_UNION
) &&
1911 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
1912 longword_offset
= STACK_ARGSIZE
- len
;
1914 write_memory (sp
+ stack_offset
+ longword_offset
,
1918 /* Note!!! This is NOT an else clause.
1919 Odd sized structs may go thru BOTH paths. */
1920 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1922 CORE_ADDR regval
= extract_address (val
, partial_len
);
1924 /* A non-floating-point argument being passed in a
1925 general register. If a struct or union, and if
1926 the remaining length is smaller than the register
1927 size, we have to adjust the register value on
1930 It does not seem to be necessary to do the
1931 same for integral types.
1933 Also don't do this adjustment on EABI and O64
1937 && (MIPS_REGSIZE
< 8)
1938 && TARGET_BYTE_ORDER
== BIG_ENDIAN
1939 && (partial_len
< MIPS_REGSIZE
)
1940 && (typecode
== TYPE_CODE_STRUCT
||
1941 typecode
== TYPE_CODE_UNION
))
1942 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1945 write_register (argreg
, regval
);
1948 /* If this is the old ABI, prevent subsequent floating
1949 point arguments from being passed in floating point
1952 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1958 /* The offset onto the stack at which we will start
1959 copying parameters (after the registers are used up)
1960 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1961 leaves room for the "home" area for register parameters.
1963 In the new EABI (and the NABI32), the 8 register parameters
1964 do not have "home" stack space reserved for them, so the
1965 stack offset does not get incremented until after
1966 we have used up the 8 parameter registers. */
1968 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
1970 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
1975 /* Set the return address register to point to the entry
1976 point of the program, where a breakpoint lies in wait. */
1977 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1979 /* Return adjusted stack pointer. */
1984 mips_push_register(CORE_ADDR
*sp
, int regno
)
1986 char buffer
[MAX_REGISTER_RAW_SIZE
];
1987 int regsize
= REGISTER_RAW_SIZE (regno
);
1990 read_register_gen (regno
, buffer
);
1991 write_memory (*sp
, buffer
, regsize
);
1994 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1995 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1998 mips_push_dummy_frame()
2001 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2002 xmalloc(sizeof(struct linked_proc_info
));
2003 mips_extra_func_info_t proc_desc
= &link
->info
;
2004 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2005 CORE_ADDR old_sp
= sp
;
2006 link
->next
= linked_proc_desc_table
;
2007 linked_proc_desc_table
= link
;
2009 /* FIXME! are these correct ? */
2010 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2011 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2012 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2013 #define FLOAT_SINGLE_REG_SAVE_MASK \
2014 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2016 * The registers we must save are all those not preserved across
2017 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2018 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2019 * and FP Control/Status registers.
2022 * Dummy frame layout:
2025 * Saved MMHI, MMLO, FPC_CSR
2030 * Saved D18 (i.e. F19, F18)
2032 * Saved D0 (i.e. F1, F0)
2033 * Argument build area and stack arguments written via mips_push_arguments
2037 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2038 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
2039 PROC_FRAME_OFFSET(proc_desc
) = 0;
2040 PROC_FRAME_ADJUST(proc_desc
) = 0;
2041 mips_push_register (&sp
, PC_REGNUM
);
2042 mips_push_register (&sp
, HI_REGNUM
);
2043 mips_push_register (&sp
, LO_REGNUM
);
2044 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2046 /* Save general CPU registers */
2047 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
2048 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2049 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
- MIPS_REGSIZE
;
2050 for (ireg
= 32; --ireg
>= 0; )
2051 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
2052 mips_push_register (&sp
, ireg
);
2054 /* Save floating point registers starting with high order word */
2055 PROC_FREG_MASK(proc_desc
) =
2056 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2057 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2058 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2060 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
- 8;
2061 for (ireg
= 32; --ireg
>= 0; )
2062 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2063 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2065 /* Update the frame pointer for the call dummy and the stack pointer.
2066 Set the procedure's starting and ending addresses to point to the
2067 call dummy address at the entry point. */
2068 write_register (PUSH_FP_REGNUM
, old_sp
);
2069 write_register (SP_REGNUM
, sp
);
2070 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2071 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2072 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2073 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2079 register int regnum
;
2080 struct frame_info
*frame
= get_current_frame ();
2081 CORE_ADDR new_sp
= FRAME_FP (frame
);
2083 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
2085 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2086 if (frame
->saved_regs
== NULL
)
2087 mips_find_saved_regs (frame
);
2088 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2090 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2091 && frame
->saved_regs
[regnum
])
2092 write_register (regnum
,
2093 read_memory_integer (frame
->saved_regs
[regnum
],
2096 write_register (SP_REGNUM
, new_sp
);
2097 flush_cached_frames ();
2099 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2101 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2103 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2105 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2107 if (&pi_ptr
->info
== proc_desc
)
2112 error ("Can't locate dummy extra frame info\n");
2114 if (prev_ptr
!= NULL
)
2115 prev_ptr
->next
= pi_ptr
->next
;
2117 linked_proc_desc_table
= pi_ptr
->next
;
2121 write_register (HI_REGNUM
,
2122 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
2123 write_register (LO_REGNUM
,
2124 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
2125 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2126 write_register (FCRCS_REGNUM
,
2127 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
2132 mips_print_register (regnum
, all
)
2135 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2137 /* Get the data in raw format. */
2138 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2140 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2144 /* If an even floating point register, also print as double. */
2145 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2146 && !((regnum
-FP0_REGNUM
) & 1))
2147 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2149 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2151 read_relative_register_raw_bytes (regnum
, dbuffer
);
2152 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2153 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2155 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2156 val_print (builtin_type_double
, dbuffer
, 0, 0,
2157 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2158 printf_filtered ("); ");
2160 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2162 /* The problem with printing numeric register names (r26, etc.) is that
2163 the user can't use them on input. Probably the best solution is to
2164 fix it so that either the numeric or the funky (a2, etc.) names
2165 are accepted on input. */
2166 if (regnum
< MIPS_NUMREGS
)
2167 printf_filtered ("(r%d): ", regnum
);
2169 printf_filtered (": ");
2171 /* If virtual format is floating, print it that way. */
2172 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2173 if (FP_REGISTER_DOUBLE
)
2174 { /* show 8-byte floats as float AND double: */
2175 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2177 printf_filtered (" (float) ");
2178 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2179 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2180 printf_filtered (", (double) ");
2181 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2182 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2185 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2186 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2187 /* Else print as integer in hex. */
2189 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2190 'x', 0, gdb_stdout
);
2193 /* Replacement for generic do_registers_info.
2194 Print regs in pretty columns. */
2197 do_fp_register_row (regnum
)
2199 { /* do values for FP (float) regs */
2200 char *raw_buffer
[2];
2202 /* use HI and LO to control the order of combining two flt regs */
2203 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2204 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2205 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2206 int inv1
, inv2
, inv3
;
2208 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2209 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2210 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2212 /* Get the data in raw format. */
2213 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2214 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2215 if (REGISTER_RAW_SIZE(regnum
) == 4)
2217 /* 4-byte registers: we can fit two registers per row. */
2218 /* Also print every pair of 4-byte regs as an 8-byte double. */
2219 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2220 error ("can't read register %d (%s)",
2221 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2223 /* copy the two floats into one double, and unpack both */
2224 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2225 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2226 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2227 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2229 printf_filtered (inv1
? " %-5s: <invalid float>" :
2230 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2231 printf_filtered (inv2
? " %-5s: <invalid float>" :
2232 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2233 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2234 " dbl: %-24.17g\n", doub
);
2235 /* may want to do hex display here (future enhancement) */
2239 { /* eight byte registers: print each one as float AND as double. */
2240 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2242 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2243 flt1
= unpack_double (builtin_type_float
,
2244 &raw_buffer
[HI
][offset
], &inv1
);
2245 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2247 printf_filtered (inv1
? " %-5s: <invalid float>" :
2248 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2249 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2250 " dbl: %-24.17g\n", doub
);
2251 /* may want to do hex display here (future enhancement) */
2257 /* Print a row's worth of GP (int) registers, with name labels above */
2260 do_gp_register_row (regnum
)
2263 /* do values for GP (int) regs */
2264 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2265 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2267 int start_regnum
= regnum
;
2268 int numregs
= NUM_REGS
;
2271 /* For GP registers, we print a separate row of names above the vals */
2272 printf_filtered (" ");
2273 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2275 if (*REGISTER_NAME (regnum
) == '\0')
2276 continue; /* unused register */
2277 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2278 break; /* end the row: reached FP register */
2279 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2280 REGISTER_NAME (regnum
));
2283 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2284 start_regnum
); /* print the R0 to R31 names */
2286 regnum
= start_regnum
; /* go back to start of row */
2287 /* now print the values in hex, 4 or 8 to the row */
2288 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2290 if (*REGISTER_NAME (regnum
) == '\0')
2291 continue; /* unused register */
2292 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2293 break; /* end row: reached FP register */
2294 /* OK: get the data in raw format. */
2295 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2296 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2297 /* pad small registers */
2298 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2299 printf_filtered (" ");
2300 /* Now print the register value in hex, endian order. */
2301 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2302 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2303 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2305 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2306 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2307 printf_filtered (" ");
2310 if (col
> 0) /* ie. if we actually printed anything... */
2311 printf_filtered ("\n");
2316 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2319 mips_do_registers_info (regnum
, fpregs
)
2323 if (regnum
!= -1) /* do one specified register */
2325 if (*(REGISTER_NAME (regnum
)) == '\0')
2326 error ("Not a valid register for the current processor type");
2328 mips_print_register (regnum
, 0);
2329 printf_filtered ("\n");
2331 else /* do all (or most) registers */
2334 while (regnum
< NUM_REGS
)
2336 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2337 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2338 regnum
= do_fp_register_row (regnum
); /* FP regs */
2340 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2342 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2347 /* Return number of args passed to a frame. described by FIP.
2348 Can return -1, meaning no way to tell. */
2351 mips_frame_num_args (frame
)
2352 struct frame_info
*frame
;
2354 #if 0 /* FIXME Use or lose this! */
2355 struct chain_info_t
*p
;
2357 p
= mips_find_cached_frame (FRAME_FP (frame
));
2359 return p
->the_info
.numargs
;
2364 /* Is this a branch with a delay slot? */
2366 static int is_delayed
PARAMS ((unsigned long));
2373 for (i
= 0; i
< NUMOPCODES
; ++i
)
2374 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2375 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2377 return (i
< NUMOPCODES
2378 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2379 | INSN_COND_BRANCH_DELAY
2380 | INSN_COND_BRANCH_LIKELY
)));
2384 mips_step_skips_delay (pc
)
2387 char buf
[MIPS_INSTLEN
];
2389 /* There is no branch delay slot on MIPS16. */
2390 if (pc_is_mips16 (pc
))
2393 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2394 /* If error reading memory, guess that it is not a delayed branch. */
2396 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2400 /* Skip the PC past function prologue instructions (32-bit version).
2401 This is a helper function for mips_skip_prologue. */
2404 mips32_skip_prologue (pc
, lenient
)
2405 CORE_ADDR pc
; /* starting PC to search from */
2410 int seen_sp_adjust
= 0;
2411 int load_immediate_bytes
= 0;
2413 /* Skip the typical prologue instructions. These are the stack adjustment
2414 instruction and the instructions that save registers on the stack
2415 or in the gcc frame. */
2416 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2418 unsigned long high_word
;
2420 inst
= mips_fetch_instruction (pc
);
2421 high_word
= (inst
>> 16) & 0xffff;
2424 if (lenient
&& is_delayed (inst
))
2428 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2429 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2431 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2432 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2434 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2435 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2436 && (inst
& 0x001F0000)) /* reg != $zero */
2439 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2441 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2443 continue; /* reg != $zero */
2445 /* move $s8,$sp. With different versions of gas this will be either
2446 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2447 Accept any one of these. */
2448 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2451 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2453 else if (high_word
== 0x3c1c) /* lui $gp,n */
2455 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2457 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2458 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2460 /* The following instructions load $at or $t0 with an immediate
2461 value in preparation for a stack adjustment via
2462 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2463 a local variable, so we accept them only before a stack adjustment
2464 instruction was seen. */
2465 else if (!seen_sp_adjust
)
2467 if (high_word
== 0x3c01 || /* lui $at,n */
2468 high_word
== 0x3c08) /* lui $t0,n */
2470 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2473 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2474 high_word
== 0x3508 || /* ori $t0,$t0,n */
2475 high_word
== 0x3401 || /* ori $at,$zero,n */
2476 high_word
== 0x3408) /* ori $t0,$zero,n */
2478 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2488 /* In a frameless function, we might have incorrectly
2489 skipped some load immediate instructions. Undo the skipping
2490 if the load immediate was not followed by a stack adjustment. */
2491 if (load_immediate_bytes
&& !seen_sp_adjust
)
2492 pc
-= load_immediate_bytes
;
2496 /* Skip the PC past function prologue instructions (16-bit version).
2497 This is a helper function for mips_skip_prologue. */
2500 mips16_skip_prologue (pc
, lenient
)
2501 CORE_ADDR pc
; /* starting PC to search from */
2505 int extend_bytes
= 0;
2506 int prev_extend_bytes
;
2508 /* Table of instructions likely to be found in a function prologue. */
2511 unsigned short inst
;
2512 unsigned short mask
;
2515 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2516 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2517 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2518 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2519 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2520 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2521 { 0x673d, 0xffff }, /* move $s1,sp */
2522 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2523 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2524 { 0xe809, 0xf81f }, /* entry pseudo-op */
2525 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2526 { 0, 0 } /* end of table marker */
2529 /* Skip the typical prologue instructions. These are the stack adjustment
2530 instruction and the instructions that save registers on the stack
2531 or in the gcc frame. */
2532 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2534 unsigned short inst
;
2537 inst
= mips_fetch_instruction (pc
);
2539 /* Normally we ignore an extend instruction. However, if it is
2540 not followed by a valid prologue instruction, we must adjust
2541 the pc back over the extend so that it won't be considered
2542 part of the prologue. */
2543 if ((inst
& 0xf800) == 0xf000) /* extend */
2545 extend_bytes
= MIPS16_INSTLEN
;
2548 prev_extend_bytes
= extend_bytes
;
2551 /* Check for other valid prologue instructions besides extend. */
2552 for (i
= 0; table
[i
].mask
!= 0; i
++)
2553 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2555 if (table
[i
].mask
!= 0) /* it was in table? */
2556 continue; /* ignore it */
2557 else /* non-prologue */
2559 /* Return the current pc, adjusted backwards by 2 if
2560 the previous instruction was an extend. */
2561 return pc
- prev_extend_bytes
;
2567 /* To skip prologues, I use this predicate. Returns either PC itself
2568 if the code at PC does not look like a function prologue; otherwise
2569 returns an address that (if we're lucky) follows the prologue. If
2570 LENIENT, then we must skip everything which is involved in setting
2571 up the frame (it's OK to skip more, just so long as we don't skip
2572 anything which might clobber the registers which are being saved.
2573 We must skip more in the case where part of the prologue is in the
2574 delay slot of a non-prologue instruction). */
2577 mips_skip_prologue (pc
, lenient
)
2581 /* See if we can determine the end of the prologue via the symbol table.
2582 If so, then return either PC, or the PC after the prologue, whichever
2585 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2587 if (post_prologue_pc
!= 0)
2588 return max (pc
, post_prologue_pc
);
2590 /* Can't determine prologue from the symbol table, need to examine
2593 if (pc_is_mips16 (pc
))
2594 return mips16_skip_prologue (pc
, lenient
);
2596 return mips32_skip_prologue (pc
, lenient
);
2600 /* The lenient prologue stuff should be superseded by the code in
2601 init_extra_frame_info which looks to see whether the stores mentioned
2602 in the proc_desc have actually taken place. */
2604 /* Is address PC in the prologue (loosely defined) for function at
2608 mips_in_lenient_prologue (startaddr
, pc
)
2609 CORE_ADDR startaddr
;
2612 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2613 return pc
>= startaddr
&& pc
< end_prologue
;
2617 /* Given a return value in `regbuf' with a type `valtype',
2618 extract and copy its value into `valbuf'. */
2620 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2621 struct type
*valtype
;
2622 char regbuf
[REGISTER_BYTES
];
2627 int len
= TYPE_LENGTH (valtype
);
2630 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2631 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2632 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2633 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2634 regnum
= FP0_REGNUM
;
2636 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2637 { /* "un-left-justify" the value from the register */
2638 if (len
< REGISTER_RAW_SIZE (regnum
))
2639 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2640 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2641 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2642 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2643 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2644 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2646 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2647 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2650 /* Given a return value in `regbuf' with a type `valtype',
2651 write it's value into the appropriate register. */
2653 mips_store_return_value (valtype
, valbuf
)
2654 struct type
*valtype
;
2659 int len
= TYPE_LENGTH (valtype
);
2660 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2663 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2664 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2665 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2666 && len
<= MIPS_REGSIZE
)))
2667 regnum
= FP0_REGNUM
;
2669 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2670 { /* "left-justify" the value in the register */
2671 if (len
< REGISTER_RAW_SIZE (regnum
))
2672 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2673 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2674 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2675 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2676 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2677 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2679 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2680 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2681 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2682 len
> REGISTER_RAW_SIZE (regnum
) ?
2683 len
: REGISTER_RAW_SIZE (regnum
));
2686 /* Exported procedure: Is PC in the signal trampoline code */
2689 in_sigtramp (pc
, ignore
)
2691 char *ignore
; /* function name */
2693 if (sigtramp_address
== 0)
2695 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2698 /* Commands to show/set the MIPS FPU type. */
2700 static void show_mipsfpu_command
PARAMS ((char *, int));
2702 show_mipsfpu_command (args
, from_tty
)
2708 switch (MIPS_FPU_TYPE
)
2710 case MIPS_FPU_SINGLE
:
2711 fpu
= "single-precision";
2713 case MIPS_FPU_DOUBLE
:
2714 fpu
= "double-precision";
2717 fpu
= "absent (none)";
2720 if (mips_fpu_type_auto
)
2721 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
2724 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
2729 static void set_mipsfpu_command
PARAMS ((char *, int));
2731 set_mipsfpu_command (args
, from_tty
)
2735 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
2736 show_mipsfpu_command (args
, from_tty
);
2739 static void set_mipsfpu_single_command
PARAMS ((char *, int));
2741 set_mipsfpu_single_command (args
, from_tty
)
2745 mips_fpu_type
= MIPS_FPU_SINGLE
;
2746 mips_fpu_type_auto
= 0;
2749 static void set_mipsfpu_double_command
PARAMS ((char *, int));
2751 set_mipsfpu_double_command (args
, from_tty
)
2755 mips_fpu_type
= MIPS_FPU_DOUBLE
;
2756 mips_fpu_type_auto
= 0;
2759 static void set_mipsfpu_none_command
PARAMS ((char *, int));
2761 set_mipsfpu_none_command (args
, from_tty
)
2765 mips_fpu_type
= MIPS_FPU_NONE
;
2766 mips_fpu_type_auto
= 0;
2769 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
2771 set_mipsfpu_auto_command (args
, from_tty
)
2775 mips_fpu_type_auto
= 1;
2778 /* Command to set the processor type. */
2781 mips_set_processor_type_command (args
, from_tty
)
2787 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2789 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2790 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2791 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2793 /* Restore the value. */
2794 tmp_mips_processor_type
= strsave (mips_processor_type
);
2799 if (!mips_set_processor_type (tmp_mips_processor_type
))
2801 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2802 /* Restore its value. */
2803 tmp_mips_processor_type
= strsave (mips_processor_type
);
2808 mips_show_processor_type_command (args
, from_tty
)
2814 /* Modify the actual processor type. */
2817 mips_set_processor_type (str
)
2825 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2827 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2829 mips_processor_type
= str
;
2831 for (j
= 0; j
< NUM_REGS
; ++j
)
2832 /* FIXME - MIPS should be defining REGISTER_NAME() instead */
2833 gdb_register_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2837 /* FIXME tweak fpu flag too */
2844 /* Attempt to identify the particular processor model by reading the
2848 mips_read_processor_type ()
2852 prid
= read_register (PRID_REGNUM
);
2854 if ((prid
& ~0xf) == 0x700)
2855 return savestring ("r3041", strlen("r3041"));
2860 /* Just like reinit_frame_cache, but with the right arguments to be
2861 callable as an sfunc. */
2864 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2867 struct cmd_list_element
*c
;
2869 reinit_frame_cache ();
2873 gdb_print_insn_mips (memaddr
, info
)
2875 disassemble_info
*info
;
2877 mips_extra_func_info_t proc_desc
;
2879 /* Search for the function containing this address. Set the low bit
2880 of the address when searching, in case we were given an even address
2881 that is the start of a 16-bit function. If we didn't do this,
2882 the search would fail because the symbol table says the function
2883 starts at an odd address, i.e. 1 byte past the given address. */
2884 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2885 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2887 /* Make an attempt to determine if this is a 16-bit function. If
2888 the procedure descriptor exists and the address therein is odd,
2889 it's definitely a 16-bit function. Otherwise, we have to just
2890 guess that if the address passed in is odd, it's 16-bits. */
2892 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
2894 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
2896 /* Round down the instruction address to the appropriate boundary. */
2897 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2899 /* Call the appropriate disassembler based on the target endian-ness. */
2900 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2901 return print_insn_big_mips (memaddr
, info
);
2903 return print_insn_little_mips (memaddr
, info
);
2906 /* Old-style breakpoint macros.
2907 The IDT board uses an unusual breakpoint value, and sometimes gets
2908 confused when it sees the usual MIPS breakpoint instruction. */
2910 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
2911 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
2912 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
2913 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
2914 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
2915 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
2916 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
2917 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
2919 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2920 counter value to determine whether a 16- or 32-bit breakpoint should be
2921 used. It returns a pointer to a string of bytes that encode a breakpoint
2922 instruction, stores the length of the string to *lenptr, and adjusts pc
2923 (if necessary) to point to the actual memory location where the
2924 breakpoint should be inserted. */
2926 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2930 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2932 if (pc_is_mips16 (*pcptr
))
2934 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2935 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2936 *lenptr
= sizeof(mips16_big_breakpoint
);
2937 return mips16_big_breakpoint
;
2941 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2942 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2943 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2945 *lenptr
= sizeof(big_breakpoint
);
2947 if (strcmp (target_shortname
, "mips") == 0)
2948 return idt_big_breakpoint
;
2949 else if (strcmp (target_shortname
, "ddb") == 0
2950 || strcmp (target_shortname
, "pmon") == 0
2951 || strcmp (target_shortname
, "lsi") == 0)
2952 return pmon_big_breakpoint
;
2954 return big_breakpoint
;
2959 if (pc_is_mips16 (*pcptr
))
2961 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2962 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2963 *lenptr
= sizeof(mips16_little_breakpoint
);
2964 return mips16_little_breakpoint
;
2968 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2969 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2970 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2972 *lenptr
= sizeof(little_breakpoint
);
2974 if (strcmp (target_shortname
, "mips") == 0)
2975 return idt_little_breakpoint
;
2976 else if (strcmp (target_shortname
, "ddb") == 0
2977 || strcmp (target_shortname
, "pmon") == 0
2978 || strcmp (target_shortname
, "lsi") == 0)
2979 return pmon_little_breakpoint
;
2981 return little_breakpoint
;
2986 /* If PC is in a mips16 call or return stub, return the address of the target
2987 PC, which is either the callee or the caller. There are several
2988 cases which must be handled:
2990 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
2991 target PC is in $31 ($ra).
2992 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
2993 and the target PC is in $2.
2994 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
2995 before the jal instruction, this is effectively a call stub
2996 and the the target PC is in $2. Otherwise this is effectively
2997 a return stub and the target PC is in $18.
2999 See the source code for the stubs in gcc/config/mips/mips16.S for
3002 This function implements the SKIP_TRAMPOLINE_CODE macro.
3010 CORE_ADDR start_addr
;
3012 /* Find the starting address and name of the function containing the PC. */
3013 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3016 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3017 target PC is in $31 ($ra). */
3018 if (strcmp (name
, "__mips16_ret_sf") == 0
3019 || strcmp (name
, "__mips16_ret_df") == 0)
3020 return read_register (RA_REGNUM
);
3022 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3024 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3025 and the target PC is in $2. */
3026 if (name
[19] >= '0' && name
[19] <= '9')
3027 return read_register (2);
3029 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3030 before the jal instruction, this is effectively a call stub
3031 and the the target PC is in $2. Otherwise this is effectively
3032 a return stub and the target PC is in $18. */
3033 else if (name
[19] == 's' || name
[19] == 'd')
3035 if (pc
== start_addr
)
3037 /* Check if the target of the stub is a compiler-generated
3038 stub. Such a stub for a function bar might have a name
3039 like __fn_stub_bar, and might look like this:
3044 la $1,bar (becomes a lui/addiu pair)
3046 So scan down to the lui/addi and extract the target
3047 address from those two instructions. */
3049 CORE_ADDR target_pc
= read_register (2);
3053 /* See if the name of the target function is __fn_stub_*. */
3054 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3056 if (strncmp (name
, "__fn_stub_", 10) != 0
3057 && strcmp (name
, "etext") != 0
3058 && strcmp (name
, "_etext") != 0)
3061 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3062 The limit on the search is arbitrarily set to 20
3063 instructions. FIXME. */
3064 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3066 inst
= mips_fetch_instruction (target_pc
);
3067 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3068 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3069 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3070 return pc
| (inst
& 0xffff); /* low word */
3073 /* Couldn't find the lui/addui pair, so return stub address. */
3077 /* This is the 'return' part of a call stub. The return
3078 address is in $r18. */
3079 return read_register (18);
3082 return 0; /* not a stub */
3086 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3087 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3090 mips_in_call_stub (pc
, name
)
3094 CORE_ADDR start_addr
;
3096 /* Find the starting address of the function containing the PC. If the
3097 caller didn't give us a name, look it up at the same time. */
3098 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3101 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3103 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3104 if (name
[19] >= '0' && name
[19] <= '9')
3106 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3107 before the jal instruction, this is effectively a call stub. */
3108 else if (name
[19] == 's' || name
[19] == 'd')
3109 return pc
== start_addr
;
3112 return 0; /* not a stub */
3116 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3117 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3120 mips_in_return_stub (pc
, name
)
3124 CORE_ADDR start_addr
;
3126 /* Find the starting address of the function containing the PC. */
3127 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3130 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3131 if (strcmp (name
, "__mips16_ret_sf") == 0
3132 || strcmp (name
, "__mips16_ret_df") == 0)
3135 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3136 i.e. after the jal instruction, this is effectively a return stub. */
3137 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3138 && (name
[19] == 's' || name
[19] == 'd')
3139 && pc
!= start_addr
)
3142 return 0; /* not a stub */
3146 /* Return non-zero if the PC is in a library helper function that should
3147 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3150 mips_ignore_helper (pc
)
3155 /* Find the starting address and name of the function containing the PC. */
3156 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3159 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3160 that we want to ignore. */
3161 return (strcmp (name
, "__mips16_ret_sf") == 0
3162 || strcmp (name
, "__mips16_ret_df") == 0);
3166 /* Return a location where we can set a breakpoint that will be hit
3167 when an inferior function call returns. This is normally the
3168 program's entry point. Executables that don't have an entry
3169 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3170 whose address is the location where the breakpoint should be placed. */
3173 mips_call_dummy_address ()
3175 struct minimal_symbol
*sym
;
3177 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3179 return SYMBOL_VALUE_ADDRESS (sym
);
3181 return entry_point_address ();
3186 _initialize_mips_tdep ()
3188 static struct cmd_list_element
*mipsfpulist
= NULL
;
3189 struct cmd_list_element
*c
;
3191 if (!tm_print_insn
) /* Someone may have already set it */
3192 tm_print_insn
= gdb_print_insn_mips
;
3194 /* Let the user turn off floating point and set the fence post for
3195 heuristic_proc_start. */
3197 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3198 "Set use of MIPS floating-point coprocessor.",
3199 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3200 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3201 "Select single-precision MIPS floating-point coprocessor.",
3203 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3204 "Select double-precision MIPS floating-point coprocessor .",
3206 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3207 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3208 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3209 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3210 "Select no MIPS floating-point coprocessor.",
3212 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3213 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3214 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3215 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3216 "Select MIPS floating-point coprocessor automatically.",
3218 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3219 "Show current use of MIPS floating-point coprocessor target.",
3222 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3223 (char *) &tmp_mips_processor_type
,
3224 "Set the type of MIPS processor in use.\n\
3225 Set this to be able to access processor-type-specific registers.\n\
3228 c
->function
.cfunc
= mips_set_processor_type_command
;
3229 c
= add_show_from_set (c
, &showlist
);
3230 c
->function
.cfunc
= mips_show_processor_type_command
;
3232 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3233 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3235 /* We really would like to have both "0" and "unlimited" work, but
3236 command.c doesn't deal with that. So make it a var_zinteger
3237 because the user can always use "999999" or some such for unlimited. */
3238 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3239 (char *) &heuristic_fence_post
,
3241 Set the distance searched for the start of a function.\n\
3242 If you are debugging a stripped executable, GDB needs to search through the\n\
3243 program for the start of a function. This command sets the distance of the\n\
3244 search. The only need to set it is when debugging a stripped executable.",
3246 /* We need to throw away the frame cache when we set this, since it
3247 might change our ability to get backtraces. */
3248 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3249 add_show_from_set (c
, &showlist
);
3251 /* Allow the user to control whether the upper bits of 64-bit
3252 addresses should be zeroed. */
3254 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *)&mask_address_p
,
3255 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3256 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3257 Without an argument, zeroing of upper address bits is enabled.", &setlist
),