gdb/nat/x86-dregs.h

   1 /* Debug register code for x86 (i386 and x86-64).
   2
   3    Copyright (C) 2009-2024 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef NAT_X86_DREGS_H
  21 #define NAT_X86_DREGS_H
  22
  23 /* Support for hardware watchpoints and breakpoints using the x86
  24    debug registers.
  25
  26    This provides several functions for inserting and removing
  27    hardware-assisted breakpoints and watchpoints, testing if one or
  28    more of the watchpoints triggered and at what address, checking
  29    whether a given region can be watched, etc.
  30
  31    The functions below implement debug registers sharing by reference
  32    counts, and allow to watch regions up to 16 bytes long
  33    (32 bytes on 64 bit hosts).  */
  34
  35
  36 #include "gdbsupport/break-common.h"
  37
  38 /* Low-level function vector.  */
  39
  40 struct x86_dr_low_type
  41   {
  42     /* Set the debug control (DR7) register to a given value for
  43        all LWPs.  May be NULL if the debug control register cannot
  44        be set.  */
  45     void (*set_control) (unsigned long);
  46
  47     /* Put an address into one debug register for all LWPs.  May
  48        be NULL if debug registers cannot be set*/
  49     void (*set_addr) (int, CORE_ADDR);
  50
  51     /* Return the address in a given debug register of the current
  52        LWP.  */
  53     CORE_ADDR (*get_addr) (int);
  54
  55     /* Return the value of the debug status (DR6) register for
  56        current LWP.  */
  57     unsigned long (*get_status) (void);
  58
  59     /* Return the value of the debug control (DR7) register for
  60        current LWP.  */
  61     unsigned long (*get_control) (void);
  62
  63     /* Number of bytes used for debug registers (4 or 8).  */
  64     int debug_register_length;
  65   };
  66
  67 extern struct x86_dr_low_type x86_dr_low;
  68
  69 /* Debug registers' indices.  */
  70 #define DR_FIRSTADDR 0
  71 #define DR_LASTADDR  3
  72 #define DR_NADDR     4  /* The number of debug address registers.  */
  73 #define DR_STATUS    6  /* Index of debug status register (DR6).  */
  74 #define DR_CONTROL   7  /* Index of debug control register (DR7).  */
  75
  76 /* Global state needed to track h/w watchpoints.  */
  77
  78 struct x86_debug_reg_state
  79 {
  80   /* Mirror the inferior's DRi registers.  We keep the status and
  81      control registers separated because they don't hold addresses.
  82      Note that since we can change these mirrors while threads are
  83      running, we never trust them to explain a cause of a trap.
  84      For that, we need to peek directly in the inferior registers.  */
  85   CORE_ADDR dr_mirror[DR_NADDR];
  86   unsigned dr_status_mirror, dr_control_mirror;
  87
  88   /* Reference counts for each debug address register.  */
  89   int dr_ref_count[DR_NADDR];
  90 };
  91
  92 /* A macro to loop over all debug address registers.  */
  93 #define ALL_DEBUG_ADDRESS_REGISTERS(i) \
  94   for (i = DR_FIRSTADDR; i <= DR_LASTADDR; i++)
  95
  96 /* Return a pointer to the local mirror of the debug registers of
  97    process PID.  This function must be provided by the client
  98    if required.  */
  99 extern struct x86_debug_reg_state *x86_debug_reg_state (pid_t pid);
 100
 101 /* Insert a watchpoint to watch a memory region which starts at
 102    address ADDR and whose length is LEN bytes.  Watch memory accesses
 103    of the type TYPE.  Return 0 on success, -1 on failure.  */
 104 extern int x86_dr_insert_watchpoint (struct x86_debug_reg_state *state,
 105                                      enum target_hw_bp_type type,
 106                                      CORE_ADDR addr,
 107                                      int len);
 108
 109 /* Remove a watchpoint that watched the memory region which starts at
 110    address ADDR, whose length is LEN bytes, and for accesses of the
 111    type TYPE.  Return 0 on success, -1 on failure.  */
 112 extern int x86_dr_remove_watchpoint (struct x86_debug_reg_state *state,
 113                                      enum target_hw_bp_type type,
 114                                      CORE_ADDR addr,
 115                                      int len);
 116
 117 /* Return non-zero if we can watch a memory region that starts at
 118    address ADDR and whose length is LEN bytes.  */
 119 extern int x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state *state,
 120                                             CORE_ADDR addr, int len);
 121
 122 /* If the inferior has some break/watchpoint that triggered, set the
 123    address associated with that break/watchpoint and return true.
 124    Otherwise, return false.  */
 125 extern int x86_dr_stopped_data_address (struct x86_debug_reg_state *state,
 126                                         CORE_ADDR *addr_p);
 127
 128 /* Return true if the inferior has some watchpoint that triggered.
 129    Otherwise return false.  */
 130 extern int x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state *state);
 131
 132 /* Return true if the inferior has some hardware breakpoint that
 133    triggered.  Otherwise return false.  */
 134 extern int x86_dr_stopped_by_hw_breakpoint (struct x86_debug_reg_state *state);
 135
 136 #endif /* NAT_X86_DREGS_H */