gdb/testsuite/gdb.arch/arc-decode-insn.S

   1 ; This testcase is part of GDB, the GNU debugger.
   2
   3 ; Copyright 2017-2023 Free Software Foundation, Inc.
   4
   5 ; This program is free software; you can redistribute it and/or modify
   6 ; it under the terms of the GNU General Public License as published by
   7 ; the Free Software Foundation; either version 3 of the License, or
   8 ; (at your option) any later version.
   9 ;
  10 ; This program is distributed in the hope that it will be useful,
  11 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ; GNU General Public License for more details.
  14 ;
  15 ; You should have received a copy of the GNU General Public License
  16 ; along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17
  18 .section .text
  19 .global main
  20
  21 #define TEST_J
  22 #define TEST_JCC
  23 #define TEST_JL
  24 #define TEST_JLCC
  25 #define TEST_B
  26 #define TEST_BBIT
  27 #define TEST_BCC
  28 #define TEST_BI
  29 #define TEST_BL
  30 #define TEST_BRCC
  31 #define TEST_JLI
  32 #define TEST_LEAVE_S
  33 #define TEST_LPCC
  34
  35 ; JLI-specific stuff
  36 #ifdef TEST_JLI
  37 jli_table:
  38     .word 0xdeadbeea
  39     .word 0xdeadbeea
  40 jli_target:
  41     .word 0xdeadbeea
  42     .word 0xdeadbeea
  43
  44 .set jli_offset, 3
  45 #endif
  46 main:
  47
  48 ; Each test case requires several symbols to be set, that identify expected
  49 ; parameters of this instruction.  Required symbols:
  50 ;   ${test}_start: symbol points to start of the test
  51 ;   ${test}_end: symbol points to the instruction after the jump/branch
  52 ;      instruction.
  53 ;   ${test}_target: branch target address.
  54 ;   ${test}_has_delay_slot: whether instruction has delay slot.
  55 ;   ${test}_cc: condition code numeric value.
  56
  57     .set r12_value, 0xdead0000
  58     .set blink_value, 0xdead0004
  59     .set limm_value, 0xdead0008
  60     ; Just an integer
  61     .set r4_value, 0xdead000c
  62     ; Just an integer
  63     .set r5_value, 0xdead0010
  64     ; offset index for BI [c]
  65     .set r7_value, 4
  66     .set u6_value, 0x20
  67     .set s12_target, 0x100
  68
  69     mov r12, @r12_value
  70     mov r4, @r4_value
  71     mov r5, @r5_value
  72     mov r7, @r7_value
  73     mov blink, @blink_value
  74 #ifdef TEST_JLI
  75     ; jli_base aux regnum = 0x290
  76     sr jli_table, [0x290]
  77 #endif
  78
  79 start_branch_tests:
  80
  81 #ifdef TEST_J
  82
  83 #define TEST_NAME j_c
  84     ; j [c]
  85     .set j_c_target, @r4_value
  86     .set j_c_has_delay_slot,   0
  87     .set j_c_cc, 0
  88     j_c_start:
  89         j [r4]
  90     j_c_end:
  91
  92     ; j [blink]
  93     .set j_blink_target, @blink_value
  94     .set j_blink_has_delay_slot,   0
  95     .set j_blink_cc, 0
  96     mov blink, @j_blink_target
  97     j_blink_start:
  98         j [blink]
  99     j_blink_end:
 100
 101     ; j limm
 102     .set j_limm_target, @limm_value
 103     .set j_limm_has_delay_slot,   0
 104     .set j_limm_cc, 0
 105     j_limm_start:
 106         j @j_limm_target
 107     j_limm_end:
 108
 109     ; j u6
 110     .set j_u6_target, @u6_value
 111     .set j_u6_has_delay_slot,   0
 112     .set j_u6_cc, 0
 113     j_u6_start:
 114         j @j_u6_target
 115     j_u6_end:
 116
 117     ; j s12
 118     .set j_s12_target, @s12_target
 119     .set j_s12_has_delay_slot,   0
 120     .set j_s12_cc, 0
 121     j_s12_start:
 122         j @j_s12_target
 123     j_s12_end:
 124
 125     ; j.d [c]
 126     .set j_d_c_target, @r4_value
 127     .set j_d_c_has_delay_slot,   1
 128     .set j_d_c_cc, 0
 129     j_d_c_start:
 130         j.d [r4]
 131     j_d_c_end:
 132         nop_s
 133
 134     ; j.d [blink]
 135     .set j_d_blink_target, @blink_value
 136     .set j_d_blink_has_delay_slot,   1
 137     .set j_d_blink_cc, 0
 138     j_d_blink_start:
 139         j.d [blink]
 140     j_d_blink_end:
 141         nop_s
 142
 143     ; j.d u6
 144     .set j_d_u6_target, @u6_value
 145     .set j_d_u6_has_delay_slot,   1
 146     .set j_d_u6_cc, 0
 147     j_d_u6_start:
 148         j.d @j_d_u6_target
 149     j_d_u6_end:
 150         nop_s
 151
 152     ; j.d s12
 153     .set j_d_s12_target, @s12_target
 154     .set j_d_s12_has_delay_slot,   1
 155     .set j_d_s12_cc, 0
 156     j_d_s12_start:
 157         j.d @j_d_s12_target
 158     j_d_s12_end:
 159         nop_s
 160
 161     ; j_s [b]
 162     .set j_s_b_target, @r12_value
 163     .set j_s_b_has_delay_slot,   0
 164     .set j_s_b_cc, 0
 165     j_s_b_start:
 166         j_s [r12]
 167     j_s_b_end:
 168
 169     ; j_s.d [b]
 170     .set j_s_d_b_target, @r12_value
 171     .set j_s_d_b_has_delay_slot,   1
 172     .set j_s_d_b_cc, 0
 173     j_s_d_b_start:
 174         j_s.d [r12]
 175     j_s_d_b_end:
 176         nop_s
 177
 178     ; j_s [blink]
 179     .set j_s_blink_target, @blink_value
 180     .set j_s_blink_has_delay_slot,   0
 181     .set j_s_blink_cc, 0
 182     j_s_blink_start:
 183         j_s [blink]
 184     j_s_blink_end:
 185
 186     ; j_s.d [blink]
 187     .set j_s_d_blink_target, @blink_value
 188     .set j_s_d_blink_has_delay_slot,   1
 189     .set j_c_cc, 0
 190     j_s_d_blink_start:
 191         j_s.d [blink]
 192     j_s_d_blink_end:
 193         nop_s
 194 #endif /* TEST_J */
 195
 196 #ifdef TEST_JCC
 197     ; jcc [c]
 198     .set jcc_c_target, @r4_value
 199     .set jcc_c_has_delay_slot,   0
 200     .set jcc_c_cc, 1
 201     jcc_c_start:
 202         jeq [r4]
 203     jcc_c_end:
 204
 205     ; jcc [blink]
 206     .set jcc_blink_target, @blink_value
 207     .set jcc_blink_has_delay_slot,   0
 208     .set jcc_blink_cc, 2
 209     jcc_blink_start:
 210         jnz [blink]
 211     jcc_blink_end:
 212
 213     ; jcc limm
 214     .set jcc_limm_target, @limm_value
 215     .set jcc_limm_has_delay_slot,   0
 216     .set jcc_limm_cc, 9
 217     jcc_limm_start:
 218         jgt @jcc_limm_target
 219     jcc_limm_end:
 220
 221     ; jcc u6
 222     .set jcc_u6_target, @u6_value
 223     .set jcc_u6_has_delay_slot,   0
 224     .set jcc_u6_cc, 0xA
 225     jcc_u6_start:
 226         jge @jcc_u6_target
 227     jcc_u6_end:
 228
 229     ; jcc.d [c]
 230     .set jcc_d_c_target, @r4_value
 231     .set jcc_d_c_has_delay_slot,   1
 232     .set jcc_d_c_cc, 0xB
 233     jcc_d_c_start:
 234         jlt.d [r4]
 235     jcc_d_c_end:
 236         nop_s
 237
 238     ; jcc.d [blink]
 239     .set jcc_d_blink_target, @blink_value
 240     .set jcc_d_blink_has_delay_slot,   1
 241     .set jcc_d_blink_cc, 0xC
 242     jcc_d_blink_start:
 243         jle.d [blink]
 244     jcc_d_blink_end:
 245         nop_s
 246
 247     ; jcc.d u6
 248     .set jcc_d_u6_target, @u6_value
 249     .set jcc_d_u6_has_delay_slot,   1
 250     .set jcc_d_u6_cc, 0xE
 251     jcc_d_u6_start:
 252         jls.d @jcc_d_u6_target
 253     jcc_d_u6_end:
 254         nop_s
 255
 256     ; jeq_s [blink]
 257     .set jcc_eq_s_blink_target, @blink_value
 258     .set jcc_eq_s_blink_has_delay_slot,   0
 259     .set jcc_eq_s_blink_cc, 1
 260     jcc_eq_s_blink_start:
 261         jeq_s [blink]
 262     jcc_eq_s_blink_end:
 263
 264     ; jne_s [blink]
 265     .set jcc_ne_s_blink_target, @blink_value
 266     .set jcc_ne_s_blink_has_delay_slot,   0
 267     .set jcc_ne_s_blink_cc, 2
 268     jcc_ne_s_blink_start:
 269         jne_s [blink]
 270     jcc_ne_s_blink_end:
 271 #endif /* TEST_JCC */
 272
 273 #ifdef TEST_JL
 274     ; jl [c]
 275     .set jl_c_target, @r4_value
 276     .set jl_c_has_delay_slot,   0
 277     .set jl_c_cc, 0
 278     jl_c_start:
 279         jl [r4]
 280     jl_c_end:
 281
 282     ; jl limm
 283     .set jl_limm_target, @limm_value
 284     .set jl_limm_has_delay_slot,   0
 285     .set jl_limm_cc, 0
 286     jl_limm_start:
 287         jl @jl_limm_target
 288     jl_limm_end:
 289
 290     ; jl u6
 291     .set jl_u6_target, @u6_value
 292     .set jl_u6_has_delay_slot,   0
 293     .set jl_u6_cc, 0
 294     jl_u6_start:
 295         jl @jl_u6_target
 296     jl_u6_end:
 297
 298     ; jl s12
 299     .set jl_s12_target, @s12_target
 300     .set jl_s12_has_delay_slot,   0
 301     .set jl_s12_cc, 0
 302     jl_s12_start:
 303         jl @jl_s12_target
 304     jl_s12_end:
 305
 306     ; jl.d [c]
 307     .set jl_d_c_target, @r4_value
 308     .set jl_d_c_has_delay_slot,   1
 309     .set jl_d_c_cc, 0
 310     jl_d_c_start:
 311         jl.d [r4]
 312     jl_d_c_end:
 313         nop_s
 314
 315     ; jl.d u6
 316     .set jl_d_u6_target, @u6_value
 317     .set jl_d_u6_has_delay_slot,   1
 318     .set jl_d_u6_cc, 0
 319     jl_d_u6_start:
 320         jl.d @jl_d_u6_target
 321     jl_d_u6_end:
 322         nop_s
 323
 324     ; jl.d s12
 325     .set jl_d_s12_target, @s12_target
 326     .set jl_d_s12_has_delay_slot,   1
 327     .set jl_d_s12_cc, 0
 328     jl_d_s12_start:
 329         jl.d @jl_d_s12_target
 330     jl_d_s12_end:
 331         nop_s
 332
 333     ; jl_s [b]
 334     .set jl_s_b_target, @r12_value
 335     .set jl_s_b_has_delay_slot,   0
 336     .set jl_s_b_cc, 0
 337     jl_s_b_start:
 338         jl_s [r12]
 339     jl_s_b_end:
 340
 341     ; jl_s.d [b]
 342     .set jl_s_d_b_target, @r12_value
 343     .set jl_s_d_b_has_delay_slot,   1
 344     .set jl_s_d_b_cc, 0
 345     jl_s_d_b_start:
 346         jl_s.d [r12]
 347     jl_s_d_b_end:
 348         nop_s
 349 #endif /* TEST_JL */
 350
 351 #ifdef TEST_JLCC
 352     ; jlcc [c]
 353     .set jlcc_c_target, @r4_value
 354     .set jlcc_c_has_delay_slot,   0
 355     .set jlcc_c_cc, 1
 356     jlcc_c_start:
 357         jleq [r4]
 358     jlcc_c_end:
 359
 360     ; jlcc limm
 361     .set jlcc_limm_target, @limm_value
 362     .set jlcc_limm_has_delay_slot,   0
 363     .set jlcc_limm_cc, 0x9
 364     jlcc_limm_start:
 365         jlgt @jlcc_limm_target
 366     jlcc_limm_end:
 367
 368     ; jlcc u6
 369     .set jlcc_u6_target, @u6_value
 370     .set jlcc_u6_has_delay_slot,   0
 371     .set jlcc_u6_cc, 0xA
 372     jlcc_u6_start:
 373         jlge @jlcc_u6_target
 374     jlcc_u6_end:
 375
 376     ; jlcc.d [c]
 377     .set jlcc_d_c_target, @r4_value
 378     .set jlcc_d_c_has_delay_slot,   1
 379     .set jlcc_d_c_cc, 0xB
 380     jlcc_d_c_start:
 381         jllt.d [r4]
 382     jlcc_d_c_end:
 383         nop_s
 384
 385     ; jlcc.d u6
 386     .set jlcc_d_u6_target, @u6_value
 387     .set jlcc_d_u6_has_delay_slot,   1
 388     .set jlcc_d_u6_cc, 0xE
 389     jlcc_d_u6_start:
 390         jlls.d @jlcc_d_u6_target
 391     jlcc_d_u6_end:
 392         nop_s
 393 #endif /* TEST_JLCC */
 394
 395 #ifdef TEST_B
 396 .Lb_target:
 397     ; Artifical nop, so that first b will not branch to itself.
 398     nop_s
 399     ; b s25
 400     .set b_s25_target, @.Lb_target
 401     .set b_s25_has_delay_slot,   0
 402     .set b_s25_cc, 0
 403     b_s25_start:
 404         b @b_s25_target
 405     b_s25_end:
 406
 407     ; b.d s25
 408     .set b_d_s25_target, @.Lb_target
 409     .set b_d_s25_has_delay_slot,   1
 410     .set b_d_s25_cc, 0
 411     b_d_s25_start:
 412         b.d @b_d_s25_target
 413     b_d_s25_end:
 414         nop_s
 415
 416     ; b_s s10
 417     .set b_s_s10_target, @.Lb_target
 418     .set b_s_s10_has_delay_slot,   0
 419     .set b_s_s10_cc, 0
 420     b_s_s10_start:
 421         b_s @b_s_s10_target
 422     b_s_s10_end:
 423 #endif /* TEST_B */
 424
 425 #ifdef TEST_BBIT
 426
 427 ; Due to specifics of bbit implementation in assembler, only local symbols can
 428 ; be used as a branch targets for bbit and brcc.
 429 ; bbits and brcc don't have condition code set to anything.
 430 .Lbbit_target:
 431     nop_s
 432
 433     ; bbit0.nt b,c,s9
 434     .set bbit0_nt_b_c_s9_target, @.Lbbit_target
 435     .set bbit0_nt_b_c_s9_has_delay_slot,   0
 436     .set bbit0_nt_b_c_s9_cc, 0
 437     bbit0_nt_b_c_s9_start:
 438         bbit0.nt r4,r5,@bbit0_nt_b_c_s9_target
 439     bbit0_nt_b_c_s9_end:
 440
 441     ; bbit0.d.nt b,c,s9
 442     .set bbit0_d_nt_b_c_s9_target, @.Lbbit_target
 443     .set bbit0_d_nt_b_c_s9_has_delay_slot,   1
 444     .set bbit0_d_nt_b_c_s9_cc, 0
 445     bbit0_d_nt_b_c_s9_start:
 446         bbit0.d.nt r4,r5,@.Lbbit_target
 447     bbit0_d_nt_b_c_s9_end:
 448         nop_s
 449
 450     ; bbit0.t b,c,s9
 451     .set bbit0_t_b_c_s9_target, @.Lbbit_target
 452     .set bbit0_t_b_c_s9_has_delay_slot,   0
 453     .set bbit0_t_b_c_s9_cc, 0
 454     bbit0_t_b_c_s9_start:
 455         bbit0.t r4,r5,@.Lbbit_target
 456     bbit0_t_b_c_s9_end:
 457
 458     ; bbit0.d.t b,c,s9
 459     .set bbit0_d_t_b_c_s9_target, @.Lbbit_target
 460     .set bbit0_d_t_b_c_s9_has_delay_slot,   1
 461     .set bbit0_d_t_b_c_s9_cc, 0
 462     bbit0_d_t_b_c_s9_start:
 463         bbit0.d.t r4,r5,@.Lbbit_target
 464     bbit0_d_t_b_c_s9_end:
 465         nop_s
 466
 467     ; bbit0.nt b,u6,s9
 468     .set bbit0_nt_b_u6_s9_target, @.Lbbit_target
 469     .set bbit0_nt_b_u6_s9_has_delay_slot,   0
 470     .set bbit0_nt_b_u6_s9_cc, 0
 471     bbit0_nt_b_u6_s9_start:
 472         bbit0.nt r4,u6_value,@.Lbbit_target
 473     bbit0_nt_b_u6_s9_end:
 474
 475     ; bbit0.d.nt b,u6,s9
 476     .set bbit0_d_nt_b_u6_s9_target, @.Lbbit_target
 477     .set bbit0_d_nt_b_u6_s9_has_delay_slot,   1
 478     .set bbit0_d_nt_b_u6_s9_cc, 0
 479     bbit0_d_nt_b_u6_s9_start:
 480         bbit0.d.nt r4,u6_value,@.Lbbit_target
 481     bbit0_d_nt_b_u6_s9_end:
 482         nop_s
 483
 484     ; bbit0.nt b,u6,s9
 485     .set bbit0_t_b_u6_s9_target, @.Lbbit_target
 486     .set bbit0_t_b_u6_s9_has_delay_slot,   0
 487     .set bbit0_t_b_u6_s9_cc, 0
 488     bbit0_t_b_u6_s9_start:
 489         bbit0.t r4,u6_value,@.Lbbit_target
 490     bbit0_t_b_u6_s9_end:
 491
 492     ; bbit0.d.nt b,u6,s9
 493     .set bbit0_d_t_b_u6_s9_target, @.Lbbit_target
 494     .set bbit0_d_t_b_u6_s9_has_delay_slot,   1
 495     .set bbit0_d_t_b_u6_s9_cc, 0
 496     bbit0_d_t_b_u6_s9_start:
 497         bbit0.d.t r4,u6_value,@.Lbbit_target
 498     bbit0_d_t_b_u6_s9_end:
 499         nop_s
 500
 501     ; bbit0.nt b,limm,s9
 502     .set bbit0_nt_b_limm_s9_target, @.Lbbit_target
 503     .set bbit0_nt_b_limm_s9_has_delay_slot,   0
 504     .set bbit0_nt_b_limm_s9_cc, 0
 505     bbit0_nt_b_limm_s9_start:
 506         bbit0.nt r4,limm_value,@.Lbbit_target
 507     bbit0_nt_b_limm_s9_end:
 508
 509     ; bbit0.t b,limm,s9
 510     .set bbit0_t_b_limm_s9_target, @.Lbbit_target
 511     .set bbit0_t_b_limm_s9_has_delay_slot,   0
 512     .set bbit0_t_b_limm_s9_cc, 0
 513     bbit0_t_b_limm_s9_start:
 514         bbit0.t r4,limm_value,@.Lbbit_target
 515     bbit0_t_b_limm_s9_end:
 516
 517     ; bbit0.nt limm,c,s9
 518     .set bbit0_nt_limm_c_s9_target, @.Lbbit_target
 519     .set bbit0_nt_limm_c_s9_has_delay_slot,   0
 520     .set bbit0_nt_limm_c_s9_cc, 0
 521     bbit0_nt_limm_c_s9_start:
 522         bbit0.nt limm_value,r4,@.Lbbit_target
 523     bbit0_nt_limm_c_s9_end:
 524
 525     ; bbit0.t limm,c,s9
 526     .set bbit0_t_limm_c_s9_target, @.Lbbit_target
 527     .set bbit0_t_limm_c_s9_has_delay_slot,   0
 528     .set bbit0_t_limm_c_s9_cc, 0
 529     bbit0_t_limm_c_s9_start:
 530         bbit0.t limm_value,r4,@.Lbbit_target
 531     bbit0_t_limm_c_s9_end:
 532
 533     ; bbit0.nt limm,u6,s9
 534     .set bbit0_nt_limm_u6_s9_target, @.Lbbit_target
 535     .set bbit0_nt_limm_u6_s9_has_delay_slot,   0
 536     .set bbit0_nt_limm_u6_s9_cc, 0
 537     bbit0_nt_limm_u6_s9_start:
 538         bbit0.nt limm_value,u6_value,@.Lbbit_target
 539     bbit0_nt_limm_u6_s9_end:
 540
 541     ; bbit0.t limm,u6,s9
 542     .set bbit0_t_limm_u6_s9_target, @.Lbbit_target
 543     .set bbit0_t_limm_u6_s9_has_delay_slot,   0
 544     .set bbit0_t_limm_u6_s9_cc, 0
 545     bbit0_t_limm_u6_s9_start:
 546         bbit0.t limm_value,u6_value,@.Lbbit_target
 547     bbit0_t_limm_u6_s9_end:
 548
 549     ; bbit1.nt b,c,s9
 550     .set bbit1_nt_b_c_s9_target, @.Lbbit_target
 551     .set bbit1_nt_b_c_s9_has_delay_slot,   0
 552     .set bbit1_nt_b_c_s9_cc, 0
 553     bbit1_nt_b_c_s9_start:
 554         bbit1.nt r4,r5,@.Lbbit_target
 555     bbit1_nt_b_c_s9_end:
 556
 557     ; bbit1.d.nt b,c,s9
 558     .set bbit1_d_nt_b_c_s9_target, @.Lbbit_target
 559     .set bbit1_d_nt_b_c_s9_has_delay_slot,   1
 560     .set bbit1_d_nt_b_c_s9_cc, 0
 561     bbit1_d_nt_b_c_s9_start:
 562         bbit1.d.nt r4,r5,@.Lbbit_target
 563     bbit1_d_nt_b_c_s9_end:
 564         nop_s
 565
 566     ; bbit1.t b,c,s9
 567     .set bbit1_t_b_c_s9_target, @.Lbbit_target
 568     .set bbit1_t_b_c_s9_has_delay_slot,   0
 569     .set bbit1_t_b_c_s9_cc, 0
 570     bbit1_t_b_c_s9_start:
 571         bbit1.t r4,r5,@.Lbbit_target
 572     bbit1_t_b_c_s9_end:
 573
 574     ; bbit1.d.t b,c,s9
 575     .set bbit1_d_t_b_c_s9_target, @.Lbbit_target
 576     .set bbit1_d_t_b_c_s9_has_delay_slot,   1
 577     .set bbit1_d_t_b_c_s9_cc, 0
 578     bbit1_d_t_b_c_s9_start:
 579         bbit1.d.t r4,r5,@.Lbbit_target
 580     bbit1_d_t_b_c_s9_end:
 581         nop_s
 582
 583     ; bbit1.nt b,u6,s9
 584     .set bbit1_nt_b_u6_s9_target, @.Lbbit_target
 585     .set bbit1_nt_b_u6_s9_has_delay_slot,   0
 586     .set bbit1_nt_b_u6_s9_cc, 0
 587     bbit1_nt_b_u6_s9_start:
 588         bbit1.nt r4,u6_value,@.Lbbit_target
 589     bbit1_nt_b_u6_s9_end:
 590
 591     ; bbit1.d.nt b,u6,s9
 592     .set bbit1_d_nt_b_u6_s9_target, @.Lbbit_target
 593     .set bbit1_d_nt_b_u6_s9_has_delay_slot,   1
 594     .set bbit1_d_nt_b_u6_s9_cc, 0
 595     bbit1_d_nt_b_u6_s9_start:
 596         bbit1.d.nt r4,u6_value,@.Lbbit_target
 597     bbit1_d_nt_b_u6_s9_end:
 598         nop_s
 599
 600     ; bbit1.nt b,u6,s9
 601     .set bbit1_t_b_u6_s9_target, @.Lbbit_target
 602     .set bbit1_t_b_u6_s9_has_delay_slot,   0
 603     .set bbit1_t_b_u6_s9_cc, 0
 604     bbit1_t_b_u6_s9_start:
 605         bbit1.t r4,u6_value,@.Lbbit_target
 606     bbit1_t_b_u6_s9_end:
 607
 608     ; bbit1.d.nt b,u6,s9
 609     .set bbit1_d_t_b_u6_s9_target, @.Lbbit_target
 610     .set bbit1_d_t_b_u6_s9_has_delay_slot,   1
 611     .set bbit1_d_t_b_u6_s9_cc, 0
 612     bbit1_d_t_b_u6_s9_start:
 613         bbit1.d.t r4,u6_value,@.Lbbit_target
 614     bbit1_d_t_b_u6_s9_end:
 615         nop_s
 616
 617     ; bbit1.nt b,limm,s9
 618     .set bbit1_nt_b_limm_s9_target, @.Lbbit_target
 619     .set bbit1_nt_b_limm_s9_has_delay_slot,   0
 620     .set bbit1_nt_b_limm_s9_cc, 0
 621     bbit1_nt_b_limm_s9_start:
 622         bbit1.nt r4,limm_value,@.Lbbit_target
 623     bbit1_nt_b_limm_s9_end:
 624
 625     ; bbit1.t b,limm,s9
 626     .set bbit1_t_b_limm_s9_target, @.Lbbit_target
 627     .set bbit1_t_b_limm_s9_has_delay_slot,   0
 628     .set bbit1_t_b_limm_s9_cc, 0
 629     bbit1_t_b_limm_s9_start:
 630         bbit1.t r4,limm_value,@.Lbbit_target
 631     bbit1_t_b_limm_s9_end:
 632
 633     ; bbit1.nt limm,c,s9
 634     .set bbit1_nt_limm_c_s9_target, @.Lbbit_target
 635     .set bbit1_nt_limm_c_s9_has_delay_slot,   0
 636     .set bbit1_nt_limm_c_s9_cc, 0
 637     bbit1_nt_limm_c_s9_start:
 638         bbit1.nt limm_value,r4,@.Lbbit_target
 639     bbit1_nt_limm_c_s9_end:
 640
 641     ; bbit1.t limm,c,s9
 642     .set bbit1_t_limm_c_s9_target, @.Lbbit_target
 643     .set bbit1_t_limm_c_s9_has_delay_slot,   0
 644     .set bbit1_t_limm_c_s9_cc, 0
 645     bbit1_t_limm_c_s9_start:
 646         bbit1.t limm_value,r4,@.Lbbit_target
 647     bbit1_t_limm_c_s9_end:
 648
 649     ; bbit1.nt limm,u6,s9
 650     .set bbit1_nt_limm_u6_s9_target, @.Lbbit_target
 651     .set bbit1_nt_limm_u6_s9_has_delay_slot,   0
 652     .set bbit1_nt_limm_u6_s9_cc, 0
 653     bbit1_nt_limm_u6_s9_start:
 654         bbit1.nt limm_value,u6_value,@.Lbbit_target
 655     bbit1_nt_limm_u6_s9_end:
 656
 657     ; bbit1.t limm,u6,s9
 658     .set bbit1_t_limm_u6_s9_target, @.Lbbit_target
 659     .set bbit1_t_limm_u6_s9_has_delay_slot,   0
 660     .set bbit1_t_limm_u6_s9_cc, 0
 661     bbit1_t_limm_u6_s9_start:
 662         bbit1.t limm_value,u6_value,@.Lbbit_target
 663     bbit1_t_limm_u6_s9_end:
 664 #endif /* TEST_BBIT */
 665
 666 #ifdef TEST_BCC
 667 .Lbcc_target:
 668     ; bcc s21
 669     .set bcc_s21_target, @.Lbcc_target
 670     .set bcc_s21_has_delay_slot,   0
 671     .set bcc_s21_cc, 1
 672     bcc_s21_start:
 673         ; beq @bcc_s21_target
 674         beq @.Lbcc_target
 675     bcc_s21_end:
 676
 677     ; bcc.d s21
 678     .set bcc_d_s21_target, @.Lbcc_target
 679     .set bcc_d_s21_has_delay_slot,   1
 680     .set bcc_d_s21_cc, 1
 681     bcc_d_s21_start:
 682         beq.d @bcc_d_s21_target
 683     bcc_d_s21_end:
 684         nop_s
 685
 686 .Lbcc_s_target:
 687     ; beq_s s10
 688     .set beq_s_s10_target, @.Lbcc_s_target
 689     .set beq_s_s10_has_delay_slot,   0
 690     .set beq_s_s10_cc, 1
 691     beq_s_s10_start:
 692         # beq_s.d @beq_s_s10_target
 693         beq_s @.Lbcc_s_target
 694     beq_s_s10_end:
 695
 696     ; bne_s s10
 697     .set bne_s_s10_target, @.Lbcc_s_target
 698     .set bne_s_s10_has_delay_slot,   0
 699     .set bne_s_s10_cc, 2
 700     bne_s_s10_start:
 701         bne_s @bne_s_s10_target
 702     bne_s_s10_end:
 703
 704     ; bgt_s s7
 705     .set bgt_s_s7_target, @.Lbcc_s_target
 706     .set bgt_s_s7_has_delay_slot,   0
 707     .set bgt_s_s7_cc, 0x9
 708     bgt_s_s7_start:
 709         bgt_s @bgt_s_s7_target
 710     bgt_s_s7_end:
 711
 712     ; bge_s s7
 713     .set bge_s_s7_target, @.Lbcc_s_target
 714     .set bge_s_s7_has_delay_slot,   0
 715     .set bge_s_s7_cc, 0xA
 716     bge_s_s7_start:
 717         bge_s @bge_s_s7_target
 718     bge_s_s7_end:
 719
 720     ; blt_s s7
 721     .set blt_s_s7_target, @.Lbcc_s_target
 722     .set blt_s_s7_has_delay_slot,   0
 723     .set blt_s_s7_cc, 0xB
 724     blt_s_s7_start:
 725         blt_s @blt_s_s7_target
 726     blt_s_s7_end:
 727
 728     ; ble_s s7
 729     .set ble_s_s7_target, @.Lbcc_s_target
 730     .set ble_s_s7_has_delay_slot,   0
 731     .set ble_s_s7_cc, 0xC
 732     ble_s_s7_start:
 733         ble_s @ble_s_s7_target
 734     ble_s_s7_end:
 735
 736     ; bhi_s s7
 737     .set bhi_s_s7_target, @.Lbcc_s_target
 738     .set bhi_s_s7_has_delay_slot,   0
 739     .set bhi_s_s7_cc, 0xD
 740     bhi_s_s7_start:
 741         bhi_s @bhi_s_s7_target
 742     bhi_s_s7_end:
 743
 744     ; bhs_s s7
 745     .set bhs_s_s7_target, @.Lbcc_s_target
 746     .set bhs_s_s7_has_delay_slot,   0
 747     .set bhs_s_s7_cc, 0x6
 748     bhs_s_s7_start:
 749         bhs_s @bhs_s_s7_target
 750     bhs_s_s7_end:
 751
 752     ; blo_s s7
 753     .set blo_s_s7_target, @.Lbcc_s_target
 754     .set blo_s_s7_has_delay_slot,   0
 755     .set blo_s_s7_cc, 0x5
 756     blo_s_s7_start:
 757         blo_s @blo_s_s7_target
 758     blo_s_s7_end:
 759
 760     ; bls_s s7
 761     .set bls_s_s7_target, @.Lbcc_s_target
 762     .set bls_s_s7_has_delay_slot,   0
 763     .set bls_s_s7_cc, 0xE
 764     bls_s_s7_start:
 765         bls_s @bls_s_s7_target
 766     bls_s_s7_end:
 767 #endif /* TEST_BCC */
 768
 769 #ifdef TEST_BI
 770     ; bi [c]
 771     .set bi_c_target, @bi_c_end + (@r7_value << 2)
 772     .set bi_c_has_delay_slot,   0
 773     .set bi_c_cc, 0
 774     bi_c_start:
 775         bi [r7]
 776     bi_c_end:
 777
 778     ; bih [c]
 779     .set bih_c_target, @bih_c_end + (@r7_value << 1)
 780     .set bih_c_has_delay_slot,   0
 781     .set bih_c_cc, 0
 782     bih_c_start:
 783         bih [r7]
 784     bih_c_end:
 785 #endif /* TEST_BI */
 786
 787 #ifdef TEST_BL
 788 .Lbl_target:
 789     ; bl s25
 790     .set bl_s25_target, @.Lbl_target
 791     .set bl_s25_has_delay_slot,   0
 792     .set bl_s25_cc, 0
 793     bl_s25_start:
 794         bl @bl_s25_target
 795     bl_s25_end:
 796
 797     ; bl.d s25
 798     .set bl_d_s25_target, @.Lbl_target
 799     .set bl_d_s25_has_delay_slot,   1
 800     .set bl_d_s25_cc, 0
 801     bl_d_s25_start:
 802         bl.d @bl_d_s25_target
 803     bl_d_s25_end:
 804         nop_s
 805
 806     ; bl_s s13
 807     .set bl_s_s13_target, @.Lbl_target
 808     .set bl_s_s13_has_delay_slot,   0
 809     .set bl_s_s13_cc, 0
 810     bl_s_s13_start:
 811         bl_s @bl_s_s13_target
 812     bl_s_s13_end:
 813
 814     ; blcc s21
 815     .set blcc_s21_target, @.Lbl_target
 816     .set blcc_s21_has_delay_slot,   0
 817     .set blcc_s21_cc, 1
 818     blcc_s21_start:
 819         bleq @blcc_s21_target
 820     blcc_s21_end:
 821
 822     ; blcc.d s21
 823     .set blcc_d_s21_target, @.Lbl_target
 824     .set blcc_d_s21_has_delay_slot,   1
 825     .set blcc_d_s21_cc, 2
 826     blcc_d_s21_start:
 827         blnz.d @blcc_d_s21_target
 828     blcc_d_s21_end:
 829         nop_s
 830 #endif /* TEST_BL */
 831
 832 #ifdef TEST_BRCC
 833 .Lbrcc_target:
 834     ; breq.nt b,c,s9
 835     .set breq_nt_b_c_s9_target, @.Lbrcc_target
 836     .set breq_nt_b_c_s9_has_delay_slot,   0
 837     .set breq_nt_b_c_s9_cc, 1
 838     breq_nt_b_c_s9_start:
 839         breq.nt r4,r5,@.Lbrcc_target
 840     breq_nt_b_c_s9_end:
 841
 842     ; breq.d.nt b,c,s9
 843     .set breq_d_nt_b_c_s9_target, @.Lbrcc_target
 844     .set breq_d_nt_b_c_s9_has_delay_slot,   1
 845     .set breq_d_nt_b_c_s9_cc, 1
 846     breq_d_nt_b_c_s9_start:
 847         breq.d.nt r4,r5,@.Lbrcc_target
 848     breq_d_nt_b_c_s9_end:
 849         nop_s
 850
 851     ; breq.t b,c,s9
 852     .set breq_t_b_c_s9_target, @.Lbrcc_target
 853     .set breq_t_b_c_s9_has_delay_slot,   0
 854     .set breq_t_b_c_s9_cc, 1
 855     breq_t_b_c_s9_start:
 856         breq.t r4,r5,@.Lbrcc_target
 857     breq_t_b_c_s9_end:
 858
 859     ; breq.d.t b,c,s9
 860     .set breq_d_t_b_c_s9_target, @.Lbrcc_target
 861     .set breq_d_t_b_c_s9_has_delay_slot,   1
 862     .set breq_d_t_b_c_s9_cc, 1
 863     breq_d_t_b_c_s9_start:
 864         breq.d.t r4,r5,@.Lbrcc_target
 865     breq_d_t_b_c_s9_end:
 866         nop_s
 867
 868     ; breq.nt b,u6,s9
 869     .set breq_nt_b_u6_s9_target, @.Lbrcc_target
 870     .set breq_nt_b_u6_s9_has_delay_slot,   0
 871     .set breq_nt_b_u6_s9_cc, 1
 872     breq_nt_b_u6_s9_start:
 873         breq.nt r4,u6_value,@.Lbrcc_target
 874     breq_nt_b_u6_s9_end:
 875
 876     ; breq.d.nt b,u6,s9
 877     .set breq_d_nt_b_u6_s9_target, @.Lbrcc_target
 878     .set breq_d_nt_b_u6_s9_has_delay_slot,   1
 879     .set breq_d_nt_b_u6_s9_cc, 1
 880     breq_d_nt_b_u6_s9_start:
 881         breq.d.nt r4,u6_value,@.Lbrcc_target
 882     breq_d_nt_b_u6_s9_end:
 883         nop_s
 884
 885     ; breq.nt b,u6,s9
 886     .set breq_t_b_u6_s9_target, @.Lbrcc_target
 887     .set breq_t_b_u6_s9_has_delay_slot,   0
 888     .set breq_t_b_u6_s9_cc, 1
 889     breq_t_b_u6_s9_start:
 890         breq.t r4,u6_value,@.Lbrcc_target
 891     breq_t_b_u6_s9_end:
 892
 893     ; breq.d.nt b,u6,s9
 894     .set breq_d_t_b_u6_s9_target, @.Lbrcc_target
 895     .set breq_d_t_b_u6_s9_has_delay_slot,   1
 896     .set breq_d_t_b_u6_s9_cc, 1
 897     breq_d_t_b_u6_s9_start:
 898         breq.d.t r4,u6_value,@.Lbrcc_target
 899     breq_d_t_b_u6_s9_end:
 900         nop_s
 901
 902     ; breq.nt b,limm,s9
 903     .set breq_nt_b_limm_s9_target, @.Lbrcc_target
 904     .set breq_nt_b_limm_s9_has_delay_slot,   0
 905     .set breq_nt_b_limm_s9_cc, 1
 906     breq_nt_b_limm_s9_start:
 907         breq.nt r4,limm_value,@.Lbrcc_target
 908     breq_nt_b_limm_s9_end:
 909
 910     ; breq.t b,limm,s9
 911     .set breq_t_b_limm_s9_target, @.Lbrcc_target
 912     .set breq_t_b_limm_s9_has_delay_slot,   0
 913     .set breq_t_b_limm_s9_cc, 1
 914     breq_t_b_limm_s9_start:
 915         breq.t r4,limm_value,@.Lbrcc_target
 916     breq_t_b_limm_s9_end:
 917
 918     ; breq.nt limm,c,s9
 919     .set breq_nt_limm_c_s9_target, @.Lbrcc_target
 920     .set breq_nt_limm_c_s9_has_delay_slot,   0
 921     .set breq_nt_limm_c_s9_cc, 1
 922     breq_nt_limm_c_s9_start:
 923         breq.nt limm_value,r4,@.Lbrcc_target
 924     breq_nt_limm_c_s9_end:
 925
 926     ; breq.t limm,c,s9
 927     .set breq_t_limm_c_s9_target, @.Lbrcc_target
 928     .set breq_t_limm_c_s9_has_delay_slot,   0
 929     .set breq_t_limm_c_s9_cc, 1
 930     breq_t_limm_c_s9_start:
 931         breq.t limm_value,r4,@.Lbrcc_target
 932     breq_t_limm_c_s9_end:
 933
 934     ; breq.nt limm,u6,s9
 935     .set breq_nt_limm_u6_s9_target, @.Lbrcc_target
 936     .set breq_nt_limm_u6_s9_has_delay_slot,   0
 937     .set breq_nt_limm_u6_s9_cc, 1
 938     breq_nt_limm_u6_s9_start:
 939         breq.nt limm_value,u6_value,@.Lbrcc_target
 940     breq_nt_limm_u6_s9_end:
 941
 942     ; breq.t limm,u6,s9
 943     .set breq_t_limm_u6_s9_target, @.Lbrcc_target
 944     .set breq_t_limm_u6_s9_has_delay_slot,   0
 945     .set breq_t_limm_u6_s9_cc, 1
 946     breq_t_limm_u6_s9_start:
 947         breq.t limm_value,u6_value,@.Lbrcc_target
 948     breq_t_limm_u6_s9_end:
 949
 950     ; brne_s b,0,s8
 951     .set brne_s_b_0_s8_target, @.Lbrcc_target
 952     .set brne_s_b_0_s8_has_delay_slot,   0
 953     .set brne_s_b_0_s8_cc, 1
 954     brne_s_b_0_s8_start:
 955         brne r12,0,@.Lbrcc_target
 956     brne_s_b_0_s8_end:
 957
 958     ; breq_s b,0,s8
 959     .set breq_s_b_0_s8_target, @.Lbrcc_target
 960     .set breq_s_b_0_s8_has_delay_slot,   0
 961     .set breq_s_b_0_s8_cc, 1
 962     breq_s_b_0_s8_start:
 963         breq r12,0,@.Lbrcc_target
 964     breq_s_b_0_s8_end:
 965 #endif /* TEST_BRCC */
 966
 967 #ifdef TEST_JLI
 968     ; jli_s u10
 969     .set jli_s_u10_target, @jli_target
 970     .set jli_s_u10_has_delay_slot,   0
 971     .set jli_s_u10_cc, 0
 972     jli_s_u10_start:
 973         jli_s jli_offset
 974     jli_s_u10_end:
 975 #endif
 976
 977 #ifdef TEST_LEAVE_S
 978     ; leave_s
 979     .set leave_s_target, @blink_value
 980     .set leave_s_has_delay_slot,   0
 981     .set leave_s_cc, 0
 982     leave_s_start:
 983         ; leave_s [r13-gp,fp,blink,pcl]
 984         leave_s (14 + 16 + 32 + 64)
 985     leave_s_end:
 986 #endif
 987
 988 #ifdef TEST_LPCC
 989     ; lpcc
 990     .set lpcc_u7_target, @.Llpcc_end
 991     .set lpcc_u7_has_delay_slot,   0
 992     .set lpcc_u7_cc, 1
 993     lpcc_u7_start:
 994         lpeq @lpcc_u7_target
 995     lpcc_u7_end:
 996         nop
 997         nop
 998 .Llpcc_end:
 999 #endif
1000
1001 .Lend:
1002
1003         .section        .note.GNU-stack,"",@progbits