include/opcode/ChangeLog

   1 2010-07-29  DJ Delorie  <dj@redhat.com>
   2
   3         * rx.h (RX_Operand_Type): Add TwoReg.
   4         (RX_Opcode_ID): Remove ediv and ediv2.
   5
   6 2010-07-27  DJ Delorie  <dj@redhat.com>
   7
   8         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
   9
  10 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
  11             Ina Pandit  <ina.pandit@kpitcummins.com>
  12
  13         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
  14         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
  15         PROCESSOR_V850E2_ALL.
  16         Remove PROCESSOR_V850EA support.
  17         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
  18         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
  19         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
  20         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
  21         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
  22         V850_OPERAND_PERCENT.
  23         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
  24         V850_NOT_R0.
  25         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
  26         and V850E_PUSH_POP
  27
  28 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
  29
  30         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
  31         (MIPS16_INSN_BRANCH): Rename to...
  32         (MIPS16_INSN_COND_BRANCH): ... this.
  33
  34 2010-07-03  Alan Modra  <amodra@gmail.com>
  35
  36         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
  37         Renumber other PPC_OPCODE defines.
  38
  39 2010-07-03  Alan Modra  <amodra@gmail.com>
  40
  41         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
  42
  43 2010-06-29  Alan Modra  <amodra@gmail.com>
  44
  45         * maxq.h: Delete file.
  46
  47 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
  48
  49         * ppc.h (PPC_OPCODE_E500): Define.
  50
  51 2010-05-26  Catherine Moore  <clm@codesourcery.com>
  52
  53         * opcode/mips.h (INSN_MIPS16): Remove.
  54
  55 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
  56
  57         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
  58
  59 2010-04-15  Nick Clifton  <nickc@redhat.com>
  60
  61         * alpha.h: Update copyright notice to use GPLv3.
  62         * arc.h: Likewise.
  63         * arm.h: Likewise.
  64         * avr.h: Likewise.
  65         * bfin.h: Likewise.
  66         * cgen.h: Likewise.
  67         * convex.h: Likewise.
  68         * cr16.h: Likewise.
  69         * cris.h: Likewise.
  70         * crx.h: Likewise.
  71         * d10v.h: Likewise.
  72         * d30v.h: Likewise.
  73         * dlx.h: Likewise.
  74         * h8300.h: Likewise.
  75         * hppa.h: Likewise.
  76         * i370.h: Likewise.
  77         * i386.h: Likewise.
  78         * i860.h: Likewise.
  79         * i960.h: Likewise.
  80         * ia64.h: Likewise.
  81         * m68hc11.h: Likewise.
  82         * m68k.h: Likewise.
  83         * m88k.h: Likewise.
  84         * maxq.h: Likewise.
  85         * mips.h: Likewise.
  86         * mmix.h: Likewise.
  87         * mn10200.h: Likewise.
  88         * mn10300.h: Likewise.
  89         * msp430.h: Likewise.
  90         * np1.h: Likewise.
  91         * ns32k.h: Likewise.
  92         * or32.h: Likewise.
  93         * pdp11.h: Likewise.
  94         * pj.h: Likewise.
  95         * pn.h: Likewise.
  96         * ppc.h: Likewise.
  97         * pyr.h: Likewise.
  98         * rx.h: Likewise.
  99         * s390.h: Likewise.
 100         * score-datadep.h: Likewise.
 101         * score-inst.h: Likewise.
 102         * sparc.h: Likewise.
 103         * spu-insns.h: Likewise.
 104         * spu.h: Likewise.
 105         * tic30.h: Likewise.
 106         * tic4x.h: Likewise.
 107         * tic54x.h: Likewise.
 108         * tic80.h: Likewise.
 109         * v850.h: Likewise.
 110         * vax.h: Likewise.
 111
 112 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 113
 114         * tic6x-control-registers.h, tic6x-insn-formats.h,
 115         tic6x-opcode-table.h, tic6x.h: New.
 116
 117 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 118
 119         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 120
 121 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 122
 123         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 124
 125 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 126
 127         * ia64.h (ia64_find_opcode): Remove argument name.
 128         (ia64_find_next_opcode): Likewise.
 129         (ia64_dis_opcode): Likewise.
 130         (ia64_free_opcode): Likewise.
 131         (ia64_find_dependency): Likewise.
 132
 133 2009-11-22  Doug Evans  <dje@sebabeach.org>
 134
 135         * cgen.h: Include bfd_stdint.h.
 136         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 137
 138 2009-11-18  Paul Brook  <paul@codesourcery.com>
 139
 140         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 141
 142 2009-11-17  Paul Brook  <paul@codesourcery.com>
 143         Daniel Jacobowitz  <dan@codesourcery.com>
 144
 145         * arm.h (ARM_EXT_V6_DSP): Define.
 146         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 147         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 148
 149 2009-11-04  DJ Delorie  <dj@redhat.com>
 150
 151         * rx.h (rx_decode_opcode) (mvtipl): Add.
 152         (mvtcp, mvfcp, opecp): Remove.
 153
 154 2009-11-02  Paul Brook  <paul@codesourcery.com>
 155
 156         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 157         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 158         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 159         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 160         FPU_ARCH_NEON_VFP_V4): Define.
 161
 162 2009-10-23  Doug Evans  <dje@sebabeach.org>
 163
 164         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 165         * cgen.h: Update.  Improve multi-inclusion macro name.
 166
 167 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 168
 169         * ppc.h (PPC_OPCODE_476): Define.
 170
 171 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 172
 173         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 174
 175 2009-09-29  DJ Delorie  <dj@redhat.com>
 176
 177         * rx.h: New file.
 178
 179 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 180
 181         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 182
 183 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 184
 185         * ppc.h (PPC_OPCODE_PPCA2): New.
 186
 187 2009-09-05  Martin Thuresson  <martin@mtme.org>
 188
 189         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 190
 191 2009-08-29  Martin Thuresson  <martin@mtme.org>
 192
 193         * tic30.h (template): Rename type template to
 194         insn_template. Updated code to use new name.
 195         * tic54x.h (template): Rename type template to
 196         insn_template.
 197
 198 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 199
 200         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 201
 202 2009-06-11  Anthony Green  <green@moxielogic.com>
 203
 204         * moxie.h (MOXIE_F3_PCREL): Define.
 205         (moxie_form3_opc_info): Grow.
 206
 207 2009-06-06  Anthony Green  <green@moxielogic.com>
 208
 209         * moxie.h (MOXIE_F1_M): Define.
 210
 211 2009-04-15  Anthony Green  <green@moxielogic.com>
 212
 213         * moxie.h: Created.
 214
 215 2009-04-06  DJ Delorie  <dj@redhat.com>
 216
 217         * h8300.h: Add relaxation attributes to MOVA opcodes.
 218
 219 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 220
 221         * ppc.h (ppc_parse_cpu): Declare.
 222
 223 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 224
 225         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 226         and _IMM11 for mbitclr and mbitset.
 227         * score-datadep.h: Update dependency information.
 228
 229 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 230
 231         * ppc.h (PPC_OPCODE_POWER7): New.
 232
 233 2009-02-06  Doug Evans  <dje@google.com>
 234
 235         * i386.h: Add comment regarding sse* insns and prefixes.
 236
 237 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 238
 239         * mips.h (INSN_XLR): Define.
 240         (INSN_CHIP_MASK): Update.
 241         (CPU_XLR): Define.
 242         (OPCODE_IS_MEMBER): Update.
 243         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 244
 245 2009-01-28  Doug Evans  <dje@google.com>
 246
 247         * opcode/i386.h: Add multiple inclusion protection.
 248         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 249         (EDI_REG_NUM): New macros.
 250         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 251         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 252         (REX_PREFIX_P): New macro.
 253
 254 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 255
 256         * ppc.h (struct powerpc_opcode): New field "deprecated".
 257         (PPC_OPCODE_NOPOWER4): Delete.
 258
 259 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 260
 261         * mips.h: Define CPU_R14000, CPU_R16000.
 262         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 263
 264 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 265
 266         * arm.h (FPU_NEON_FP16): New.
 267         (FPU_ARCH_NEON_FP16): New.
 268
 269 2008-11-06  Chao-ying Fu  <fu@mips.com>
 270
 271         * mips.h: Doucument '1' for 5-bit sync type.
 272
 273 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 276         IA64_RS_CR.
 277
 278 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 279
 280         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 281
 282 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 283
 284         * ppc.h (PPC_OPCODE_405): Define.
 285         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 286
 287 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 288
 289         * ppc.h (ppc_cpu_t): New typedef.
 290         (struct powerpc_opcode <flags>): Use it.
 291         (struct powerpc_operand <insert, extract>): Likewise.
 292         (struct powerpc_macro <flags>): Likewise.
 293
 294 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 295
 296         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 297         Update comment before MIPS16 field descriptors to mention MIPS16.
 298         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 299         BBIT.
 300         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 301         New bit masks and shift counts for cins and exts.
 302
 303         * mips.h: Document new field descriptors +Q.
 304         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 305
 306 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 307
 308         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 309         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 310
 311 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 312
 313         * ppc.h: (PPC_OPCODE_E500MC): New.
 314
 315 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 316
 317         * i386.h (MAX_OPERANDS): Set to 5.
 318         (MAX_MNEM_SIZE): Changed to 20.
 319
 320 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 321
 322         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 323
 324 2008-03-09  Paul Brook  <paul@codesourcery.com>
 325
 326         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 327
 328 2008-03-04  Paul Brook  <paul@codesourcery.com>
 329
 330         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 331         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 332         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 333
 334 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 335             Nick Clifton  <nickc@redhat.com>
 336
 337         PR 3134
 338         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 339         with a 32-bit displacement but without the top bit of the 4th byte
 340         set.
 341
 342 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 343
 344         * cr16.h (cr16_num_optab): Declared.
 345
 346 2008-02-14  Hakan Ardo  <hakan@debian.org>
 347
 348         PR gas/2626
 349         * avr.h (AVR_ISA_2xxe): Define.
 350
 351 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 352
 353         * mips.h: Update copyright.
 354         (INSN_CHIP_MASK): New macro.
 355         (INSN_OCTEON): New macro.
 356         (CPU_OCTEON): New macro.
 357         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 358
 359 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 360
 361         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 362
 363 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 364
 365         * avr.h (AVR_ISA_USB162): Add new opcode set.
 366         (AVR_ISA_AVR3): Likewise.
 367
 368 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 369
 370         * mips.h (INSN_LOONGSON_2E): New.
 371         (INSN_LOONGSON_2F): New.
 372         (CPU_LOONGSON_2E): New.
 373         (CPU_LOONGSON_2F): New.
 374         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 375
 376 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 377
 378         * mips.h (INSN_ISA*): Redefine certain values as an
 379         enumeration.  Update comments.
 380         (mips_isa_table): New.
 381         (ISA_MIPS*): Redefine to match enumeration.
 382         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 383         values.
 384
 385 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 386
 387         * ppc.h (PPC_OPCODE_PPCPS): New.
 388
 389 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 390
 391         * m68k.h: Document j K & E.
 392
 393 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 394
 395         * cr16.h: New file for CR16 target.
 396
 397 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 398
 399         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 400
 401 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 402
 403         * m68k.h (mcfisa_c): New.
 404         (mcfusp, mcf_mask): Adjust.
 405
 406 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 407
 408         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 409         (num_powerpc_operands): Declare.
 410         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 411         (PPC_OPERAND_PLUS1): Define.
 412
 413 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 414
 415         * i386.h (REX_MODE64): Renamed to ...
 416         (REX_W): This.
 417         (REX_EXTX): Renamed to ...
 418         (REX_R): This.
 419         (REX_EXTY): Renamed to ...
 420         (REX_X): This.
 421         (REX_EXTZ): Renamed to ...
 422         (REX_B): This.
 423
 424 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386.h: Add entries from config/tc-i386.h and move tables
 427         to opcodes/i386-opc.h.
 428
 429 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         * i386.h (FloatDR): Removed.
 432         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 433
 434 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 435
 436         * spu-insns.h: Add soma double-float insns.
 437
 438 2007-02-20  Thiemo Seufer  <ths@mips.com>
 439             Chao-Ying Fu  <fu@mips.com>
 440
 441         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 442         (INSN_DSPR2): Add flag for DSP R2 instructions.
 443         (M_BALIGN): New macro.
 444
 445 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 446
 447         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 448         and Seg3ShortFrom with Shortform.
 449
 450 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         PR gas/4027
 453         * i386.h (i386_optab): Put the real "test" before the pseudo
 454         one.
 455
 456 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 457
 458         * m68k.h (m68010up): OR fido_a.
 459
 460 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 461
 462         * m68k.h (fido_a): New.
 463
 464 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 465
 466         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 467         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 468         values.
 469
 470 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 471
 472         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 473
 474 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 475
 476         * score-inst.h (enum score_insn_type): Add Insn_internal.
 477
 478 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 479             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 480             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 481             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 482             Alan Modra  <amodra@bigpond.net.au>
 483
 484         * spu-insns.h: New file.
 485         * spu.h: New file.
 486
 487 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 488
 489         * ppc.h (PPC_OPCODE_CELL): Define.
 490
 491 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 492
 493         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 494         in amdfam10 architecture.
 495
 496 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 497
 498         * i386.h: Replace CpuMNI with CpuSSSE3.
 499
 500 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 501             Joseph Myers  <joseph@codesourcery.com>
 502             Ian Lance Taylor  <ian@wasabisystems.com>
 503             Ben Elliston  <bje@wasabisystems.com>
 504
 505         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 506
 507 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 508
 509         * score-datadep.h: New file.
 510         * score-inst.h: New file.
 511
 512 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 513
 514         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 515         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 516         movdq2q and movq2dq.
 517
 518 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 519            Michael Meissner             <michael.meissner@amd.com>
 520
 521         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 522
 523 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 524
 525         * i386.h (i386_optab): Add "nop" with memory reference.
 526
 527 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * i386.h (i386_optab): Update comment for 64bit NOP.
 530
 531 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 532             Anton Blanchard  <anton@samba.org>
 533
 534         * ppc.h (PPC_OPCODE_POWER6): Define.
 535         Adjust whitespace.
 536
 537 2006-06-05  Thiemo Seufer  <ths@mips.com>
 538
 539         * mips.h: Improve description of MT flags.
 540
 541 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 542
 543         * m68k.h (mcf_mask): Define.
 544
 545 2006-05-05  Thiemo Seufer  <ths@mips.com>
 546             David Ung  <davidu@mips.com>
 547
 548         * mips.h (enum): Add macro M_CACHE_AB.
 549
 550 2006-05-04  Thiemo Seufer  <ths@mips.com>
 551             Nigel Stephens  <nigel@mips.com>
 552             David Ung  <davidu@mips.com>
 553
 554         * mips.h: Add INSN_SMARTMIPS define.
 555
 556 2006-04-30  Thiemo Seufer  <ths@mips.com>
 557             David Ung  <davidu@mips.com>
 558
 559         * mips.h: Defines udi bits and masks.  Add description of
 560         characters which may appear in the args field of udi
 561         instructions.
 562
 563 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 564
 565         * mips.h: Improve comments describing the bitfield instruction
 566         fields.
 567
 568 2006-04-26  Julian Brown  <julian@codesourcery.com>
 569
 570         * arm.h (FPU_VFP_EXT_V3): Define constant.
 571         (FPU_NEON_EXT_V1): Likewise.
 572         (FPU_VFP_HARD): Update.
 573         (FPU_VFP_V3): Define macro.
 574         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 575
 576 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 577
 578         * avr.h (AVR_ISA_PWMx): New.
 579
 580 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 581
 582         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 583         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 584         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 585         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 586         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 587
 588 2006-03-10  Paul Brook  <paul@codesourcery.com>
 589
 590         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 591
 592 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 593
 594         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 595         first.  Correct mask of bb "B" opcode.
 596
 597 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 598
 599         * i386.h (i386_optab): Support Intel Merom New Instructions.
 600
 601 2006-02-24  Paul Brook  <paul@codesourcery.com>
 602
 603         * arm.h: Add V7 feature bits.
 604
 605 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 606
 607         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 608
 609 2006-01-31  Paul Brook  <paul@codesourcery.com>
 610         Richard Earnshaw <rearnsha@arm.com>
 611
 612         * arm.h: Use ARM_CPU_FEATURE.
 613         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 614         (arm_feature_set): Change to a structure.
 615         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 616         ARM_FEATURE): New macros.
 617
 618 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 619
 620         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 621         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 622         (ADD_PC_INCR_OPCODE): Don't define.
 623
 624 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 625
 626         PR gas/1874
 627         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 628
 629 2005-11-14  David Ung  <davidu@mips.com>
 630
 631         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 632         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 633         save/restore encoding of the args field.
 634
 635 2005-10-28  Dave Brolley  <brolley@redhat.com>
 636
 637         Contribute the following changes:
 638         2005-02-16  Dave Brolley  <brolley@redhat.com>
 639
 640         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 641         cgen_isa_mask_* to cgen_bitset_*.
 642         * cgen.h: Likewise.
 643
 644         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 645
 646         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 647         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 648         (CGEN_CPU_TABLE): Make isas a ponter.
 649
 650         2003-09-29  Dave Brolley  <brolley@redhat.com>
 651
 652         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 653         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 654         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 655
 656         2002-12-13  Dave Brolley  <brolley@redhat.com>
 657
 658         * cgen.h (symcat.h): #include it.
 659         (cgen-bitset.h): #include it.
 660         (CGEN_ATTR_VALUE_TYPE): Now a union.
 661         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 662         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 663         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 664         * cgen-bitset.h: New file.
 665
 666 2005-09-30  Catherine Moore  <clm@cm00re.com>
 667
 668         * bfin.h: New file.
 669
 670 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 671
 672         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 673         indirect operands.
 674
 675 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 676
 677         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 678         Add FLAG_STRICT to pa10 ftest opcode.
 679
 680 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 681
 682         * hppa.h (pa_opcodes): Remove lha entries.
 683
 684 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 685
 686         * hppa.h (FLAG_STRICT): Revise comment.
 687         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 688         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 689         entries for "fdc".
 690
 691 2005-09-30  Catherine Moore  <clm@cm00re.com>
 692
 693         * bfin.h: New file.
 694
 695 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 696
 697         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 698
 699 2005-09-06  Chao-ying Fu  <fu@mips.com>
 700
 701         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 702         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 703         define.
 704         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 705         (INSN_ASE_MASK): Update to include INSN_MT.
 706         (INSN_MT): New define for MT ASE.
 707
 708 2005-08-25  Chao-ying Fu  <fu@mips.com>
 709
 710         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 711         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 712         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 713         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 714         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 715         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 716         instructions.
 717         (INSN_DSP): New define for DSP ASE.
 718
 719 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 720
 721         * a29k.h: Delete.
 722
 723 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 724
 725         * ppc.h (PPC_OPCODE_E300): Define.
 726
 727 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 728
 729         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 730
 731 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 732
 733         PR gas/336
 734         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 735         and pitlb.
 736
 737 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 738
 739         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 740         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 741         Add movq-s as 64-bit variants of movd-s.
 742
 743 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 744
 745         * hppa.h: Fix punctuation in comment.
 746
 747         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 748         implicit space-register addressing.  Set space-register bits on opcodes
 749         using implicit space-register addressing.  Add various missing pa20
 750         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 751         space-register addressing.  Use "fE" instead of "fe" in various
 752         fstw opcodes.
 753
 754 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 755
 756         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 757
 758 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 759
 760         * i386.h (i386_optab): Support Intel VMX Instructions.
 761
 762 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 763
 764         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 765
 766 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 767
 768         * i386.h (i386_optab): Add new insns.
 769
 770 2005-07-01  Nick Clifton  <nickc@redhat.com>
 771
 772         * sparc.h: Add typedefs to structure declarations.
 773
 774 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 775
 776         PR 1013
 777         * i386.h (i386_optab): Update comments for 64bit addressing on
 778         mov. Allow 64bit addressing for mov and movq.
 779
 780 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 781
 782         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 783         respectively, in various floating-point load and store patterns.
 784
 785 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 786
 787         * hppa.h (FLAG_STRICT): Correct comment.
 788         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 789         PA 2.0 mneumonics when equivalent.  Entries with cache control
 790         completers now require PA 1.1.  Adjust whitespace.
 791
 792 2005-05-19  Anton Blanchard  <anton@samba.org>
 793
 794         * ppc.h (PPC_OPCODE_POWER5): Define.
 795
 796 2005-05-10  Nick Clifton  <nickc@redhat.com>
 797
 798         * Update the address and phone number of the FSF organization in
 799         the GPL notices in the following files:
 800         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 801         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 802         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 803         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 804         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 805         tic54x.h, tic80.h, v850.h, vax.h
 806
 807 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 808
 809         * i386.h (i386_optab): Add ht and hnt.
 810
 811 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 812
 813         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 814         Add xcrypt-ctr.  Provide aliases without hyphens.
 815
 816 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         Moved from ../ChangeLog
 819
 820         2005-04-12  Paul Brook  <paul@codesourcery.com>
 821         * m88k.h: Rename psr macros to avoid conflicts.
 822
 823         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 824         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 825         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 826         and ARM_ARCH_V6ZKT2.
 827
 828         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 829         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 830         Remove redundant instruction types.
 831         (struct argument): X_op - new field.
 832         (struct cst4_entry): Remove.
 833         (no_op_insn): Declare.
 834
 835         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 836         * crx.h (enum argtype): Rename types, remove unused types.
 837
 838         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 839         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 840         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 841         (enum operand_type): Rearrange operands, edit comments.
 842         replace us<N> with ui<N> for unsigned immediate.
 843         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 844         displacements (respectively).
 845         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 846         (instruction type): Add NO_TYPE_INS.
 847         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 848         (operand_entry): New field - 'flags'.
 849         (operand flags): New.
 850
 851         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 852         * crx.h (operand_type): Remove redundant types i3, i4,
 853         i5, i8, i12.
 854         Add new unsigned immediate types us3, us4, us5, us16.
 855
 856 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 857
 858         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 859         adjust them accordingly.
 860
 861 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 862
 863         * i386.h (i386_optab): Add rdtscp.
 864
 865 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 866
 867         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 868         between memory and segment register. Allow movq for moving between
 869         general-purpose register and segment register.
 870
 871 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 872
 873         PR gas/707
 874         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 875         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 876         fnstsw.
 877
 878 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 879
 880         * m68k.h (m68008, m68ec030, m68882): Remove.
 881         (m68k_mask): New.
 882         (cpu_m68k, cpu_cf): New.
 883         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 884         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 885
 886 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 887
 888         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 889         * cgen.h (enum cgen_parse_operand_type): Add
 890         CGEN_PARSE_OPERAND_SYMBOLIC.
 891
 892 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 893
 894         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 895         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 896         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 897
 898 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 899
 900         * mips.h (struct mips_opcode): Add new pinfo2 member.
 901         (INSN_ALIAS): New define for opcode table entries that are
 902         specific instances of another entry, such as 'move' for an 'or'
 903         with a zero operand.
 904         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 905         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 906
 907 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 908
 909         * mips.h (CPU_RM9000): Define.
 910         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 911
 912 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 913
 914         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 915         to/from test registers are illegal in 64-bit mode. Add missing
 916         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 917         (previously one had to explicitly encode a rex64 prefix). Re-enable
 918         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 919         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 920
 921 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 922
 923         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 924         available only with SSE2. Change the MMX additions introduced by SSE
 925         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 926         instructions by their now designated identifier (since combining i686
 927         and 3DNow! does not really imply 3DNow!A).
 928
 929 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 930
 931         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 932         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 933
 934 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 935             Vineet Sharma      <vineets@noida.hcltech.com>
 936
 937         * maxq.h: New file: Disassembly information for the maxq port.
 938
 939 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 940
 941         * i386.h (i386_optab): Put back "movzb".
 942
 943 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 944
 945         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 946         comments.  Remove member cris_ver_sim.  Add members
 947         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 948         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 949         (struct cris_support_reg, struct cris_cond15): New types.
 950         (cris_conds15): Declare.
 951         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 952         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 953         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 954         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 955         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 956         SIZE_FIELD_UNSIGNED.
 957
 958 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 959
 960         * i386.h (sldx_Suf): Remove.
 961         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 962         (q_FP): Define, implying no REX64.
 963         (x_FP, sl_FP): Imply FloatMF.
 964         (i386_optab): Split reg and mem forms of moving from segment registers
 965         so that the memory forms can ignore the 16-/32-bit operand size
 966         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 967         all non-floating-point instructions. Unite 32- and 64-bit forms of
 968         movsx, movzx, and movd. Adjust floating point operations for the above
 969         changes to the *FP macros. Add DefaultSize to floating point control
 970         insns operating on larger memory ranges. Remove left over comments
 971         hinting at certain insns being Intel-syntax ones where the ones
 972         actually meant are already gone.
 973
 974 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 975
 976         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 977         instruction type.
 978
 979 2004-09-30  Paul Brook  <paul@codesourcery.com>
 980
 981         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 982         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 983
 984 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 985
 986         * avr.h: Add support for
 987         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 988
 989 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 990
 991         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 992
 993 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 994
 995         * msp430.h (msp430_opc): Add new instructions.
 996         (msp430_rcodes): Declare new instructions.
 997         (msp430_hcodes): Likewise..
 998
 999 2004-08-13  Nick Clifton  <nickc@redhat.com>
1000
1001         PR/301
1002         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1003         processors.
1004
1005 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1006
1007         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1008
1009 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1010
1011         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1012
1013 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1014
1015         * i386.h: Adjust instruction descriptions to better match the
1016         specification.
1017
1018 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1019
1020         * arm.h: Remove all old content.  Replace with architecture defines
1021         from gas/config/tc-arm.c.
1022
1023 2004-07-09  Andreas Schwab  <schwab@suse.de>
1024
1025         * m68k.h: Fix comment.
1026
1027 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1028
1029         * crx.h: New file.
1030
1031 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1032
1033         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1034
1035 2004-05-24  Peter Barada  <peter@the-baradas.com>
1036
1037         * m68k.h: Add 'size' to m68k_opcode.
1038
1039 2004-05-05  Peter Barada  <peter@the-baradas.com>
1040
1041         * m68k.h: Switch from ColdFire chip name to core variant.
1042
1043 2004-04-22  Peter Barada  <peter@the-baradas.com>
1044
1045         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1046         descriptions for new EMAC cases.
1047         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1048         handle Motorola MAC syntax.
1049         Allow disassembly of ColdFire V4e object files.
1050
1051 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1052
1053         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1054
1055 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1056
1057         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1058
1059 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1060
1061         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1062
1063 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1064
1065         * i386.h (i386_optab): Added xstore/xcrypt insns.
1066
1067 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1068
1069         * h8300.h (32bit ldc/stc): Add relaxing support.
1070
1071 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1072
1073         * h8300.h (BITOP): Pass MEMRELAX flag.
1074
1075 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1076
1077         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1078         except for the H8S.
1079
1080 For older changes see ChangeLog-9103
1081 \f
1082 Local Variables:
1083 mode: change-log
1084 left-margin: 8
1085 fill-column: 74
1086 version-control: never
1087 End: