include/opcode/ChangeLog

   1 2014-09-16  Kuan-Lin Chen <kuanlinchentw@gmail.com>
   2
   3         * nds32.h: Add new opcode declaration.
   4
   5 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
   6             Matthew Fortune  <matthew.fortune@imgtec.com>
   7
   8         * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
   9         OP_CHECK_PREV and OP_NON_ZERO_REG.  Add descriptions for the MIPS R6
  10         instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
  11          +I, +O, +R, +:, +\, +", +;
  12         (mips_check_prev_operand): New struct.
  13         (INSN2_FORBIDDEN_SLOT): New define.
  14         (INSN_ISA32R6): New define.
  15         (INSN_ISA64R6): New define.
  16         (INSN_UPTO32R6): New define.
  17         (INSN_UPTO64R6): New define.
  18         (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
  19         (ISA_MIPS32R6): New define.
  20         (ISA_MIPS64R6): New define.
  21         (CPU_MIPS32R6): New define.
  22         (CPU_MIPS64R6): New define.
  23         (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
  24
  25 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
  26
  27         * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
  28         (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
  29         (aarch64_insn_class): Add lse_atomic.
  30         (F_LSE_SZ): New field added.
  31         (opcode_has_special_coder): Recognize F_LSE_SZ.
  32
  33 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
  34
  35         * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
  36         over to `+J'.
  37
  38 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
  39
  40         * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
  41         (INSN_LOAD_COPROC): New define.
  42         (INSN_COPROC_MOVE_DELAY): Rename to...
  43         (INSN_COPROC_MOVE): New define.
  44
  45 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
  46             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
  47             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
  48             Soundararajan  <Sounderarajan.D@atmel.com>
  49
  50         * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
  51         (AVR_ISA_2xxxa): Define ISA without LPM.
  52         (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
  53         Add doc for contraint used in 16 bit lds/sts.
  54         Adjust ISA group for icall, ijmp, pop and push.
  55         Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
  56
  57 2014-05-19  Nick Clifton  <nickc@redhat.com>
  58
  59         * msp430.h (struct msp430_operand_s): Add vshift field.
  60
  61 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
  62
  63         * mips.h (INSN_ISA_MASK): Updated.
  64         (INSN_ISA32R3): New define.
  65         (INSN_ISA32R5): New define.
  66         (INSN_ISA64R3): New define.
  67         (INSN_ISA64R5): New define.
  68         (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
  69         INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
  70         (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
  71         mips64r5.
  72         (INSN_UPTO32R3): New define.
  73         (INSN_UPTO32R5): New define.
  74         (INSN_UPTO64R3): New define.
  75         (INSN_UPTO64R5): New define.
  76         (ISA_MIPS32R3): New define.
  77         (ISA_MIPS32R5): New define.
  78         (ISA_MIPS64R3): New define.
  79         (ISA_MIPS64R5): New define.
  80         (CPU_MIPS32R3): New define.
  81         (CPU_MIPS32R5): New define.
  82         (CPU_MIPS64R3): New define.
  83         (CPU_MIPS64R5): New define.
  84
  85 2014-05-01  Richard Sandiford  <rdsandiford@googlemail.com>
  86
  87         * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
  88
  89 2014-04-22  Christian Svensson  <blue@cmd.nu>
  90
  91         * or32.h: Delete.
  92
  93 2014-03-05  Alan Modra  <amodra@gmail.com>
  94
  95         Update copyright years.
  96
  97 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
  98
  99         * mips.h: Updated description of +o, +u, +v and +w for MIPS and
 100         microMIPS.
 101
 102 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 103             Wei-Cheng Wang  <cole945@gmail.com>
 104
 105         * nds32.h: New file for Andes NDS32.
 106
 107 2013-12-07  Mike Frysinger  <vapier@gentoo.org>
 108
 109         * bfin.h: Remove +x file mode.
 110
 111 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 112
 113         * aarch64.h (aarch64_pstatefields): Change element type to
 114         aarch64_sys_reg.
 115
 116 2013-11-18  Renlin Li  <Renlin.Li@arm.com>
 117
 118         * arm.h (ARM_AEXT_V7VE): New define.
 119         (ARM_ARCH_V7VE): New define.
 120         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
 121
 122 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
 123
 124         Revert
 125
 126         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 127
 128         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
 129         (aarch64_sys_reg_writeonly_p): Ditto.
 130
 131 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
 132
 133         * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
 134         (aarch64_sys_reg_writeonly_p): Ditto.
 135
 136 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 137
 138         * aarch64.h (aarch64_sys_reg): New typedef.
 139         (aarch64_sys_regs): Change to define with the new type.
 140         (aarch64_sys_reg_deprecated_p): Declare.
 141
 142 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 143
 144         * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
 145         (enum aarch64_opnd): Add AARCH64_OPND_COND1.
 146
 147 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 148
 149         * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
 150         (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
 151         For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 152         +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 153         For MIPS, update extension character sequences after +.
 154         (ASE_MSA): New define.
 155         (ASE_MSA64): New define.
 156         For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
 157         +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 158         For microMIPS, update extension character sequences after +.
 159
 160 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 161
 162         PR binutils/15834
 163         * i960.h: Fix typos.
 164
 165 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 166
 167         * mips.h: Remove references to "+I" and imm2_expr.
 168
 169 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 170
 171         * mips.h (M_DEXT, M_DINS): Delete.
 172
 173 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 174
 175         * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
 176         (mips_optional_operand_p): New function.
 177
 178 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 179             Richard Sandiford  <rdsandiford@googlemail.com>
 180
 181         * mips.h: Document new VU0 operand characters.
 182         (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
 183         (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
 184         (OP_REG_R5900_ACC): New mips_reg_operand_types.
 185         (INSN2_VU0_CHANNEL_SUFFIX): New macro.
 186         (mips_vu0_channel_mask): Declare.
 187
 188 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 189
 190         * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
 191         (mips_int_operand_min, mips_int_operand_max): New functions.
 192         (mips_decode_pcrel_operand): Use mips_decode_int_operand.
 193
 194 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 195
 196         * mips.h (mips_decode_reg_operand): New function.
 197         (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
 198         (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
 199         (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
 200         New macros.
 201         (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
 202         (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
 203         (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
 204         (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
 205         (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
 206         (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
 207         (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
 208         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
 209         (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
 210         (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
 211         macros to cover the gaps.
 212         (INSN2_MOD_SP): Replace with...
 213         (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
 214         (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
 215         (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
 216         (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
 217         (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
 218         Delete.
 219
 220 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 221
 222         * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
 223         (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
 224         (MIPS16_INSN_COND_BRANCH): Delete.
 225
 226 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 227             Kirill Yukhin  <kirill.yukhin@intel.com>
 228             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 229
 230         * i386.h (BND_PREFIX_OPCODE): New.
 231
 232 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 233
 234         * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
 235         OP_SAVE_RESTORE_LIST.
 236         (decode_mips16_operand): Declare.
 237
 238 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 239
 240         * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
 241         (mips_operand, mips_int_operand, mips_mapped_int_operand)
 242         (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
 243         (mips_pcrel_operand): New structures.
 244         (mips_insert_operand, mips_extract_operand, mips_signed_operand)
 245         (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
 246         (decode_mips_operand, decode_micromips_operand): Declare.
 247
 248 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 249
 250         * mips.h: Document MIPS16 "I" opcode.
 251
 252 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 253
 254         * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
 255         (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
 256         (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
 257         (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
 258         (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
 259         (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
 260         (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
 261         (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
 262         (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
 263         (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
 264         (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
 265         (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
 266         (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
 267         Rename to...
 268         (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
 269         (M_USD_AB): ...these.
 270
 271 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 272
 273         * mips.h: Remove documentation of "[" and "]".  Update documentation
 274         of "k" and the MDMX formats.
 275
 276 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 277
 278         * mips.h: Update documentation of "+s" and "+S".
 279
 280 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 281
 282         * mips.h: Document "+i".
 283
 284 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 285
 286         * mips.h: Remove "mi" documentation.  Update "mh" documentation.
 287         (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
 288         Delete.
 289         (INSN2_WRITE_GPR_MHI): Rename to...
 290         (INSN2_WRITE_GPR_MH): ...this.
 291
 292 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 293
 294         * mips.h: Remove documentation of "+D" and "+T".
 295
 296 2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
 297
 298         * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
 299         Use "source" rather than "destination" for microMIPS "G".
 300
 301 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 302
 303         * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
 304         values.
 305
 306 2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
 307
 308         * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
 309
 310 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 311             Maciej W. Rozycki  <macro@codesourcery.com>
 312             Chao-Ying Fu  <fu@mips.com>
 313
 314         * mips.h (OP_SH_EVAOFFSET): Define.
 315         (OP_MASK_EVAOFFSET): Define.
 316         (INSN_ASE_MASK): Delete.
 317         (ASE_EVA): Define.
 318         (M_CACHEE_AB, M_CACHEE_OB): New.
 319         (M_LBE_OB, M_LBE_AB): New.
 320         (M_LBUE_OB, M_LBUE_AB): New.
 321         (M_LHE_OB, M_LHE_AB): New.
 322         (M_LHUE_OB, M_LHUE_AB): New.
 323         (M_LLE_AB, M_LLE_OB): New.
 324         (M_LWE_OB, M_LWE_AB): New.
 325         (M_LWLE_AB, M_LWLE_OB): New.
 326         (M_LWRE_AB, M_LWRE_OB): New.
 327         (M_PREFE_AB, M_PREFE_OB): New.
 328         (M_SCE_AB, M_SCE_OB): New.
 329         (M_SBE_OB, M_SBE_AB): New.
 330         (M_SHE_OB, M_SHE_AB): New.
 331         (M_SWE_OB, M_SWE_AB): New.
 332         (M_SWLE_AB, M_SWLE_OB): New.
 333         (M_SWRE_AB, M_SWRE_OB): New.
 334         (MICROMIPSOP_SH_EVAOFFSET): Define.
 335         (MICROMIPSOP_MASK_EVAOFFSET): Define.
 336
 337 2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
 338
 339         * nios2.h (OP_MATCH_ERET): Correct eret encoding.
 340
 341 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 342
 343         * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
 344
 345 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 346
 347         * mips.h (OP_MASK_CODE10): Correct definition.
 348         (OP_SH_CODE10): Likewise.
 349         Add a comment that "+J" is used now for OP_*CODE10.
 350         (INSN_ASE_MASK): Update.
 351         (INSN_VIRT): New macro.
 352         (INSN_VIRT64): New macro
 353
 354 2013-05-02  Nick Clifton  <nickc@redhat.com>
 355
 356         * msp430.h: Add patterns for MSP430X instructions.
 357
 358 2013-04-06  David S. Miller  <davem@davemloft.net>
 359
 360         * sparc.h (F_PREFERRED): Define.
 361         (F_PREF_ALIAS): Define.
 362
 363 2013-04-03  Nick Clifton  <nickc@redhat.com>
 364
 365         * v850.h (V850_INVERSE_PCREL): Define.
 366
 367 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 368
 369         PR binutils/15068
 370         * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
 371
 372 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 373
 374         PR binutils/15068
 375         * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
 376         Add 16-bit opcodes.
 377         * tic6xc-opcode-table.h: Add 16-bit insns.
 378         * tic6x.h: Add support for 16-bit insns.
 379
 380 2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
 381
 382         * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
 383         and mov.b/w/l Rs,@(d:32,ERd).
 384
 385 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 386
 387         PR gas/15082
 388         * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
 389         from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
 390         tic6x_operand_xregpair operand coding type.
 391         Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
 392         opcode field, usu ORXREGD1324 for the src2 operand and remove the
 393         TIC6X_FLAG_NO_CROSS.
 394
 395 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 396
 397         PR gas/15095
 398         * tic6x.h (enum tic6x_coding_method): Add
 399         tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
 400         separately the msb and lsb of a register pair.  This is needed to
 401         encode the opcodes in the same way as TI assembler does.
 402         * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
 403         and rsqrdp opcodes to use the new field coding types.
 404
 405 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 406
 407         * arm.h (CRC_EXT_ARMV8): New constant.
 408         (ARCH_CRC_ARMV8): New macro.
 409
 410 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 411
 412         * aarch64.h (AARCH64_FEATURE_CRC): New macro.
 413
 414 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 415             Andrew Jenner <andrew@codesourcery.com>
 416
 417         Based on patches from Altera Corporation.
 418
 419         * nios2.h: New file.
 420
 421 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 422
 423         * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
 424
 425 2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
 426
 427         PR gas/15069
 428         * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
 429
 430 2013-01-24  Nick Clifton  <nickc@redhat.com>
 431
 432         * v850.h: Add e3v5 support.
 433
 434 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 435
 436         * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
 437
 438 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 439
 440         * ppc.h (PPC_OPCODE_POWER8): New define.
 441         (PPC_OPCODE_HTM): Likewise.
 442
 443 2013-01-10  Will Newton <will.newton@imgtec.com>
 444
 445         * metag.h: New file.
 446
 447 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 448
 449         * cr16.h (make_instruction): Rename to cr16_make_instruction.
 450         (match_opcode): Rename to cr16_match_opcode.
 451
 452 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 453
 454         * mips.h: Add support for r5900 instructions including lq and sq.
 455
 456 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 457
 458         * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
 459         (make_instruction,match_opcode): Added function prototypes.
 460         (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
 461
 462 2012-11-23  Alan Modra  <amodra@gmail.com>
 463
 464         * ppc.h (ppc_parse_cpu): Update prototype.
 465
 466 2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 467
 468         * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
 469         opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
 470
 471 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 472
 473         * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
 474
 475 2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
 476
 477         * ia64.h (ia64_opnd): Add new operand types.
 478
 479 2012-08-21  David S. Miller  <davem@davemloft.net>
 480
 481         * sparc.h (F3F4): New macro.
 482
 483 2012-08-13  Ian Bolton  <ian.bolton@arm.com>
 484             Laurent Desnogues  <laurent.desnogues@arm.com>
 485             Jim MacArthur  <jim.macarthur@arm.com>
 486             Marcus Shawcroft  <marcus.shawcroft@arm.com>
 487             Nigel Stephens  <nigel.stephens@arm.com>
 488             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 489             Richard Earnshaw  <rearnsha@arm.com>
 490             Sofiane Naci  <sofiane.naci@arm.com>
 491             Tejas Belagod  <tejas.belagod@arm.com>
 492             Yufeng Zhang  <yufeng.zhang@arm.com>
 493
 494         * aarch64.h: New file.
 495
 496 2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
 497             Maciej W. Rozycki  <macro@codesourcery.com>
 498
 499         * mips.h (mips_opcode): Add the exclusions field.
 500         (OPCODE_IS_MEMBER): Remove macro.
 501         (cpu_is_member): New inline function.
 502         (opcode_is_member): Likewise.
 503
 504 2012-07-31  Chao-Ying Fu  <fu@mips.com>
 505             Catherine Moore  <clm@codesourcery.com>
 506             Maciej W. Rozycki  <macro@codesourcery.com>
 507
 508         * mips.h: Document microMIPS DSP ASE usage.
 509         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
 510         microMIPS DSP ASE support.
 511         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 512         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 513         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 514         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 515         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 516         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 517         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 518
 519 2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 520
 521         * mips.h: Fix a typo in description.
 522
 523 2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
 524
 525         * avr.h: (AVR_ISA_XCH): New define.
 526         (AVR_ISA_XMEGA): Use it.
 527         (XCH, LAS, LAT, LAC): New XMEGA opcodes.
 528
 529 2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
 530
 531         * m68hc11.h: Add XGate definitions.
 532         (struct m68hc11_opcode): Add xg_mask field.
 533
 534 2012-05-14  Catherine Moore  <clm@codesourcery.com>
 535             Maciej W. Rozycki  <macro@codesourcery.com>
 536             Rhonda Wittels  <rhonda@codesourcery.com>
 537
 538         * ppc.h (PPC_OPCODE_VLE): New definition.
 539         (PPC_OP_SA): New macro.
 540         (PPC_OP_SE_VLE): New macro.
 541         (PPC_OP): Use a variable shift amount.
 542         (powerpc_operand): Update comments.
 543         (PPC_OPSHIFT_INV): New macro.
 544         (PPC_OPERAND_CR): Replace with...
 545         (PPC_OPERAND_CR_BIT): ...this and
 546         (PPC_OPERAND_CR_REG): ...this.
 547
 548
 549 2012-05-03  Sean Keys  <skeys@ipdatasys.com>
 550
 551         * xgate.h: Header file for XGATE assembler.
 552
 553 2012-04-27  David S. Miller  <davem@davemloft.net>
 554
 555         * sparc.h: Document new arg code' )' for crypto RS3
 556         immediates.
 557
 558         * sparc.h (struct sparc_opcode): New field 'hwcaps'.
 559         F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 560         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 561         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
 562         (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
 563         HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
 564         HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
 565         HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
 566         HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
 567         HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
 568         HWCAP_CBCOND, HWCAP_CRC32): New defines.
 569
 570 2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
 571
 572         * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
 573
 574 2012-02-27  Alan Modra  <amodra@gmail.com>
 575
 576         * crx.h (cst4_map): Update declaration.
 577
 578 2012-02-25  Walter Lee  <walt@tilera.com>
 579
 580         * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
 581         TILEGX_OPC_LD_TLS.
 582         * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
 583         TILEPRO_OPC_LW_TLS_SN.
 584
 585 2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
 586
 587         * i386.h (XACQUIRE_PREFIX_OPCODE): New.
 588         (XRELEASE_PREFIX_OPCODE): Likewise.
 589
 590 2011-12-08  Andrew Pinski  <apinski@cavium.com>
 591             Adam Nemet  <anemet@caviumnetworks.com>
 592
 593         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
 594         (INSN_OCTEON2): New macro.
 595         (CPU_OCTEON2): New macro.
 596         (OPCODE_IS_MEMBER): Add Octeon2.
 597
 598 2011-11-29  Andrew Pinski  <apinski@cavium.com>
 599
 600         * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
 601         (INSN_OCTEONP): New macro.
 602         (CPU_OCTEONP): New macro.
 603         (OPCODE_IS_MEMBER): Add Octeon+.
 604         (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
 605
 606 2011-11-01  DJ Delorie  <dj@redhat.com>
 607
 608         * rl78.h: New file.
 609
 610 2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
 611
 612         * mips.h: Fix a typo in description.
 613
 614 2011-09-21  David S. Miller  <davem@davemloft.net>
 615
 616         * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
 617         (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
 618         F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
 619         F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
 620
 621 2011-08-09  Chao-ying Fu  <fu@mips.com>
 622             Maciej W. Rozycki  <macro@codesourcery.com>
 623
 624         * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
 625         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
 626         (INSN_ASE_MASK): Add the MCU bit.
 627         (INSN_MCU): New macro.
 628         (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
 629         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 630
 631 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 632
 633         * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
 634         (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
 635         (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
 636         (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
 637         (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
 638         (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
 639         (INSN2_READ_GPR_MMN): Likewise.
 640         (INSN2_READ_FPR_D): Change the bit used.
 641         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
 642         (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
 643         (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
 644         (INSN2_COND_BRANCH): Likewise.
 645         (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
 646         (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
 647         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
 648         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
 649         (INSN2_MOD_GPR_MN): Likewise.
 650
 651 2011-08-05  David S. Miller  <davem@davemloft.net>
 652
 653         * sparc.h: Document new format codes '4', '5', and '('.
 654         (OPF_LOW4, RS3): New macros.
 655
 656 2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
 657
 658         * mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
 659         order of flags documented.
 660
 661 2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
 662
 663         * mips.h: Clarify the description of microMIPS instruction
 664         manipulation macros.
 665         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 666
 667 2011-07-24  Chao-ying Fu  <fu@mips.com>
 668             Maciej W. Rozycki  <macro@codesourcery.com>
 669
 670         * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
 671         (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
 672         (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
 673         (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
 674         (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
 675         (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
 676         (OP_MASK_RS3, OP_SH_RS3): Likewise.
 677         (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
 678         (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
 679         (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
 680         (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
 681         (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
 682         (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
 683         (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
 684         (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
 685         (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
 686         (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
 687         (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
 688         (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
 689         (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
 690         (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
 691         (INSN_WRITE_GPR_S): New macro.
 692         (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
 693         (INSN2_READ_FPR_D): Likewise.
 694         (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
 695         (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
 696         (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
 697         (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
 698         (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
 699         (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
 700         (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
 701         (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
 702         (CPU_MICROMIPS): New macro.
 703         (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
 704         (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
 705         (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
 706         (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
 707         (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
 708         (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
 709         (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
 710         (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
 711         (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
 712         (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
 713         (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
 714         (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
 715         (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
 716         (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
 717         (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
 718         (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
 719         (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
 720         (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
 721         (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
 722         (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
 723         (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
 724         (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
 725         (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
 726         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 727         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 728         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 729         (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
 730         (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
 731         (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
 732         (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
 733         (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
 734         (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
 735         (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
 736         (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
 737         (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
 738         (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
 739         (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
 740         (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
 741         (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
 742         (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
 743         (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
 744         (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
 745         (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
 746         (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
 747         (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
 748         (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
 749         (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
 750         (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
 751         (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
 752         (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
 753         (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
 754         (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
 755         (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
 756         (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
 757         (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
 758         (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
 759         (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
 760         (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
 761         (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
 762         (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
 763         (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
 764         (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
 765         (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
 766         (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
 767         (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
 768         (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
 769         (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
 770         (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
 771         (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
 772         (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
 773         (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
 774         (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
 775         (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
 776         (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
 777         (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
 778         (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
 779         (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
 780         (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
 781         (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
 782         (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
 783         (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
 784         (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
 785         (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
 786         (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
 787         (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
 788         (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
 789         (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
 790         (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
 791         (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
 792         (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
 793         (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
 794         (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
 795         (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
 796         (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
 797         (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
 798         (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
 799         (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
 800         (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
 801         (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
 802         (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
 803         (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
 804         (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
 805         (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
 806         (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
 807         (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
 808         (micromips_opcodes): New declaration.
 809         (bfd_micromips_num_opcodes): Likewise.
 810
 811 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 812
 813         * mips.h (INSN_TRAP): Rename to...
 814         (INSN_NO_DELAY_SLOT): ... this.
 815         (INSN_SYNC): Remove macro.
 816
 817 2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
 818
 819         * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
 820         a duplicate of AVR_ISA_SPM.
 821
 822 2011-07-01  Nick Clifton  <nickc@redhat.com>
 823
 824         * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 825
 826 2011-06-18  Robin Getz  <robin.getz@analog.com>
 827
 828         * bfin.h (is_macmod_signed): New func
 829
 830 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
 831
 832         * bfin.h (is_macmod_pmove): Add missing space before func args.
 833         (is_macmod_hmove): Likewise.
 834
 835 2011-06-13  Walter Lee  <walt@tilera.com>
 836
 837         * tilegx.h: New file.
 838         * tilepro.h: New file.
 839
 840 2011-05-31  Paul Brook  <paul@codesourcery.com>
 841
 842         * arm.h (ARM_ARCH_V7R_IDIV): Define.
 843
 844 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 845
 846         * s390.h: Replace S390_OPERAND_REG_EVEN with
 847         S390_OPERAND_REG_PAIR.
 848
 849 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 850
 851         * s390.h: Add S390_OPCODE_REG_EVEN flag.
 852
 853 2011-04-18  Julian Brown  <julian@codesourcery.com>
 854
 855         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
 856
 857 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
 858
 859         PR gas/12296
 860         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
 861
 862 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 863
 864         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
 865         New instruction set flags.
 866         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
 867
 868 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 869
 870         * mips.h (M_PREF_AB): New enum value.
 871
 872 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 873
 874         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
 875         M_IU): Define.
 876         (is_macmod_pmove, is_macmod_hmove): New functions.
 877
 878 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 879
 880         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
 881
 882 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
 883
 884         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
 885         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
 886
 887 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 888
 889         PR gas/11395
 890         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
 891         "bb" entries.
 892
 893 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 894
 895         PR gas/11395
 896         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
 897
 898 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
 899
 900         * mips.h: Update commentary after last commit.
 901
 902 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 903
 904         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
 905         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
 906         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
 907
 908 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 909
 910         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
 911
 912 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
 913
 914         * mips.h: Fix previous commit.
 915
 916 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
 917
 918         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
 919         (INSN_LOONGSON_3A): Clear bit 31.
 920
 921 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 922
 923         PR gas/12198
 924         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 925         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 926         (ARM_ARCH_V6M_ONLY): New define.
 927
 928 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 929
 930         * mips.h (INSN_LOONGSON_3A): Defined.
 931         (CPU_LOONGSON_3A): Defined.
 932         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 933
 934 2010-10-09  Matt Rice  <ratmice@gmail.com>
 935
 936         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 937         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 938
 939 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 940
 941         * arm.h (ARM_EXT_VIRT): New define.
 942         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 943         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 944         Extensions.
 945
 946 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 947
 948         * arm.h (ARM_AEXT_ADIV): New define.
 949         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 950
 951 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 952
 953         * arm.h (ARM_EXT_OS): New define.
 954         (ARM_AEXT_V6SM): Likewise.
 955         (ARM_ARCH_V6SM): Likewise.
 956
 957 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 958
 959         * arm.h (ARM_EXT_MP): Add.
 960         (ARM_ARCH_V7A_MP): Likewise.
 961
 962 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 963
 964         * bfin.h: Declare pseudoChr structs/defines.
 965
 966 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 967
 968         * bfin.h: Strip trailing whitespace.
 969
 970 2010-07-29  DJ Delorie  <dj@redhat.com>
 971
 972         * rx.h (RX_Operand_Type): Add TwoReg.
 973         (RX_Opcode_ID): Remove ediv and ediv2.
 974
 975 2010-07-27  DJ Delorie  <dj@redhat.com>
 976
 977         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 978
 979 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 980             Ina Pandit  <ina.pandit@kpitcummins.com>
 981
 982         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 983         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 984         PROCESSOR_V850E2_ALL.
 985         Remove PROCESSOR_V850EA support.
 986         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 987         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 988         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 989         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 990         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 991         V850_OPERAND_PERCENT.
 992         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 993         V850_NOT_R0.
 994         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 995         and V850E_PUSH_POP
 996
 997 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 998
 999         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1000         (MIPS16_INSN_BRANCH): Rename to...
1001         (MIPS16_INSN_COND_BRANCH): ... this.
1002
1003 2010-07-03  Alan Modra  <amodra@gmail.com>
1004
1005         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1006         Renumber other PPC_OPCODE defines.
1007
1008 2010-07-03  Alan Modra  <amodra@gmail.com>
1009
1010         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1011
1012 2010-06-29  Alan Modra  <amodra@gmail.com>
1013
1014         * maxq.h: Delete file.
1015
1016 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
1017
1018         * ppc.h (PPC_OPCODE_E500): Define.
1019
1020 2010-05-26  Catherine Moore  <clm@codesourcery.com>
1021
1022         * opcode/mips.h (INSN_MIPS16): Remove.
1023
1024 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
1025
1026         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1027
1028 2010-04-15  Nick Clifton  <nickc@redhat.com>
1029
1030         * alpha.h: Update copyright notice to use GPLv3.
1031         * arc.h: Likewise.
1032         * arm.h: Likewise.
1033         * avr.h: Likewise.
1034         * bfin.h: Likewise.
1035         * cgen.h: Likewise.
1036         * convex.h: Likewise.
1037         * cr16.h: Likewise.
1038         * cris.h: Likewise.
1039         * crx.h: Likewise.
1040         * d10v.h: Likewise.
1041         * d30v.h: Likewise.
1042         * dlx.h: Likewise.
1043         * h8300.h: Likewise.
1044         * hppa.h: Likewise.
1045         * i370.h: Likewise.
1046         * i386.h: Likewise.
1047         * i860.h: Likewise.
1048         * i960.h: Likewise.
1049         * ia64.h: Likewise.
1050         * m68hc11.h: Likewise.
1051         * m68k.h: Likewise.
1052         * m88k.h: Likewise.
1053         * maxq.h: Likewise.
1054         * mips.h: Likewise.
1055         * mmix.h: Likewise.
1056         * mn10200.h: Likewise.
1057         * mn10300.h: Likewise.
1058         * msp430.h: Likewise.
1059         * np1.h: Likewise.
1060         * ns32k.h: Likewise.
1061         * or32.h: Likewise.
1062         * pdp11.h: Likewise.
1063         * pj.h: Likewise.
1064         * pn.h: Likewise.
1065         * ppc.h: Likewise.
1066         * pyr.h: Likewise.
1067         * rx.h: Likewise.
1068         * s390.h: Likewise.
1069         * score-datadep.h: Likewise.
1070         * score-inst.h: Likewise.
1071         * sparc.h: Likewise.
1072         * spu-insns.h: Likewise.
1073         * spu.h: Likewise.
1074         * tic30.h: Likewise.
1075         * tic4x.h: Likewise.
1076         * tic54x.h: Likewise.
1077         * tic80.h: Likewise.
1078         * v850.h: Likewise.
1079         * vax.h: Likewise.
1080
1081 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
1082
1083         * tic6x-control-registers.h, tic6x-insn-formats.h,
1084         tic6x-opcode-table.h, tic6x.h: New.
1085
1086 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
1087
1088         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1089
1090 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
1091
1092         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1093
1094 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
1095
1096         * ia64.h (ia64_find_opcode): Remove argument name.
1097         (ia64_find_next_opcode): Likewise.
1098         (ia64_dis_opcode): Likewise.
1099         (ia64_free_opcode): Likewise.
1100         (ia64_find_dependency): Likewise.
1101
1102 2009-11-22  Doug Evans  <dje@sebabeach.org>
1103
1104         * cgen.h: Include bfd_stdint.h.
1105         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1106
1107 2009-11-18  Paul Brook  <paul@codesourcery.com>
1108
1109         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1110
1111 2009-11-17  Paul Brook  <paul@codesourcery.com>
1112         Daniel Jacobowitz  <dan@codesourcery.com>
1113
1114         * arm.h (ARM_EXT_V6_DSP): Define.
1115         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1116         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1117
1118 2009-11-04  DJ Delorie  <dj@redhat.com>
1119
1120         * rx.h (rx_decode_opcode) (mvtipl): Add.
1121         (mvtcp, mvfcp, opecp): Remove.
1122
1123 2009-11-02  Paul Brook  <paul@codesourcery.com>
1124
1125         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1126         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1127         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1128         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1129         FPU_ARCH_NEON_VFP_V4): Define.
1130
1131 2009-10-23  Doug Evans  <dje@sebabeach.org>
1132
1133         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1134         * cgen.h: Update.  Improve multi-inclusion macro name.
1135
1136 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
1137
1138         * ppc.h (PPC_OPCODE_476): Define.
1139
1140 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
1141
1142         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1143
1144 2009-09-29  DJ Delorie  <dj@redhat.com>
1145
1146         * rx.h: New file.
1147
1148 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
1149
1150         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1151
1152 2009-09-21  Ben Elliston  <bje@au.ibm.com>
1153
1154         * ppc.h (PPC_OPCODE_PPCA2): New.
1155
1156 2009-09-05  Martin Thuresson  <martin@mtme.org>
1157
1158         * ia64.h (struct ia64_operand): Renamed member class to op_class.
1159
1160 2009-08-29  Martin Thuresson  <martin@mtme.org>
1161
1162         * tic30.h (template): Rename type template to
1163         insn_template. Updated code to use new name.
1164         * tic54x.h (template): Rename type template to
1165         insn_template.
1166
1167 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
1168
1169         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1170
1171 2009-06-11  Anthony Green  <green@moxielogic.com>
1172
1173         * moxie.h (MOXIE_F3_PCREL): Define.
1174         (moxie_form3_opc_info): Grow.
1175
1176 2009-06-06  Anthony Green  <green@moxielogic.com>
1177
1178         * moxie.h (MOXIE_F1_M): Define.
1179
1180 2009-04-15  Anthony Green  <green@moxielogic.com>
1181
1182         * moxie.h: Created.
1183
1184 2009-04-06  DJ Delorie  <dj@redhat.com>
1185
1186         * h8300.h: Add relaxation attributes to MOVA opcodes.
1187
1188 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
1189
1190         * ppc.h (ppc_parse_cpu): Declare.
1191
1192 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
1193
1194         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1195         and _IMM11 for mbitclr and mbitset.
1196         * score-datadep.h: Update dependency information.
1197
1198 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
1199
1200         * ppc.h (PPC_OPCODE_POWER7): New.
1201
1202 2009-02-06  Doug Evans  <dje@google.com>
1203
1204         * i386.h: Add comment regarding sse* insns and prefixes.
1205
1206 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
1207
1208         * mips.h (INSN_XLR): Define.
1209         (INSN_CHIP_MASK): Update.
1210         (CPU_XLR): Define.
1211         (OPCODE_IS_MEMBER): Update.
1212         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1213
1214 2009-01-28  Doug Evans  <dje@google.com>
1215
1216         * opcode/i386.h: Add multiple inclusion protection.
1217         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1218         (EDI_REG_NUM): New macros.
1219         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1220         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1221         (REX_PREFIX_P): New macro.
1222
1223 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
1224
1225         * ppc.h (struct powerpc_opcode): New field "deprecated".
1226         (PPC_OPCODE_NOPOWER4): Delete.
1227
1228 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
1229
1230         * mips.h: Define CPU_R14000, CPU_R16000.
1231         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1232
1233 2008-11-18  Catherine Moore  <clm@codesourcery.com>
1234
1235         * arm.h (FPU_NEON_FP16): New.
1236         (FPU_ARCH_NEON_FP16): New.
1237
1238 2008-11-06  Chao-ying Fu  <fu@mips.com>
1239
1240         * mips.h: Doucument '1' for 5-bit sync type.
1241
1242 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
1243
1244         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
1245         IA64_RS_CR.
1246
1247 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
1248
1249         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1250
1251 2008-07-30  Michael J. Eager  <eager@eagercon.com>
1252
1253         * ppc.h (PPC_OPCODE_405): Define.
1254         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1255
1256 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
1257
1258         * ppc.h (ppc_cpu_t): New typedef.
1259         (struct powerpc_opcode <flags>): Use it.
1260         (struct powerpc_operand <insert, extract>): Likewise.
1261         (struct powerpc_macro <flags>): Likewise.
1262
1263 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
1264
1265         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1266         Update comment before MIPS16 field descriptors to mention MIPS16.
1267         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1268         BBIT.
1269         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1270         New bit masks and shift counts for cins and exts.
1271
1272         * mips.h: Document new field descriptors +Q.
1273         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1274
1275 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
1276
1277         * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1278         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1279
1280 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
1281
1282         * ppc.h: (PPC_OPCODE_E500MC): New.
1283
1284 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
1285
1286         * i386.h (MAX_OPERANDS): Set to 5.
1287         (MAX_MNEM_SIZE): Changed to 20.
1288
1289 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
1290
1291         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1292
1293 2008-03-09  Paul Brook  <paul@codesourcery.com>
1294
1295         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1296
1297 2008-03-04  Paul Brook  <paul@codesourcery.com>
1298
1299         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1300         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1301         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1302
1303 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
1304             Nick Clifton  <nickc@redhat.com>
1305
1306         PR 3134
1307         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1308         with a 32-bit displacement but without the top bit of the 4th byte
1309         set.
1310
1311 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1312
1313         * cr16.h (cr16_num_optab): Declared.
1314
1315 2008-02-14  Hakan Ardo  <hakan@debian.org>
1316
1317         PR gas/2626
1318         * avr.h (AVR_ISA_2xxe): Define.
1319
1320 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
1321
1322         * mips.h: Update copyright.
1323         (INSN_CHIP_MASK): New macro.
1324         (INSN_OCTEON): New macro.
1325         (CPU_OCTEON): New macro.
1326         (OPCODE_IS_MEMBER): Handle Octeon instructions.
1327
1328 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
1329
1330         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1331
1332 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
1333
1334         * avr.h (AVR_ISA_USB162): Add new opcode set.
1335         (AVR_ISA_AVR3): Likewise.
1336
1337 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1338
1339         * mips.h (INSN_LOONGSON_2E): New.
1340         (INSN_LOONGSON_2F): New.
1341         (CPU_LOONGSON_2E): New.
1342         (CPU_LOONGSON_2F): New.
1343         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1344
1345 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
1346
1347         * mips.h (INSN_ISA*): Redefine certain values as an
1348         enumeration.  Update comments.
1349         (mips_isa_table): New.
1350         (ISA_MIPS*): Redefine to match enumeration.
1351         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1352         values.
1353
1354 2007-08-08  Ben Elliston  <bje@au.ibm.com>
1355
1356         * ppc.h (PPC_OPCODE_PPCPS): New.
1357
1358 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
1359
1360         * m68k.h: Document j K & E.
1361
1362 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
1363
1364         * cr16.h: New file for CR16 target.
1365
1366 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
1367
1368         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1369
1370 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
1371
1372         * m68k.h (mcfisa_c): New.
1373         (mcfusp, mcf_mask): Adjust.
1374
1375 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
1376
1377         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1378         (num_powerpc_operands): Declare.
1379         (PPC_OPERAND_SIGNED et al): Redefine as hex.
1380         (PPC_OPERAND_PLUS1): Define.
1381
1382 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
1383
1384         * i386.h (REX_MODE64): Renamed to ...
1385         (REX_W): This.
1386         (REX_EXTX): Renamed to ...
1387         (REX_R): This.
1388         (REX_EXTY): Renamed to ...
1389         (REX_X): This.
1390         (REX_EXTZ): Renamed to ...
1391         (REX_B): This.
1392
1393 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
1394
1395         * i386.h: Add entries from config/tc-i386.h and move tables
1396         to opcodes/i386-opc.h.
1397
1398 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
1399
1400         * i386.h (FloatDR): Removed.
1401         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1402
1403 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
1404
1405         * spu-insns.h: Add soma double-float insns.
1406
1407 2007-02-20  Thiemo Seufer  <ths@mips.com>
1408             Chao-Ying Fu  <fu@mips.com>
1409
1410         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1411         (INSN_DSPR2): Add flag for DSP R2 instructions.
1412         (M_BALIGN): New macro.
1413
1414 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
1415
1416         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1417         and Seg3ShortFrom with Shortform.
1418
1419 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
1420
1421         PR gas/4027
1422         * i386.h (i386_optab): Put the real "test" before the pseudo
1423         one.
1424
1425 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
1426
1427         * m68k.h (m68010up): OR fido_a.
1428
1429 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
1430
1431         * m68k.h (fido_a): New.
1432
1433 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
1434
1435         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1436         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1437         values.
1438
1439 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
1440
1441         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1442
1443 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
1444
1445         * score-inst.h (enum score_insn_type): Add Insn_internal.
1446
1447 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
1448             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
1449             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
1450             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
1451             Alan Modra  <amodra@bigpond.net.au>
1452
1453         * spu-insns.h: New file.
1454         * spu.h: New file.
1455
1456 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
1457
1458         * ppc.h (PPC_OPCODE_CELL): Define.
1459
1460 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
1461
1462         * i386.h :  Modify opcode to support for the change in POPCNT opcode
1463         in amdfam10 architecture.
1464
1465 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
1466
1467         * i386.h: Replace CpuMNI with CpuSSSE3.
1468
1469 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
1470             Joseph Myers  <joseph@codesourcery.com>
1471             Ian Lance Taylor  <ian@wasabisystems.com>
1472             Ben Elliston  <bje@wasabisystems.com>
1473
1474         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1475
1476 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
1477
1478         * score-datadep.h: New file.
1479         * score-inst.h: New file.
1480
1481 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
1482
1483         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1484         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1485         movdq2q and movq2dq.
1486
1487 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
1488            Michael Meissner             <michael.meissner@amd.com>
1489
1490         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1491
1492 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1493
1494         * i386.h (i386_optab): Add "nop" with memory reference.
1495
1496 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
1497
1498         * i386.h (i386_optab): Update comment for 64bit NOP.
1499
1500 2006-06-06  Ben Elliston  <bje@au.ibm.com>
1501             Anton Blanchard  <anton@samba.org>
1502
1503         * ppc.h (PPC_OPCODE_POWER6): Define.
1504         Adjust whitespace.
1505
1506 2006-06-05  Thiemo Seufer  <ths@mips.com>
1507
1508         * mips.h: Improve description of MT flags.
1509
1510 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
1511
1512         * m68k.h (mcf_mask): Define.
1513
1514 2006-05-05  Thiemo Seufer  <ths@mips.com>
1515             David Ung  <davidu@mips.com>
1516
1517         * mips.h (enum): Add macro M_CACHE_AB.
1518
1519 2006-05-04  Thiemo Seufer  <ths@mips.com>
1520             Nigel Stephens  <nigel@mips.com>
1521             David Ung  <davidu@mips.com>
1522
1523         * mips.h: Add INSN_SMARTMIPS define.
1524
1525 2006-04-30  Thiemo Seufer  <ths@mips.com>
1526             David Ung  <davidu@mips.com>
1527
1528         * mips.h: Defines udi bits and masks.  Add description of
1529         characters which may appear in the args field of udi
1530         instructions.
1531
1532 2006-04-26  Thiemo Seufer  <ths@networkno.de>
1533
1534         * mips.h: Improve comments describing the bitfield instruction
1535         fields.
1536
1537 2006-04-26  Julian Brown  <julian@codesourcery.com>
1538
1539         * arm.h (FPU_VFP_EXT_V3): Define constant.
1540         (FPU_NEON_EXT_V1): Likewise.
1541         (FPU_VFP_HARD): Update.
1542         (FPU_VFP_V3): Define macro.
1543         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1544
1545 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
1546
1547         * avr.h (AVR_ISA_PWMx): New.
1548
1549 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
1550
1551         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1552         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1553         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1554         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1555         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1556
1557 2006-03-10  Paul Brook  <paul@codesourcery.com>
1558
1559         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1560
1561 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1562
1563         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1564         first.  Correct mask of bb "B" opcode.
1565
1566 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
1567
1568         * i386.h (i386_optab): Support Intel Merom New Instructions.
1569
1570 2006-02-24  Paul Brook  <paul@codesourcery.com>
1571
1572         * arm.h: Add V7 feature bits.
1573
1574 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
1575
1576         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1577
1578 2006-01-31  Paul Brook  <paul@codesourcery.com>
1579         Richard Earnshaw <rearnsha@arm.com>
1580
1581         * arm.h: Use ARM_CPU_FEATURE.
1582         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1583         (arm_feature_set): Change to a structure.
1584         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1585         ARM_FEATURE): New macros.
1586
1587 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
1588
1589         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1590         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1591         (ADD_PC_INCR_OPCODE): Don't define.
1592
1593 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
1594
1595         PR gas/1874
1596         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1597
1598 2005-11-14  David Ung  <davidu@mips.com>
1599
1600         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1601         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1602         save/restore encoding of the args field.
1603
1604 2005-10-28  Dave Brolley  <brolley@redhat.com>
1605
1606         Contribute the following changes:
1607         2005-02-16  Dave Brolley  <brolley@redhat.com>
1608
1609         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1610         cgen_isa_mask_* to cgen_bitset_*.
1611         * cgen.h: Likewise.
1612
1613         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
1614
1615         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1616         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1617         (CGEN_CPU_TABLE): Make isas a ponter.
1618
1619         2003-09-29  Dave Brolley  <brolley@redhat.com>
1620
1621         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1622         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1623         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1624
1625         2002-12-13  Dave Brolley  <brolley@redhat.com>
1626
1627         * cgen.h (symcat.h): #include it.
1628         (cgen-bitset.h): #include it.
1629         (CGEN_ATTR_VALUE_TYPE): Now a union.
1630         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1631         (CGEN_ATTR_ENTRY): 'value' now unsigned.
1632         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1633         * cgen-bitset.h: New file.
1634
1635 2005-09-30  Catherine Moore  <clm@cm00re.com>
1636
1637         * bfin.h: New file.
1638
1639 2005-10-24  Jan Beulich  <jbeulich@novell.com>
1640
1641         * ia64.h (enum ia64_opnd): Move memory operand out of set of
1642         indirect operands.
1643
1644 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1645
1646         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
1647         Add FLAG_STRICT to pa10 ftest opcode.
1648
1649 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1650
1651         * hppa.h (pa_opcodes): Remove lha entries.
1652
1653 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1654
1655         * hppa.h (FLAG_STRICT): Revise comment.
1656         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
1657         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
1658         entries for "fdc".
1659
1660 2005-09-30  Catherine Moore  <clm@cm00re.com>
1661
1662         * bfin.h: New file.
1663
1664 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1665
1666         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1667
1668 2005-09-06  Chao-ying Fu  <fu@mips.com>
1669
1670         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1671         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1672         define.
1673         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1674         (INSN_ASE_MASK): Update to include INSN_MT.
1675         (INSN_MT): New define for MT ASE.
1676
1677 2005-08-25  Chao-ying Fu  <fu@mips.com>
1678
1679         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1680         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1681         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1682         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1683         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1684         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1685         instructions.
1686         (INSN_DSP): New define for DSP ASE.
1687
1688 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
1689
1690         * a29k.h: Delete.
1691
1692 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
1693
1694         * ppc.h (PPC_OPCODE_E300): Define.
1695
1696 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
1697
1698         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1699
1700 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1701
1702         PR gas/336
1703         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1704         and pitlb.
1705
1706 2005-07-27  Jan Beulich  <jbeulich@novell.com>
1707
1708         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1709         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1710         Add movq-s as 64-bit variants of movd-s.
1711
1712 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1713
1714         * hppa.h: Fix punctuation in comment.
1715
1716         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
1717         implicit space-register addressing.  Set space-register bits on opcodes
1718         using implicit space-register addressing.  Add various missing pa20
1719         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
1720         space-register addressing.  Use "fE" instead of "fe" in various
1721         fstw opcodes.
1722
1723 2005-07-18  Jan Beulich  <jbeulich@novell.com>
1724
1725         * i386.h (i386_optab): Operands of aam and aad are unsigned.
1726
1727 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
1728
1729         * i386.h (i386_optab): Support Intel VMX Instructions.
1730
1731 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1732
1733         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1734
1735 2005-07-05  Jan Beulich  <jbeulich@novell.com>
1736
1737         * i386.h (i386_optab): Add new insns.
1738
1739 2005-07-01  Nick Clifton  <nickc@redhat.com>
1740
1741         * sparc.h: Add typedefs to structure declarations.
1742
1743 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
1744
1745         PR 1013
1746         * i386.h (i386_optab): Update comments for 64bit addressing on
1747         mov. Allow 64bit addressing for mov and movq.
1748
1749 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1750
1751         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1752         respectively, in various floating-point load and store patterns.
1753
1754 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
1755
1756         * hppa.h (FLAG_STRICT): Correct comment.
1757         (pa_opcodes): Update load and store entries to allow both PA 1.X and
1758         PA 2.0 mneumonics when equivalent.  Entries with cache control
1759         completers now require PA 1.1.  Adjust whitespace.
1760
1761 2005-05-19  Anton Blanchard  <anton@samba.org>
1762
1763         * ppc.h (PPC_OPCODE_POWER5): Define.
1764
1765 2005-05-10  Nick Clifton  <nickc@redhat.com>
1766
1767         * Update the address and phone number of the FSF organization in
1768         the GPL notices in the following files:
1769         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1770         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1771         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1772         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1773         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1774         tic54x.h, tic80.h, v850.h, vax.h
1775
1776 2005-05-09  Jan Beulich  <jbeulich@novell.com>
1777
1778         * i386.h (i386_optab): Add ht and hnt.
1779
1780 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
1781
1782         * i386.h: Insert hyphens into selected VIA PadLock extensions.
1783         Add xcrypt-ctr.  Provide aliases without hyphens.
1784
1785 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
1786
1787         Moved from ../ChangeLog
1788
1789         2005-04-12  Paul Brook  <paul@codesourcery.com>
1790         * m88k.h: Rename psr macros to avoid conflicts.
1791
1792         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
1793         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1794         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1795         and ARM_ARCH_V6ZKT2.
1796
1797         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
1798         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1799         Remove redundant instruction types.
1800         (struct argument): X_op - new field.
1801         (struct cst4_entry): Remove.
1802         (no_op_insn): Declare.
1803
1804         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
1805         * crx.h (enum argtype): Rename types, remove unused types.
1806
1807         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
1808         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1809         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1810         (enum operand_type): Rearrange operands, edit comments.
1811         replace us<N> with ui<N> for unsigned immediate.
1812         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1813         displacements (respectively).
1814         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1815         (instruction type): Add NO_TYPE_INS.
1816         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1817         (operand_entry): New field - 'flags'.
1818         (operand flags): New.
1819
1820         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
1821         * crx.h (operand_type): Remove redundant types i3, i4,
1822         i5, i8, i12.
1823         Add new unsigned immediate types us3, us4, us5, us16.
1824
1825 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1826
1827         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1828         adjust them accordingly.
1829
1830 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1831
1832         * i386.h (i386_optab): Add rdtscp.
1833
1834 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1835
1836         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1837         between memory and segment register. Allow movq for moving between
1838         general-purpose register and segment register.
1839
1840 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1841
1842         PR gas/707
1843         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1844         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1845         fnstsw.
1846
1847 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1848
1849         * m68k.h (m68008, m68ec030, m68882): Remove.
1850         (m68k_mask): New.
1851         (cpu_m68k, cpu_cf): New.
1852         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1853         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1854
1855 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1856
1857         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1858         * cgen.h (enum cgen_parse_operand_type): Add
1859         CGEN_PARSE_OPERAND_SYMBOLIC.
1860
1861 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1862
1863         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1864         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1865         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1866
1867 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1868
1869         * mips.h (struct mips_opcode): Add new pinfo2 member.
1870         (INSN_ALIAS): New define for opcode table entries that are
1871         specific instances of another entry, such as 'move' for an 'or'
1872         with a zero operand.
1873         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1874         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1875
1876 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1877
1878         * mips.h (CPU_RM9000): Define.
1879         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1880
1881 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1882
1883         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1884         to/from test registers are illegal in 64-bit mode. Add missing
1885         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1886         (previously one had to explicitly encode a rex64 prefix). Re-enable
1887         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1888         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1889
1890 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1891
1892         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1893         available only with SSE2. Change the MMX additions introduced by SSE
1894         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1895         instructions by their now designated identifier (since combining i686
1896         and 3DNow! does not really imply 3DNow!A).
1897
1898 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1899
1900         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1901         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1902
1903 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1904             Vineet Sharma      <vineets@noida.hcltech.com>
1905
1906         * maxq.h: New file: Disassembly information for the maxq port.
1907
1908 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1909
1910         * i386.h (i386_optab): Put back "movzb".
1911
1912 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1913
1914         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1915         comments.  Remove member cris_ver_sim.  Add members
1916         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1917         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1918         (struct cris_support_reg, struct cris_cond15): New types.
1919         (cris_conds15): Declare.
1920         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1921         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1922         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1923         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1924         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1925         SIZE_FIELD_UNSIGNED.
1926
1927 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1928
1929         * i386.h (sldx_Suf): Remove.
1930         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1931         (q_FP): Define, implying no REX64.
1932         (x_FP, sl_FP): Imply FloatMF.
1933         (i386_optab): Split reg and mem forms of moving from segment registers
1934         so that the memory forms can ignore the 16-/32-bit operand size
1935         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1936         all non-floating-point instructions. Unite 32- and 64-bit forms of
1937         movsx, movzx, and movd. Adjust floating point operations for the above
1938         changes to the *FP macros. Add DefaultSize to floating point control
1939         insns operating on larger memory ranges. Remove left over comments
1940         hinting at certain insns being Intel-syntax ones where the ones
1941         actually meant are already gone.
1942
1943 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1944
1945         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1946         instruction type.
1947
1948 2004-09-30  Paul Brook  <paul@codesourcery.com>
1949
1950         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1951         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1952
1953 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1954
1955         * avr.h: Add support for
1956         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1957
1958 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1959
1960         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1961
1962 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1963
1964         * msp430.h (msp430_opc): Add new instructions.
1965         (msp430_rcodes): Declare new instructions.
1966         (msp430_hcodes): Likewise..
1967
1968 2004-08-13  Nick Clifton  <nickc@redhat.com>
1969
1970         PR/301
1971         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1972         processors.
1973
1974 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1975
1976         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1977
1978 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1979
1980         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1981
1982 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1983
1984         * i386.h: Adjust instruction descriptions to better match the
1985         specification.
1986
1987 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1988
1989         * arm.h: Remove all old content.  Replace with architecture defines
1990         from gas/config/tc-arm.c.
1991
1992 2004-07-09  Andreas Schwab  <schwab@suse.de>
1993
1994         * m68k.h: Fix comment.
1995
1996 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1997
1998         * crx.h: New file.
1999
2000 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
2001
2002         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2003
2004 2004-05-24  Peter Barada  <peter@the-baradas.com>
2005
2006         * m68k.h: Add 'size' to m68k_opcode.
2007
2008 2004-05-05  Peter Barada  <peter@the-baradas.com>
2009
2010         * m68k.h: Switch from ColdFire chip name to core variant.
2011
2012 2004-04-22  Peter Barada  <peter@the-baradas.com>
2013
2014         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
2015         descriptions for new EMAC cases.
2016         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2017         handle Motorola MAC syntax.
2018         Allow disassembly of ColdFire V4e object files.
2019
2020 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
2021
2022         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
2023
2024 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
2025
2026         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2027
2028 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
2029
2030         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2031
2032 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
2033
2034         * i386.h (i386_optab): Added xstore/xcrypt insns.
2035
2036 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2037
2038         * h8300.h (32bit ldc/stc): Add relaxing support.
2039
2040 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
2041
2042         * h8300.h (BITOP): Pass MEMRELAX flag.
2043
2044 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
2045
2046         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2047         except for the H8S.
2048
2049 For older changes see ChangeLog-9103
2050 \f
2051 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2052
2053 Copying and distribution of this file, with or without modification,
2054 are permitted in any medium without royalty provided the copyright
2055 notice and this notice are preserved.
2056
2057 Local Variables:
2058 mode: change-log
2059 left-margin: 8
2060 fill-column: 74
2061 version-control: never
2062 End: