include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2021 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8           (1ULL << 0) /* All processors.  */
  41 #define AARCH64_FEATURE_V8_6         (1ULL << 1) /* ARMv8.6 processors.  */
  42 #define AARCH64_FEATURE_BFLOAT16     (1ULL << 2) /* Bfloat16 insns.  */
  43 #define AARCH64_FEATURE_V8_A         (1ULL << 3) /* Armv8-A processors.  */
  44 #define AARCH64_FEATURE_SVE2         (1ULL << 4) /* SVE2 instructions.  */
  45 #define AARCH64_FEATURE_V8_2         (1ULL << 5) /* ARMv8.2 processors.  */
  46 #define AARCH64_FEATURE_V8_3         (1ULL << 6) /* ARMv8.3 processors.  */
  47 #define AARCH64_FEATURE_SVE2_AES     (1ULL << 7)
  48 #define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
  49 #define AARCH64_FEATURE_SVE2_SM4     (1ULL << 9)
  50 #define AARCH64_FEATURE_SVE2_SHA3    (1ULL << 10)
  51 #define AARCH64_FEATURE_V8_4         (1ULL << 11) /* ARMv8.4 processors.  */
  52 #define AARCH64_FEATURE_V8_R         (1ULL << 12) /* Armv8-R processors.  */
  53 #define AARCH64_FEATURE_V8_7         (1ULL << 13) /* Armv8.7 processors.  */
  54 #define AARCH64_FEATURE_CSRE         (1ULL << 14) /* CSRE feature.  */
  55 #define AARCH64_FEATURE_LS64         (1ULL << 15) /* Atomic 64-byte load/store.  */
  56 #define AARCH64_FEATURE_PAC          (1ULL << 16) /* v8.3 Pointer Authentication.  */
  57 #define AARCH64_FEATURE_FP           (1ULL << 17) /* FP instructions.  */
  58 #define AARCH64_FEATURE_SIMD         (1ULL << 18) /* SIMD instructions.  */
  59 #define AARCH64_FEATURE_CRC          (1ULL << 19) /* CRC instructions.  */
  60 #define AARCH64_FEATURE_LSE          (1ULL << 20) /* LSE instructions.  */
  61 #define AARCH64_FEATURE_PAN          (1ULL << 21) /* PAN instructions.  */
  62 #define AARCH64_FEATURE_LOR          (1ULL << 22) /* LOR instructions.  */
  63 #define AARCH64_FEATURE_RDMA         (1ULL << 23) /* v8.1 SIMD instructions.  */
  64 #define AARCH64_FEATURE_V8_1         (1ULL << 24) /* v8.1 features.  */
  65 #define AARCH64_FEATURE_F16          (1ULL << 25) /* v8.2 FP16 instructions.  */
  66 #define AARCH64_FEATURE_RAS          (1ULL << 26) /* RAS Extensions.  */
  67 #define AARCH64_FEATURE_PROFILE      (1ULL << 27) /* Statistical Profiling.  */
  68 #define AARCH64_FEATURE_SVE          (1ULL << 28) /* SVE instructions.  */
  69 #define AARCH64_FEATURE_RCPC         (1ULL << 29) /* RCPC instructions.  */
  70 #define AARCH64_FEATURE_COMPNUM      (1ULL << 30) /* Complex # instructions.  */
  71 #define AARCH64_FEATURE_DOTPROD      (1ULL << 31) /* Dot Product instructions.  */
  72 #define AARCH64_FEATURE_SM4          (1ULL << 32) /* SM3 & SM4 instructions.  */
  73 #define AARCH64_FEATURE_SHA2         (1ULL << 33) /* SHA2 instructions.  */
  74 #define AARCH64_FEATURE_SHA3         (1ULL << 34) /* SHA3 instructions.  */
  75 #define AARCH64_FEATURE_AES          (1ULL << 35) /* AES instructions.  */
  76 #define AARCH64_FEATURE_F16_FML      (1ULL << 36) /* v8.2 FP16FML ins.  */
  77 #define AARCH64_FEATURE_V8_5         (1ULL << 37) /* ARMv8.5 processors.  */
  78 #define AARCH64_FEATURE_FLAGMANIP    (1ULL << 38) /* v8.5 Flag Manipulation version 2.  */
  79 #define AARCH64_FEATURE_FRINTTS      (1ULL << 39) /* FRINT[32,64][Z,X] insns.  */
  80 #define AARCH64_FEATURE_SB           (1ULL << 40) /* SB instruction.  */
  81 #define AARCH64_FEATURE_PREDRES      (1ULL << 41) /* Execution and Data Prediction Restriction instructions.  */
  82 #define AARCH64_FEATURE_CVADP        (1ULL << 42) /* DC CVADP.  */
  83 #define AARCH64_FEATURE_RNG          (1ULL << 43) /* Random Number instructions.  */
  84 #define AARCH64_FEATURE_BTI          (1ULL << 44) /* BTI instructions.  */
  85 #define AARCH64_FEATURE_SCXTNUM      (1ULL << 45) /* SCXTNUM_ELx.  */
  86 #define AARCH64_FEATURE_ID_PFR2      (1ULL << 46) /* ID_PFR2 instructions.  */
  87 #define AARCH64_FEATURE_SSBS         (1ULL << 47) /* SSBS mechanism enabled.  */
  88 #define AARCH64_FEATURE_MEMTAG       (1ULL << 48) /* Memory Tagging Extension.  */
  89 #define AARCH64_FEATURE_TME          (1ULL << 49) /* Transactional Memory Extension.  */
  90 #define AARCH64_FEATURE_I8MM         (1ULL << 52) /* Matrix Multiply instructions.  */
  91 #define AARCH64_FEATURE_F32MM        (1ULL << 53)
  92 #define AARCH64_FEATURE_F64MM        (1ULL << 54)
  93 #define AARCH64_FEATURE_FLAGM        (1ULL << 55) /* v8.4 Flag Manipulation.  */
  94
  95 /* Crypto instructions are the combination of AES and SHA2.  */
  96 #define AARCH64_FEATURE_CRYPTO  (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
  97
  98 /* Architectures are the sum of the base and extensions.  */
  99 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
 100                                                  AARCH64_FEATURE_V8_A \
 101                                                  | AARCH64_FEATURE_FP  \
 102                                                  | AARCH64_FEATURE_RAS \
 103                                                  | AARCH64_FEATURE_SIMD)
 104 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 105                                                  AARCH64_FEATURE_CRC    \
 106                                                  | AARCH64_FEATURE_V8_1 \
 107                                                  | AARCH64_FEATURE_LSE  \
 108                                                  | AARCH64_FEATURE_PAN  \
 109                                                  | AARCH64_FEATURE_LOR  \
 110                                                  | AARCH64_FEATURE_RDMA)
 111 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 112                                                  AARCH64_FEATURE_V8_2)
 113 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 114                                                  AARCH64_FEATURE_V8_3   \
 115                                                  | AARCH64_FEATURE_PAC  \
 116                                                  | AARCH64_FEATURE_RCPC \
 117                                                  | AARCH64_FEATURE_COMPNUM)
 118 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 119                                                  AARCH64_FEATURE_V8_4   \
 120                                                  | AARCH64_FEATURE_DOTPROD \
 121                                                  | AARCH64_FEATURE_FLAGM \
 122                                                  | AARCH64_FEATURE_F16_FML)
 123 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 124                                                  AARCH64_FEATURE_V8_5   \
 125                                                  | AARCH64_FEATURE_FLAGMANIP \
 126                                                  | AARCH64_FEATURE_FRINTTS \
 127                                                  | AARCH64_FEATURE_SB   \
 128                                                  | AARCH64_FEATURE_PREDRES \
 129                                                  | AARCH64_FEATURE_CVADP \
 130                                                  | AARCH64_FEATURE_BTI  \
 131                                                  | AARCH64_FEATURE_SCXTNUM \
 132                                                  | AARCH64_FEATURE_ID_PFR2 \
 133                                                  | AARCH64_FEATURE_SSBS)
 134 #define AARCH64_ARCH_V8_6       AARCH64_FEATURE (AARCH64_ARCH_V8_5,     \
 135                                                  AARCH64_FEATURE_V8_6   \
 136                                                  | AARCH64_FEATURE_BFLOAT16 \
 137                                                  | AARCH64_FEATURE_I8MM)
 138 #define AARCH64_ARCH_V8_7       AARCH64_FEATURE (AARCH64_ARCH_V8_6,     \
 139                                                  AARCH64_FEATURE_V8_7   \
 140                                                  | AARCH64_FEATURE_LS64)
 141 #define AARCH64_ARCH_V8_R       (AARCH64_FEATURE (AARCH64_ARCH_V8_4,    \
 142                                                  AARCH64_FEATURE_V8_R)  \
 143                               & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
 144
 145 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 146 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 147
 148 /* CPU-specific features.  */
 149 typedef unsigned long long aarch64_feature_set;
 150
 151 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 152   ((~(CPU) & (FEAT)) == 0)
 153
 154 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 155   (((CPU) & (FEAT)) != 0)
 156
 157 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 158   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 159
 160 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 161   do                                            \
 162     {                                           \
 163       (TARG) = (F1) | (F2);                     \
 164     }                                           \
 165   while (0)
 166
 167 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 168   do                                            \
 169     {                                           \
 170       (TARG) = (F1) &~ (F2);                    \
 171     }                                           \
 172   while (0)
 173
 174 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 175
 176 enum aarch64_operand_class
 177 {
 178   AARCH64_OPND_CLASS_NIL,
 179   AARCH64_OPND_CLASS_INT_REG,
 180   AARCH64_OPND_CLASS_MODIFIED_REG,
 181   AARCH64_OPND_CLASS_FP_REG,
 182   AARCH64_OPND_CLASS_SIMD_REG,
 183   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 184   AARCH64_OPND_CLASS_SISD_REG,
 185   AARCH64_OPND_CLASS_SIMD_REGLIST,
 186   AARCH64_OPND_CLASS_SVE_REG,
 187   AARCH64_OPND_CLASS_PRED_REG,
 188   AARCH64_OPND_CLASS_ADDRESS,
 189   AARCH64_OPND_CLASS_IMMEDIATE,
 190   AARCH64_OPND_CLASS_SYSTEM,
 191   AARCH64_OPND_CLASS_COND,
 192 };
 193
 194 /* Operand code that helps both parsing and coding.
 195    Keep AARCH64_OPERANDS synced.  */
 196
 197 enum aarch64_opnd
 198 {
 199   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 200
 201   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 202   AARCH64_OPND_Rn,      /* Integer register as source.  */
 203   AARCH64_OPND_Rm,      /* Integer register as source.  */
 204   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 205   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 206   AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions.  */
 207   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 208   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 209   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 210   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 211
 212   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 213   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 214   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 215   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 216   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 217   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 218
 219   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 220   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 221   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 222   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 223   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 224   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 225
 226   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 227   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 228   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 229
 230   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 231   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 232   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 233   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 234   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 235   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 236   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 237   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 238   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 239   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 240                            qualifier is S_H.  */
 241   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 242   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 243   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 244                            structure to all lanes.  */
 245   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 246
 247   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 248   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 249
 250   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 251   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 252   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 253   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 254   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 255   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 256   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 257   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 258                            (no encoding).  */
 259   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 260   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 261   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 262   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 263   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 264   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 265   AARCH64_OPND_IMM,     /* Immediate.  */
 266   AARCH64_OPND_IMM_2,   /* Immediate.  */
 267   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 268   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 269   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 270   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 271   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 272   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 273   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 274   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 275   AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
 276   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 277   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 278   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 279                            each condition flag.  */
 280
 281   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 282   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 283   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 284   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 285   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 286   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 287   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 288   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 289
 290   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 291   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 292
 293   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 294   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 295   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 296   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 297   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 298
 299   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 300   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 301   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 302   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 303   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 304                                    negative or unaligned and there is
 305                                    no writeback allowed.  This operand code
 306                                    is only used to support the programmer-
 307                                    friendly feature of using LDR/STR as the
 308                                    the mnemonic name for LDUR/STUR instructions
 309                                    wherever there is no ambiguity.  */
 310   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 311   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 312                                    16) immediate.  */
 313   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 314   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 315                                    16) immediate.  */
 316   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 317   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 318   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 319
 320   AARCH64_OPND_SYSREG,          /* System register operand.  */
 321   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 322   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 323   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 324   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 325   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 326   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 327   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 328   AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant.  */
 329   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 330   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 331   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 332   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 333
 334   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 335   AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
 336   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 337   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 338   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 339   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 340   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 341   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 342   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 343   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 344   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 345   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 346   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 347   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 348   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 349   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 350   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 351   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 352   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 353   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 354   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 355   AARCH64_OPND_SVE_ADDR_ZX,         /* SVE [Zn.<T>{, <Xm>}].  */
 356   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 357   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 358   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 359   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 360   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 361                                        Bit 14 controls S/U choice.  */
 362   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 363                                        Bit 22 controls S/U choice.  */
 364   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 365                                        Bit 14 controls S/U choice.  */
 366   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 367                                        Bit 22 controls S/U choice.  */
 368   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 369                                        Bit 14 controls S/U choice.  */
 370   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 371                                        Bit 22 controls S/U choice.  */
 372   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 373                                        Bit 14 controls S/U choice.  */
 374   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 375                                        Bit 22 controls S/U choice.  */
 376   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 377   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 378   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 379   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 380   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 381   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 382   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 383   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 384   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 385   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 386   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 387   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 388   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 389   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 390   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 391   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 392   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 393   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 394   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 395   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 396   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 397   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 398   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 399   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 400   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 401   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 402   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 403   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 404   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 405   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 406   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 407   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 408   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 409   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 410   AARCH64_OPND_SVE_SHLIMM_UNPRED_22,    /* SVE 3 bit shift left unpred.  */
 411   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 412   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 413   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,    /* SVE 3 bit shift right unpred.  */
 414   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 415   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 416   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 417   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 418   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 419   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 420   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 421   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 422   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 423   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 424   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 425   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 426   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 427   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 428   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 429   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 430   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 431   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 432   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 433   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
 434   AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
 435   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 436   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 437   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 438   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 439   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 440   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 441   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 442   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 443   AARCH64_OPND_CSRE_CSR,        /* CSRE CSR instruction Rt field.  */
 444 };
 445
 446 /* Qualifier constrains an operand.  It either specifies a variant of an
 447    operand type or limits values available to an operand type.
 448
 449    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 450
 451 enum aarch64_opnd_qualifier
 452 {
 453   /* Indicating no further qualification on an operand.  */
 454   AARCH64_OPND_QLF_NIL,
 455
 456   /* Qualifying an operand which is a general purpose (integer) register;
 457      indicating the operand data size or a specific register.  */
 458   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 459   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 460   AARCH64_OPND_QLF_WSP, /* WSP.  */
 461   AARCH64_OPND_QLF_SP,  /* SP.  */
 462
 463   /* Qualifying an operand which is a floating-point register, a SIMD
 464      vector element or a SIMD vector element list; indicating operand data
 465      size or the size of each SIMD vector element in the case of a SIMD
 466      vector element list.
 467      These qualifiers are also used to qualify an address operand to
 468      indicate the size of data element a load/store instruction is
 469      accessing.
 470      They are also used for the immediate shift operand in e.g. SSHR.  Such
 471      a use is only for the ease of operand encoding/decoding and qualifier
 472      sequence matching; such a use should not be applied widely; use the value
 473      constraint qualifiers for immediate operands wherever possible.  */
 474   AARCH64_OPND_QLF_S_B,
 475   AARCH64_OPND_QLF_S_H,
 476   AARCH64_OPND_QLF_S_S,
 477   AARCH64_OPND_QLF_S_D,
 478   AARCH64_OPND_QLF_S_Q,
 479   /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
 480      or 2 x 2 byte are selected by the instruction.  Other than that they have
 481      no difference with AARCH64_OPND_QLF_S_B in encoding.  They are here purely
 482      for syntactical reasons and is an exception from normal AArch64
 483      disassembly scheme.  */
 484   AARCH64_OPND_QLF_S_4B,
 485   AARCH64_OPND_QLF_S_2H,
 486
 487   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 488      register list; indicating register shape.
 489      They are also used for the immediate shift operand in e.g. SSHR.  Such
 490      a use is only for the ease of operand encoding/decoding and qualifier
 491      sequence matching; such a use should not be applied widely; use the value
 492      constraint qualifiers for immediate operands wherever possible.  */
 493   AARCH64_OPND_QLF_V_4B,
 494   AARCH64_OPND_QLF_V_8B,
 495   AARCH64_OPND_QLF_V_16B,
 496   AARCH64_OPND_QLF_V_2H,
 497   AARCH64_OPND_QLF_V_4H,
 498   AARCH64_OPND_QLF_V_8H,
 499   AARCH64_OPND_QLF_V_2S,
 500   AARCH64_OPND_QLF_V_4S,
 501   AARCH64_OPND_QLF_V_1D,
 502   AARCH64_OPND_QLF_V_2D,
 503   AARCH64_OPND_QLF_V_1Q,
 504
 505   AARCH64_OPND_QLF_P_Z,
 506   AARCH64_OPND_QLF_P_M,
 507
 508   /* Used in scaled signed immediate that are scaled by a Tag granule
 509      like in stg, st2g, etc.   */
 510   AARCH64_OPND_QLF_imm_tag,
 511
 512   /* Constraint on value.  */
 513   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 514   AARCH64_OPND_QLF_imm_0_7,
 515   AARCH64_OPND_QLF_imm_0_15,
 516   AARCH64_OPND_QLF_imm_0_31,
 517   AARCH64_OPND_QLF_imm_0_63,
 518   AARCH64_OPND_QLF_imm_1_32,
 519   AARCH64_OPND_QLF_imm_1_64,
 520
 521   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 522      or shift-ones.  */
 523   AARCH64_OPND_QLF_LSL,
 524   AARCH64_OPND_QLF_MSL,
 525
 526   /* Special qualifier helping retrieve qualifier information during the
 527      decoding time (currently not in use).  */
 528   AARCH64_OPND_QLF_RETRIEVE,
 529 };
 530 \f
 531 /* Instruction class.  */
 532
 533 enum aarch64_insn_class
 534 {
 535   aarch64_misc,
 536   addsub_carry,
 537   addsub_ext,
 538   addsub_imm,
 539   addsub_shift,
 540   asimdall,
 541   asimddiff,
 542   asimdelem,
 543   asimdext,
 544   asimdimm,
 545   asimdins,
 546   asimdmisc,
 547   asimdperm,
 548   asimdsame,
 549   asimdshf,
 550   asimdtbl,
 551   asisddiff,
 552   asisdelem,
 553   asisdlse,
 554   asisdlsep,
 555   asisdlso,
 556   asisdlsop,
 557   asisdmisc,
 558   asisdone,
 559   asisdpair,
 560   asisdsame,
 561   asisdshf,
 562   bitfield,
 563   branch_imm,
 564   branch_reg,
 565   compbranch,
 566   condbranch,
 567   condcmp_imm,
 568   condcmp_reg,
 569   condsel,
 570   cryptoaes,
 571   cryptosha2,
 572   cryptosha3,
 573   dp_1src,
 574   dp_2src,
 575   dp_3src,
 576   exception,
 577   extract,
 578   float2fix,
 579   float2int,
 580   floatccmp,
 581   floatcmp,
 582   floatdp1,
 583   floatdp2,
 584   floatdp3,
 585   floatimm,
 586   floatsel,
 587   ldst_immpost,
 588   ldst_immpre,
 589   ldst_imm9,    /* immpost or immpre */
 590   ldst_imm10,   /* LDRAA/LDRAB */
 591   ldst_pos,
 592   ldst_regoff,
 593   ldst_unpriv,
 594   ldst_unscaled,
 595   ldstexcl,
 596   ldstnapair_offs,
 597   ldstpair_off,
 598   ldstpair_indexed,
 599   loadlit,
 600   log_imm,
 601   log_shift,
 602   lse_atomic,
 603   movewide,
 604   pcreladdr,
 605   ic_system,
 606   sve_cpy,
 607   sve_index,
 608   sve_limm,
 609   sve_misc,
 610   sve_movprfx,
 611   sve_pred_zm,
 612   sve_shift_pred,
 613   sve_shift_unpred,
 614   sve_size_bhs,
 615   sve_size_bhsd,
 616   sve_size_hsd,
 617   sve_size_hsd2,
 618   sve_size_sd,
 619   sve_size_bh,
 620   sve_size_sd2,
 621   sve_size_13,
 622   sve_shift_tsz_hsd,
 623   sve_shift_tsz_bhsd,
 624   sve_size_tsz_bhs,
 625   testbranch,
 626   cryptosm3,
 627   cryptosm4,
 628   dotproduct,
 629   bfloat16,
 630 };
 631
 632 /* Opcode enumerators.  */
 633
 634 enum aarch64_op
 635 {
 636   OP_NIL,
 637   OP_STRB_POS,
 638   OP_LDRB_POS,
 639   OP_LDRSB_POS,
 640   OP_STRH_POS,
 641   OP_LDRH_POS,
 642   OP_LDRSH_POS,
 643   OP_STR_POS,
 644   OP_LDR_POS,
 645   OP_STRF_POS,
 646   OP_LDRF_POS,
 647   OP_LDRSW_POS,
 648   OP_PRFM_POS,
 649
 650   OP_STURB,
 651   OP_LDURB,
 652   OP_LDURSB,
 653   OP_STURH,
 654   OP_LDURH,
 655   OP_LDURSH,
 656   OP_STUR,
 657   OP_LDUR,
 658   OP_STURV,
 659   OP_LDURV,
 660   OP_LDURSW,
 661   OP_PRFUM,
 662
 663   OP_LDR_LIT,
 664   OP_LDRV_LIT,
 665   OP_LDRSW_LIT,
 666   OP_PRFM_LIT,
 667
 668   OP_ADD,
 669   OP_B,
 670   OP_BL,
 671
 672   OP_MOVN,
 673   OP_MOVZ,
 674   OP_MOVK,
 675
 676   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 677   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 678   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 679
 680   OP_MOV_V,             /* MOV alias for moving vector register.  */
 681
 682   OP_ASR_IMM,
 683   OP_LSR_IMM,
 684   OP_LSL_IMM,
 685
 686   OP_BIC,
 687
 688   OP_UBFX,
 689   OP_BFXIL,
 690   OP_SBFX,
 691   OP_SBFIZ,
 692   OP_BFI,
 693   OP_BFC,               /* ARMv8.2.  */
 694   OP_UBFIZ,
 695   OP_UXTB,
 696   OP_UXTH,
 697   OP_UXTW,
 698
 699   OP_CINC,
 700   OP_CINV,
 701   OP_CNEG,
 702   OP_CSET,
 703   OP_CSETM,
 704
 705   OP_FCVT,
 706   OP_FCVTN,
 707   OP_FCVTN2,
 708   OP_FCVTL,
 709   OP_FCVTL2,
 710   OP_FCVTXN_S,          /* Scalar version.  */
 711
 712   OP_ROR_IMM,
 713
 714   OP_SXTL,
 715   OP_SXTL2,
 716   OP_UXTL,
 717   OP_UXTL2,
 718
 719   OP_MOV_P_P,
 720   OP_MOV_Z_P_Z,
 721   OP_MOV_Z_V,
 722   OP_MOV_Z_Z,
 723   OP_MOV_Z_Zi,
 724   OP_MOVM_P_P_P,
 725   OP_MOVS_P_P,
 726   OP_MOVZS_P_P_P,
 727   OP_MOVZ_P_P_P,
 728   OP_NOTS_P_P_P_Z,
 729   OP_NOT_P_P_P_Z,
 730
 731   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 732
 733   OP_TOTAL_NUM,         /* Pseudo.  */
 734 };
 735
 736 /* Error types.  */
 737 enum err_type
 738 {
 739   ERR_OK,
 740   ERR_UND,
 741   ERR_UNP,
 742   ERR_NYI,
 743   ERR_VFI,
 744   ERR_NR_ENTRIES
 745 };
 746
 747 /* Maximum number of operands an instruction can have.  */
 748 #define AARCH64_MAX_OPND_NUM 6
 749 /* Maximum number of qualifier sequences an instruction can have.  */
 750 #define AARCH64_MAX_QLF_SEQ_NUM 10
 751 /* Operand qualifier typedef; optimized for the size.  */
 752 typedef unsigned char aarch64_opnd_qualifier_t;
 753 /* Operand qualifier sequence typedef.  */
 754 typedef aarch64_opnd_qualifier_t        \
 755           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 756
 757 /* FIXME: improve the efficiency.  */
 758 static inline bfd_boolean
 759 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 760 {
 761   int i;
 762   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 763     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 764       return FALSE;
 765   return TRUE;
 766 }
 767
 768 /*  Forward declare error reporting type.  */
 769 typedef struct aarch64_operand_error aarch64_operand_error;
 770 /* Forward declare instruction sequence type.  */
 771 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 772 /* Forward declare instruction definition.  */
 773 typedef struct aarch64_inst aarch64_inst;
 774
 775 /* This structure holds information for a particular opcode.  */
 776
 777 struct aarch64_opcode
 778 {
 779   /* The name of the mnemonic.  */
 780   const char *name;
 781
 782   /* The opcode itself.  Those bits which will be filled in with
 783      operands are zeroes.  */
 784   aarch64_insn opcode;
 785
 786   /* The opcode mask.  This is used by the disassembler.  This is a
 787      mask containing ones indicating those bits which must match the
 788      opcode field, and zeroes indicating those bits which need not
 789      match (and are presumably filled in by operands).  */
 790   aarch64_insn mask;
 791
 792   /* Instruction class.  */
 793   enum aarch64_insn_class iclass;
 794
 795   /* Enumerator identifier.  */
 796   enum aarch64_op op;
 797
 798   /* Which architecture variant provides this instruction.  */
 799   const aarch64_feature_set *avariant;
 800
 801   /* An array of operand codes.  Each code is an index into the
 802      operand table.  They appear in the order which the operands must
 803      appear in assembly code, and are terminated by a zero.  */
 804   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 805
 806   /* A list of operand qualifier code sequence.  Each operand qualifier
 807      code qualifies the corresponding operand code.  Each operand
 808      qualifier sequence specifies a valid opcode variant and related
 809      constraint on operands.  */
 810   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 811
 812   /* Flags providing information about this instruction */
 813   uint64_t flags;
 814
 815   /* Extra constraints on the instruction that the verifier checks.  */
 816   uint32_t constraints;
 817
 818   /* If nonzero, this operand and operand 0 are both registers and
 819      are required to have the same register number.  */
 820   unsigned char tied_operand;
 821
 822   /* If non-NULL, a function to verify that a given instruction is valid.  */
 823   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 824                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 825                               struct aarch64_instr_sequence *);
 826 };
 827
 828 typedef struct aarch64_opcode aarch64_opcode;
 829
 830 /* Table describing all the AArch64 opcodes.  */
 831 extern aarch64_opcode aarch64_opcode_table[];
 832
 833 /* Opcode flags.  */
 834 #define F_ALIAS (1 << 0)
 835 #define F_HAS_ALIAS (1 << 1)
 836 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 837    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 838 #define F_P1 (1 << 2)
 839 #define F_P2 (2 << 2)
 840 #define F_P3 (3 << 2)
 841 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 842 #define F_COND (1 << 4)
 843 /* Instruction has the field of 'sf'.  */
 844 #define F_SF (1 << 5)
 845 /* Instruction has the field of 'size:Q'.  */
 846 #define F_SIZEQ (1 << 6)
 847 /* Floating-point instruction has the field of 'type'.  */
 848 #define F_FPTYPE (1 << 7)
 849 /* AdvSIMD scalar instruction has the field of 'size'.  */
 850 #define F_SSIZE (1 << 8)
 851 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 852 #define F_T (1 << 9)
 853 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 854 #define F_GPRSIZE_IN_Q (1 << 10)
 855 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 856 #define F_LDS_SIZE (1 << 11)
 857 /* Optional operand; assume maximum of 1 operand can be optional.  */
 858 #define F_OPD0_OPT (1 << 12)
 859 #define F_OPD1_OPT (2 << 12)
 860 #define F_OPD2_OPT (3 << 12)
 861 #define F_OPD3_OPT (4 << 12)
 862 #define F_OPD4_OPT (5 << 12)
 863 /* Default value for the optional operand when omitted from the assembly.  */
 864 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 865 /* Instruction that is an alias of another instruction needs to be
 866    encoded/decoded by converting it to/from the real form, followed by
 867    the encoding/decoding according to the rules of the real opcode.
 868    This compares to the direct coding using the alias's information.
 869    N.B. this flag requires F_ALIAS to be used together.  */
 870 #define F_CONV (1 << 20)
 871 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 872    friendly pseudo instruction available only in the assembly code (thus will
 873    not show up in the disassembly).  */
 874 #define F_PSEUDO (1 << 21)
 875 /* Instruction has miscellaneous encoding/decoding rules.  */
 876 #define F_MISC (1 << 22)
 877 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 878 #define F_N (1 << 23)
 879 /* Opcode dependent field.  */
 880 #define F_OD(X) (((X) & 0x7) << 24)
 881 /* Instruction has the field of 'sz'.  */
 882 #define F_LSE_SZ (1 << 27)
 883 /* Require an exact qualifier match, even for NIL qualifiers.  */
 884 #define F_STRICT (1ULL << 28)
 885 /* This system instruction is used to read system registers.  */
 886 #define F_SYS_READ (1ULL << 29)
 887 /* This system instruction is used to write system registers.  */
 888 #define F_SYS_WRITE (1ULL << 30)
 889 /* This instruction has an extra constraint on it that imposes a requirement on
 890    subsequent instructions.  */
 891 #define F_SCAN (1ULL << 31)
 892 /* Next bit is 32.  */
 893
 894 /* Instruction constraints.  */
 895 /* This instruction has a predication constraint on the instruction at PC+4.  */
 896 #define C_SCAN_MOVPRFX (1U << 0)
 897 /* This instruction's operation width is determined by the operand with the
 898    largest element size.  */
 899 #define C_MAX_ELEM (1U << 1)
 900 /* Next bit is 2.  */
 901
 902 static inline bfd_boolean
 903 alias_opcode_p (const aarch64_opcode *opcode)
 904 {
 905   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 906 }
 907
 908 static inline bfd_boolean
 909 opcode_has_alias (const aarch64_opcode *opcode)
 910 {
 911   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 912 }
 913
 914 /* Priority for disassembling preference.  */
 915 static inline int
 916 opcode_priority (const aarch64_opcode *opcode)
 917 {
 918   return (opcode->flags >> 2) & 0x3;
 919 }
 920
 921 static inline bfd_boolean
 922 pseudo_opcode_p (const aarch64_opcode *opcode)
 923 {
 924   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 925 }
 926
 927 static inline bfd_boolean
 928 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 929 {
 930   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 931     ? TRUE : FALSE;
 932 }
 933
 934 static inline aarch64_insn
 935 get_optional_operand_default_value (const aarch64_opcode *opcode)
 936 {
 937   return (opcode->flags >> 15) & 0x1f;
 938 }
 939
 940 static inline unsigned int
 941 get_opcode_dependent_value (const aarch64_opcode *opcode)
 942 {
 943   return (opcode->flags >> 24) & 0x7;
 944 }
 945
 946 static inline bfd_boolean
 947 opcode_has_special_coder (const aarch64_opcode *opcode)
 948 {
 949   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 950           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 951     : FALSE;
 952 }
 953 \f
 954 struct aarch64_name_value_pair
 955 {
 956   const char *  name;
 957   aarch64_insn  value;
 958 };
 959
 960 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 961 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 962 extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
 963 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 964 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 965
 966 #define AARCH64_MAX_SYSREG_NAME_LEN 32
 967
 968 typedef struct
 969 {
 970   const char *  name;
 971   aarch64_insn  value;
 972   uint32_t      flags;
 973
 974   /* A set of features, all of which are required for this system register to be
 975      available.  */
 976   aarch64_feature_set features;
 977 } aarch64_sys_reg;
 978
 979 extern const aarch64_sys_reg aarch64_sys_regs [];
 980 extern const aarch64_sys_reg aarch64_pstatefields [];
 981 extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
 982 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 983                                                     const aarch64_sys_reg *);
 984
 985 typedef struct
 986 {
 987   const char *name;
 988   uint32_t value;
 989   uint32_t flags ;
 990 } aarch64_sys_ins_reg;
 991
 992 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 993 extern bfd_boolean
 994 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 995                                  const char *reg_name, aarch64_insn,
 996                                  uint32_t, aarch64_feature_set);
 997
 998 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 999 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
1000 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
1001 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
1002 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
1003
1004 /* Shift/extending operator kinds.
1005    N.B. order is important; keep aarch64_operand_modifiers synced.  */
1006 enum aarch64_modifier_kind
1007 {
1008   AARCH64_MOD_NONE,
1009   AARCH64_MOD_MSL,
1010   AARCH64_MOD_ROR,
1011   AARCH64_MOD_ASR,
1012   AARCH64_MOD_LSR,
1013   AARCH64_MOD_LSL,
1014   AARCH64_MOD_UXTB,
1015   AARCH64_MOD_UXTH,
1016   AARCH64_MOD_UXTW,
1017   AARCH64_MOD_UXTX,
1018   AARCH64_MOD_SXTB,
1019   AARCH64_MOD_SXTH,
1020   AARCH64_MOD_SXTW,
1021   AARCH64_MOD_SXTX,
1022   AARCH64_MOD_MUL,
1023   AARCH64_MOD_MUL_VL,
1024 };
1025
1026 bfd_boolean
1027 aarch64_extend_operator_p (enum aarch64_modifier_kind);
1028
1029 enum aarch64_modifier_kind
1030 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1031 /* Condition.  */
1032
1033 typedef struct
1034 {
1035   /* A list of names with the first one as the disassembly preference;
1036      terminated by NULL if fewer than 3.  */
1037   const char *names[4];
1038   aarch64_insn value;
1039 } aarch64_cond;
1040
1041 extern const aarch64_cond aarch64_conds[16];
1042
1043 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1044 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1045 \f
1046 /* Structure representing an operand.  */
1047
1048 struct aarch64_opnd_info
1049 {
1050   enum aarch64_opnd type;
1051   aarch64_opnd_qualifier_t qualifier;
1052   int idx;
1053
1054   union
1055     {
1056       struct
1057         {
1058           unsigned regno;
1059         } reg;
1060       struct
1061         {
1062           unsigned int regno;
1063           int64_t index;
1064         } reglane;
1065       /* e.g. LVn.  */
1066       struct
1067         {
1068           unsigned first_regno : 5;
1069           unsigned num_regs : 3;
1070           /* 1 if it is a list of reg element.  */
1071           unsigned has_index : 1;
1072           /* Lane index; valid only when has_index is 1.  */
1073           int64_t index;
1074         } reglist;
1075       /* e.g. immediate or pc relative address offset.  */
1076       struct
1077         {
1078           int64_t value;
1079           unsigned is_fp : 1;
1080         } imm;
1081       /* e.g. address in STR (register offset).  */
1082       struct
1083         {
1084           unsigned base_regno;
1085           struct
1086             {
1087               union
1088                 {
1089                   int imm;
1090                   unsigned regno;
1091                 };
1092               unsigned is_reg;
1093             } offset;
1094           unsigned pcrel : 1;           /* PC-relative.  */
1095           unsigned writeback : 1;
1096           unsigned preind : 1;          /* Pre-indexed.  */
1097           unsigned postind : 1;         /* Post-indexed.  */
1098         } addr;
1099
1100       struct
1101         {
1102           /* The encoding of the system register.  */
1103           aarch64_insn value;
1104
1105           /* The system register flags.  */
1106           uint32_t flags;
1107         } sysreg;
1108
1109       const aarch64_cond *cond;
1110       /* The encoding of the PSTATE field.  */
1111       aarch64_insn pstatefield;
1112       const aarch64_sys_ins_reg *sysins_op;
1113       const struct aarch64_name_value_pair *barrier;
1114       const struct aarch64_name_value_pair *hint_option;
1115       const struct aarch64_name_value_pair *prfop;
1116     };
1117
1118   /* Operand shifter; in use when the operand is a register offset address,
1119      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1120   struct
1121     {
1122       enum aarch64_modifier_kind kind;
1123       unsigned operator_present: 1;     /* Only valid during encoding.  */
1124       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1125       unsigned amount_present: 1;
1126       int64_t amount;
1127     } shifter;
1128
1129   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1130                            to be done on it.  In some (but not all) of these
1131                            cases, we need to tell libopcodes to skip the
1132                            constraint checking and the encoding for this
1133                            operand, so that the libopcodes can pick up the
1134                            right opcode before the operand is fixed-up.  This
1135                            flag should only be used during the
1136                            assembling/encoding.  */
1137   unsigned present:1;   /* Whether this operand is present in the assembly
1138                            line; not used during the disassembly.  */
1139 };
1140
1141 typedef struct aarch64_opnd_info aarch64_opnd_info;
1142
1143 /* Structure representing an instruction.
1144
1145    It is used during both the assembling and disassembling.  The assembler
1146    fills an aarch64_inst after a successful parsing and then passes it to the
1147    encoding routine to do the encoding.  During the disassembling, the
1148    disassembler calls the decoding routine to decode a binary instruction; on a
1149    successful return, such a structure will be filled with information of the
1150    instruction; then the disassembler uses the information to print out the
1151    instruction.  */
1152
1153 struct aarch64_inst
1154 {
1155   /* The value of the binary instruction.  */
1156   aarch64_insn value;
1157
1158   /* Corresponding opcode entry.  */
1159   const aarch64_opcode *opcode;
1160
1161   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1162   const aarch64_cond *cond;
1163
1164   /* Operands information.  */
1165   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1166 };
1167
1168 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1169 #define HINT_OPD_CSYNC  0x11
1170 #define HINT_OPD_C      0x22
1171 #define HINT_OPD_J      0x24
1172 #define HINT_OPD_JC     0x26
1173 #define HINT_OPD_NULL   0x00
1174
1175 \f
1176 /* Diagnosis related declaration and interface.  */
1177
1178 /* Operand error kind enumerators.
1179
1180    AARCH64_OPDE_RECOVERABLE
1181      Less severe error found during the parsing, very possibly because that
1182      GAS has picked up a wrong instruction template for the parsing.
1183
1184    AARCH64_OPDE_SYNTAX_ERROR
1185      General syntax error; it can be either a user error, or simply because
1186      that GAS is trying a wrong instruction template.
1187
1188    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1189      Definitely a user syntax error.
1190
1191    AARCH64_OPDE_INVALID_VARIANT
1192      No syntax error, but the operands are not a valid combination, e.g.
1193      FMOV D0,S0
1194
1195    AARCH64_OPDE_UNTIED_OPERAND
1196      The asm failed to use the same register for a destination operand
1197      and a tied source operand.
1198
1199    AARCH64_OPDE_OUT_OF_RANGE
1200      Error about some immediate value out of a valid range.
1201
1202    AARCH64_OPDE_UNALIGNED
1203      Error about some immediate value not properly aligned (i.e. not being a
1204      multiple times of a certain value).
1205
1206    AARCH64_OPDE_REG_LIST
1207      Error about the register list operand having unexpected number of
1208      registers.
1209
1210    AARCH64_OPDE_OTHER_ERROR
1211      Error of the highest severity and used for any severe issue that does not
1212      fall into any of the above categories.
1213
1214    The enumerators are only interesting to GAS.  They are declared here (in
1215    libopcodes) because that some errors are detected (and then notified to GAS)
1216    by libopcodes (rather than by GAS solely).
1217
1218    The first three errors are only deteced by GAS while the
1219    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1220    only libopcodes has the information about the valid variants of each
1221    instruction.
1222
1223    The enumerators have an increasing severity.  This is helpful when there are
1224    multiple instruction templates available for a given mnemonic name (e.g.
1225    FMOV); this mechanism will help choose the most suitable template from which
1226    the generated diagnostics can most closely describe the issues, if any.  */
1227
1228 enum aarch64_operand_error_kind
1229 {
1230   AARCH64_OPDE_NIL,
1231   AARCH64_OPDE_RECOVERABLE,
1232   AARCH64_OPDE_SYNTAX_ERROR,
1233   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1234   AARCH64_OPDE_INVALID_VARIANT,
1235   AARCH64_OPDE_UNTIED_OPERAND,
1236   AARCH64_OPDE_OUT_OF_RANGE,
1237   AARCH64_OPDE_UNALIGNED,
1238   AARCH64_OPDE_REG_LIST,
1239   AARCH64_OPDE_OTHER_ERROR
1240 };
1241
1242 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1243 struct aarch64_operand_error
1244 {
1245   enum aarch64_operand_error_kind kind;
1246   int index;
1247   const char *error;
1248   int data[3];  /* Some data for extra information.  */
1249   bfd_boolean non_fatal;
1250 };
1251
1252 /* AArch64 sequence structure used to track instructions with F_SCAN
1253    dependencies for both assembler and disassembler.  */
1254 struct aarch64_instr_sequence
1255 {
1256   /* The instruction that caused this sequence to be opened.  */
1257   aarch64_inst *instr;
1258   /* The number of instructions the above instruction allows to be kept in the
1259      sequence before an automatic close is done.  */
1260   int num_insns;
1261   /* The instructions currently added to the sequence.  */
1262   aarch64_inst **current_insns;
1263   /* The number of instructions already in the sequence.  */
1264   int next_insn;
1265 };
1266
1267 /* Encoding entrypoint.  */
1268
1269 extern int
1270 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1271                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1272                        aarch64_operand_error *, aarch64_instr_sequence *);
1273
1274 extern const aarch64_opcode *
1275 aarch64_replace_opcode (struct aarch64_inst *,
1276                         const aarch64_opcode *);
1277
1278 /* Given the opcode enumerator OP, return the pointer to the corresponding
1279    opcode entry.  */
1280
1281 extern const aarch64_opcode *
1282 aarch64_get_opcode (enum aarch64_op);
1283
1284 /* Generate the string representation of an operand.  */
1285 extern void
1286 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1287                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1288                        char **,
1289                        aarch64_feature_set features);
1290
1291 /* Miscellaneous interface.  */
1292
1293 extern int
1294 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1295
1296 extern aarch64_opnd_qualifier_t
1297 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1298                                 const aarch64_opnd_qualifier_t, int);
1299
1300 extern bfd_boolean
1301 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1302
1303 extern int
1304 aarch64_num_of_operands (const aarch64_opcode *);
1305
1306 extern int
1307 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1308
1309 extern int
1310 aarch64_zero_register_p (const aarch64_opnd_info *);
1311
1312 extern enum err_type
1313 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1314                      aarch64_operand_error *);
1315
1316 extern void
1317 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1318
1319 /* Given an operand qualifier, return the expected data element size
1320    of a qualified operand.  */
1321 extern unsigned char
1322 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1323
1324 extern enum aarch64_operand_class
1325 aarch64_get_operand_class (enum aarch64_opnd);
1326
1327 extern const char *
1328 aarch64_get_operand_name (enum aarch64_opnd);
1329
1330 extern const char *
1331 aarch64_get_operand_desc (enum aarch64_opnd);
1332
1333 extern bfd_boolean
1334 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1335
1336 #ifdef DEBUG_AARCH64
1337 extern int debug_dump;
1338
1339 extern void
1340 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1341
1342 #define DEBUG_TRACE(M, ...)                                     \
1343   {                                                             \
1344     if (debug_dump)                                             \
1345       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1346   }
1347
1348 #define DEBUG_TRACE_IF(C, M, ...)                               \
1349   {                                                             \
1350     if (debug_dump && (C))                                      \
1351       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1352   }
1353 #else  /* !DEBUG_AARCH64 */
1354 #define DEBUG_TRACE(M, ...) ;
1355 #define DEBUG_TRACE_IF(C, M, ...) ;
1356 #endif /* DEBUG_AARCH64 */
1357
1358 extern const char *const aarch64_sve_pattern_array[32];
1359 extern const char *const aarch64_sve_prfop_array[16];
1360
1361 #ifdef __cplusplus
1362 }
1363 #endif
1364
1365 #endif /* OPCODE_AARCH64_H */