include/opcode/avr.h

   1 /* Opcode table for the Atmel AVR micro controllers.
   2
   3    Copyright (C) 2000-2021 Free Software Foundation, Inc.
   4    Contributed by Denis Chertykov <denisc@overta.ru>
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 #define AVR_ISA_1200  0x0001 /* In the beginning there was ...  */
  22 #define AVR_ISA_LPM   0x0002 /* device has LPM */
  23 #define AVR_ISA_LPMX  0x0004 /* device has LPM Rd,Z[+] */
  24 #define AVR_ISA_SRAM  0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
  25 #define AVR_ISA_TINY  0x0010 /* device has Tiny core specific encodings */
  26 #define AVR_ISA_MEGA  0x0020 /* device has >8K program memory (JMP and CALL
  27                                 supported, no 8K wrap on RJMP and RCALL) */
  28 #define AVR_ISA_MUL   0x0040 /* device has new core (MUL, FMUL, ...) */
  29 #define AVR_ISA_ELPM  0x0080 /* device has >64K program memory (ELPM) */
  30 #define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */
  31 #define AVR_ISA_SPM   0x0200 /* device can program itself */
  32 #define AVR_ISA_BRK   0x0400 /* device has BREAK (on-chip debug) */
  33 #define AVR_ISA_EIND  0x0800 /* device has >128K program memory (none yet) */
  34 #define AVR_ISA_MOVW  0x1000 /* device has MOVW */
  35 #define AVR_ISA_SPMX  0x2000 /* device has SPM Z[+] */
  36 #define AVR_ISA_DES   0x4000 /* device has DES */
  37 #define AVR_ISA_RMW   0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */
  38
  39 #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
  40 #define AVR_ISA_2xxx  (AVR_ISA_TINY1 | AVR_ISA_SRAM)
  41 #define AVR_ISA_2xxxa (AVR_ISA_1200 | AVR_ISA_SRAM)
  42 /* For the attiny26 which is missing LPM Rd,Z+.  */
  43 #define AVR_ISA_2xxe  (AVR_ISA_2xxx | AVR_ISA_LPMX)
  44 #define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX)
  45 #define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \
  46                        AVR_ISA_SPM  | AVR_ISA_BRK)
  47 #define AVR_ISA_M603  (AVR_ISA_2xxx | AVR_ISA_MEGA)
  48 #define AVR_ISA_M103  (AVR_ISA_M603 | AVR_ISA_ELPM)
  49 #define AVR_ISA_M8    (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
  50                        AVR_ISA_LPMX | AVR_ISA_SPM)
  51 #define AVR_ISA_PWMx  (AVR_ISA_M8   | AVR_ISA_BRK)
  52 #define AVR_ISA_M161  (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \
  53                        AVR_ISA_LPMX | AVR_ISA_SPM)
  54 #define AVR_ISA_94K   (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
  55 #define AVR_ISA_M323  (AVR_ISA_M161 | AVR_ISA_BRK)
  56 #define AVR_ISA_M128  (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
  57 #define AVR_ISA_M256  (AVR_ISA_M128 | AVR_ISA_EIND)
  58 #define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES)
  59 #define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW)
  60
  61 #define AVR_ISA_AVR1   AVR_ISA_TINY1
  62 #define AVR_ISA_AVR2   AVR_ISA_2xxx
  63 #define AVR_ISA_AVR25  AVR_ISA_TINY2
  64 #define AVR_ISA_AVR3   AVR_ISA_M603
  65 #define AVR_ISA_AVR31   AVR_ISA_M103
  66 #define AVR_ISA_AVR35   (AVR_ISA_AVR3 | AVR_ISA_MOVW | \
  67                         AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK)
  68 #define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35)
  69 #define AVR_ISA_AVR4   AVR_ISA_PWMx
  70 #define AVR_ISA_AVR5   AVR_ISA_M323
  71 #define AVR_ISA_AVR51  AVR_ISA_M128
  72 #define AVR_ISA_AVR6   (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \
  73                         AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \
  74                         AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
  75                         AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW)
  76
  77 #define AVR_ISA_AVRTINY (AVR_ISA_1200 | AVR_ISA_BRK | AVR_ISA_SRAM | \
  78                          AVR_ISA_TINY)
  79
  80 #define REGISTER_P(x) ((x) == 'r'               \
  81                        || (x) == 'd'            \
  82                        || (x) == 'w'            \
  83                        || (x) == 'a'            \
  84                        || (x) == 'v')
  85
  86 /* Undefined combination of operands - does the register
  87    operand overlap with pre-decremented or post-incremented
  88    pointer register (like ld r31,Z+)?  */
  89 #define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 ||             \
  90   ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE ||       \
  91   ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA ||       \
  92   ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2)
  93
  94 /* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}?  */
  95 #define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 ||              \
  96   ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00)
  97
  98 /* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as
  99    `ld r,b' or `st b,r' respectively - next opcode entry)?  */
 100 #define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
 101
 102 /* Constraint letters:
 103    r - any register
 104    d - `ldi' register (r16-r31)
 105    v - `movw' even register (r0, r2, ..., r28, r30)
 106    a - `fmul' register (r16-r23)
 107    w - `adiw' register (r24,r26,r28,r30)
 108    e - pointer registers (X,Y,Z)
 109    b - base pointer register and displacement ([YZ]+disp)
 110    z - Z pointer register (for [e]lpm Rd,Z[+])
 111    M - immediate value from 0 to 255
 112    n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
 113    N - immediate value from 0 to 255. Relocation impossible
 114    s - immediate value from 0 to 7
 115    P - Port address value from 0 to 63. (in, out)
 116    p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
 117    K - immediate value from 0 to 63 (used in `adiw', `sbiw')
 118    i - immediate value
 119    j - 7 bit immediate value from 0x40 to 0xBF (for 16-bit 'lds'/'sts')
 120    l - signed pc relative offset from -64 to 63
 121    L - signed pc relative offset from -2048 to 2047
 122    h - absolute code address (call, jmp)
 123    S - immediate value from 0 to 7 (S = s << 4)
 124    E - immediate value from 0 to 15, shifted left by 4 (des)
 125    ? - use this opcode entry if no parameters, else use next opcode entry
 126
 127    Order is important - some binary opcodes have more than one name,
 128    the disassembler will only see the first match.
 129
 130    Remaining undefined opcodes (1699 total - some of them might work
 131    as normal instructions if not all of the bits are decoded):
 132
 133     0x0001...0x00ff    (255) (known to be decoded as `nop' by the old core)
 134    "100100xxxxxxx011"  (128) 0x9[0-3][0-9a-f][3b]
 135    "100100xxxxxx1000"   (64) 0x9[0-3][0-9a-f]8
 136    "1001010xxxxx0100"   (32) 0x9[45][0-9a-f]4
 137    "1001010x001x1001"    (4) 0x9[45][23]9
 138    "1001010x01xx1001"    (8) 0x9[45][4-7]9
 139    "1001010x1xxx1001"   (16) 0x9[45][8-9a-f]9
 140    "1001010xxxxx1011"   (32) 0x9[45][0-9a-f]b
 141    "10010101001x1000"    (2) 0x95[23]8
 142    "1001010101xx1000"    (4) 0x95[4-7]8
 143    "1001010110111000"    (1) 0x95b8
 144    "1001010111111000"    (1) 0x95f8 (`espm' removed in databook update)
 145    "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
 146  */
 147
 148 AVR_INSN (clc,  "",    "1001010010001000", 1, AVR_ISA_1200, 0x9488)
 149 AVR_INSN (clh,  "",    "1001010011011000", 1, AVR_ISA_1200, 0x94d8)
 150 AVR_INSN (cli,  "",    "1001010011111000", 1, AVR_ISA_1200, 0x94f8)
 151 AVR_INSN (cln,  "",    "1001010010101000", 1, AVR_ISA_1200, 0x94a8)
 152 AVR_INSN (cls,  "",    "1001010011001000", 1, AVR_ISA_1200, 0x94c8)
 153 AVR_INSN (clt,  "",    "1001010011101000", 1, AVR_ISA_1200, 0x94e8)
 154 AVR_INSN (clv,  "",    "1001010010111000", 1, AVR_ISA_1200, 0x94b8)
 155 AVR_INSN (clz,  "",    "1001010010011000", 1, AVR_ISA_1200, 0x9498)
 156
 157 AVR_INSN (sec,  "",    "1001010000001000", 1, AVR_ISA_1200, 0x9408)
 158 AVR_INSN (seh,  "",    "1001010001011000", 1, AVR_ISA_1200, 0x9458)
 159 AVR_INSN (sei,  "",    "1001010001111000", 1, AVR_ISA_1200, 0x9478)
 160 AVR_INSN (sen,  "",    "1001010000101000", 1, AVR_ISA_1200, 0x9428)
 161 AVR_INSN (ses,  "",    "1001010001001000", 1, AVR_ISA_1200, 0x9448)
 162 AVR_INSN (set,  "",    "1001010001101000", 1, AVR_ISA_1200, 0x9468)
 163 AVR_INSN (sev,  "",    "1001010000111000", 1, AVR_ISA_1200, 0x9438)
 164 AVR_INSN (sez,  "",    "1001010000011000", 1, AVR_ISA_1200, 0x9418)
 165
 166 /* Same as {cl,se}[chinstvz] above.  */
 167 AVR_INSN (bclr, "S",   "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
 168 AVR_INSN (bset, "S",   "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
 169
 170 AVR_INSN (icall,"",    "1001010100001001", 1, AVR_ISA_2xxxa,0x9509)
 171 AVR_INSN (ijmp, "",    "1001010000001001", 1, AVR_ISA_2xxxa,0x9409)
 172
 173 AVR_INSN (lpm,  "?",   "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
 174 AVR_INSN (lpm,  "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
 175 AVR_INSN (elpm, "?",   "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8)
 176 AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006)
 177
 178 AVR_INSN (nop,  "",    "0000000000000000", 1, AVR_ISA_1200, 0x0000)
 179 AVR_INSN (ret,  "",    "1001010100001000", 1, AVR_ISA_1200, 0x9508)
 180 AVR_INSN (reti, "",    "1001010100011000", 1, AVR_ISA_1200, 0x9518)
 181 AVR_INSN (sleep,"",    "1001010110001000", 1, AVR_ISA_1200, 0x9588)
 182 AVR_INSN (break,"",    "1001010110011000", 1, AVR_ISA_BRK,  0x9598)
 183 AVR_INSN (wdr,  "",    "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
 184 AVR_INSN (spm,  "?",   "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)
 185 AVR_INSN (spm,  "z",   "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8)
 186
 187 AVR_INSN (adc,  "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
 188 AVR_INSN (add,  "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
 189 AVR_INSN (and,  "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
 190 AVR_INSN (cp,   "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400)
 191 AVR_INSN (cpc,  "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400)
 192 AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000)
 193 AVR_INSN (eor,  "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
 194 AVR_INSN (mov,  "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00)
 195 AVR_INSN (mul,  "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL,  0x9c00)
 196 AVR_INSN (or,   "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800)
 197 AVR_INSN (sbc,  "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800)
 198 AVR_INSN (sub,  "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800)
 199
 200 /* Shorthand for {eor,add,adc,and} r,r above.  */
 201 AVR_INSN (clr,  "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
 202 AVR_INSN (lsl,  "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
 203 AVR_INSN (rol,  "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
 204 AVR_INSN (tst,  "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
 205
 206 AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
 207   /*XXX special case*/
 208 AVR_INSN (cbr,  "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
 209
 210 AVR_INSN (ldi,  "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000)
 211 AVR_INSN (ser,  "d",   "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
 212
 213 AVR_INSN (ori,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
 214 AVR_INSN (sbr,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
 215
 216 AVR_INSN (cpi,  "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
 217 AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
 218 AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000)
 219
 220 AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00)
 221 AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00)
 222 AVR_INSN (bld,  "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800)
 223 AVR_INSN (bst,  "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00)
 224
 225 AVR_INSN (in,   "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000)
 226 AVR_INSN (out,  "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800)
 227
 228 AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600)
 229 AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700)
 230
 231 AVR_INSN (cbi,  "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800)
 232 AVR_INSN (sbi,  "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00)
 233 AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900)
 234 AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00)
 235
 236 AVR_INSN (brcc, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
 237 AVR_INSN (brcs, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
 238 AVR_INSN (breq, "l",   "111100lllllll001", 1, AVR_ISA_1200, 0xf001)
 239 AVR_INSN (brge, "l",   "111101lllllll100", 1, AVR_ISA_1200, 0xf404)
 240 AVR_INSN (brhc, "l",   "111101lllllll101", 1, AVR_ISA_1200, 0xf405)
 241 AVR_INSN (brhs, "l",   "111100lllllll101", 1, AVR_ISA_1200, 0xf005)
 242 AVR_INSN (brid, "l",   "111101lllllll111", 1, AVR_ISA_1200, 0xf407)
 243 AVR_INSN (brie, "l",   "111100lllllll111", 1, AVR_ISA_1200, 0xf007)
 244 AVR_INSN (brlo, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
 245 AVR_INSN (brlt, "l",   "111100lllllll100", 1, AVR_ISA_1200, 0xf004)
 246 AVR_INSN (brmi, "l",   "111100lllllll010", 1, AVR_ISA_1200, 0xf002)
 247 AVR_INSN (brne, "l",   "111101lllllll001", 1, AVR_ISA_1200, 0xf401)
 248 AVR_INSN (brpl, "l",   "111101lllllll010", 1, AVR_ISA_1200, 0xf402)
 249 AVR_INSN (brsh, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
 250 AVR_INSN (brtc, "l",   "111101lllllll110", 1, AVR_ISA_1200, 0xf406)
 251 AVR_INSN (brts, "l",   "111100lllllll110", 1, AVR_ISA_1200, 0xf006)
 252 AVR_INSN (brvc, "l",   "111101lllllll011", 1, AVR_ISA_1200, 0xf403)
 253 AVR_INSN (brvs, "l",   "111100lllllll011", 1, AVR_ISA_1200, 0xf003)
 254
 255 /* Same as br?? above.  */
 256 AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400)
 257 AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000)
 258
 259 AVR_INSN (rcall, "L",  "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000)
 260 AVR_INSN (rjmp,  "L",  "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000)
 261
 262 AVR_INSN (call, "h",   "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e)
 263 AVR_INSN (jmp,  "h",   "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c)
 264
 265 AVR_INSN (asr,  "r",   "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405)
 266 AVR_INSN (com,  "r",   "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400)
 267 AVR_INSN (dec,  "r",   "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
 268 AVR_INSN (inc,  "r",   "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
 269 AVR_INSN (lsr,  "r",   "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
 270 AVR_INSN (neg,  "r",   "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
 271 AVR_INSN (pop,  "r",   "1001000rrrrr1111", 1, AVR_ISA_2xxxa,0x900f)
 272 AVR_INSN (push, "r",   "1001001rrrrr1111", 1, AVR_ISA_2xxxa,0x920f)
 273 AVR_INSN (ror,  "r",   "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
 274 AVR_INSN (swap, "r",   "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
 275
 276 /* Atomic memory operations for XMEGA.  List before `sts'.  */
 277 AVR_INSN (xch,  "z,r",   "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204)
 278 AVR_INSN (las,  "z,r",   "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205)
 279 AVR_INSN (lac,  "z,r",   "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206)
 280 AVR_INSN (lat,  "z,r",   "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207)
 281
 282 /* Known to be decoded as `nop' by the old core.  */
 283 AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)
 284 AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL,  0x0200)
 285 AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL,  0x0300)
 286 AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL,  0x0308)
 287 AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL,  0x0380)
 288 AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL,  0x0388)
 289
 290 AVR_INSN (sts, "j,d", "10101kkkddddkkkk", 1, AVR_ISA_TINY, 0xA800)
 291 AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
 292 AVR_INSN (lds, "d,j", "10100kkkddddkkkk", 1, AVR_ISA_TINY, 0xA000)
 293 AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
 294
 295 /* Special case for b+0, `e' must be next entry after `b',
 296    b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X.  */
 297 AVR_INSN (ldd,  "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000)
 298 AVR_INSN (ld,   "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000)
 299 AVR_INSN (std,  "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
 300 AVR_INSN (st,   "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
 301
 302 /* These are for devices that don't exist yet
 303    (>128K program memory, PC = EIND:Z).  */
 304 AVR_INSN (eicall, "",  "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
 305 AVR_INSN (eijmp, "",   "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
 306
 307 /* DES instruction for encryption and decryption.  */
 308 AVR_INSN (des,  "E",   "10010100EEEE1011", 1, AVR_ISA_DES,  0x940B)
 309
 310 /* Operands are evaluated by hand and won't pop new fux-ups.
 311    The pseudo-insn is hidden behind NOP so that avr-dis.c don't see it. */
 312 AVR_INSN (__gcc_isr, "", "0000000000000000", 1, AVR_ISA_1200,  0x0)
 313