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* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that
[thirdparty/binutils-gdb.git] / include / opcode / i386.h
1 /* i386-opcode.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
3
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20 /* The UnixWare assembler, and probably other AT&T derived ix86 Unix
21 assemblers, generate floating point instructions with reversed
22 source and destination registers in certain cases. Unfortunately,
23 gcc and possibly many other programs use this reversed syntax, so
24 we're stuck with it.
25
26 eg. `fsub %st(3),%st' results in st <- st - st(3) as expected, but
27 `fsub %st,%st(3)' results in st(3) <- st - st(3), rather than
28 the expected st(3) <- st(3) - st !
29
30 This happens with all the non-commutative arithmetic floating point
31 operations with two register operands, where the source register is
32 %st, and destination register is %st(i). Look for FloatDR below. */
33
34 #ifndef UNIXWARE_COMPAT
35 /* Set non-zero for broken, compatible instructions. Set to zero for
36 non-broken opcodes at your peril. gcc generates UnixWare
37 compatible instructions. */
38 #define UNIXWARE_COMPAT 1
39 #endif
40
41
42 static const template i386_optab[] = {
43
44 #define X None
45 #define ReverseModrm (ReverseRegRegmem|Modrm)
46 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf)
47 #define b_Suf (No_wSuf|No_lSuf|No_sSuf)
48 #define w_Suf (No_bSuf|No_lSuf|No_sSuf)
49 #define l_Suf (No_bSuf|No_wSuf|No_sSuf)
50 #define bw_Suf (No_lSuf|No_sSuf)
51 #define bl_Suf (No_wSuf|No_sSuf)
52 #define wl_Suf (No_bSuf|No_sSuf)
53 #define sl_Suf (No_bSuf|No_wSuf)
54 #define bwl_Suf No_sSuf
55 #define FP (NoSuf|IgnoreSize)
56 #define l_FP (l_Suf|IgnoreSize)
57 #define sl_FP (sl_Suf|IgnoreSize)
58 #if UNIXWARE_COMPAT
59 #define FloatDR FloatD
60 #else
61 #define FloatDR (FloatD|FloatR)
62 #endif
63
64 /* move instructions */
65 #define MOV_AX_DISP32 0xa0
66 { "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
67 { "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
68 { "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } },
69 { "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } },
70 /* The next two instructions accept WordReg so that a segment register
71 can be copied to a 32 bit register, and vice versa, without using a
72 size prefix. When moving to a 32 bit register, the upper 16 bits
73 are set to an implementation defined value (on the Pentium Pro,
74 the implementation defined value is zero). */
75 { "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } },
76 { "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } },
77 /* move to/from control debug registers */
78 { "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32, 0} },
79 { "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32, 0} },
80 { "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32, 0} },
81
82 /* move with sign extend */
83 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
84 conflict with the "movs" string move instruction. */
85 {"movsbl", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg32, 0} },
86 {"movsbw", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg16, 0} },
87 {"movswl", 2, 0x0fbf, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} },
88
89 /* move with zero extend */
90 {"movzb", 2, 0x0fb6, X, wl_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} },
91 {"movzwl", 2, 0x0fb7, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} },
92
93 /* push instructions */
94 {"push", 1, 0x50, X, wl_Suf|ShortForm, { WordReg,0,0 } },
95 {"push", 1, 0xff, 6, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } },
96 {"push", 1, 0x6a, X, wl_Suf, { Imm8S, 0, 0} },
97 {"push", 1, 0x68, X, wl_Suf, { Imm16|Imm32, 0, 0} },
98 {"push", 1, 0x06, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } },
99 {"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } },
100 /* push all */
101 {"pusha", 0, 0x60, X, wl_Suf, { 0, 0, 0 } },
102
103 /* pop instructions */
104 {"pop", 1, 0x58, X, wl_Suf|ShortForm, { WordReg,0,0 } },
105 {"pop", 1, 0x8f, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } },
106 #define POP_SEG_SHORT 0x07
107 {"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } },
108 {"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } },
109 /* pop all */
110 {"popa", 0, 0x61, X, wl_Suf, { 0, 0, 0 } },
111
112 /* xchg exchange instructions
113 xchg commutes: we allow both operand orders */
114 {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
115 {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
116 {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
117 {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
118
119 /* in/out from ports */
120 {"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } },
121 {"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
122 {"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } },
123 {"in", 1, 0xec, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
124 {"out", 2, 0xe6, X, bwl_Suf|W, { Acc, Imm8, 0 } },
125 {"out", 2, 0xee, X, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
126 {"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } },
127 {"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
128
129 /* load effective address */
130 {"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } },
131
132 /* load segment registers from memory */
133 {"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
134 {"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
135 {"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
136 {"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
137 {"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
138
139 /* flags register instructions */
140 {"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} },
141 {"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} },
142 {"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} },
143 {"clts", 0, 0x0f06, X, NoSuf, { 0, 0, 0} },
144 {"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} },
145 {"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} },
146 {"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} },
147 {"pushf", 0, 0x9c, X, wl_Suf, { 0, 0, 0} },
148 {"popf", 0, 0x9d, X, wl_Suf, { 0, 0, 0} },
149 {"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} },
150 {"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} },
151 {"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} },
152
153 /* arithmetic */
154 {"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
155 {"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
156 {"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} },
157 {"add", 2, 0x80, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
158
159 {"inc", 1, 0x40, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
160 {"inc", 1, 0xfe, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
161
162 {"sub", 2, 0x28, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
163 {"sub", 2, 0x83, 5, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
164 {"sub", 2, 0x2c, X, bwl_Suf|W, { Imm, Acc, 0} },
165 {"sub", 2, 0x80, 5, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
166
167 {"dec", 1, 0x48, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
168 {"dec", 1, 0xfe, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
169
170 {"sbb", 2, 0x18, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
171 {"sbb", 2, 0x83, 3, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
172 {"sbb", 2, 0x1c, X, bwl_Suf|W, { Imm, Acc, 0} },
173 {"sbb", 2, 0x80, 3, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
174
175 {"cmp", 2, 0x38, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
176 {"cmp", 2, 0x83, 7, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
177 {"cmp", 2, 0x3c, X, bwl_Suf|W, { Imm, Acc, 0} },
178 {"cmp", 2, 0x80, 7, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
179
180 {"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
181 {"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
182 {"test", 2, 0xa8, X, bwl_Suf|W, { Imm, Acc, 0} },
183 {"test", 2, 0xf6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
184
185 {"and", 2, 0x20, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
186 {"and", 2, 0x83, 4, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
187 {"and", 2, 0x24, X, bwl_Suf|W, { Imm, Acc, 0} },
188 {"and", 2, 0x80, 4, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
189
190 {"or", 2, 0x08, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
191 {"or", 2, 0x83, 1, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
192 {"or", 2, 0x0c, X, bwl_Suf|W, { Imm, Acc, 0} },
193 {"or", 2, 0x80, 1, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
194
195 {"xor", 2, 0x30, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
196 {"xor", 2, 0x83, 6, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
197 {"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} },
198 {"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
199
200 /* iclr with 1 operand is really xor with 2 operands. */
201 {"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
202
203 {"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
204 {"adc", 2, 0x83, 2, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
205 {"adc", 2, 0x14, X, bwl_Suf|W, { Imm, Acc, 0} },
206 {"adc", 2, 0x80, 2, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
207
208 {"neg", 1, 0xf6, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
209 {"not", 1, 0xf6, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
210
211 {"aaa", 0, 0x37, X, NoSuf, { 0, 0, 0} },
212 {"aas", 0, 0x3f, X, NoSuf, { 0, 0, 0} },
213 {"daa", 0, 0x27, X, NoSuf, { 0, 0, 0} },
214 {"das", 0, 0x2f, X, NoSuf, { 0, 0, 0} },
215 {"aad", 0, 0xd50a, X, NoSuf, { 0, 0, 0} },
216 {"aad", 1, 0xd5, X, NoSuf, { Imm8S, 0, 0} },
217 {"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} },
218 {"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} },
219
220 /* conversion insns */
221 /* conversion: intel naming */
222 {"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
223 {"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
224 {"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
225 {"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
226 /* att naming */
227 {"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
228 {"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
229 {"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
230 {"cltd", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
231
232 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
233 expanding 64-bit multiplies, and *cannot* be selected to accomplish
234 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
235 These multiplies can only be selected with single operand forms. */
236 {"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
237 {"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
238 {"imul", 2, 0x0faf, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
239 {"imul", 3, 0x6b, X, wl_Suf|ReverseModrm, { Imm8S, WordReg|WordMem, WordReg} },
240 {"imul", 3, 0x69, X, wl_Suf|ReverseModrm, { Imm16|Imm32, WordReg|WordMem, WordReg} },
241 /* imul with 2 operands mimics imul with 3 by putting the register in
242 both i.rm.reg & i.rm.regmem fields. regKludge enables this
243 transformation. */
244 {"imul", 2, 0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
245 {"imul", 2, 0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
246
247 {"div", 1, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
248 {"div", 2, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
249 {"idiv", 1, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
250 {"idiv", 2, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
251
252 {"rol", 2, 0xd0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
253 {"rol", 2, 0xc0, 0, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
254 {"rol", 2, 0xd2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
255 {"rol", 1, 0xd0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
256
257 {"ror", 2, 0xd0, 1, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
258 {"ror", 2, 0xc0, 1, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
259 {"ror", 2, 0xd2, 1, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
260 {"ror", 1, 0xd0, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
261
262 {"rcl", 2, 0xd0, 2, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
263 {"rcl", 2, 0xc0, 2, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
264 {"rcl", 2, 0xd2, 2, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
265 {"rcl", 1, 0xd0, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
266
267 {"rcr", 2, 0xd0, 3, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
268 {"rcr", 2, 0xc0, 3, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
269 {"rcr", 2, 0xd2, 3, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
270 {"rcr", 1, 0xd0, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
271
272 {"sal", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
273 {"sal", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
274 {"sal", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
275 {"sal", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
276 {"shl", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
277 {"shl", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
278 {"shl", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
279 {"shl", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
280
281 {"shld", 3, 0x0fa4, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
282 {"shld", 3, 0x0fa5, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
283 {"shld", 2, 0x0fa5, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
284
285 {"shr", 2, 0xd0, 5, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
286 {"shr", 2, 0xc0, 5, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
287 {"shr", 2, 0xd2, 5, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
288 {"shr", 1, 0xd0, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
289
290 {"shrd", 3, 0x0fac, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
291 {"shrd", 3, 0x0fad, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
292 {"shrd", 2, 0x0fad, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
293
294 {"sar", 2, 0xd0, 7, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
295 {"sar", 2, 0xc0, 7, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
296 {"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
297 {"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
298
299 /* control transfer instructions */
300 {"call", 1, 0xe8, X, wl_Suf|JumpDword, { Disp16|Disp32, 0, 0} },
301 {"call", 1, 0xff, 2, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
302 {"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
303 {"lcall", 1, 0xff, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
304
305 #define JUMP_PC_RELATIVE 0xeb
306 {"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} },
307 {"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
308 {"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
309 {"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} },
310
311 {"ret", 0, 0xc3, X, wl_Suf, { 0, 0, 0} },
312 {"ret", 1, 0xc2, X, wl_Suf, { Imm16, 0, 0} },
313 {"lret", 0, 0xcb, X, wl_Suf, { 0, 0, 0} },
314 {"lret", 1, 0xca, X, wl_Suf, { Imm16, 0, 0} },
315 {"enter", 2, 0xc8, X, wl_Suf, { Imm16, Imm8, 0} },
316 {"leave", 0, 0xc9, X, wl_Suf, { 0, 0, 0} },
317
318 /* conditional jumps */
319 {"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} },
320 {"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} },
321 {"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
322 {"jc", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
323 {"jnae", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
324 {"jnb", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
325 {"jnc", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
326 {"jae", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
327 {"je", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
328 {"jz", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
329 {"jne", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
330 {"jnz", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
331 {"jbe", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
332 {"jna", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
333 {"jnbe", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
334 {"ja", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
335 {"js", 1, 0x78, X, NoSuf|Jump, { Disp, 0, 0} },
336 {"jns", 1, 0x79, X, NoSuf|Jump, { Disp, 0, 0} },
337 {"jp", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
338 {"jpe", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
339 {"jnp", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
340 {"jpo", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
341 {"jl", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
342 {"jnge", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
343 {"jnl", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
344 {"jge", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
345 {"jle", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
346 {"jng", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
347 {"jnle", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
348 {"jg", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
349
350 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
351 {"jcxz", 1, 0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
352 {"jecxz", 1, 0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
353
354 /* The loop instructions also use the address size prefix to select
355 %cx rather than %ecx for the loop count, so the `w' form of these
356 instructions emit an address size prefix rather than a data size
357 prefix. */
358 {"loop", 1, 0xe2, X, wl_Suf|JumpByte, { Disp, 0, 0} },
359 {"loopz", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
360 {"loope", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
361 {"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
362 {"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
363
364 /* set byte on flag instructions */
365 {"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
366 {"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
367 {"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
368 {"setc", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
369 {"setnae", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
370 {"setnb", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
371 {"setnc", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
372 {"setae", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
373 {"sete", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
374 {"setz", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
375 {"setne", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
376 {"setnz", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
377 {"setbe", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
378 {"setna", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
379 {"setnbe", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
380 {"seta", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
381 {"sets", 1, 0x0f98, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
382 {"setns", 1, 0x0f99, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
383 {"setp", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
384 {"setpe", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
385 {"setnp", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
386 {"setpo", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
387 {"setl", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
388 {"setnge", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
389 {"setnl", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
390 {"setge", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
391 {"setle", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
392 {"setng", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
393 {"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
394 {"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
395
396 /* string manipulation */
397 {"cmps", 0, 0xa6, X, bwl_Suf|W|IsString, { 0, 0, 0} },
398 {"cmps", 2, 0xa6, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
399 {"scmp", 0, 0xa6, X, bwl_Suf|W|IsString, { 0, 0, 0} },
400 {"scmp", 2, 0xa6, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
401 {"ins", 0, 0x6c, X, bwl_Suf|W|IsString, { 0, 0, 0} },
402 {"ins", 2, 0x6c, X, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
403 {"outs", 0, 0x6e, X, bwl_Suf|W|IsString, { 0, 0, 0} },
404 {"outs", 2, 0x6e, X, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
405 {"lods", 0, 0xac, X, bwl_Suf|W|IsString, { 0, 0, 0} },
406 {"lods", 1, 0xac, X, bwl_Suf|W|IsString, { AnyMem, 0, 0} },
407 {"lods", 2, 0xac, X, bwl_Suf|W|IsString, { AnyMem, Acc, 0} },
408 {"slod", 0, 0xac, X, bwl_Suf|W|IsString, { 0, 0, 0} },
409 {"slod", 1, 0xac, X, bwl_Suf|W|IsString, { AnyMem, 0, 0} },
410 {"slod", 2, 0xac, X, bwl_Suf|W|IsString, { AnyMem, Acc, 0} },
411 {"movs", 0, 0xa4, X, bwl_Suf|W|IsString, { 0, 0, 0} },
412 {"movs", 2, 0xa4, X, bwl_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
413 {"smov", 0, 0xa4, X, bwl_Suf|W|IsString, { 0, 0, 0} },
414 {"smov", 2, 0xa4, X, bwl_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
415 {"scas", 0, 0xae, X, bwl_Suf|W|IsString, { 0, 0, 0} },
416 {"scas", 1, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
417 {"scas", 2, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
418 {"ssca", 0, 0xae, X, bwl_Suf|W|IsString, { 0, 0, 0} },
419 {"ssca", 1, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
420 {"ssca", 2, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
421 {"stos", 0, 0xaa, X, bwl_Suf|W|IsString, { 0, 0, 0} },
422 {"stos", 1, 0xaa, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
423 {"stos", 2, 0xaa, X, bwl_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
424 {"ssto", 0, 0xaa, X, bwl_Suf|W|IsString, { 0, 0, 0} },
425 {"ssto", 1, 0xaa, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
426 {"ssto", 2, 0xaa, X, bwl_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
427 {"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} },
428 {"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} },
429
430 /* bit manipulation */
431 {"bsf", 2, 0x0fbc, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
432 {"bsr", 2, 0x0fbd, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
433 {"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
434 {"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
435 {"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
436 {"btc", 2, 0x0fba, 7, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
437 {"btr", 2, 0x0fb3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
438 {"btr", 2, 0x0fba, 6, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
439 {"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
440 {"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
441
442 /* interrupts & op. sys insns */
443 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
444 int 3 insn. */
445 #define INT_OPCODE 0xcd
446 #define INT3_OPCODE 0xcc
447 {"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} },
448 {"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} },
449 {"into", 0, 0xce, X, NoSuf, { 0, 0, 0} },
450 {"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} },
451 /* i386sl, i486sl, later 486, and Pentium */
452 {"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} },
453
454 {"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} },
455
456 {"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} },
457 /* nop is actually 'xchgl %eax, %eax' */
458 {"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} },
459
460 /* protection control */
461 {"arpl", 2, 0x63, X, NoSuf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
462 {"lar", 2, 0x0f02, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
463 {"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} },
464 {"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
465 {"lldt", 1, 0x0f00, 2, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
466 {"lmsw", 1, 0x0f01, 6, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
467 {"lsl", 2, 0x0f03, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
468 {"ltr", 1, 0x0f00, 3, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
469
470 {"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} },
471 {"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} },
472 {"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
473 {"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
474 {"str", 1, 0x0f00, 1, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
475
476 {"verr", 1, 0x0f00, 4, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
477 {"verw", 1, 0x0f00, 5, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
478
479 /* floating point instructions */
480
481 /* load */
482 {"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
483 {"fld", 1, 0xd9, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 <-- mem float/double */
484 {"fld", 1, 0xd9c0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
485 {"fild", 1, 0xdf, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */
486 {"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
487 {"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
488 {"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
489 {"fbld", 1, 0xdf, 4, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem bcd */
490
491 /* store (no pop) */
492 {"fst", 1, 0xddd0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
493 {"fst", 1, 0xd9, 2, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
494 {"fst", 1, 0xddd0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
495 {"fist", 1, 0xdf, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
496
497 /* store (with pop) */
498 {"fstp", 1, 0xddd8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
499 {"fstp", 1, 0xd9, 3, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
500 {"fstp", 1, 0xddd8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
501 {"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
502 {"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
503 {"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
504 {"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */
505 {"fbstp", 1, 0xdf, 6, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem bcd */
506
507 /* exchange %st<n> with %st0 */
508 {"fxch", 1, 0xd9c8, X, FP|ShortForm, { FloatReg, 0, 0} },
509 {"fxch", 0, 0xd9c9, X, FP, { 0, 0, 0} }, /* alias for fxch %st(1) */
510
511 /* comparison (without pop) */
512 {"fcom", 1, 0xd8d0, X, FP|ShortForm, { FloatReg, 0, 0} },
513 {"fcom", 0, 0xd8d1, X, FP, { 0, 0, 0} }, /* alias for fcom %st(1) */
514 {"fcom", 1, 0xd8, 2, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
515 {"fcom", 1, 0xd8d0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
516 {"ficom", 1, 0xde, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
517
518 /* comparison (with pop) */
519 {"fcomp", 1, 0xd8d8, X, FP|ShortForm, { FloatReg, 0, 0} },
520 {"fcomp", 0, 0xd8d9, X, FP, { 0, 0, 0} }, /* alias for fcomp %st(1) */
521 {"fcomp", 1, 0xd8, 3, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
522 {"fcomp", 1, 0xd8d8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
523 {"ficomp", 1, 0xde, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
524 {"fcompp", 0, 0xded9, X, FP, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
525
526 /* unordered comparison (with pop) */
527 {"fucom", 1, 0xdde0, X, FP|ShortForm, { FloatReg, 0, 0} },
528 {"fucom", 0, 0xdde1, X, FP, { 0, 0, 0} }, /* alias for fucom %st(1) */
529 {"fucomp", 1, 0xdde8, X, FP|ShortForm, { FloatReg, 0, 0} },
530 {"fucomp", 0, 0xdde9, X, FP, { 0, 0, 0} }, /* alias for fucomp %st(1) */
531 {"fucompp",0, 0xdae9, X, FP, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
532
533 {"ftst", 0, 0xd9e4, X, FP, { 0, 0, 0} }, /* test %st0 */
534 {"fxam", 0, 0xd9e5, X, FP, { 0, 0, 0} }, /* examine %st0 */
535
536 /* load constants into %st0 */
537 {"fld1", 0, 0xd9e8, X, FP, { 0, 0, 0} }, /* %st0 <-- 1.0 */
538 {"fldl2t", 0, 0xd9e9, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(10) */
539 {"fldl2e", 0, 0xd9ea, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(e) */
540 {"fldpi", 0, 0xd9eb, X, FP, { 0, 0, 0} }, /* %st0 <-- pi */
541 {"fldlg2", 0, 0xd9ec, X, FP, { 0, 0, 0} }, /* %st0 <-- log10(2) */
542 {"fldln2", 0, 0xd9ed, X, FP, { 0, 0, 0} }, /* %st0 <-- ln(2) */
543 {"fldz", 0, 0xd9ee, X, FP, { 0, 0, 0} }, /* %st0 <-- 0.0 */
544
545 /* arithmetic */
546
547 /* add */
548 {"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
549 {"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */
550 #if UNIXWARE_COMPAT
551 {"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, /* alias for faddp */
552 #endif
553 {"fadd", 1, 0xd8, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
554 {"fiadd", 1, 0xde, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
555
556 {"faddp", 2, 0xdec0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
557 {"faddp", 1, 0xdec0, X, FP|ShortForm, { FloatReg, 0, 0} },
558 {"faddp", 0, 0xdec1, X, FP, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
559 {"faddp", 2, 0xdec0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
560
561 /* subtract */
562 {"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
563 {"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} },
564 #if UNIXWARE_COMPAT
565 {"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubp */
566 #endif
567 {"fsub", 1, 0xd8, 4, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
568 {"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
569
570 #if UNIXWARE_COMPAT
571 {"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
572 {"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
573 {"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} },
574 {"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
575 #else
576 {"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
577 {"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
578 {"fsubp", 0, 0xdee9, X, FP, { 0, 0, 0} },
579 #endif
580
581 /* subtract reverse */
582 {"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
583 {"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} },
584 #if UNIXWARE_COMPAT
585 {"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubrp */
586 #endif
587 {"fsubr", 1, 0xd8, 5, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
588 {"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
589
590 #if UNIXWARE_COMPAT
591 {"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
592 {"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
593 {"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} },
594 {"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
595 #else
596 {"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
597 {"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
598 {"fsubrp", 0, 0xdee1, X, FP, { 0, 0, 0} },
599 #endif
600
601 /* multiply */
602 {"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
603 {"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} },
604 #if UNIXWARE_COMPAT
605 {"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fmulp */
606 #endif
607 {"fmul", 1, 0xd8, 1, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
608 {"fimul", 1, 0xde, 1, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
609
610 {"fmulp", 2, 0xdec8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
611 {"fmulp", 1, 0xdec8, X, FP|ShortForm, { FloatReg, 0, 0} },
612 {"fmulp", 0, 0xdec9, X, FP, { 0, 0, 0} },
613 {"fmulp", 2, 0xdec8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
614
615 /* divide */
616 {"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
617 {"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} },
618 #if UNIXWARE_COMPAT
619 {"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivp */
620 #endif
621 {"fdiv", 1, 0xd8, 6, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
622 {"fidiv", 1, 0xde, 6, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
623
624 #if UNIXWARE_COMPAT
625 {"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
626 {"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
627 {"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} },
628 {"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
629 #else
630 {"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
631 {"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
632 {"fdivp", 0, 0xdef9, X, FP, { 0, 0, 0} },
633 #endif
634
635 /* divide reverse */
636 {"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
637 {"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} },
638 #if UNIXWARE_COMPAT
639 {"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivrp */
640 #endif
641 {"fdivr", 1, 0xd8, 7, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
642 {"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
643
644 #if UNIXWARE_COMPAT
645 {"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
646 {"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
647 {"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} },
648 {"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
649 #else
650 {"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
651 {"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
652 {"fdivrp", 0, 0xdef1, X, FP, { 0, 0, 0} },
653 #endif
654
655 {"f2xm1", 0, 0xd9f0, X, FP, { 0, 0, 0} },
656 {"fyl2x", 0, 0xd9f1, X, FP, { 0, 0, 0} },
657 {"fptan", 0, 0xd9f2, X, FP, { 0, 0, 0} },
658 {"fpatan", 0, 0xd9f3, X, FP, { 0, 0, 0} },
659 {"fxtract",0, 0xd9f4, X, FP, { 0, 0, 0} },
660 {"fprem1", 0, 0xd9f5, X, FP, { 0, 0, 0} },
661 {"fdecstp",0, 0xd9f6, X, FP, { 0, 0, 0} },
662 {"fincstp",0, 0xd9f7, X, FP, { 0, 0, 0} },
663 {"fprem", 0, 0xd9f8, X, FP, { 0, 0, 0} },
664 {"fyl2xp1",0, 0xd9f9, X, FP, { 0, 0, 0} },
665 {"fsqrt", 0, 0xd9fa, X, FP, { 0, 0, 0} },
666 {"fsincos",0, 0xd9fb, X, FP, { 0, 0, 0} },
667 {"frndint",0, 0xd9fc, X, FP, { 0, 0, 0} },
668 {"fscale", 0, 0xd9fd, X, FP, { 0, 0, 0} },
669 {"fsin", 0, 0xd9fe, X, FP, { 0, 0, 0} },
670 {"fcos", 0, 0xd9ff, X, FP, { 0, 0, 0} },
671 {"fchs", 0, 0xd9e0, X, FP, { 0, 0, 0} },
672 {"fabs", 0, 0xd9e1, X, FP, { 0, 0, 0} },
673
674 /* processor control */
675 {"fninit", 0, 0xdbe3, X, FP, { 0, 0, 0} },
676 {"finit", 0, 0xdbe3, X, FP|FWait, { 0, 0, 0} },
677 {"fldcw", 1, 0xd9, 5, FP|Modrm, { ShortMem, 0, 0} },
678 {"fnstcw", 1, 0xd9, 7, FP|Modrm, { ShortMem, 0, 0} },
679 {"fstcw", 1, 0xd9, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
680 {"fnstsw", 1, 0xdfe0, X, FP, { Acc, 0, 0} },
681 {"fnstsw", 1, 0xdd, 7, FP|Modrm, { ShortMem, 0, 0} },
682 {"fnstsw", 0, 0xdfe0, X, FP, { 0, 0, 0} },
683 {"fstsw", 1, 0xdfe0, X, FP|FWait, { Acc, 0, 0} },
684 {"fstsw", 1, 0xdd, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
685 {"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} },
686 {"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} },
687 {"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} },
688 /* Short forms of fldenv, fstenv use data size prefix.
689 FIXME: Are these the right suffixes? */
690 {"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
691 {"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
692 {"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
693 {"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
694 {"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
695 {"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
696
697 {"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} },
698 /* P6:free st(i), pop st */
699 {"ffreep", 1, 0xdfc0, X, FP|ShortForm, { FloatReg, 0, 0} },
700 {"fnop", 0, 0xd9d0, X, FP, { 0, 0, 0} },
701 #define FWAIT_OPCODE 0x9b
702 {"fwait", 0, 0x9b, X, FP, { 0, 0, 0} },
703
704 /*
705 opcode prefixes; we allow them as seperate insns too
706 */
707 #define ADDR_PREFIX_OPCODE 0x67
708 {"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
709 {"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
710 {"aword", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
711 {"adword", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
712 #define DATA_PREFIX_OPCODE 0x66
713 {"data16", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
714 {"data32", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
715 {"word", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
716 {"dword", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
717 #define LOCK_PREFIX_OPCODE 0xf0
718 {"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} },
719 {"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} },
720 #define CS_PREFIX_OPCODE 0x2e
721 {"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} },
722 #define DS_PREFIX_OPCODE 0x3e
723 {"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} },
724 #define ES_PREFIX_OPCODE 0x26
725 {"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} },
726 #define FS_PREFIX_OPCODE 0x64
727 {"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} },
728 #define GS_PREFIX_OPCODE 0x65
729 {"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} },
730 #define SS_PREFIX_OPCODE 0x36
731 {"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} },
732 #define REPNE_PREFIX_OPCODE 0xf2
733 #define REPE_PREFIX_OPCODE 0xf3
734 {"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
735 {"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
736 {"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
737 {"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
738 {"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
739
740 /* 486 extensions */
741
742 {"bswap", 1, 0x0fc8, X, NoSuf|ShortForm, { Reg32,0,0 } },
743 {"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
744 {"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
745 {"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} },
746 {"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} },
747 {"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} },
748
749 /* 586 and late 486 extensions */
750 {"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} },
751
752 /* Pentium extensions */
753 {"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} },
754 {"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} },
755 {"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} },
756 {"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} },
757 {"sysenter", 0, 0x0f34, X, NoSuf, { 0, 0, 0} },
758 {"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} },
759 {"fxsave", 1, 0x0fae, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
760 {"fxrstor", 1, 0x0fae, 1, sl_Suf|Modrm, { LLongMem, 0, 0} },
761
762 /* Pentium Pro extensions */
763 {"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} },
764
765 {"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* official undefined instr. */
766 {"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* alias for ud2 */
767 {"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */
768
769 {"cmovo", 2, 0x0f40, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
770 {"cmovno", 2, 0x0f41, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
771 {"cmovb", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
772 {"cmovae", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
773 {"cmove", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
774 {"cmovne", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
775 {"cmovbe", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
776 {"cmova", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
777 {"cmovs", 2, 0x0f48, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
778 {"cmovns", 2, 0x0f49, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
779 {"cmovp", 2, 0x0f4a, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
780 {"cmovnp", 2, 0x0f4b, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
781 {"cmovl", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
782 {"cmovge", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
783 {"cmovle", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
784 {"cmovg", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
785
786 {"fcmovb", 2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
787 {"fcmove", 2, 0xdac8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
788 {"fcmovbe", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
789 {"fcmovu", 2, 0xdad8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
790 {"fcmovnb", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
791 {"fcmovne", 2, 0xdbc8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
792 {"fcmovnbe",2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
793 {"fcmovnu", 2, 0xdbd8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
794
795 {"fcomi", 2, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
796 {"fucomi", 2, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
797 {"fcomip", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
798 {"fucomip", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
799
800 /* MMX instructions. */
801
802 {"emms", 0, 0x0f77, X, NoSuf, { 0, 0, 0 } },
803 {"movd", 2, 0x0f6e, X, NoSuf|Modrm, { Reg32|LongMem, RegMMX, 0 } },
804 {"movd", 2, 0x0f7e, X, NoSuf|Modrm, { RegMMX, Reg32|LongMem, 0 } },
805 {"movq", 2, 0x0f6f, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
806 {"movq", 2, 0x0f7f, X, NoSuf|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
807 {"packssdw", 2, 0x0f6b, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
808 {"packsswb", 2, 0x0f63, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
809 {"packuswb", 2, 0x0f67, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
810 {"paddb", 2, 0x0ffc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
811 {"paddw", 2, 0x0ffd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
812 {"paddd", 2, 0x0ffe, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
813 {"paddsb", 2, 0x0fec, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
814 {"paddsw", 2, 0x0fed, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
815 {"paddusb", 2, 0x0fdc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
816 {"paddusw", 2, 0x0fdd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
817 {"pand", 2, 0x0fdb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
818 {"pandn", 2, 0x0fdf, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
819 {"pcmpeqb", 2, 0x0f74, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
820 {"pcmpeqw", 2, 0x0f75, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
821 {"pcmpeqd", 2, 0x0f76, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
822 {"pcmpgtb", 2, 0x0f64, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
823 {"pcmpgtw", 2, 0x0f65, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
824 {"pcmpgtd", 2, 0x0f66, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
825 {"pmaddwd", 2, 0x0ff5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
826 {"pmulhw", 2, 0x0fe5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
827 {"pmullw", 2, 0x0fd5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
828 {"por", 2, 0x0feb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
829 {"psllw", 2, 0x0ff1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
830 {"psllw", 2, 0x0f71, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
831 {"pslld", 2, 0x0ff2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
832 {"pslld", 2, 0x0f72, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
833 {"psllq", 2, 0x0ff3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
834 {"psllq", 2, 0x0f73, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
835 {"psraw", 2, 0x0fe1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
836 {"psraw", 2, 0x0f71, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
837 {"psrad", 2, 0x0fe2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
838 {"psrad", 2, 0x0f72, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
839 {"psrlw", 2, 0x0fd1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
840 {"psrlw", 2, 0x0f71, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
841 {"psrld", 2, 0x0fd2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
842 {"psrld", 2, 0x0f72, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
843 {"psrlq", 2, 0x0fd3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
844 {"psrlq", 2, 0x0f73, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
845 {"psubb", 2, 0x0ff8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
846 {"psubw", 2, 0x0ff9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
847 {"psubd", 2, 0x0ffa, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
848 {"psubsb", 2, 0x0fe8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
849 {"psubsw", 2, 0x0fe9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
850 {"psubusb", 2, 0x0fd8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
851 {"psubusw", 2, 0x0fd9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
852 {"punpckhbw",2, 0x0f68, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
853 {"punpckhwd",2, 0x0f69, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
854 {"punpckhdq",2, 0x0f6a, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
855 {"punpcklbw",2, 0x0f60, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
856 {"punpcklwd",2, 0x0f61, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
857 {"punpckldq",2, 0x0f62, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
858 {"pxor", 2, 0x0fef, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
859
860 {NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
861 };
862 #undef X
863 #undef ReverseModrm
864 #undef NoSuf
865 #undef b_Suf
866 #undef w_Suf
867 #undef l_Suf
868 #undef bw_Suf
869 #undef bl_Suf
870 #undef wl_Suf
871 #undef sl_Suf
872 #undef bwl_Suf
873 #undef FP
874 #undef l_FP
875 #undef sl_FP
876
877 #define MAX_OPCODE_SIZE 16 /* for parsing opcodes from input */
878
879
880 /* 386 register table */
881
882 static const reg_entry i386_regtab[] = {
883 /* 8 bit regs */
884 {"al", Reg8|Acc, 0},
885 {"cl", Reg8|ShiftCount, 1},
886 {"dl", Reg8, 2},
887 {"bl", Reg8, 3},
888 {"ah", Reg8, 4},
889 {"ch", Reg8, 5},
890 {"dh", Reg8, 6},
891 {"bh", Reg8, 7},
892 /* 16 bit regs */
893 {"ax", Reg16|Acc, 0},
894 {"cx", Reg16, 1},
895 {"dx", Reg16|InOutPortReg, 2},
896 {"bx", Reg16|BaseIndex, 3},
897 {"sp", Reg16, 4},
898 {"bp", Reg16|BaseIndex, 5},
899 {"si", Reg16|BaseIndex, 6},
900 {"di", Reg16|BaseIndex, 7},
901 /* 32 bit regs */
902 {"eax", Reg32|BaseIndex|Acc, 0},
903 {"ecx", Reg32|BaseIndex, 1},
904 {"edx", Reg32|BaseIndex, 2},
905 {"ebx", Reg32|BaseIndex, 3},
906 {"esp", Reg32, 4},
907 {"ebp", Reg32|BaseIndex, 5},
908 {"esi", Reg32|BaseIndex, 6},
909 {"edi", Reg32|BaseIndex, 7},
910 /* segment registers */
911 {"es", SReg2, 0},
912 {"cs", SReg2, 1},
913 {"ss", SReg2, 2},
914 {"ds", SReg2, 3},
915 {"fs", SReg3, 4},
916 {"gs", SReg3, 5},
917 /* control registers */
918 {"cr0", Control, 0},
919 {"cr1", Control, 1},
920 {"cr2", Control, 2},
921 {"cr3", Control, 3},
922 {"cr4", Control, 4},
923 {"cr5", Control, 5},
924 {"cr6", Control, 6},
925 {"cr7", Control, 7},
926 /* debug registers */
927 {"db0", Debug, 0},
928 {"db1", Debug, 1},
929 {"db2", Debug, 2},
930 {"db3", Debug, 3},
931 {"db4", Debug, 4},
932 {"db5", Debug, 5},
933 {"db6", Debug, 6},
934 {"db7", Debug, 7},
935 {"dr0", Debug, 0},
936 {"dr1", Debug, 1},
937 {"dr2", Debug, 2},
938 {"dr3", Debug, 3},
939 {"dr4", Debug, 4},
940 {"dr5", Debug, 5},
941 {"dr6", Debug, 6},
942 {"dr7", Debug, 7},
943 /* test registers */
944 {"tr0", Test, 0},
945 {"tr1", Test, 1},
946 {"tr2", Test, 2},
947 {"tr3", Test, 3},
948 {"tr4", Test, 4},
949 {"tr5", Test, 5},
950 {"tr6", Test, 6},
951 {"tr7", Test, 7},
952 /* float registers */
953 {"st(0)", FloatReg|FloatAcc, 0},
954 {"st", FloatReg|FloatAcc, 0},
955 {"st(1)", FloatReg, 1},
956 {"st(2)", FloatReg, 2},
957 {"st(3)", FloatReg, 3},
958 {"st(4)", FloatReg, 4},
959 {"st(5)", FloatReg, 5},
960 {"st(6)", FloatReg, 6},
961 {"st(7)", FloatReg, 7},
962 {"mm0", RegMMX, 0},
963 {"mm1", RegMMX, 1},
964 {"mm2", RegMMX, 2},
965 {"mm3", RegMMX, 3},
966 {"mm4", RegMMX, 4},
967 {"mm5", RegMMX, 5},
968 {"mm6", RegMMX, 6},
969 {"mm7", RegMMX, 7}
970 };
971
972 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
973
974 /* segment stuff */
975 static const seg_entry cs = { "cs", 0x2e };
976 static const seg_entry ds = { "ds", 0x3e };
977 static const seg_entry ss = { "ss", 0x36 };
978 static const seg_entry es = { "es", 0x26 };
979 static const seg_entry fs = { "fs", 0x64 };
980 static const seg_entry gs = { "gs", 0x65 };
981
982 /* end of i386-opcode.h */
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