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1 /* opcode/i386.h -- Intel 80386 opcode macros
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
22 ix86 Unix assemblers, generate floating point instructions with
23 reversed source and destination registers in certain cases.
24 Unfortunately, gcc and possibly many other programs use this
25 reversed syntax, so we're stuck with it.
26
27 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
28 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
29 the expected st(3) = st(3) - st
30
31 This happens with all the non-commutative arithmetic floating point
32 operations with two register operands, where the source register is
33 %st, and destination register is %st(i).
34
35 The affected opcode map is dceX, dcfX, deeX, defX. */
36
37 #ifndef OPCODE_I386_H
38 #define OPCODE_I386_H
39
40 #ifndef SYSV386_COMPAT
41 /* Set non-zero for broken, compatible instructions. Set to zero for
42 non-broken opcodes at your peril. gcc generates SystemV/386
43 compatible instructions. */
44 #define SYSV386_COMPAT 1
45 #endif
46
47 #define MOV_AX_DISP32 0xa0
48 #define POP_SEG_SHORT 0x07
49 #define JUMP_PC_RELATIVE 0xeb
50 #define INT_OPCODE 0xcd
51 #define INT3_OPCODE 0xcc
52 /* The opcode for the fwait instruction, which disassembler treats as a
53 prefix when it can. */
54 #define FWAIT_OPCODE 0x9b
55
56 /* Instruction prefixes.
57 NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
58 part of the opcode. Other prefixes may still appear between them
59 and the 0x0f part of the opcode. */
60 #define ADDR_PREFIX_OPCODE 0x67
61 #define DATA_PREFIX_OPCODE 0x66
62 #define LOCK_PREFIX_OPCODE 0xf0
63 #define CS_PREFIX_OPCODE 0x2e
64 #define DS_PREFIX_OPCODE 0x3e
65 #define ES_PREFIX_OPCODE 0x26
66 #define FS_PREFIX_OPCODE 0x64
67 #define GS_PREFIX_OPCODE 0x65
68 #define SS_PREFIX_OPCODE 0x36
69 #define REPNE_PREFIX_OPCODE 0xf2
70 #define REPE_PREFIX_OPCODE 0xf3
71 #define XACQUIRE_PREFIX_OPCODE 0xf2
72 #define XRELEASE_PREFIX_OPCODE 0xf3
73 #define BND_PREFIX_OPCODE 0xf2
74 #define NOTRACK_PREFIX_OPCODE 0x3e
75
76 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
77 #define NOP_OPCODE (char) 0x90
78
79 /* register numbers */
80 #define EAX_REG_NUM 0
81 #define ECX_REG_NUM 1
82 #define EDX_REG_NUM 2
83 #define EBX_REG_NUM 3
84 #define ESP_REG_NUM 4
85 #define EBP_REG_NUM 5
86 #define ESI_REG_NUM 6
87 #define EDI_REG_NUM 7
88
89 /* modrm_byte.regmem for twobyte escape */
90 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
91 /* index_base_byte.index for no index register addressing */
92 #define NO_INDEX_REGISTER ESP_REG_NUM
93 /* index_base_byte.base for no base register addressing */
94 #define NO_BASE_REGISTER EBP_REG_NUM
95 #define NO_BASE_REGISTER_16 6
96
97 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
98 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
99 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
100
101 /* Extract fields from the mod/rm byte. */
102 #define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
103 #define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
104 #define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)
105
106 /* Extract fields from the sib byte. */
107 #define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
108 #define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
109 #define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)
110
111 /* x86-64 extension prefix. */
112 #define REX_OPCODE 0x40
113
114 /* Non-zero if OPCODE is the rex prefix. */
115 #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
116
117 /* Indicates 64 bit operand size. */
118 #define REX_W 8
119 /* High extension to reg field of modrm byte. */
120 #define REX_R 4
121 /* High extension to SIB index field. */
122 #define REX_X 2
123 /* High extension to base field of modrm or SIB, or reg field of opcode. */
124 #define REX_B 1
125
126 /* max operands per insn */
127 #define MAX_OPERANDS 5
128
129 /* max immediates per insn (lcall, ljmp, insertq, extrq) */
130 #define MAX_IMMEDIATE_OPERANDS 2
131
132 /* max memory refs per insn (string ops) */
133 #define MAX_MEMORY_OPERANDS 2
134
135 /* max size of insn mnemonics. */
136 #define MAX_MNEM_SIZE 20
137
138 /* max size of register name in insn mnemonics. */
139 #define MAX_REG_NAME_SIZE 8
140
141 #endif /* OPCODE_I386_H */