include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 1, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  20
  21 #ifndef PPC_H
  22 #define PPC_H
  23
  24 /* The opcode table is an array of struct powerpc_opcode.  */
  25
  26 struct powerpc_opcode
  27 {
  28   /* The opcode name.  */
  29   const char *name;
  30
  31   /* The opcode itself.  Those bits which will be filled in with
  32      operands are zeroes.  */
  33   unsigned long opcode;
  34
  35   /* The opcode mask.  This is used by the disassembler.  This is a
  36      mask containing ones indicating those bits which must match the
  37      opcode field, and zeroes indicating those bits which need not
  38      match (and are presumably filled in by operands).  */
  39   unsigned long mask;
  40
  41   /* One bit flags for the opcode.  These are used to indicate which
  42      specific processors support the instructions.  The defined values
  43      are listed below.  */
  44   unsigned long flags;
  45
  46   /* An array of operand codes.  Each code is an index into the
  47      operand table.  They appear in the order which the operands must
  48      appear in assembly code, and are terminated by a zero.  */
  49   char operands[8];
  50 };
  51
  52 /* The table itself is sorted by major opcode number, and is otherwise
  53    in the order in which the disassembler should consider
  54    instructions.  */
  55 extern const struct powerpc_opcode powerpc_opcodes[];
  56 extern const int powerpc_num_opcodes;
  57
  58 /* Values defined for the flags field of a struct powerpc_opcode.  */
  59
  60 /* Opcode is defined for the PowerPC architecture.  */
  61 #define PPC_OPCODE_PPC (01)
  62
  63 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  64 #define PPC_OPCODE_POWER (02)
  65
  66 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  67 #define PPC_OPCODE_POWER2 (04)
  68
  69 /* Opcode is only defined on 32 bit architectures.  */
  70 #define PPC_OPCODE_32 (010)
  71
  72 /* Opcode is only defined on 64 bit architectures.  */
  73 #define PPC_OPCODE_64 (020)
  74
  75 /* A macro to extract the major opcode from an instruction.  */
  76 #define PPC_OP(i) (((i) >> 26) & 0x3f)
  77 \f
  78 /* The operands table is an array of struct powerpc_operand.  */
  79
  80 struct powerpc_operand
  81 {
  82   /* The number of bits in the operand.  */
  83   int bits;
  84
  85   /* How far the operand is left shifted in the instruction.  */
  86   int shift;
  87
  88   /* Non zero if the operand is signed (this is zero for most
  89      operands).  */
  90   int signedp;
  91
  92   /* Insertion function.  This is used by the assembler.  To insert an
  93      operand value into an instruction, check this field.
  94
  95      If it is NULL, execute
  96          i |= (op & ((1 << o->bits) - 1)) << o->shift;
  97      (i is the instruction which we are filling in, o is a pointer to
  98      this structure, and op is the opcode value; this assumes twos
  99      complement arithmetic).
 100
 101      If this field is not NULL, then simply call it with the
 102      instruction and the operand value.  It will return the new value
 103      of the instruction.  If the ERRMSG argument is not NULL, then if
 104      the operand value is illegal, *ERRMSG will be set to a warning
 105      string (the operand will be inserted in any case).  If the
 106      operand value is legal, *ERRMSG will be unchanged (most operands
 107      can accept any value).  */
 108   unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
 109                                    const char **errmsg));
 110
 111   /* Extraction function.  This is used by the disassembler.  To
 112      extract this operand type from an instruction, check this field.
 113
 114      If it is NULL, compute
 115          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 116          if (o->signedp
 117              && (op & (1 << (o->bits - 1))) != 0)
 118            op -= 1 << o->bits;
 119      (i is the instruction, o is a pointer to this structure, and op
 120      is the result; this assumes twos complement arithmetic).
 121
 122      If this field is not NULL, then simply call it with the
 123      instruction value.  It will return the value of the operand.  If
 124      the INVALID argument is not NULL, *INVALID will be set to
 125      non-zero if this operand type can not actually be extracted from
 126      this operand (i.e., the instruction does not match).  If the
 127      operand is valid, *INVALID will not be changed.  */
 128   long (*extract) PARAMS ((unsigned long instruction, int *invalid));
 129
 130   /* One bit syntax flags.  */
 131   unsigned long flags;
 132 };
 133
 134 /* Elements in the table are retrieved by indexing with values from
 135    the operands field of the powerpc_opcodes table.  */
 136
 137 extern const struct powerpc_operand powerpc_operands[];
 138
 139 /* Values defined for the flags field of a struct powerpc_operand.  */
 140
 141 /* This operand does not actually exist in the assembler input.  This
 142    is used to support extended mnemonics such as mr, for which two
 143    operands fields are identical.  The assembler should call the
 144    insert function with any op value.  The disassembler should call
 145    the extract function, ignore the return value, and check the value
 146    placed in the valid argument.  */
 147 #define PPC_OPERAND_FAKE (01)
 148
 149 /* The next operand should be wrapped in parentheses rather than
 150    separated from this one by a comma.  This is used for the load and
 151    store instructions which want their operands to look like
 152        reg,displacement(reg)
 153    */
 154 #define PPC_OPERAND_PARENS (02)
 155
 156 /* This operand may use the symbolic names for the CR fields, which
 157    are
 158        lt  0    gt  1   eq  2   so  3   un  3
 159        cr0 0    cr1 1   cr2 2   cr3 3
 160        cr4 4    cr5 5   cr6 6   cr7 7
 161    These may be combined arithmetically, as in cr2*4+gt.  These are
 162    only supported on the PowerPC, not the POWER.  */
 163 #define PPC_OPERAND_CR (04)
 164
 165 /* This operand names a register.  The disassembler uses this to print
 166    register names with a leading 'r'.  */
 167 #define PPC_OPERAND_GPR (010)
 168
 169 /* This operand names a floating point register.  The disassembler
 170    prints these with a leading 'f'.  */
 171 #define PPC_OPERAND_FPR (020)
 172
 173 /* This operand is a relative branch displacement.  The disassembler
 174    prints these symbolically if possible.  */
 175 #define PPC_OPERAND_RELATIVE (0100)
 176
 177 /* This operand is an absolute branch address.  The disassembler
 178    prints these symbolically if possible.  */
 179 #define PPC_OPERAND_ABSOLUTE (0200)
 180
 181 /* This operand is optional, and is zero if omitted.  This is used for
 182    the optional BF and L fields in the comparison instructions.  The
 183    assembler must count the number of operands remaining on the line,
 184    and the number of operands remaining for the opcode, and decide
 185    whether this operand is present or not.  The disassembler should
 186    print this operand out only if it is not zero.  */
 187 #define PPC_OPERAND_OPTIONAL (0400)
 188
 189 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 190    is omitted, then for the next operand use this operand value plus
 191    1, ignoring the next operand field for the opcode.  This wretched
 192    hack is needed because the Power rotate instructions can take
 193    either 4 or 5 operands.  The disassembler should print this operand
 194    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 195 #define PPC_OPERAND_NEXT (01000)
 196
 197 /* This operand should be regarded as a negative number for the
 198    purposes of overflow checking (i.e., the normal most negative
 199    number is disallowed and one more than the normal most positive
 200    number is allowed).  This flag will only be set for a signed
 201    operand.  */
 202 #define PPC_OPERAND_NEGATIVE (02000)
 203 \f
 204 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 205    with the operands table for simplicity.  The macro table is an
 206    array of struct powerpc_macro.  */
 207
 208 struct powerpc_macro
 209 {
 210   /* The macro name.  */
 211   const char *name;
 212
 213   /* The number of operands the macro takes.  */
 214   unsigned int operands;
 215
 216   /* One bit flags for the opcode.  These are used to indicate which
 217      specific processors support the instructions.  The values are the
 218      same as those for the struct powerpc_opcode flags field.  */
 219   unsigned long flags;
 220
 221   /* A format string to turn the macro into a normal instruction.
 222      Each %N in the string is replaced with operand number N (zero
 223      based).  */
 224   const char *format;
 225 };
 226
 227 extern const struct powerpc_macro powerpc_macros[];
 228 extern const int powerpc_num_macros;
 229
 230 #endif /* PPC_H */