opcodes/ChangeLog

   1 2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>
   2
   3         * arc-tbl.h (dbnz): Use "DBNZ" class.
   4         * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class.
   5
   6 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
   7
   8         * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and
   9         BPF_INSN_LDABSDW instructions.
  10
  11 2024-01-15  Nick Clifton  <nickc@redhat.com>
  12
  13         * configure: Regenerate.
  14         * po/opcodes.pot: Regenerate.
  15
  16 2024-01-15  Nick Clifton  <nickc@redhat.com>
  17
  18         * 2.42 branch point.
  19
  20 2023-11-15  Arsen Arsenović  <arsen@aarsen.me>
  21
  22         * aclocal.m4: Regenerate.
  23         * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
  24         temporary file to suppress xgettext checking charset names.
  25         * configure.ac (SHARED_LIBADD): Use LTLIBINTL rather than
  26         LIBINTL.
  27         * configure: Regenerate.
  28         * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
  29         temporary file, to suppress xgettext checking charset names.
  30
  31 2023-10-05  Neal frager  <neal.frager@amd.com>
  32
  33         * microblaze-opcm.h (struct op_code_struct): Tidy and remove
  34         redundant entries.
  35         * microblaze-opc.h (MAX_OPCODES): Increase to 300.
  36         (op_code_struct): Add address extension instructions.
  37
  38 2023-10-04  Neal frager  <neal.frager@amd.com>
  39
  40         * microblaze-opc.h (struct op_code_struct): Add hiberante
  41         and suspend entries.
  42         * microblaze-opcm.h (enum microblaze_instr): Add microblaze_sleep,
  43         hibernate, suspend entries.
  44
  45 2023-08-24  Tom Tromey  <tom@tromey.com>
  46
  47         * cgen.sh: Don't pass "-s" to cgen.
  48         * Makefile.in: Rebuild.
  49         * Makefile.am (GUILE): Simplify.
  50
  51 2023-07-31  Jose E. Marchesi  <jose.marchesi@oracle.com>
  52
  53         PR 30705
  54         * bpf-dis.c (print_insn_bpf): Check that info->section->owner is
  55         actually available before using it.
  56
  57 2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
  58
  59         * bpf-dis.c: Initialize asm_bpf_version to -1.
  60         (print_insn_bpf): Set BPF ISA version from the cpu version ELF
  61         header flags if no explicit version set in the command line.
  62         * disassemble.c (disassemble_init_for_target): Remove unused code.
  63
  64 2023-07-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  65
  66         * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
  67         register.
  68
  69 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
  70
  71         * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
  72         instructions.
  73
  74 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
  75
  76         * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
  77         instructions.
  78
  79 2023-07-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  80
  81         * bpf-opc.c (bpf_opcodes): Add entry for jal.
  82
  83 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  84
  85         * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
  86         instructions.
  87
  88 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  89
  90         * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
  91         MOVS32{8,16,32}R instructions.  and MOVS32I instructions.
  92
  93 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  94
  95         * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
  96         * Makefile.in: Regenerate.
  97
  98 2023-07-03  Nick Clifton  <nickc@redhat.com>
  99
 100         * configure: Regenerate.
 101         * po/opcodes.pot: Regenerate.
 102
 103 2023-07-03  Nick Clifton  <nickc@redhat.com>
 104
 105         2.41 Branch Point.
 106
 107 2023-05-23  Nick Clifton  <nickc@redhat.com>
 108
 109         * po/sv.po: Updated translation.
 110
 111 2023-04-21  Tom Tromey  <tromey@adacore.com>
 112
 113         * i386-dis.c (OP_J): Check result of get16.
 114
 115 2023-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 116
 117         * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
 118         vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
 119         vsubs2h, and vsubs4h instructions.
 120
 121 2023-04-11  Nick Clifton  <nickc@redhat.com>
 122
 123         PR 30310
 124         * nfp-dis.c (init_nfp6000_priv): Check that the output section
 125         exists.
 126
 127 2023-03-15  Nick Clifton  <nickc@redhat.com>
 128
 129         PR 30231
 130         * mep-dis.c: Regenerate.
 131
 132 2023-03-15  Nick Clifton  <nickc@redhat.com>
 133
 134         PR 30230
 135         * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
 136
 137 2023-02-28  Richard Ball  <richard.ball@arm.com>
 138
 139         * aarch64-opc.c: Add MEC system registers.
 140
 141 2023-01-03  Nick Clifton  <nickc@redhat.com>
 142
 143         * po/de.po: Updated German translation.
 144         * po/ro.po: Updated Romainian translation.
 145         * po/uk.po: Updated Ukrainian translation.
 146
 147 2022-12-31  Nick Clifton  <nickc@redhat.com>
 148
 149         * 2.40 branch created.
 150
 151 2022-11-22  Shahab Vahedi  <shahab@synopsys.com>
 152
 153         * arc-regs.h: Change isa_config address to 0xc1.
 154         isa_config exists for ARC700 and ARCV2 and not ARCALL.
 155
 156 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
 157
 158         * rx-decode.opc: Switch arguments of the MVTACGU insn.
 159         * rx-decode.c: Regenerate.
 160
 161 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
 162
 163         * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
 164         Rm_BANK,Rn is always 1.
 165
 166 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
 167
 168         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
 169         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
 170         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
 171         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
 172         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
 173         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
 174         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
 175
 176 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
 177
 178         * disassemble.c (disassemble_init_for_target): Set
 179         created_styled_output for ARC based targets.
 180         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
 181         instead of fprintf_ftype throughout.
 182         (find_format): Likewise.
 183         (print_flags): Likewise.
 184         (print_insn_arc): Likewise.
 185
 186 2022-07-08  Nick Clifton  <nickc@redhat.com>
 187
 188         * 2.39 branch created.
 189
 190 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
 191
 192         * disassemble.c: (disassemble_init_for_target): Set
 193         created_styled_output for AVR based targets.
 194         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
 195         instead of fprintf_ftype throughout.
 196         (avr_operand): Pass in and fill disassembler_style when
 197         parsing operands.
 198
 199 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 200
 201         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
 202         table.
 203
 204 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
 205
 206         * configure.ac: Handle bfd_amdgcn_arch.
 207         * configure: Re-generate.
 208
 209 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
 210             Maciej W. Rozycki  <macro@orcam.me.uk>
 211
 212         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
 213         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
 214         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
 215         "bnez" instructions.
 216
 217 2022-02-17  Nick Clifton  <nickc@redhat.com>
 218
 219         * po/sr.po: Updated Serbian translation.
 220
 221 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
 222
 223         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
 224         * microblaze-opc.h: Follow 'fsqrt' rename.
 225
 226 2022-01-24  Nick Clifton  <nickc@redhat.com>
 227
 228         * po/ro.po: Updated Romanian translation.
 229         * po/uk.po: Updated Ukranian translation.
 230
 231 2022-01-22  Nick Clifton  <nickc@redhat.com>
 232
 233         * configure: Regenerate.
 234         * po/opcodes.pot: Regenerate.
 235
 236 2022-01-22  Nick Clifton  <nickc@redhat.com>
 237
 238         * 2.38 release branch created.
 239
 240 2022-01-17  Nick Clifton  <nickc@redhat.com>
 241
 242         * Makefile.in: Regenerate.
 243         * po/opcodes.pot: Regenerate.
 244
 245 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
 246
 247         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
 248         in insn_type on branching instructions.
 249
 250 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
 251             Simon Cook  <simon.cook@embecosm.com>
 252
 253         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
 254         (riscv_options): New static global.
 255         (disassembler_options_riscv): New function.
 256         (print_riscv_disassembler_options): Rewrite to use
 257         disassembler_options_riscv.
 258
 259 2021-11-25  Nick Clifton  <nickc@redhat.com>
 260
 261         PR 28614
 262         * aarch64-asm.c: Replace assert(0) with real code.
 263         * aarch64-dis.c: Likewise.
 264         * aarch64-opc.c: Likewise.
 265
 266 2021-11-25  Nick Clifton  <nickc@redhat.com>
 267
 268         * po/fr.po; Updated French translation.
 269
 270 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 271
 272         * Makefile.am: Remove obsolete comment.
 273         * configure.ac: Refer `libbfd.la' to link shared BFD library
 274         except for Cygwin.
 275         * Makefile.in: Regenerate.
 276         * configure: Regenerate.
 277
 278 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 279
 280         * configure: Regenerate.
 281
 282 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 283
 284         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 285         on POWER5 and later.
 286
 287 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 288
 289         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 290         before an unknown instruction, '%d' is replaced with the
 291         instruction length.
 292
 293 2021-09-02  Nick Clifton  <nickc@redhat.com>
 294
 295         PR 28292
 296         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 297         of BFD_RELOC_16.
 298
 299 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 300
 301         * arc-regs.h (DEF): Fix the register numbers.
 302
 303 2021-08-10  Nick Clifton  <nickc@redhat.com>
 304
 305         * po/sr.po: Updated Serbian translation.
 306
 307 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 308
 309         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 310
 311 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 312
 313         * s390-opc.txt: Add qpaci.
 314
 315 2021-07-03  Nick Clifton  <nickc@redhat.com>
 316
 317         * configure: Regenerate.
 318         * po/opcodes.pot: Regenerate.
 319
 320 2021-07-03  Nick Clifton  <nickc@redhat.com>
 321
 322         * 2.37 release branch created.
 323
 324 2021-07-02  Alan Modra  <amodra@gmail.com>
 325
 326         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 327         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 328         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 329         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 330         (nds32_keyword_gpr): Move declarations to..
 331         * nds32-asm.h: ..here, constifying to match definitions.
 332
 333 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 334
 335         * Makefile.am (GUILE): New variable.
 336         (CGEN): Use $(GUILE).
 337         * Makefile.in: Regenerate.
 338
 339 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 340
 341         * mep-asm.c (macros): Mark static & const.
 342         (lookup_macro): Change return & m to const.
 343         (expand_macro): Change mac to const.
 344         (expand_string): Change pmacro to const.
 345
 346 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * nds32-asm.c (operand_fields): Rename to ...
 349         (nds32_operand_fields): ... this.
 350         (keyword_gpr): Rename to ...
 351         (nds32_keyword_gpr): ... this.
 352         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 353         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 354         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 355         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 356         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 357         Mark static.
 358         (keywords): Rename to ...
 359         (nds32_keywords): ... this.
 360         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 361         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 362
 363 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 364
 365         * z80-dis.c (opc_ed): Make const.
 366         (pref_ed): Make p const.
 367
 368 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 369
 370         * microblaze-dis.c (get_field_special): Make op const.
 371         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 372         microblaze_opcodes.
 373         (print_insn_microblaze): Make op & pop const.
 374         (get_insn_microblaze): Make op const.  Rename opcodes to
 375         microblaze_opcodes.
 376         (microblaze_get_target_address): Likewise.
 377         * microblaze-opc.h (struct op_code_struct): Make const.
 378         Rename opcodes to microblaze_opcodes.
 379
 380 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 381
 382         * aarch64-gen.c (aarch64_opcode_table): Add const.
 383         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 384
 385 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 386
 387         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 388         available.
 389
 390 2021-06-22  Alan Modra  <amodra@gmail.com>
 391
 392         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 393         print separator for pcrel insns.
 394
 395 2021-06-19  Alan Modra  <amodra@gmail.com>
 396
 397         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 398
 399 2021-06-19  Alan Modra  <amodra@gmail.com>
 400
 401         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 402         entire buffer.
 403
 404 2021-06-17  Alan Modra  <amodra@gmail.com>
 405
 406         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 407         in table.
 408
 409 2021-06-03  Alan Modra  <amodra@gmail.com>
 410
 411         PR 1202
 412         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 413         Use unsigned int for inst.
 414
 415 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 416
 417         * arc-dis.c (arc_option_arg_t): New enumeration.
 418         (arc_options): New variable.
 419         (disassembler_options_arc): New function.
 420         (print_arc_disassembler_options): Reimplement in terms of
 421         "disassembler_options_arc".
 422
 423 2021-05-29  Alan Modra  <amodra@gmail.com>
 424
 425         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 426         Don't special case PPC_OPCODE_RAW.
 427         (lookup_prefix): Likewise.
 428         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 429         (print_insn_powerpc): ..update caller.
 430         * ppc-opc.c (EXT): Define.
 431         (powerpc_opcodes): Mark extended mnemonics with EXT.
 432         (prefix_opcodes, vle_opcodes): Likewise.
 433         (XISEL, XISEL_MASK): Add cr field and simplify.
 434         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 435         all isel variants to where the base mnemonic belongs.  Sort dstt,
 436         dststt and dssall.
 437
 438 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 439
 440         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 441         COP3 opcode instructions.
 442
 443 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 444
 445         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 446         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 447         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 448         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 449         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 450         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 451         "cop2", and "cop3" entries.
 452
 453 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 454
 455         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 456         entries and associated comments.
 457
 458 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 459
 460         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 461         of "c0".
 462
 463 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 464
 465         * mips-dis.c (mips_cp1_names_mips): New variable.
 466         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 467         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 468         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 469         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 470         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 471         "loongson2f".
 472
 473 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 474
 475         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 476         handling code over to...
 477         <OP_REG_CONTROL>: ... this new case.
 478         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 479         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 480         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 481         replacing the `G' operand code with `g'.  Update "cftc1" and
 482         "cftc2" entries replacing the `E' operand code with `y'.
 483         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 484         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 485         entries replacing the `G' operand code with `g'.
 486
 487 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 488
 489         * mips-dis.c (mips_cp0_names_r3900): New variable.
 490         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 491         for "r3900".
 492
 493 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 494
 495         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 496         and "mtthc2" to using the `G' rather than `g' operand code for
 497         the coprocessor control register referred.
 498
 499 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 500
 501         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 502         entries with each other.
 503
 504 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 505
 506         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 507
 508 2021-05-25  Alan Modra  <amodra@gmail.com>
 509
 510         * cris-desc.c: Regenerate.
 511         * cris-desc.h: Regenerate.
 512         * cris-opc.h: Regenerate.
 513         * po/POTFILES.in: Regenerate.
 514
 515 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 516
 517         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 518         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 519         (CGEN_CPUS): Add cris.
 520         (CRIS_DEPS): Define.
 521         (stamp-cris): New rule.
 522         * cgen.sh: Handle desc action.
 523         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 524         * Makefile.in, configure: Regenerate.
 525
 526 2021-05-18  Job Noorman  <mtvec@pm.me>
 527
 528         PR 27814
 529         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 530         the elf objects.
 531
 532 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 533
 534         * arm-dis.c (mve_opcodes): Fix disassembly of
 535         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 536         (is_mve_encoding_conflict): MVE vector loads should not match
 537         when P = W = 0.
 538         (is_mve_unpredictable): It's not unpredictable to use the same
 539         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 540
 541 2021-05-11  Nick Clifton  <nickc@redhat.com>
 542
 543         PR 27840
 544         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 545         the end of the code buffer.
 546
 547 2021-05-06  Stafford Horne  <shorne@gmail.com>
 548
 549         PR 21464
 550         * or1k-asm.c: Regenerate.
 551
 552 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 553
 554         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 555         info->insn_info_valid.
 556
 557 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-opc.tbl (lea): Add Optimize.
 560         * opcodes/i386-tbl.h: Re-generate.
 561
 562 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 563
 564         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 565         of l32r fetch and display referenced literal value.
 566
 567 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 568
 569         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 570         to 4 for literal disassembly.
 571
 572 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 573
 574         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 575         for TLBI instruction.
 576
 577 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 578
 579         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 580         DC instruction.
 581
 582 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 583
 584         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 585         "qualifier".
 586         (convert_mov_to_movewide): Add initializer for "value".
 587
 588 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 589
 590         * aarch64-opc.c: Add RME system registers.
 591
 592 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 593
 594         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 595         "addi d,CV,z" to "c.mv d,CV".
 596
 597 2021-04-12  Alan Modra  <amodra@gmail.com>
 598
 599         * configure.ac (--enable-checking): Add support.
 600         * config.in: Regenerate.
 601         * configure: Regenerate.
 602
 603 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 604
 605         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 606         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 607
 608 2021-04-09  Alan Modra  <amodra@gmail.com>
 609
 610         * ppc-dis.c (struct dis_private): Add "special".
 611         (POWERPC_DIALECT): Delete.  Replace uses with..
 612         (private_data): ..this.  New inline function.
 613         (disassemble_init_powerpc): Init "special" names.
 614         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 615         field of prefix instructions.
 616         (bsearch_reloc, print_got_plt): New functions.
 617         (print_insn_powerpc): For pcrel instructions, print target address
 618         and symbol if known, and decode plt and got loads too.
 619
 620 2021-04-08  Alan Modra  <amodra@gmail.com>
 621
 622         PR 27684
 623         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 624
 625 2021-04-08  Alan Modra  <amodra@gmail.com>
 626
 627         PR 27676
 628         * ppc-opc.c (DCBT_EO): Move earlier.
 629         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 630         (powerpc_operands): Add THCT and THDS entries.
 631         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 632
 633 2021-04-06  Alan Modra  <amodra@gmail.com>
 634
 635         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 636         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 637         symbol_at_address_func.
 638
 639 2021-04-05  Alan Modra  <amodra@gmail.com>
 640
 641         * configure.ac: Don't check for limits.h, string.h, strings.h or
 642         stdlib.h.
 643         (AC_ISC_POSIX): Don't invoke.
 644         * sysdep.h: Include stdlib.h and string.h unconditionally.
 645         * i386-opc.h: Include limits.h unconditionally.
 646         * wasm32-dis.c: Likewise.
 647         * cgen-opc.c: Don't include alloca-conf.h.
 648         * config.in: Regenerate.
 649         * configure: Regenerate.
 650
 651 2021-04-01  Martin Liska  <mliska@suse.cz>
 652
 653         * arm-dis.c (strneq): Remove strneq and use startswith.
 654         * cr16-dis.c (print_insn_cr16): Likewise.
 655         * score-dis.c (streq): Likewise.
 656         (strneq): Likewise.
 657         * score7-dis.c (strneq): Likewise.
 658
 659 2021-04-01  Alan Modra  <amodra@gmail.com>
 660
 661         PR 27675
 662         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 663
 664 2021-03-31  Alan Modra  <amodra@gmail.com>
 665
 666         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 667         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 668         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 669         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 670         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 671         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 672         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 673         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 674         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 675         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 676         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 677         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 678         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 679         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 680         and TRUE with true throughout.
 681
 682 2021-03-31  Alan Modra  <amodra@gmail.com>
 683
 684         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 685         * aarch64-dis.h: Likewise.
 686         * aarch64-opc.c: Likewise.
 687         * avr-dis.c: Likewise.
 688         * csky-dis.c: Likewise.
 689         * nds32-asm.c: Likewise.
 690         * nds32-dis.c: Likewise.
 691         * nfp-dis.c: Likewise.
 692         * riscv-dis.c: Likewise.
 693         * s12z-dis.c: Likewise.
 694         * wasm32-dis.c: Likewise.
 695
 696 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 699         (i386_seg_prefixes): New.
 700         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 701         (i386_seg_prefixes): Declare.
 702
 703 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 704
 705         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 706
 707 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 708
 709         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 710         * i386-reg.tbl (st): Move down.
 711         (st(0)): Delete. Extend comment.
 712         * i386-tbl.h: Re-generate.
 713
 714 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 715
 716         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 717         (cmpsd): Move next to cmps.
 718         (movsd): Move next to movs.
 719         (cmpxchg16b): Move to separate section.
 720         (fisttp, fisttpll): Likewise.
 721         (monitor, mwait): Likewise.
 722         * i386-tbl.h: Re-generate.
 723
 724 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 725
 726         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 727         (vpsadbw): Add C.
 728         * i386-tbl.h: Re-generate.
 729
 730 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 733         pclmul, gfni): New templates. Use them wherever possible. Move
 734         SSE4.1 pextrw into respective section.
 735         * i386-tbl.h: Re-generate.
 736
 737 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 738
 739         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 740         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 741         "length".
 742         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 743         Convert all of their uses to representation in opcode.
 744
 745 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 746
 747         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 748         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 749         value of None. Shrink operands to 3 bits.
 750
 751 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-gen.c (process_i386_opcode_modifier): New parameter
 754         "space".
 755         (output_i386_opcode): New local variable "space". Adjust
 756         process_i386_opcode_modifier() invocation.
 757         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 758         invocation.
 759         * i386-tbl.h: Re-generate.
 760
 761 2021-03-29  Alan Modra  <amodra@gmail.com>
 762
 763         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 764         (fp_qualifier_p, get_data_pattern): Likewise.
 765         (aarch64_get_operand_modifier_from_value): Likewise.
 766         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 767         (operand_variant_qualifier_p): Likewise.
 768         (qualifier_value_in_range_constraint_p): Likewise.
 769         (aarch64_get_qualifier_esize): Likewise.
 770         (aarch64_get_qualifier_nelem): Likewise.
 771         (aarch64_get_qualifier_standard_value): Likewise.
 772         (get_lower_bound, get_upper_bound): Likewise.
 773         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 774         (aarch64_print_operand): Likewise.
 775         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 776         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 777         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 778         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 779         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 780         (print_insn_tic6x): Likewise.
 781
 782 2021-03-29  Alan Modra  <amodra@gmail.com>
 783
 784         * arc-dis.c (extract_operand_value): Correct NULL cast.
 785         * frv-opc.h: Regenerate.
 786
 787 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 790         MMX form.
 791         * i386-tbl.h: Re-generate.
 792
 793 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 794
 795         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 796         immediate in br.n instruction.
 797
 798 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 799
 800         * i386-dis.c (XMGatherD, VexGatherD): New.
 801         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 802         (print_insn): Check masking for S/G insns.
 803         (OP_E_memory): New local variable check_gather. Extend mandatory
 804         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 805         Extend check for disallowed 16-bit addressing.
 806         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 807         if()s to switch(). Check register conflicts for (VEX-encoded)
 808         gathers. Drop no longer reachable cases.
 809         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 810         vgatherdp*.
 811
 812 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 815         zeroing-masking without masking.
 816
 817 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 818
 819         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 820         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 821         single-operand forms as deprecated.
 822         * i386-tbl.h: Re-generate.
 823
 824 2021-03-25  Alan Modra  <amodra@gmail.com>
 825
 826         PR 27647
 827         * ppc-opc.c (XLOCB_MASK): Delete.
 828         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 829         XLBH_MASK.
 830         (powerpc_opcodes): Accept a BH field on all extended forms of
 831         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 832
 833 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 834
 835         * i386-gen.c (output_i386_opcode): Drop processing of
 836         opcode_length. Calculate length from base_opcode. Adjust prefix
 837         encoding determination.
 838         (process_i386_opcodes): Drop output of fake opcode_length.
 839         * i386-opc.h (struct insn_template): Drop opcode_length field.
 840         * i386-opc.tbl: Drop opcode length field from all templates.
 841         * i386-tbl.h: Re-generate.
 842
 843 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 846         parameter "prefix". Drop local variable "regular_encoding".
 847         Record prefix setting / check for consistency.
 848         (output_i386_opcode): Parse opcode_length and base_opcode
 849         earlier. Derive prefix encoding. Drop no longer applicable
 850         consistency checking. Adjust process_i386_opcode_modifier()
 851         invocation.
 852         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 853         invocation.
 854         * i386-tbl.h: Re-generate.
 855
 856 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 859         check.
 860         * i386-opc.h (Prefix_*): Move #define-s.
 861         * i386-opc.tbl: Move pseudo prefix enumerator values to
 862         extension opcode field. Introduce pseudopfx template.
 863         * i386-tbl.h: Re-generate.
 864
 865 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 868         comment.
 869         * i386-tbl.h: Re-generate.
 870
 871 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 872
 873         * i386-opc.h (struct insn_template): Move cpu_flags field past
 874         opcode_modifier one.
 875         * i386-tbl.h: Re-generate.
 876
 877 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 880         * i386-opc.h (OpcodeSpace): New enumerator.
 881         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 882         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 883         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 884         (struct i386_opcode_modifier): New field opcodespace. Shrink
 885         opcodeprefix field.
 886         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 887         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 888         OpcodePrefix uses.
 889         * i386-tbl.h: Re-generate.
 890
 891 2021-03-22  Martin Liska  <mliska@suse.cz>
 892
 893         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 894         * arc-dis.c (parse_option): Likewise.
 895         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 896         * cris-dis.c (print_with_operands): Likewise.
 897         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 898         * i386-dis.c (print_insn): Likewise.
 899         * ia64-gen.c (fetch_insn_class): Likewise.
 900         (parse_resource_users): Likewise.
 901         (in_iclass): Likewise.
 902         (lookup_specifier): Likewise.
 903         (insert_opcode_dependencies): Likewise.
 904         * mips-dis.c (parse_mips_ase_option): Likewise.
 905         (parse_mips_dis_option): Likewise.
 906         * s390-dis.c (disassemble_init_s390): Likewise.
 907         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 908
 909 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 910
 911         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 912
 913 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 914
 915         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 916         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 917
 918 2021-03-12  Alan Modra  <amodra@gmail.com>
 919
 920         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 921
 922 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-dis.c (OP_XMM): Re-order checks.
 925
 926 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 927
 928         * i386-dis.c (putop): Drop need_vex check when also checking
 929         vex.evex.
 930         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 931         checking vex.b.
 932
 933 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 936         checks. Move case label past broadcast check.
 937
 938 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 939
 940         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 941         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 942         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 943         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 944         EVEX_W_0F38C7_M_0_L_2): Delete.
 945         (REG_EVEX_0F38C7_M_0_L_2): New.
 946         (intel_operand_size): Handle VEX and EVEX the same for
 947         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 948         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 949         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 950         vex_vsib_q_w_d_mode uses.
 951         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 952         0F38A1, and 0F38A3 entries.
 953         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 954         entry.
 955         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 956         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 957         0F38A3 entries.
 958
 959 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 960
 961         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 962         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 963         MOD_VEX_0FXOP_09_12): Rename to ...
 964         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 965         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 966         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 967         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 968         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 969         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 970         (reg_table): Adjust comments.
 971         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 972         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 973         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 974         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 975         (vex_len_table): Adjust opcode 0A_12 entry.
 976         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 977         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 978         (rm_table): Move hreset entry.
 979
 980 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 981
 982         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 983         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 984         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 985         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 986         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 987         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 988         (get_valid_dis386): Also handle 512-bit vector length when
 989         vectoring into vex_len_table[].
 990         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 991         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 992         entries.
 993         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 994         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 995         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 996         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 997         entries.
 998
 999 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1000
1001         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
1002         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
1003         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
1004         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
1005         entries.
1006         * i386-dis-evex-len.h (evex_len_table): Likewise.
1007         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
1008
1009 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1010
1011         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
1012         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
1013         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
1014         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
1015         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
1016         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
1017         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
1018         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
1019         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1020         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1021         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1022         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
1023         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
1024         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
1025         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
1026         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
1027         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
1028         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
1029         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
1030         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1031         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
1032         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
1033         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1034         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
1035         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1036         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
1037         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
1038         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
1039         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
1040         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
1041         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
1042         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
1043         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
1044         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
1045         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
1046         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
1047         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
1048         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
1049         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
1050         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
1051         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
1052         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
1053         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
1054         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
1055         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
1056         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
1057         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
1058         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
1059         EVEX_W_0F3A43_L_n): New.
1060         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
1061         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
1062         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
1063         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
1064         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
1065         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
1066         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
1067         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1068         0F385B, 0F38C6, and 0F38C7 entries.
1069         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1070         0F38C6 and 0F38C7.
1071         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1072         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1073         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1074         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1075
1076 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1077
1078         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1079         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1080         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1081         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1082         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1083         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1084         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1085         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1086         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1087         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1088         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1089         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1090         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1091         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1092         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1093         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1094         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1095         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1096         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1097         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1098         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1099         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1100         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1101         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1102         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1103         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1104         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1105         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1106         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1107         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1108         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1109         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1110         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1111         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1112         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1113         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1114         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1115         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1116         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1117         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1118         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1119         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1120         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1121         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1122         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1123         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1124         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1125         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1126         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1127         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1128         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1129         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1130         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1131         VEX_W_0F99_P_2_LEN_0): Delete.
1132         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1133         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1134         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1135         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1136         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1137         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1138         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1139         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1140         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1141         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1142         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1143         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1144         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1145         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1146         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1147         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1148         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1149         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1150         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1151         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1152         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1153         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1154         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1155         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1156         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1157         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1158         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1159         (prefix_table): No longer link to vex_len_table[] for opcodes
1160         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1161         0F92, 0F93, 0F98, and 0F99.
1162         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1163         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1164         0F98, and 0F99.
1165         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1166         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1167         0F98, and 0F99.
1168         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1169         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1170         0F98, and 0F99.
1171         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1172         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1173         0F98, and 0F99.
1174
1175 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1176
1177         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1178         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1179         REG_VEX_0F73_M_0 respectively.
1180         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1181         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1182         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1183         MOD_VEX_0F73_REG_7): Delete.
1184         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1185         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1186         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1187         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1188         PREFIX_VEX_0F3AF0_L_0 respectively.
1189         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1190         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1191         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1192         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1193         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1194         VEX_LEN_0F38F7): New.
1195         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1196         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1197         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1198         0F38F3.
1199         (prefix_table): No longer link to vex_len_table[] for opcodes
1200         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1201         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1202         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1203         0F38F6, 0F38F7, and 0F3AF0.
1204         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1205         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1206         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1207         0F73.
1208
1209 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1210
1211         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1212         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1213         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1214         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1215         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1216         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1217         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1218         73.
1219         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1220         0F72, and 0F73.
1221         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1222         0F73.
1223
1224 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1225
1226         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1227         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1228         (reg_table): Don't link to mod_table[] where not needed. Add
1229         PREFIX_IGNORED to nop entries.
1230         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1231         (mod_table): Add nop entries next to prefetch ones. Drop
1232         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1233         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1234         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1235         PREFIX_OPCODE from endbr* entries.
1236         (get_valid_dis386): Also consider entry's name when zapping
1237         vindex.
1238         (print_insn): Handle PREFIX_IGNORED.
1239
1240 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1241
1242         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1243         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1244         element.
1245         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1246         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1247         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1248         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1249         (struct i386_opcode_modifier): Delete notrackprefixok,
1250         islockable, hleprefixok, and repprefixok fields. Add prefixok
1251         field.
1252         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1253         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1254         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1255         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1256         Replace HLEPrefixOk.
1257         * opcodes/i386-tbl.h: Re-generate.
1258
1259 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1260
1261         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1262         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1263         64-bit form.
1264         * opcodes/i386-tbl.h: Re-generate.
1265
1266 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1269         for {} instead of {0}. Don't look for '0'.
1270         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1271         size specifiers.
1272
1273 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1274
1275         PR 27158
1276         * riscv-dis.c (print_insn_args): Updated encoding macros.
1277         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1278         (match_c_addi16sp): Updated encoding macros.
1279         (match_c_lui): Likewise.
1280         (match_c_lui_with_hint): Likewise.
1281         (match_c_addi4spn): Likewise.
1282         (match_c_slli): Likewise.
1283         (match_slli_as_c_slli): Likewise.
1284         (match_c_slli64): Likewise.
1285         (match_srxi_as_c_srxi): Likewise.
1286         (riscv_insn_types): Added .insn css/cl/cs.
1287
1288 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1289
1290         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1291         (default_priv_spec): Updated type to riscv_spec_class.
1292         (parse_riscv_dis_option): Updated.
1293         * riscv-opc.c: Moved stuff and make the file tidy.
1294
1295 2021-02-17  Alan Modra  <amodra@gmail.com>
1296
1297         * wasm32-dis.c: Include limits.h.
1298         (CHAR_BIT): Provide backup define.
1299         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1300         Correct signed overflow checking.
1301
1302 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1303
1304         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1305         * i386-tbl.h: Re-generate.
1306
1307 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1308
1309         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1310         Oword.
1311         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1312
1313 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1314
1315         * s390-mkopc.c (main): Accept arch14 as cpu string.
1316         * s390-opc.txt: Add new arch14 instructions.
1317
1318 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1319
1320         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1321         favour of LIBINTL.
1322         * configure: Regenerated.
1323
1324 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1325
1326         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1327         * tic54x-opc.c (regs): Rename to ...
1328         (tic54x_regs): ... this.
1329         (mmregs): Rename to ...
1330         (tic54x_mmregs): ... this.
1331         (condition_codes): Rename to ...
1332         (tic54x_condition_codes): ... this.
1333         (cc2_codes): Rename to ...
1334         (tic54x_cc2_codes): ... this.
1335         (cc3_codes): Rename to ...
1336         (tic54x_cc3_codes): ... this.
1337         (status_bits): Rename to ...
1338         (tic54x_status_bits): ... this.
1339         (misc_symbols): Rename to ...
1340         (tic54x_misc_symbols): ... this.
1341
1342 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1343
1344         * riscv-opc.c (MASK_RVB_IMM): Removed.
1345         (riscv_opcodes): Removed zb* instructions.
1346         (riscv_ext_version_table): Removed versions for zb*.
1347
1348 2021-01-26  Alan Modra  <amodra@gmail.com>
1349
1350         * i386-gen.c (parse_template): Ensure entire template_instance
1351         is initialised.
1352
1353 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1354
1355         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1356         (riscv_fpr_names_abi): Likewise.
1357         (riscv_opcodes): Likewise.
1358         (riscv_insn_types): Likewise.
1359
1360 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1361
1362         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1363
1364 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1365
1366         * riscv-dis.c: Comments tidy and improvement.
1367         * riscv-opc.c: Likewise.
1368
1369 2021-01-13  Alan Modra  <amodra@gmail.com>
1370
1371         * Makefile.in: Regenerate.
1372
1373 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1374
1375         PR binutils/26792
1376         * configure.ac: Use GNU_MAKE_JOBSERVER.
1377         * aclocal.m4: Regenerated.
1378         * configure: Likewise.
1379
1380 2021-01-12  Nick Clifton  <nickc@redhat.com>
1381
1382         * po/sr.po: Updated Serbian translation.
1383
1384 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1385
1386         PR ld/27173
1387         * configure: Regenerated.
1388
1389 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1390
1391         * aarch64-asm-2.c: Regenerate.
1392         * aarch64-dis-2.c: Likewise.
1393         * aarch64-opc-2.c: Likewise.
1394         * aarch64-opc.c (aarch64_print_operand):
1395         Delete handling of AARCH64_OPND_CSRE_CSR.
1396         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1397         (CSRE): Likewise.
1398         (_CSRE_INSN): Likewise.
1399         (aarch64_opcode_table): Delete csr.
1400
1401 2021-01-11  Nick Clifton  <nickc@redhat.com>
1402
1403         * po/de.po: Updated German translation.
1404         * po/fr.po: Updated French translation.
1405         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1406         * po/sv.po: Updated Swedish translation.
1407         * po/uk.po: Updated Ukranian translation.
1408
1409 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1410
1411         * configure: Regenerated.
1412
1413 2021-01-09  Nick Clifton  <nickc@redhat.com>
1414
1415         * configure: Regenerate.
1416         * po/opcodes.pot: Regenerate.
1417
1418 2021-01-09  Nick Clifton  <nickc@redhat.com>
1419
1420         * 2.36 release branch crated.
1421
1422 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1423
1424         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1425         (DW, (XRC_MASK): Define.
1426         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1427
1428 2021-01-09  Alan Modra  <amodra@gmail.com>
1429
1430         * configure: Regenerate.
1431
1432 2021-01-08  Nick Clifton  <nickc@redhat.com>
1433
1434         * po/sv.po: Updated Swedish translation.
1435
1436 2021-01-08  Nick Clifton  <nickc@redhat.com>
1437
1438         PR 27129
1439         * aarch64-dis.c (determine_disassembling_preference): Move call to
1440         aarch64_match_operands_constraint outside of the assertion.
1441         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1442         Replace with a return of FALSE.
1443
1444         PR 27139
1445         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1446         core system register.
1447
1448 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1449
1450         * configure: Regenerate.
1451
1452 2021-01-07  Nick Clifton  <nickc@redhat.com>
1453
1454         * po/fr.po: Updated French translation.
1455
1456 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1457
1458         * m68k-opc.c (chkl): Change minimum architecture requirement to
1459         m68020.
1460
1461 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1462
1463         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1464
1465 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1466             Jim Wilson  <jimw@sifive.com>
1467             Andrew Waterman  <andrew@sifive.com>
1468             Maxim Blinov  <maxim.blinov@embecosm.com>
1469             Kito Cheng  <kito.cheng@sifive.com>
1470             Nelson Chu  <nelson.chu@sifive.com>
1471
1472         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1473         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1474
1475 2021-01-01  Alan Modra  <amodra@gmail.com>
1476
1477         Update year range in copyright notice of all files.
1478
1479 For older changes see ChangeLog-2020
1480 \f
1481 Copyright (C) 2021-2024 Free Software Foundation, Inc.
1482
1483 Copying and distribution of this file, with or without modification,
1484 are permitted in any medium without royalty provided the copyright
1485 notice and this notice are preserved.
1486
1487 Local Variables:
1488 mode: change-log
1489 left-margin: 8
1490 fill-column: 74
1491 version-control: never
1492 End: