opcodes/ChangeLog

   1 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
   4         MOVS32{8,16,32}R instructions.  and MOVS32I instructions.
   5
   6 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
   7
   8         * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
   9         * Makefile.in: Regenerate.
  10
  11 2023-07-03  Nick Clifton  <nickc@redhat.com>
  12
  13         * configure: Regenerate.
  14         * po/opcodes.pot: Regenerate.
  15
  16 2023-07-03  Nick Clifton  <nickc@redhat.com>
  17
  18         2.41 Branch Point.
  19
  20 2023-05-23  Nick Clifton  <nickc@redhat.com>
  21
  22         * po/sv.po: Updated translation.
  23
  24 2023-04-21  Tom Tromey  <tromey@adacore.com>
  25
  26         * i386-dis.c (OP_J): Check result of get16.
  27
  28 2023-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
  29
  30         * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
  31         vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
  32         vsubs2h, and vsubs4h instructions.
  33
  34 2023-04-11  Nick Clifton  <nickc@redhat.com>
  35
  36         PR 30310
  37         * nfp-dis.c (init_nfp6000_priv): Check that the output section
  38         exists.
  39
  40 2023-03-15  Nick Clifton  <nickc@redhat.com>
  41
  42         PR 30231
  43         * mep-dis.c: Regenerate.
  44
  45 2023-03-15  Nick Clifton  <nickc@redhat.com>
  46
  47         PR 30230
  48         * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
  49
  50 2023-02-28  Richard Ball  <richard.ball@arm.com>
  51
  52         * aarch64-opc.c: Add MEC system registers.
  53
  54 2023-01-03  Nick Clifton  <nickc@redhat.com>
  55
  56         * po/de.po: Updated German translation.
  57         * po/ro.po: Updated Romainian translation.
  58         * po/uk.po: Updated Ukrainian translation.
  59
  60 2022-12-31  Nick Clifton  <nickc@redhat.com>
  61
  62         * 2.40 branch created.
  63
  64 2022-11-22  Shahab Vahedi  <shahab@synopsys.com>
  65
  66         * arc-regs.h: Change isa_config address to 0xc1.
  67         isa_config exists for ARC700 and ARCV2 and not ARCALL.
  68
  69 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
  70
  71         * rx-decode.opc: Switch arguments of the MVTACGU insn.
  72         * rx-decode.c: Regenerate.
  73
  74 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
  75
  76         * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
  77         Rm_BANK,Rn is always 1.
  78
  79 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
  80
  81         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
  82         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
  83         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
  84         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
  85         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
  86         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
  87         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
  88
  89 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
  90
  91         * disassemble.c (disassemble_init_for_target): Set
  92         created_styled_output for ARC based targets.
  93         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
  94         instead of fprintf_ftype throughout.
  95         (find_format): Likewise.
  96         (print_flags): Likewise.
  97         (print_insn_arc): Likewise.
  98
  99 2022-07-08  Nick Clifton  <nickc@redhat.com>
 100
 101         * 2.39 branch created.
 102
 103 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
 104
 105         * disassemble.c: (disassemble_init_for_target): Set
 106         created_styled_output for AVR based targets.
 107         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
 108         instead of fprintf_ftype throughout.
 109         (avr_operand): Pass in and fill disassembler_style when
 110         parsing operands.
 111
 112 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 113
 114         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
 115         table.
 116
 117 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
 118
 119         * configure.ac: Handle bfd_amdgcn_arch.
 120         * configure: Re-generate.
 121
 122 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
 123             Maciej W. Rozycki  <macro@orcam.me.uk>
 124
 125         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
 126         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
 127         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
 128         "bnez" instructions.
 129
 130 2022-02-17  Nick Clifton  <nickc@redhat.com>
 131
 132         * po/sr.po: Updated Serbian translation.
 133
 134 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
 135
 136         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
 137         * microblaze-opc.h: Follow 'fsqrt' rename.
 138
 139 2022-01-24  Nick Clifton  <nickc@redhat.com>
 140
 141         * po/ro.po: Updated Romanian translation.
 142         * po/uk.po: Updated Ukranian translation.
 143
 144 2022-01-22  Nick Clifton  <nickc@redhat.com>
 145
 146         * configure: Regenerate.
 147         * po/opcodes.pot: Regenerate.
 148
 149 2022-01-22  Nick Clifton  <nickc@redhat.com>
 150
 151         * 2.38 release branch created.
 152
 153 2022-01-17  Nick Clifton  <nickc@redhat.com>
 154
 155         * Makefile.in: Regenerate.
 156         * po/opcodes.pot: Regenerate.
 157
 158 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
 159
 160         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
 161         in insn_type on branching instructions.
 162
 163 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
 164             Simon Cook  <simon.cook@embecosm.com>
 165
 166         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
 167         (riscv_options): New static global.
 168         (disassembler_options_riscv): New function.
 169         (print_riscv_disassembler_options): Rewrite to use
 170         disassembler_options_riscv.
 171
 172 2021-11-25  Nick Clifton  <nickc@redhat.com>
 173
 174         PR 28614
 175         * aarch64-asm.c: Replace assert(0) with real code.
 176         * aarch64-dis.c: Likewise.
 177         * aarch64-opc.c: Likewise.
 178
 179 2021-11-25  Nick Clifton  <nickc@redhat.com>
 180
 181         * po/fr.po; Updated French translation.
 182
 183 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 184
 185         * Makefile.am: Remove obsolete comment.
 186         * configure.ac: Refer `libbfd.la' to link shared BFD library
 187         except for Cygwin.
 188         * Makefile.in: Regenerate.
 189         * configure: Regenerate.
 190
 191 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 192
 193         * configure: Regenerate.
 194
 195 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 196
 197         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 198         on POWER5 and later.
 199
 200 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 201
 202         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 203         before an unknown instruction, '%d' is replaced with the
 204         instruction length.
 205
 206 2021-09-02  Nick Clifton  <nickc@redhat.com>
 207
 208         PR 28292
 209         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 210         of BFD_RELOC_16.
 211
 212 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 213
 214         * arc-regs.h (DEF): Fix the register numbers.
 215
 216 2021-08-10  Nick Clifton  <nickc@redhat.com>
 217
 218         * po/sr.po: Updated Serbian translation.
 219
 220 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 221
 222         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 223
 224 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 225
 226         * s390-opc.txt: Add qpaci.
 227
 228 2021-07-03  Nick Clifton  <nickc@redhat.com>
 229
 230         * configure: Regenerate.
 231         * po/opcodes.pot: Regenerate.
 232
 233 2021-07-03  Nick Clifton  <nickc@redhat.com>
 234
 235         * 2.37 release branch created.
 236
 237 2021-07-02  Alan Modra  <amodra@gmail.com>
 238
 239         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 240         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 241         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 242         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 243         (nds32_keyword_gpr): Move declarations to..
 244         * nds32-asm.h: ..here, constifying to match definitions.
 245
 246 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 247
 248         * Makefile.am (GUILE): New variable.
 249         (CGEN): Use $(GUILE).
 250         * Makefile.in: Regenerate.
 251
 252 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 253
 254         * mep-asm.c (macros): Mark static & const.
 255         (lookup_macro): Change return & m to const.
 256         (expand_macro): Change mac to const.
 257         (expand_string): Change pmacro to const.
 258
 259 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 260
 261         * nds32-asm.c (operand_fields): Rename to ...
 262         (nds32_operand_fields): ... this.
 263         (keyword_gpr): Rename to ...
 264         (nds32_keyword_gpr): ... this.
 265         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 266         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 267         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 268         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 269         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 270         Mark static.
 271         (keywords): Rename to ...
 272         (nds32_keywords): ... this.
 273         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 274         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 275
 276 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 277
 278         * z80-dis.c (opc_ed): Make const.
 279         (pref_ed): Make p const.
 280
 281 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 282
 283         * microblaze-dis.c (get_field_special): Make op const.
 284         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 285         microblaze_opcodes.
 286         (print_insn_microblaze): Make op & pop const.
 287         (get_insn_microblaze): Make op const.  Rename opcodes to
 288         microblaze_opcodes.
 289         (microblaze_get_target_address): Likewise.
 290         * microblaze-opc.h (struct op_code_struct): Make const.
 291         Rename opcodes to microblaze_opcodes.
 292
 293 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 294
 295         * aarch64-gen.c (aarch64_opcode_table): Add const.
 296         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 297
 298 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 299
 300         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 301         available.
 302
 303 2021-06-22  Alan Modra  <amodra@gmail.com>
 304
 305         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 306         print separator for pcrel insns.
 307
 308 2021-06-19  Alan Modra  <amodra@gmail.com>
 309
 310         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 311
 312 2021-06-19  Alan Modra  <amodra@gmail.com>
 313
 314         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 315         entire buffer.
 316
 317 2021-06-17  Alan Modra  <amodra@gmail.com>
 318
 319         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 320         in table.
 321
 322 2021-06-03  Alan Modra  <amodra@gmail.com>
 323
 324         PR 1202
 325         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 326         Use unsigned int for inst.
 327
 328 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 329
 330         * arc-dis.c (arc_option_arg_t): New enumeration.
 331         (arc_options): New variable.
 332         (disassembler_options_arc): New function.
 333         (print_arc_disassembler_options): Reimplement in terms of
 334         "disassembler_options_arc".
 335
 336 2021-05-29  Alan Modra  <amodra@gmail.com>
 337
 338         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 339         Don't special case PPC_OPCODE_RAW.
 340         (lookup_prefix): Likewise.
 341         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 342         (print_insn_powerpc): ..update caller.
 343         * ppc-opc.c (EXT): Define.
 344         (powerpc_opcodes): Mark extended mnemonics with EXT.
 345         (prefix_opcodes, vle_opcodes): Likewise.
 346         (XISEL, XISEL_MASK): Add cr field and simplify.
 347         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 348         all isel variants to where the base mnemonic belongs.  Sort dstt,
 349         dststt and dssall.
 350
 351 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 352
 353         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 354         COP3 opcode instructions.
 355
 356 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 357
 358         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 359         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 360         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 361         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 362         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 363         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 364         "cop2", and "cop3" entries.
 365
 366 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 367
 368         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 369         entries and associated comments.
 370
 371 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 372
 373         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 374         of "c0".
 375
 376 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 377
 378         * mips-dis.c (mips_cp1_names_mips): New variable.
 379         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 380         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 381         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 382         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 383         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 384         "loongson2f".
 385
 386 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 387
 388         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 389         handling code over to...
 390         <OP_REG_CONTROL>: ... this new case.
 391         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 392         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 393         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 394         replacing the `G' operand code with `g'.  Update "cftc1" and
 395         "cftc2" entries replacing the `E' operand code with `y'.
 396         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 397         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 398         entries replacing the `G' operand code with `g'.
 399
 400 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 401
 402         * mips-dis.c (mips_cp0_names_r3900): New variable.
 403         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 404         for "r3900".
 405
 406 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 407
 408         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 409         and "mtthc2" to using the `G' rather than `g' operand code for
 410         the coprocessor control register referred.
 411
 412 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 413
 414         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 415         entries with each other.
 416
 417 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 418
 419         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 420
 421 2021-05-25  Alan Modra  <amodra@gmail.com>
 422
 423         * cris-desc.c: Regenerate.
 424         * cris-desc.h: Regenerate.
 425         * cris-opc.h: Regenerate.
 426         * po/POTFILES.in: Regenerate.
 427
 428 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 429
 430         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 431         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 432         (CGEN_CPUS): Add cris.
 433         (CRIS_DEPS): Define.
 434         (stamp-cris): New rule.
 435         * cgen.sh: Handle desc action.
 436         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 437         * Makefile.in, configure: Regenerate.
 438
 439 2021-05-18  Job Noorman  <mtvec@pm.me>
 440
 441         PR 27814
 442         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 443         the elf objects.
 444
 445 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 446
 447         * arm-dis.c (mve_opcodes): Fix disassembly of
 448         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 449         (is_mve_encoding_conflict): MVE vector loads should not match
 450         when P = W = 0.
 451         (is_mve_unpredictable): It's not unpredictable to use the same
 452         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 453
 454 2021-05-11  Nick Clifton  <nickc@redhat.com>
 455
 456         PR 27840
 457         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 458         the end of the code buffer.
 459
 460 2021-05-06  Stafford Horne  <shorne@gmail.com>
 461
 462         PR 21464
 463         * or1k-asm.c: Regenerate.
 464
 465 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 466
 467         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 468         info->insn_info_valid.
 469
 470 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-opc.tbl (lea): Add Optimize.
 473         * opcodes/i386-tbl.h: Re-generate.
 474
 475 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 476
 477         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 478         of l32r fetch and display referenced literal value.
 479
 480 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 481
 482         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 483         to 4 for literal disassembly.
 484
 485 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 486
 487         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 488         for TLBI instruction.
 489
 490 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 491
 492         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 493         DC instruction.
 494
 495 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 496
 497         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 498         "qualifier".
 499         (convert_mov_to_movewide): Add initializer for "value".
 500
 501 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 502
 503         * aarch64-opc.c: Add RME system registers.
 504
 505 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 506
 507         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 508         "addi d,CV,z" to "c.mv d,CV".
 509
 510 2021-04-12  Alan Modra  <amodra@gmail.com>
 511
 512         * configure.ac (--enable-checking): Add support.
 513         * config.in: Regenerate.
 514         * configure: Regenerate.
 515
 516 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 517
 518         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 519         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 520
 521 2021-04-09  Alan Modra  <amodra@gmail.com>
 522
 523         * ppc-dis.c (struct dis_private): Add "special".
 524         (POWERPC_DIALECT): Delete.  Replace uses with..
 525         (private_data): ..this.  New inline function.
 526         (disassemble_init_powerpc): Init "special" names.
 527         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 528         field of prefix instructions.
 529         (bsearch_reloc, print_got_plt): New functions.
 530         (print_insn_powerpc): For pcrel instructions, print target address
 531         and symbol if known, and decode plt and got loads too.
 532
 533 2021-04-08  Alan Modra  <amodra@gmail.com>
 534
 535         PR 27684
 536         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 537
 538 2021-04-08  Alan Modra  <amodra@gmail.com>
 539
 540         PR 27676
 541         * ppc-opc.c (DCBT_EO): Move earlier.
 542         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 543         (powerpc_operands): Add THCT and THDS entries.
 544         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 545
 546 2021-04-06  Alan Modra  <amodra@gmail.com>
 547
 548         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 549         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 550         symbol_at_address_func.
 551
 552 2021-04-05  Alan Modra  <amodra@gmail.com>
 553
 554         * configure.ac: Don't check for limits.h, string.h, strings.h or
 555         stdlib.h.
 556         (AC_ISC_POSIX): Don't invoke.
 557         * sysdep.h: Include stdlib.h and string.h unconditionally.
 558         * i386-opc.h: Include limits.h unconditionally.
 559         * wasm32-dis.c: Likewise.
 560         * cgen-opc.c: Don't include alloca-conf.h.
 561         * config.in: Regenerate.
 562         * configure: Regenerate.
 563
 564 2021-04-01  Martin Liska  <mliska@suse.cz>
 565
 566         * arm-dis.c (strneq): Remove strneq and use startswith.
 567         * cr16-dis.c (print_insn_cr16): Likewise.
 568         * score-dis.c (streq): Likewise.
 569         (strneq): Likewise.
 570         * score7-dis.c (strneq): Likewise.
 571
 572 2021-04-01  Alan Modra  <amodra@gmail.com>
 573
 574         PR 27675
 575         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 576
 577 2021-03-31  Alan Modra  <amodra@gmail.com>
 578
 579         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 580         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 581         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 582         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 583         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 584         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 585         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 586         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 587         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 588         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 589         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 590         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 591         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 592         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 593         and TRUE with true throughout.
 594
 595 2021-03-31  Alan Modra  <amodra@gmail.com>
 596
 597         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 598         * aarch64-dis.h: Likewise.
 599         * aarch64-opc.c: Likewise.
 600         * avr-dis.c: Likewise.
 601         * csky-dis.c: Likewise.
 602         * nds32-asm.c: Likewise.
 603         * nds32-dis.c: Likewise.
 604         * nfp-dis.c: Likewise.
 605         * riscv-dis.c: Likewise.
 606         * s12z-dis.c: Likewise.
 607         * wasm32-dis.c: Likewise.
 608
 609 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 612         (i386_seg_prefixes): New.
 613         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 614         (i386_seg_prefixes): Declare.
 615
 616 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 619
 620 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 623         * i386-reg.tbl (st): Move down.
 624         (st(0)): Delete. Extend comment.
 625         * i386-tbl.h: Re-generate.
 626
 627 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 630         (cmpsd): Move next to cmps.
 631         (movsd): Move next to movs.
 632         (cmpxchg16b): Move to separate section.
 633         (fisttp, fisttpll): Likewise.
 634         (monitor, mwait): Likewise.
 635         * i386-tbl.h: Re-generate.
 636
 637 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 640         (vpsadbw): Add C.
 641         * i386-tbl.h: Re-generate.
 642
 643 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 646         pclmul, gfni): New templates. Use them wherever possible. Move
 647         SSE4.1 pextrw into respective section.
 648         * i386-tbl.h: Re-generate.
 649
 650 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 651
 652         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 653         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 654         "length".
 655         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 656         Convert all of their uses to representation in opcode.
 657
 658 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 661         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 662         value of None. Shrink operands to 3 bits.
 663
 664 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 665
 666         * i386-gen.c (process_i386_opcode_modifier): New parameter
 667         "space".
 668         (output_i386_opcode): New local variable "space". Adjust
 669         process_i386_opcode_modifier() invocation.
 670         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 671         invocation.
 672         * i386-tbl.h: Re-generate.
 673
 674 2021-03-29  Alan Modra  <amodra@gmail.com>
 675
 676         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 677         (fp_qualifier_p, get_data_pattern): Likewise.
 678         (aarch64_get_operand_modifier_from_value): Likewise.
 679         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 680         (operand_variant_qualifier_p): Likewise.
 681         (qualifier_value_in_range_constraint_p): Likewise.
 682         (aarch64_get_qualifier_esize): Likewise.
 683         (aarch64_get_qualifier_nelem): Likewise.
 684         (aarch64_get_qualifier_standard_value): Likewise.
 685         (get_lower_bound, get_upper_bound): Likewise.
 686         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 687         (aarch64_print_operand): Likewise.
 688         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 689         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 690         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 691         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 692         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 693         (print_insn_tic6x): Likewise.
 694
 695 2021-03-29  Alan Modra  <amodra@gmail.com>
 696
 697         * arc-dis.c (extract_operand_value): Correct NULL cast.
 698         * frv-opc.h: Regenerate.
 699
 700 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 703         MMX form.
 704         * i386-tbl.h: Re-generate.
 705
 706 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 707
 708         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 709         immediate in br.n instruction.
 710
 711 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-dis.c (XMGatherD, VexGatherD): New.
 714         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 715         (print_insn): Check masking for S/G insns.
 716         (OP_E_memory): New local variable check_gather. Extend mandatory
 717         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 718         Extend check for disallowed 16-bit addressing.
 719         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 720         if()s to switch(). Check register conflicts for (VEX-encoded)
 721         gathers. Drop no longer reachable cases.
 722         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 723         vgatherdp*.
 724
 725 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 728         zeroing-masking without masking.
 729
 730 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 733         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 734         single-operand forms as deprecated.
 735         * i386-tbl.h: Re-generate.
 736
 737 2021-03-25  Alan Modra  <amodra@gmail.com>
 738
 739         PR 27647
 740         * ppc-opc.c (XLOCB_MASK): Delete.
 741         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 742         XLBH_MASK.
 743         (powerpc_opcodes): Accept a BH field on all extended forms of
 744         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 745
 746 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-gen.c (output_i386_opcode): Drop processing of
 749         opcode_length. Calculate length from base_opcode. Adjust prefix
 750         encoding determination.
 751         (process_i386_opcodes): Drop output of fake opcode_length.
 752         * i386-opc.h (struct insn_template): Drop opcode_length field.
 753         * i386-opc.tbl: Drop opcode length field from all templates.
 754         * i386-tbl.h: Re-generate.
 755
 756 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 759         parameter "prefix". Drop local variable "regular_encoding".
 760         Record prefix setting / check for consistency.
 761         (output_i386_opcode): Parse opcode_length and base_opcode
 762         earlier. Derive prefix encoding. Drop no longer applicable
 763         consistency checking. Adjust process_i386_opcode_modifier()
 764         invocation.
 765         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 766         invocation.
 767         * i386-tbl.h: Re-generate.
 768
 769 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 772         check.
 773         * i386-opc.h (Prefix_*): Move #define-s.
 774         * i386-opc.tbl: Move pseudo prefix enumerator values to
 775         extension opcode field. Introduce pseudopfx template.
 776         * i386-tbl.h: Re-generate.
 777
 778 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 779
 780         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 781         comment.
 782         * i386-tbl.h: Re-generate.
 783
 784 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 785
 786         * i386-opc.h (struct insn_template): Move cpu_flags field past
 787         opcode_modifier one.
 788         * i386-tbl.h: Re-generate.
 789
 790 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 791
 792         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 793         * i386-opc.h (OpcodeSpace): New enumerator.
 794         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 795         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 796         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 797         (struct i386_opcode_modifier): New field opcodespace. Shrink
 798         opcodeprefix field.
 799         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 800         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 801         OpcodePrefix uses.
 802         * i386-tbl.h: Re-generate.
 803
 804 2021-03-22  Martin Liska  <mliska@suse.cz>
 805
 806         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 807         * arc-dis.c (parse_option): Likewise.
 808         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 809         * cris-dis.c (print_with_operands): Likewise.
 810         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 811         * i386-dis.c (print_insn): Likewise.
 812         * ia64-gen.c (fetch_insn_class): Likewise.
 813         (parse_resource_users): Likewise.
 814         (in_iclass): Likewise.
 815         (lookup_specifier): Likewise.
 816         (insert_opcode_dependencies): Likewise.
 817         * mips-dis.c (parse_mips_ase_option): Likewise.
 818         (parse_mips_dis_option): Likewise.
 819         * s390-dis.c (disassemble_init_s390): Likewise.
 820         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 821
 822 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 823
 824         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 825
 826 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 827
 828         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 829         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 830
 831 2021-03-12  Alan Modra  <amodra@gmail.com>
 832
 833         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 834
 835 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 836
 837         * i386-dis.c (OP_XMM): Re-order checks.
 838
 839 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 840
 841         * i386-dis.c (putop): Drop need_vex check when also checking
 842         vex.evex.
 843         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 844         checking vex.b.
 845
 846 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 847
 848         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 849         checks. Move case label past broadcast check.
 850
 851 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 852
 853         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 854         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 855         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 856         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 857         EVEX_W_0F38C7_M_0_L_2): Delete.
 858         (REG_EVEX_0F38C7_M_0_L_2): New.
 859         (intel_operand_size): Handle VEX and EVEX the same for
 860         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 861         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 862         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 863         vex_vsib_q_w_d_mode uses.
 864         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 865         0F38A1, and 0F38A3 entries.
 866         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 867         entry.
 868         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 869         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 870         0F38A3 entries.
 871
 872 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 873
 874         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 875         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 876         MOD_VEX_0FXOP_09_12): Rename to ...
 877         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 878         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 879         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 880         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 881         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 882         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 883         (reg_table): Adjust comments.
 884         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 885         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 886         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 887         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 888         (vex_len_table): Adjust opcode 0A_12 entry.
 889         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 890         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 891         (rm_table): Move hreset entry.
 892
 893 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 894
 895         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 896         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 897         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 898         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 899         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 900         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 901         (get_valid_dis386): Also handle 512-bit vector length when
 902         vectoring into vex_len_table[].
 903         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 904         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 905         entries.
 906         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 907         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 908         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 909         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 910         entries.
 911
 912 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 913
 914         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 915         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 916         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 917         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 918         entries.
 919         * i386-dis-evex-len.h (evex_len_table): Likewise.
 920         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 921
 922 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 923
 924         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 925         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 926         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 927         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 928         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 929         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 930         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 931         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 932         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 933         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 934         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 935         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 936         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 937         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 938         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 939         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 940         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 941         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 942         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 943         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 944         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 945         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 946         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 947         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 948         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 949         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 950         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 951         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 952         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 953         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 954         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 955         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 956         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 957         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 958         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 959         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 960         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 961         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 962         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 963         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 964         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 965         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 966         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 967         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 968         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 969         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 970         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 971         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 972         EVEX_W_0F3A43_L_n): New.
 973         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 974         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 975         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 976         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 977         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 978         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 979         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 980         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 981         0F385B, 0F38C6, and 0F38C7 entries.
 982         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 983         0F38C6 and 0F38C7.
 984         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 985         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 986         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 987         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 988
 989 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 990
 991         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 992         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 993         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 994         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 995         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 996         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 997         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 998         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 999         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1000         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1001         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1002         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1003         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1004         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1005         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1006         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1007         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1008         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1009         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1010         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1011         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1012         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1013         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1014         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1015         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1016         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1017         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1018         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1019         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1020         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1021         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1022         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1023         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1024         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1025         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1026         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1027         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1028         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1029         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1030         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1031         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1032         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1033         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1034         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1035         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1036         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1037         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1038         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1039         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1040         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1041         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1042         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1043         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1044         VEX_W_0F99_P_2_LEN_0): Delete.
1045         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1046         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1047         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1048         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1049         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1050         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1051         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1052         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1053         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1054         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1055         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1056         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1057         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1058         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1059         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1060         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1061         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1062         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1063         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1064         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1065         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1066         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1067         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1068         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1069         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1070         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1071         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1072         (prefix_table): No longer link to vex_len_table[] for opcodes
1073         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1074         0F92, 0F93, 0F98, and 0F99.
1075         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1076         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1077         0F98, and 0F99.
1078         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1079         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1080         0F98, and 0F99.
1081         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1082         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1083         0F98, and 0F99.
1084         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1085         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1086         0F98, and 0F99.
1087
1088 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1089
1090         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1091         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1092         REG_VEX_0F73_M_0 respectively.
1093         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1094         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1095         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1096         MOD_VEX_0F73_REG_7): Delete.
1097         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1098         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1099         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1100         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1101         PREFIX_VEX_0F3AF0_L_0 respectively.
1102         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1103         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1104         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1105         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1106         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1107         VEX_LEN_0F38F7): New.
1108         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1109         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1110         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1111         0F38F3.
1112         (prefix_table): No longer link to vex_len_table[] for opcodes
1113         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1114         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1115         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1116         0F38F6, 0F38F7, and 0F3AF0.
1117         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1118         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1119         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1120         0F73.
1121
1122 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1123
1124         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1125         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1126         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1127         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1128         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1129         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1130         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1131         73.
1132         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1133         0F72, and 0F73.
1134         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1135         0F73.
1136
1137 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1138
1139         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1140         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1141         (reg_table): Don't link to mod_table[] where not needed. Add
1142         PREFIX_IGNORED to nop entries.
1143         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1144         (mod_table): Add nop entries next to prefetch ones. Drop
1145         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1146         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1147         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1148         PREFIX_OPCODE from endbr* entries.
1149         (get_valid_dis386): Also consider entry's name when zapping
1150         vindex.
1151         (print_insn): Handle PREFIX_IGNORED.
1152
1153 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1154
1155         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1156         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1157         element.
1158         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1159         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1160         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1161         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1162         (struct i386_opcode_modifier): Delete notrackprefixok,
1163         islockable, hleprefixok, and repprefixok fields. Add prefixok
1164         field.
1165         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1166         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1167         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1168         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1169         Replace HLEPrefixOk.
1170         * opcodes/i386-tbl.h: Re-generate.
1171
1172 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1173
1174         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1175         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1176         64-bit form.
1177         * opcodes/i386-tbl.h: Re-generate.
1178
1179 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1182         for {} instead of {0}. Don't look for '0'.
1183         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1184         size specifiers.
1185
1186 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1187
1188         PR 27158
1189         * riscv-dis.c (print_insn_args): Updated encoding macros.
1190         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1191         (match_c_addi16sp): Updated encoding macros.
1192         (match_c_lui): Likewise.
1193         (match_c_lui_with_hint): Likewise.
1194         (match_c_addi4spn): Likewise.
1195         (match_c_slli): Likewise.
1196         (match_slli_as_c_slli): Likewise.
1197         (match_c_slli64): Likewise.
1198         (match_srxi_as_c_srxi): Likewise.
1199         (riscv_insn_types): Added .insn css/cl/cs.
1200
1201 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1202
1203         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1204         (default_priv_spec): Updated type to riscv_spec_class.
1205         (parse_riscv_dis_option): Updated.
1206         * riscv-opc.c: Moved stuff and make the file tidy.
1207
1208 2021-02-17  Alan Modra  <amodra@gmail.com>
1209
1210         * wasm32-dis.c: Include limits.h.
1211         (CHAR_BIT): Provide backup define.
1212         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1213         Correct signed overflow checking.
1214
1215 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1216
1217         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1218         * i386-tbl.h: Re-generate.
1219
1220 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1221
1222         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1223         Oword.
1224         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1225
1226 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1227
1228         * s390-mkopc.c (main): Accept arch14 as cpu string.
1229         * s390-opc.txt: Add new arch14 instructions.
1230
1231 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1232
1233         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1234         favour of LIBINTL.
1235         * configure: Regenerated.
1236
1237 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1238
1239         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1240         * tic54x-opc.c (regs): Rename to ...
1241         (tic54x_regs): ... this.
1242         (mmregs): Rename to ...
1243         (tic54x_mmregs): ... this.
1244         (condition_codes): Rename to ...
1245         (tic54x_condition_codes): ... this.
1246         (cc2_codes): Rename to ...
1247         (tic54x_cc2_codes): ... this.
1248         (cc3_codes): Rename to ...
1249         (tic54x_cc3_codes): ... this.
1250         (status_bits): Rename to ...
1251         (tic54x_status_bits): ... this.
1252         (misc_symbols): Rename to ...
1253         (tic54x_misc_symbols): ... this.
1254
1255 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1256
1257         * riscv-opc.c (MASK_RVB_IMM): Removed.
1258         (riscv_opcodes): Removed zb* instructions.
1259         (riscv_ext_version_table): Removed versions for zb*.
1260
1261 2021-01-26  Alan Modra  <amodra@gmail.com>
1262
1263         * i386-gen.c (parse_template): Ensure entire template_instance
1264         is initialised.
1265
1266 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1267
1268         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1269         (riscv_fpr_names_abi): Likewise.
1270         (riscv_opcodes): Likewise.
1271         (riscv_insn_types): Likewise.
1272
1273 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1274
1275         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1276
1277 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1278
1279         * riscv-dis.c: Comments tidy and improvement.
1280         * riscv-opc.c: Likewise.
1281
1282 2021-01-13  Alan Modra  <amodra@gmail.com>
1283
1284         * Makefile.in: Regenerate.
1285
1286 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1287
1288         PR binutils/26792
1289         * configure.ac: Use GNU_MAKE_JOBSERVER.
1290         * aclocal.m4: Regenerated.
1291         * configure: Likewise.
1292
1293 2021-01-12  Nick Clifton  <nickc@redhat.com>
1294
1295         * po/sr.po: Updated Serbian translation.
1296
1297 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1298
1299         PR ld/27173
1300         * configure: Regenerated.
1301
1302 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1303
1304         * aarch64-asm-2.c: Regenerate.
1305         * aarch64-dis-2.c: Likewise.
1306         * aarch64-opc-2.c: Likewise.
1307         * aarch64-opc.c (aarch64_print_operand):
1308         Delete handling of AARCH64_OPND_CSRE_CSR.
1309         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1310         (CSRE): Likewise.
1311         (_CSRE_INSN): Likewise.
1312         (aarch64_opcode_table): Delete csr.
1313
1314 2021-01-11  Nick Clifton  <nickc@redhat.com>
1315
1316         * po/de.po: Updated German translation.
1317         * po/fr.po: Updated French translation.
1318         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1319         * po/sv.po: Updated Swedish translation.
1320         * po/uk.po: Updated Ukranian translation.
1321
1322 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1323
1324         * configure: Regenerated.
1325
1326 2021-01-09  Nick Clifton  <nickc@redhat.com>
1327
1328         * configure: Regenerate.
1329         * po/opcodes.pot: Regenerate.
1330
1331 2021-01-09  Nick Clifton  <nickc@redhat.com>
1332
1333         * 2.36 release branch crated.
1334
1335 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1336
1337         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1338         (DW, (XRC_MASK): Define.
1339         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1340
1341 2021-01-09  Alan Modra  <amodra@gmail.com>
1342
1343         * configure: Regenerate.
1344
1345 2021-01-08  Nick Clifton  <nickc@redhat.com>
1346
1347         * po/sv.po: Updated Swedish translation.
1348
1349 2021-01-08  Nick Clifton  <nickc@redhat.com>
1350
1351         PR 27129
1352         * aarch64-dis.c (determine_disassembling_preference): Move call to
1353         aarch64_match_operands_constraint outside of the assertion.
1354         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1355         Replace with a return of FALSE.
1356
1357         PR 27139
1358         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1359         core system register.
1360
1361 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1362
1363         * configure: Regenerate.
1364
1365 2021-01-07  Nick Clifton  <nickc@redhat.com>
1366
1367         * po/fr.po: Updated French translation.
1368
1369 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1370
1371         * m68k-opc.c (chkl): Change minimum architecture requirement to
1372         m68020.
1373
1374 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1375
1376         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1377
1378 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1379             Jim Wilson  <jimw@sifive.com>
1380             Andrew Waterman  <andrew@sifive.com>
1381             Maxim Blinov  <maxim.blinov@embecosm.com>
1382             Kito Cheng  <kito.cheng@sifive.com>
1383             Nelson Chu  <nelson.chu@sifive.com>
1384
1385         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1386         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1387
1388 2021-01-01  Alan Modra  <amodra@gmail.com>
1389
1390         Update year range in copyright notice of all files.
1391
1392 For older changes see ChangeLog-2020
1393 \f
1394 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1395
1396 Copying and distribution of this file, with or without modification,
1397 are permitted in any medium without royalty provided the copyright
1398 notice and this notice are preserved.
1399
1400 Local Variables:
1401 mode: change-log
1402 left-margin: 8
1403 fill-column: 74
1404 version-control: never
1405 End: