1 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
3 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
4 * Makefile.in: Regenerate.
6 2023-07-03 Nick Clifton <nickc@redhat.com>
8 * configure: Regenerate.
9 * po/opcodes.pot: Regenerate.
11 2023-07-03 Nick Clifton <nickc@redhat.com>
15 2023-05-23 Nick Clifton <nickc@redhat.com>
17 * po/sv.po: Updated translation.
19 2023-04-21 Tom Tromey <tromey@adacore.com>
21 * i386-dis.c (OP_J): Check result of get16.
23 2023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
25 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
26 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
27 vsubs2h, and vsubs4h instructions.
29 2023-04-11 Nick Clifton <nickc@redhat.com>
32 * nfp-dis.c (init_nfp6000_priv): Check that the output section
35 2023-03-15 Nick Clifton <nickc@redhat.com>
38 * mep-dis.c: Regenerate.
40 2023-03-15 Nick Clifton <nickc@redhat.com>
43 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
45 2023-02-28 Richard Ball <richard.ball@arm.com>
47 * aarch64-opc.c: Add MEC system registers.
49 2023-01-03 Nick Clifton <nickc@redhat.com>
51 * po/de.po: Updated German translation.
52 * po/ro.po: Updated Romainian translation.
53 * po/uk.po: Updated Ukrainian translation.
55 2022-12-31 Nick Clifton <nickc@redhat.com>
57 * 2.40 branch created.
59 2022-11-22 Shahab Vahedi <shahab@synopsys.com>
61 * arc-regs.h: Change isa_config address to 0xc1.
62 isa_config exists for ARC700 and ARCV2 and not ARCALL.
64 2022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
66 * rx-decode.opc: Switch arguments of the MVTACGU insn.
67 * rx-decode.c: Regenerate.
69 2022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
71 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
72 Rm_BANK,Rn is always 1.
74 2022-07-21 Peter Bergner <bergner@linux.ibm.com>
76 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
77 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
78 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
79 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
80 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
81 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
82 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
84 2022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
86 * disassemble.c (disassemble_init_for_target): Set
87 created_styled_output for ARC based targets.
88 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
89 instead of fprintf_ftype throughout.
90 (find_format): Likewise.
91 (print_flags): Likewise.
92 (print_insn_arc): Likewise.
94 2022-07-08 Nick Clifton <nickc@redhat.com>
96 * 2.39 branch created.
98 2022-07-04 Marcus Nilsson <brainbomb@gmail.com>
100 * disassemble.c: (disassemble_init_for_target): Set
101 created_styled_output for AVR based targets.
102 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
103 instead of fprintf_ftype throughout.
104 (avr_operand): Pass in and fill disassembler_style when
107 2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
109 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
112 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
114 * configure.ac: Handle bfd_amdgcn_arch.
115 * configure: Re-generate.
117 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
118 Maciej W. Rozycki <macro@orcam.me.uk>
120 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
121 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
122 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
125 2022-02-17 Nick Clifton <nickc@redhat.com>
127 * po/sr.po: Updated Serbian translation.
129 2022-02-14 Sergei Trofimovich <siarheit@google.com>
131 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
132 * microblaze-opc.h: Follow 'fsqrt' rename.
134 2022-01-24 Nick Clifton <nickc@redhat.com>
136 * po/ro.po: Updated Romanian translation.
137 * po/uk.po: Updated Ukranian translation.
139 2022-01-22 Nick Clifton <nickc@redhat.com>
141 * configure: Regenerate.
142 * po/opcodes.pot: Regenerate.
144 2022-01-22 Nick Clifton <nickc@redhat.com>
146 * 2.38 release branch created.
148 2022-01-17 Nick Clifton <nickc@redhat.com>
150 * Makefile.in: Regenerate.
151 * po/opcodes.pot: Regenerate.
153 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
155 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
156 in insn_type on branching instructions.
158 2021-11-25 Andrew Burgess <aburgess@redhat.com>
159 Simon Cook <simon.cook@embecosm.com>
161 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
162 (riscv_options): New static global.
163 (disassembler_options_riscv): New function.
164 (print_riscv_disassembler_options): Rewrite to use
165 disassembler_options_riscv.
167 2021-11-25 Nick Clifton <nickc@redhat.com>
170 * aarch64-asm.c: Replace assert(0) with real code.
171 * aarch64-dis.c: Likewise.
172 * aarch64-opc.c: Likewise.
174 2021-11-25 Nick Clifton <nickc@redhat.com>
176 * po/fr.po; Updated French translation.
178 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
180 * Makefile.am: Remove obsolete comment.
181 * configure.ac: Refer `libbfd.la' to link shared BFD library
183 * Makefile.in: Regenerate.
184 * configure: Regenerate.
186 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
188 * configure: Regenerate.
190 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
192 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
195 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
197 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
198 before an unknown instruction, '%d' is replaced with the
201 2021-09-02 Nick Clifton <nickc@redhat.com>
204 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
207 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
209 * arc-regs.h (DEF): Fix the register numbers.
211 2021-08-10 Nick Clifton <nickc@redhat.com>
213 * po/sr.po: Updated Serbian translation.
215 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
217 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
219 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
221 * s390-opc.txt: Add qpaci.
223 2021-07-03 Nick Clifton <nickc@redhat.com>
225 * configure: Regenerate.
226 * po/opcodes.pot: Regenerate.
228 2021-07-03 Nick Clifton <nickc@redhat.com>
230 * 2.37 release branch created.
232 2021-07-02 Alan Modra <amodra@gmail.com>
234 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
235 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
236 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
237 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
238 (nds32_keyword_gpr): Move declarations to..
239 * nds32-asm.h: ..here, constifying to match definitions.
241 2021-07-01 Mike Frysinger <vapier@gentoo.org>
243 * Makefile.am (GUILE): New variable.
244 (CGEN): Use $(GUILE).
245 * Makefile.in: Regenerate.
247 2021-07-01 Mike Frysinger <vapier@gentoo.org>
249 * mep-asm.c (macros): Mark static & const.
250 (lookup_macro): Change return & m to const.
251 (expand_macro): Change mac to const.
252 (expand_string): Change pmacro to const.
254 2021-07-01 Mike Frysinger <vapier@gentoo.org>
256 * nds32-asm.c (operand_fields): Rename to ...
257 (nds32_operand_fields): ... this.
258 (keyword_gpr): Rename to ...
259 (nds32_keyword_gpr): ... this.
260 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
261 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
262 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
263 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
264 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
266 (keywords): Rename to ...
267 (nds32_keywords): ... this.
268 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
269 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
271 2021-07-01 Mike Frysinger <vapier@gentoo.org>
273 * z80-dis.c (opc_ed): Make const.
274 (pref_ed): Make p const.
276 2021-07-01 Mike Frysinger <vapier@gentoo.org>
278 * microblaze-dis.c (get_field_special): Make op const.
279 (read_insn_microblaze): Make opr & op const. Rename opcodes to
281 (print_insn_microblaze): Make op & pop const.
282 (get_insn_microblaze): Make op const. Rename opcodes to
284 (microblaze_get_target_address): Likewise.
285 * microblaze-opc.h (struct op_code_struct): Make const.
286 Rename opcodes to microblaze_opcodes.
288 2021-07-01 Mike Frysinger <vapier@gentoo.org>
290 * aarch64-gen.c (aarch64_opcode_table): Add const.
291 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
293 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
295 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
298 2021-06-22 Alan Modra <amodra@gmail.com>
300 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
301 print separator for pcrel insns.
303 2021-06-19 Alan Modra <amodra@gmail.com>
305 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
307 2021-06-19 Alan Modra <amodra@gmail.com>
309 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
312 2021-06-17 Alan Modra <amodra@gmail.com>
314 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
317 2021-06-03 Alan Modra <amodra@gmail.com>
320 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
321 Use unsigned int for inst.
323 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
325 * arc-dis.c (arc_option_arg_t): New enumeration.
326 (arc_options): New variable.
327 (disassembler_options_arc): New function.
328 (print_arc_disassembler_options): Reimplement in terms of
329 "disassembler_options_arc".
331 2021-05-29 Alan Modra <amodra@gmail.com>
333 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
334 Don't special case PPC_OPCODE_RAW.
335 (lookup_prefix): Likewise.
336 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
337 (print_insn_powerpc): ..update caller.
338 * ppc-opc.c (EXT): Define.
339 (powerpc_opcodes): Mark extended mnemonics with EXT.
340 (prefix_opcodes, vle_opcodes): Likewise.
341 (XISEL, XISEL_MASK): Add cr field and simplify.
342 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
343 all isel variants to where the base mnemonic belongs. Sort dstt,
346 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
348 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
349 COP3 opcode instructions.
351 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
353 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
354 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
355 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
356 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
357 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
358 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
359 "cop2", and "cop3" entries.
361 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
363 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
364 entries and associated comments.
366 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
368 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
371 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
373 * mips-dis.c (mips_cp1_names_mips): New variable.
374 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
375 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
376 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
377 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
378 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
381 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
383 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
384 handling code over to...
385 <OP_REG_CONTROL>: ... this new case.
386 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
387 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
388 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
389 replacing the `G' operand code with `g'. Update "cftc1" and
390 "cftc2" entries replacing the `E' operand code with `y'.
391 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
392 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
393 entries replacing the `G' operand code with `g'.
395 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
397 * mips-dis.c (mips_cp0_names_r3900): New variable.
398 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
401 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
403 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
404 and "mtthc2" to using the `G' rather than `g' operand code for
405 the coprocessor control register referred.
407 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
409 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
410 entries with each other.
412 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
414 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
416 2021-05-25 Alan Modra <amodra@gmail.com>
418 * cris-desc.c: Regenerate.
419 * cris-desc.h: Regenerate.
420 * cris-opc.h: Regenerate.
421 * po/POTFILES.in: Regenerate.
423 2021-05-24 Mike Frysinger <vapier@gentoo.org>
425 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
426 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
427 (CGEN_CPUS): Add cris.
429 (stamp-cris): New rule.
430 * cgen.sh: Handle desc action.
431 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
432 * Makefile.in, configure: Regenerate.
434 2021-05-18 Job Noorman <mtvec@pm.me>
437 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
440 2021-05-17 Alex Coplan <alex.coplan@arm.com>
442 * arm-dis.c (mve_opcodes): Fix disassembly of
443 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
444 (is_mve_encoding_conflict): MVE vector loads should not match
446 (is_mve_unpredictable): It's not unpredictable to use the same
447 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
449 2021-05-11 Nick Clifton <nickc@redhat.com>
452 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
453 the end of the code buffer.
455 2021-05-06 Stafford Horne <shorne@gmail.com>
458 * or1k-asm.c: Regenerate.
460 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
462 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
463 info->insn_info_valid.
465 2021-04-26 Jan Beulich <jbeulich@suse.com>
467 * i386-opc.tbl (lea): Add Optimize.
468 * opcodes/i386-tbl.h: Re-generate.
470 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
472 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
473 of l32r fetch and display referenced literal value.
475 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
477 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
478 to 4 for literal disassembly.
480 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
482 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
483 for TLBI instruction.
485 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
487 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
490 2021-04-19 Jan Beulich <jbeulich@suse.com>
492 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
494 (convert_mov_to_movewide): Add initializer for "value".
496 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
498 * aarch64-opc.c: Add RME system registers.
500 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
502 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
503 "addi d,CV,z" to "c.mv d,CV".
505 2021-04-12 Alan Modra <amodra@gmail.com>
507 * configure.ac (--enable-checking): Add support.
508 * config.in: Regenerate.
509 * configure: Regenerate.
511 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
513 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
514 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
516 2021-04-09 Alan Modra <amodra@gmail.com>
518 * ppc-dis.c (struct dis_private): Add "special".
519 (POWERPC_DIALECT): Delete. Replace uses with..
520 (private_data): ..this. New inline function.
521 (disassemble_init_powerpc): Init "special" names.
522 (skip_optional_operands): Add is_pcrel arg, set when detecting R
523 field of prefix instructions.
524 (bsearch_reloc, print_got_plt): New functions.
525 (print_insn_powerpc): For pcrel instructions, print target address
526 and symbol if known, and decode plt and got loads too.
528 2021-04-08 Alan Modra <amodra@gmail.com>
531 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
533 2021-04-08 Alan Modra <amodra@gmail.com>
536 * ppc-opc.c (DCBT_EO): Move earlier.
537 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
538 (powerpc_operands): Add THCT and THDS entries.
539 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
541 2021-04-06 Alan Modra <amodra@gmail.com>
543 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
544 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
545 symbol_at_address_func.
547 2021-04-05 Alan Modra <amodra@gmail.com>
549 * configure.ac: Don't check for limits.h, string.h, strings.h or
551 (AC_ISC_POSIX): Don't invoke.
552 * sysdep.h: Include stdlib.h and string.h unconditionally.
553 * i386-opc.h: Include limits.h unconditionally.
554 * wasm32-dis.c: Likewise.
555 * cgen-opc.c: Don't include alloca-conf.h.
556 * config.in: Regenerate.
557 * configure: Regenerate.
559 2021-04-01 Martin Liska <mliska@suse.cz>
561 * arm-dis.c (strneq): Remove strneq and use startswith.
562 * cr16-dis.c (print_insn_cr16): Likewise.
563 * score-dis.c (streq): Likewise.
565 * score7-dis.c (strneq): Likewise.
567 2021-04-01 Alan Modra <amodra@gmail.com>
570 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
572 2021-03-31 Alan Modra <amodra@gmail.com>
574 * sysdep.h (POISON_BFD_BOOLEAN): Define.
575 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
576 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
577 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
578 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
579 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
580 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
581 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
582 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
583 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
584 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
585 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
586 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
587 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
588 and TRUE with true throughout.
590 2021-03-31 Alan Modra <amodra@gmail.com>
592 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
593 * aarch64-dis.h: Likewise.
594 * aarch64-opc.c: Likewise.
595 * avr-dis.c: Likewise.
596 * csky-dis.c: Likewise.
597 * nds32-asm.c: Likewise.
598 * nds32-dis.c: Likewise.
599 * nfp-dis.c: Likewise.
600 * riscv-dis.c: Likewise.
601 * s12z-dis.c: Likewise.
602 * wasm32-dis.c: Likewise.
604 2021-03-30 Jan Beulich <jbeulich@suse.com>
606 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
607 (i386_seg_prefixes): New.
608 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
609 (i386_seg_prefixes): Declare.
611 2021-03-30 Jan Beulich <jbeulich@suse.com>
613 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
615 2021-03-30 Jan Beulich <jbeulich@suse.com>
617 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
618 * i386-reg.tbl (st): Move down.
619 (st(0)): Delete. Extend comment.
620 * i386-tbl.h: Re-generate.
622 2021-03-29 Jan Beulich <jbeulich@suse.com>
624 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
625 (cmpsd): Move next to cmps.
626 (movsd): Move next to movs.
627 (cmpxchg16b): Move to separate section.
628 (fisttp, fisttpll): Likewise.
629 (monitor, mwait): Likewise.
630 * i386-tbl.h: Re-generate.
632 2021-03-29 Jan Beulich <jbeulich@suse.com>
634 * i386-opc.tbl (psadbw): Add <sse2:comm>.
636 * i386-tbl.h: Re-generate.
638 2021-03-29 Jan Beulich <jbeulich@suse.com>
640 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
641 pclmul, gfni): New templates. Use them wherever possible. Move
642 SSE4.1 pextrw into respective section.
643 * i386-tbl.h: Re-generate.
645 2021-03-29 Jan Beulich <jbeulich@suse.com>
647 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
648 strtoull(). Bump upper loop bound. Widen masks. Sanity check
650 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
651 Convert all of their uses to representation in opcode.
653 2021-03-29 Jan Beulich <jbeulich@suse.com>
655 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
656 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
657 value of None. Shrink operands to 3 bits.
659 2021-03-29 Jan Beulich <jbeulich@suse.com>
661 * i386-gen.c (process_i386_opcode_modifier): New parameter
663 (output_i386_opcode): New local variable "space". Adjust
664 process_i386_opcode_modifier() invocation.
665 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
667 * i386-tbl.h: Re-generate.
669 2021-03-29 Alan Modra <amodra@gmail.com>
671 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
672 (fp_qualifier_p, get_data_pattern): Likewise.
673 (aarch64_get_operand_modifier_from_value): Likewise.
674 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
675 (operand_variant_qualifier_p): Likewise.
676 (qualifier_value_in_range_constraint_p): Likewise.
677 (aarch64_get_qualifier_esize): Likewise.
678 (aarch64_get_qualifier_nelem): Likewise.
679 (aarch64_get_qualifier_standard_value): Likewise.
680 (get_lower_bound, get_upper_bound): Likewise.
681 (aarch64_find_best_match, match_operands_qualifier): Likewise.
682 (aarch64_print_operand): Likewise.
683 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
684 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
685 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
686 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
687 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
688 (print_insn_tic6x): Likewise.
690 2021-03-29 Alan Modra <amodra@gmail.com>
692 * arc-dis.c (extract_operand_value): Correct NULL cast.
693 * frv-opc.h: Regenerate.
695 2021-03-26 Jan Beulich <jbeulich@suse.com>
697 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
699 * i386-tbl.h: Re-generate.
701 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
703 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
704 immediate in br.n instruction.
706 2021-03-25 Jan Beulich <jbeulich@suse.com>
708 * i386-dis.c (XMGatherD, VexGatherD): New.
709 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
710 (print_insn): Check masking for S/G insns.
711 (OP_E_memory): New local variable check_gather. Extend mandatory
712 SIB check. Check register conflicts for (EVEX-encoded) gathers.
713 Extend check for disallowed 16-bit addressing.
714 (OP_VEX): New local variables modrm_reg and sib_index. Convert
715 if()s to switch(). Check register conflicts for (VEX-encoded)
716 gathers. Drop no longer reachable cases.
717 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
720 2021-03-25 Jan Beulich <jbeulich@suse.com>
722 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
723 zeroing-masking without masking.
725 2021-03-25 Jan Beulich <jbeulich@suse.com>
727 * i386-opc.tbl (invlpgb): Fix multi-operand form.
728 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
729 single-operand forms as deprecated.
730 * i386-tbl.h: Re-generate.
732 2021-03-25 Alan Modra <amodra@gmail.com>
735 * ppc-opc.c (XLOCB_MASK): Delete.
736 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
738 (powerpc_opcodes): Accept a BH field on all extended forms of
739 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
741 2021-03-24 Jan Beulich <jbeulich@suse.com>
743 * i386-gen.c (output_i386_opcode): Drop processing of
744 opcode_length. Calculate length from base_opcode. Adjust prefix
745 encoding determination.
746 (process_i386_opcodes): Drop output of fake opcode_length.
747 * i386-opc.h (struct insn_template): Drop opcode_length field.
748 * i386-opc.tbl: Drop opcode length field from all templates.
749 * i386-tbl.h: Re-generate.
751 2021-03-24 Jan Beulich <jbeulich@suse.com>
753 * i386-gen.c (process_i386_opcode_modifier): Return void. New
754 parameter "prefix". Drop local variable "regular_encoding".
755 Record prefix setting / check for consistency.
756 (output_i386_opcode): Parse opcode_length and base_opcode
757 earlier. Derive prefix encoding. Drop no longer applicable
758 consistency checking. Adjust process_i386_opcode_modifier()
760 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
762 * i386-tbl.h: Re-generate.
764 2021-03-24 Jan Beulich <jbeulich@suse.com>
766 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
768 * i386-opc.h (Prefix_*): Move #define-s.
769 * i386-opc.tbl: Move pseudo prefix enumerator values to
770 extension opcode field. Introduce pseudopfx template.
771 * i386-tbl.h: Re-generate.
773 2021-03-23 Jan Beulich <jbeulich@suse.com>
775 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
777 * i386-tbl.h: Re-generate.
779 2021-03-23 Jan Beulich <jbeulich@suse.com>
781 * i386-opc.h (struct insn_template): Move cpu_flags field past
783 * i386-tbl.h: Re-generate.
785 2021-03-23 Jan Beulich <jbeulich@suse.com>
787 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
788 * i386-opc.h (OpcodeSpace): New enumerator.
789 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
790 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
791 SPACE_XOP09, SPACE_XOP0A): ... respectively.
792 (struct i386_opcode_modifier): New field opcodespace. Shrink
794 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
795 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
797 * i386-tbl.h: Re-generate.
799 2021-03-22 Martin Liska <mliska@suse.cz>
801 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
802 * arc-dis.c (parse_option): Likewise.
803 * arm-dis.c (parse_arm_disassembler_options): Likewise.
804 * cris-dis.c (print_with_operands): Likewise.
805 * h8300-dis.c (bfd_h8_disassemble): Likewise.
806 * i386-dis.c (print_insn): Likewise.
807 * ia64-gen.c (fetch_insn_class): Likewise.
808 (parse_resource_users): Likewise.
809 (in_iclass): Likewise.
810 (lookup_specifier): Likewise.
811 (insert_opcode_dependencies): Likewise.
812 * mips-dis.c (parse_mips_ase_option): Likewise.
813 (parse_mips_dis_option): Likewise.
814 * s390-dis.c (disassemble_init_s390): Likewise.
815 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
817 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
819 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
821 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
823 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
824 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
826 2021-03-12 Alan Modra <amodra@gmail.com>
828 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
830 2021-03-11 Jan Beulich <jbeulich@suse.com>
832 * i386-dis.c (OP_XMM): Re-order checks.
834 2021-03-11 Jan Beulich <jbeulich@suse.com>
836 * i386-dis.c (putop): Drop need_vex check when also checking
838 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
841 2021-03-11 Jan Beulich <jbeulich@suse.com>
843 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
844 checks. Move case label past broadcast check.
846 2021-03-10 Jan Beulich <jbeulich@suse.com>
848 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
849 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
850 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
851 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
852 EVEX_W_0F38C7_M_0_L_2): Delete.
853 (REG_EVEX_0F38C7_M_0_L_2): New.
854 (intel_operand_size): Handle VEX and EVEX the same for
855 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
856 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
857 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
858 vex_vsib_q_w_d_mode uses.
859 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
860 0F38A1, and 0F38A3 entries.
861 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
863 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
864 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
867 2021-03-10 Jan Beulich <jbeulich@suse.com>
869 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
870 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
871 MOD_VEX_0FXOP_09_12): Rename to ...
872 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
873 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
874 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
875 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
876 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
877 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
878 (reg_table): Adjust comments.
879 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
880 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
881 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
882 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
883 (vex_len_table): Adjust opcode 0A_12 entry.
884 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
885 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
886 (rm_table): Move hreset entry.
888 2021-03-10 Jan Beulich <jbeulich@suse.com>
890 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
891 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
892 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
893 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
894 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
895 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
896 (get_valid_dis386): Also handle 512-bit vector length when
897 vectoring into vex_len_table[].
898 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
899 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
901 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
902 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
903 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
904 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
907 2021-03-10 Jan Beulich <jbeulich@suse.com>
909 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
910 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
911 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
912 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
914 * i386-dis-evex-len.h (evex_len_table): Likewise.
915 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
917 2021-03-10 Jan Beulich <jbeulich@suse.com>
919 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
920 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
921 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
922 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
923 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
924 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
925 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
926 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
927 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
928 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
929 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
930 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
931 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
932 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
933 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
934 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
935 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
936 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
937 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
938 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
939 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
940 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
941 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
942 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
943 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
944 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
945 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
946 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
947 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
948 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
949 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
950 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
951 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
952 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
953 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
954 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
955 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
956 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
957 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
958 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
959 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
960 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
961 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
962 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
963 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
964 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
965 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
966 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
967 EVEX_W_0F3A43_L_n): New.
968 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
969 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
970 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
971 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
972 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
973 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
974 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
975 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
976 0F385B, 0F38C6, and 0F38C7 entries.
977 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
979 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
980 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
981 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
982 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
984 2021-03-10 Jan Beulich <jbeulich@suse.com>
986 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
987 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
988 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
989 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
990 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
991 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
992 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
993 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
994 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
995 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
996 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
997 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
998 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
999 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1000 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1001 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1002 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1003 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1004 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1005 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1006 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1007 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1008 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1009 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1010 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1011 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1012 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1013 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1014 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1015 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1016 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1017 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1018 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1019 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1020 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1021 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1022 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1023 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1024 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1025 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1026 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1027 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1028 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1029 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1030 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1031 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1032 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1033 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1034 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1035 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1036 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1037 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1038 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1039 VEX_W_0F99_P_2_LEN_0): Delete.
1040 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1041 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1042 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1043 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1044 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1045 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1046 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1047 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1048 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1049 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1050 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1051 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1052 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1053 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1054 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1055 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1056 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1057 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1058 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1059 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1060 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1061 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1062 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1063 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1064 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1065 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1066 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1067 (prefix_table): No longer link to vex_len_table[] for opcodes
1068 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1069 0F92, 0F93, 0F98, and 0F99.
1070 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1071 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1073 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1074 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1076 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1077 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1079 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1080 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1083 2021-03-10 Jan Beulich <jbeulich@suse.com>
1085 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1086 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1087 REG_VEX_0F73_M_0 respectively.
1088 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1089 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1090 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1091 MOD_VEX_0F73_REG_7): Delete.
1092 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1093 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1094 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1095 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1096 PREFIX_VEX_0F3AF0_L_0 respectively.
1097 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1098 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1099 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1100 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1101 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1102 VEX_LEN_0F38F7): New.
1103 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1104 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1105 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1107 (prefix_table): No longer link to vex_len_table[] for opcodes
1108 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1109 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1110 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1111 0F38F6, 0F38F7, and 0F3AF0.
1112 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1113 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1114 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1117 2021-03-10 Jan Beulich <jbeulich@suse.com>
1119 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1120 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1121 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1122 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1123 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1124 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1125 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1127 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1129 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1132 2021-03-10 Jan Beulich <jbeulich@suse.com>
1134 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1135 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1136 (reg_table): Don't link to mod_table[] where not needed. Add
1137 PREFIX_IGNORED to nop entries.
1138 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1139 (mod_table): Add nop entries next to prefetch ones. Drop
1140 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1141 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1142 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1143 PREFIX_OPCODE from endbr* entries.
1144 (get_valid_dis386): Also consider entry's name when zapping
1146 (print_insn): Handle PREFIX_IGNORED.
1148 2021-03-09 Jan Beulich <jbeulich@suse.com>
1150 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1151 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1153 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1154 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1155 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1156 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1157 (struct i386_opcode_modifier): Delete notrackprefixok,
1158 islockable, hleprefixok, and repprefixok fields. Add prefixok
1160 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1161 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1162 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1163 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1164 Replace HLEPrefixOk.
1165 * opcodes/i386-tbl.h: Re-generate.
1167 2021-03-09 Jan Beulich <jbeulich@suse.com>
1169 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1170 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1172 * opcodes/i386-tbl.h: Re-generate.
1174 2021-03-03 Jan Beulich <jbeulich@suse.com>
1176 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1177 for {} instead of {0}. Don't look for '0'.
1178 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1181 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1184 * riscv-dis.c (print_insn_args): Updated encoding macros.
1185 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1186 (match_c_addi16sp): Updated encoding macros.
1187 (match_c_lui): Likewise.
1188 (match_c_lui_with_hint): Likewise.
1189 (match_c_addi4spn): Likewise.
1190 (match_c_slli): Likewise.
1191 (match_slli_as_c_slli): Likewise.
1192 (match_c_slli64): Likewise.
1193 (match_srxi_as_c_srxi): Likewise.
1194 (riscv_insn_types): Added .insn css/cl/cs.
1196 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1198 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1199 (default_priv_spec): Updated type to riscv_spec_class.
1200 (parse_riscv_dis_option): Updated.
1201 * riscv-opc.c: Moved stuff and make the file tidy.
1203 2021-02-17 Alan Modra <amodra@gmail.com>
1205 * wasm32-dis.c: Include limits.h.
1206 (CHAR_BIT): Provide backup define.
1207 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1208 Correct signed overflow checking.
1210 2021-02-16 Jan Beulich <jbeulich@suse.com>
1212 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1213 * i386-tbl.h: Re-generate.
1215 2021-02-16 Jan Beulich <jbeulich@suse.com>
1217 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1219 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1221 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1223 * s390-mkopc.c (main): Accept arch14 as cpu string.
1224 * s390-opc.txt: Add new arch14 instructions.
1226 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1228 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1230 * configure: Regenerated.
1232 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1234 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1235 * tic54x-opc.c (regs): Rename to ...
1236 (tic54x_regs): ... this.
1237 (mmregs): Rename to ...
1238 (tic54x_mmregs): ... this.
1239 (condition_codes): Rename to ...
1240 (tic54x_condition_codes): ... this.
1241 (cc2_codes): Rename to ...
1242 (tic54x_cc2_codes): ... this.
1243 (cc3_codes): Rename to ...
1244 (tic54x_cc3_codes): ... this.
1245 (status_bits): Rename to ...
1246 (tic54x_status_bits): ... this.
1247 (misc_symbols): Rename to ...
1248 (tic54x_misc_symbols): ... this.
1250 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1252 * riscv-opc.c (MASK_RVB_IMM): Removed.
1253 (riscv_opcodes): Removed zb* instructions.
1254 (riscv_ext_version_table): Removed versions for zb*.
1256 2021-01-26 Alan Modra <amodra@gmail.com>
1258 * i386-gen.c (parse_template): Ensure entire template_instance
1261 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1263 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1264 (riscv_fpr_names_abi): Likewise.
1265 (riscv_opcodes): Likewise.
1266 (riscv_insn_types): Likewise.
1268 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1270 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1272 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1274 * riscv-dis.c: Comments tidy and improvement.
1275 * riscv-opc.c: Likewise.
1277 2021-01-13 Alan Modra <amodra@gmail.com>
1279 * Makefile.in: Regenerate.
1281 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1284 * configure.ac: Use GNU_MAKE_JOBSERVER.
1285 * aclocal.m4: Regenerated.
1286 * configure: Likewise.
1288 2021-01-12 Nick Clifton <nickc@redhat.com>
1290 * po/sr.po: Updated Serbian translation.
1292 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1295 * configure: Regenerated.
1297 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1299 * aarch64-asm-2.c: Regenerate.
1300 * aarch64-dis-2.c: Likewise.
1301 * aarch64-opc-2.c: Likewise.
1302 * aarch64-opc.c (aarch64_print_operand):
1303 Delete handling of AARCH64_OPND_CSRE_CSR.
1304 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1306 (_CSRE_INSN): Likewise.
1307 (aarch64_opcode_table): Delete csr.
1309 2021-01-11 Nick Clifton <nickc@redhat.com>
1311 * po/de.po: Updated German translation.
1312 * po/fr.po: Updated French translation.
1313 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1314 * po/sv.po: Updated Swedish translation.
1315 * po/uk.po: Updated Ukranian translation.
1317 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1319 * configure: Regenerated.
1321 2021-01-09 Nick Clifton <nickc@redhat.com>
1323 * configure: Regenerate.
1324 * po/opcodes.pot: Regenerate.
1326 2021-01-09 Nick Clifton <nickc@redhat.com>
1328 * 2.36 release branch crated.
1330 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1332 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1333 (DW, (XRC_MASK): Define.
1334 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1336 2021-01-09 Alan Modra <amodra@gmail.com>
1338 * configure: Regenerate.
1340 2021-01-08 Nick Clifton <nickc@redhat.com>
1342 * po/sv.po: Updated Swedish translation.
1344 2021-01-08 Nick Clifton <nickc@redhat.com>
1347 * aarch64-dis.c (determine_disassembling_preference): Move call to
1348 aarch64_match_operands_constraint outside of the assertion.
1349 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1350 Replace with a return of FALSE.
1353 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1354 core system register.
1356 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1358 * configure: Regenerate.
1360 2021-01-07 Nick Clifton <nickc@redhat.com>
1362 * po/fr.po: Updated French translation.
1364 2021-01-07 Fredrik Noring <noring@nocrew.org>
1366 * m68k-opc.c (chkl): Change minimum architecture requirement to
1369 2021-01-07 Philipp Tomsich <prt@gnu.org>
1371 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1373 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1374 Jim Wilson <jimw@sifive.com>
1375 Andrew Waterman <andrew@sifive.com>
1376 Maxim Blinov <maxim.blinov@embecosm.com>
1377 Kito Cheng <kito.cheng@sifive.com>
1378 Nelson Chu <nelson.chu@sifive.com>
1380 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1381 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1383 2021-01-01 Alan Modra <amodra@gmail.com>
1385 Update year range in copyright notice of all files.
1387 For older changes see ChangeLog-2020
1389 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1391 Copying and distribution of this file, with or without modification,
1392 are permitted in any medium without royalty provided the copyright
1393 notice and this notice are preserved.
1399 version-control: never