opcodes/ChangeLog

   1 2020-07-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (EXqScalarS): Delete.
   4         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
   5         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
   6
   7 2020-07-06  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-dis.c (safe-ctype.h): Include.
  10         (EXdScalar, EXqScalar): Delete.
  11         (d_scalar_mode, q_scalar_mode): Delete.
  12         (prefix_table, vex_len_table): Use EXxmm_md in place of
  13         EXdScalar and EXxmm_mq in place of EXqScalar.
  14         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
  15         d_scalar_mode and q_scalar_mode.
  16         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
  17         (vmovsd): Use EXxmm_mq.
  18
  19 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
  20
  21         PR 26204
  22         * arc-dis.c: Fix spelling mistake.
  23         * po/opcodes.pot: Regenerate.
  24
  25 2020-07-06  Nick Clifton  <nickc@redhat.com>
  26
  27         * po/pt_BR.po: Updated Brazilian Portugugese translation.
  28         * po/uk.po: Updated Ukranian translation.
  29
  30 2020-07-04  Nick Clifton  <nickc@redhat.com>
  31
  32         * configure: Regenerate.
  33         * po/opcodes.pot: Regenerate.
  34
  35 2020-07-04  Nick Clifton  <nickc@redhat.com>
  36
  37         Binutils 2.35 branch created.
  38
  39 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
  42         * i386-opc.h (VexSwapSources): New.
  43         (i386_opcode_modifier): Add vexswapsources.
  44         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
  45         with two source operands swapped.
  46         * i386-tbl.h: Regenerated.
  47
  48 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
  49
  50         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
  51         unprivileged CSR can also be initialized.
  52
  53 2020-06-29  Alan Modra  <amodra@gmail.com>
  54
  55         * arm-dis.c: Use C style comments.
  56         * cr16-opc.c: Likewise.
  57         * ft32-dis.c: Likewise.
  58         * moxie-opc.c: Likewise.
  59         * tic54x-dis.c: Likewise.
  60         * s12z-opc.c: Remove useless comment.
  61         * xgate-dis.c: Likewise.
  62
  63 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         * i386-opc.tbl: Add a blank line.
  66
  67 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  68
  69         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
  70         (VecSIB128): Renamed to ...
  71         (VECSIB128): This.
  72         (VecSIB256): Renamed to ...
  73         (VECSIB256): This.
  74         (VecSIB512): Renamed to ...
  75         (VECSIB512): This.
  76         (VecSIB): Renamed to ...
  77         (SIB): This.
  78         (i386_opcode_modifier): Replace vecsib with sib.
  79         * i386-opc.tbl (VecSIB128): New.
  80         (VecSIB256): Likewise.
  81         (VecSIB512): Likewise.
  82         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
  83         and VecSIB512, respectively.
  84
  85 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-dis.c: Adjust description of I macro.
  88         (x86_64_table): Drop use of I.
  89         (float_mem): Replace use of I.
  90         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  91
  92 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-dis.c: (print_insn): Avoid straight assignment to
  95         priv.orig_sizeflag when processing -M sub-options.
  96
  97 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-dis.c: Adjust description of J macro.
 100         (dis386, x86_64_table, mod_table): Replace J.
 101         (putop): Remove handling of J.
 102
 103 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 104
 105         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 106
 107 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-dis.c: Adjust description of "LQ" macro.
 110         (dis386_twobyte): Use LQ for sysret.
 111         (putop): Adjust handling of LQ.
 112
 113 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 114
 115         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 116         * riscv-dis.c: Include elfxx-riscv.h.
 117
 118 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 121
 122 2020-06-17  Lili Cui  <lili.cui@intel.com>
 123
 124         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 125
 126 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         PR gas/26115
 129         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 130         * i386-opc.tbl: Likewise.
 131         * i386-tbl.h: Regenerated.
 132
 133 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 134
 135         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 136
 137 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 138
 139         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 140         (SR_CORE): Likewise.
 141         (SR_FEAT): Likewise.
 142         (SR_RNG): Likewise.
 143         (SR_V8_1): Likewise.
 144         (SR_V8_2): Likewise.
 145         (SR_V8_3): Likewise.
 146         (SR_V8_4): Likewise.
 147         (SR_PAN): Likewise.
 148         (SR_RAS): Likewise.
 149         (SR_SSBS): Likewise.
 150         (SR_SVE): Likewise.
 151         (SR_ID_PFR2): Likewise.
 152         (SR_PROFILE): Likewise.
 153         (SR_MEMTAG): Likewise.
 154         (SR_SCXTNUM): Likewise.
 155         (aarch64_sys_regs): Refactor to store feature information in the table.
 156         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 157         that now describe their own features.
 158         (aarch64_pstatefield_supported_p): Likewise.
 159
 160 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         * i386-dis.c (prefix_table): Fix a typo in comments.
 163
 164 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-dis.c (rex_ignored): Delete.
 167         (ckprefix): Drop rex_ignored initialization.
 168         (get_valid_dis386): Drop setting of rex_ignored.
 169         (print_insn): Drop checking of rex_ignored. Don't record data
 170         size prefix as used with VEX-and-alike encodings.
 171
 172 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 175         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 176         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 177         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 178         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 179         VEX_0F12, and VEX_0F16.
 180         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 181         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 182         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 183         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 184         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 185         MOD_VEX_0F16_PREFIX_2 entries.
 186
 187 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 190         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 191         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 192         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 193         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 194         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 195         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 196         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 197         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 198         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 199         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 200         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 201         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 202         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 203         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 204         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 205         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 206         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 207         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 208         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 209         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 210         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 211         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 212         EVEX_W_0FC6_P_2): Delete.
 213         (print_insn): Add EVEX.W vs embedded prefix consistency check
 214         to prefix validation.
 215         * i386-dis-evex.h (evex_table): Don't further descend for
 216         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 217         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 218         and 0F2B.
 219         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 220         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 221         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 222         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 223         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 224         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 225         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 226         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 227         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 228         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 229         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 230         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 231         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 232         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 233         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 234         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 235         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 236         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 237         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 238         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 239         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 240         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 241         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 242         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 243         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 244         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 245         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 246
 247 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 250         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 251         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 252         vmovmskpX.
 253         (print_insn): Drop pointless check against bad_opcode. Split
 254         prefix validation into legacy and VEX-and-alike parts.
 255         (putop): Re-work 'X' macro handling.
 256
 257 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-dis.c (MOD_0F51): Rename to ...
 260         (MOD_0F50): ... this.
 261
 262 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 263
 264         * arm-dis.c (arm_opcodes): Add dfb.
 265         (thumb32_opcodes): Add dfb.
 266
 267 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 270
 271 2020-06-06  Alan Modra  <amodra@gmail.com>
 272
 273         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 274
 275 2020-06-05  Alan Modra  <amodra@gmail.com>
 276
 277         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 278         size is large enough.
 279
 280 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 281
 282         * disassemble.c (disassemble_init_for_target): Set endian_code for
 283         bpf targets.
 284         * bpf-desc.c: Regenerate.
 285         * bpf-opc.c: Likewise.
 286         * bpf-dis.c: Likewise.
 287
 288 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 289
 290         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 291         (cgen_put_insn_value): Likewise.
 292         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 293         * cgen-dis.in (print_insn): Likewise.
 294         * cgen-ibld.in (insert_1): Likewise.
 295         (insert_1): Likewise.
 296         (insert_insn_normal): Likewise.
 297         (extract_1): Likewise.
 298         * bpf-dis.c: Regenerate.
 299         * bpf-ibld.c: Likewise.
 300         * bpf-ibld.c: Likewise.
 301         * cgen-dis.in: Likewise.
 302         * cgen-ibld.in: Likewise.
 303         * cgen-opc.c: Likewise.
 304         * epiphany-dis.c: Likewise.
 305         * epiphany-ibld.c: Likewise.
 306         * fr30-dis.c: Likewise.
 307         * fr30-ibld.c: Likewise.
 308         * frv-dis.c: Likewise.
 309         * frv-ibld.c: Likewise.
 310         * ip2k-dis.c: Likewise.
 311         * ip2k-ibld.c: Likewise.
 312         * iq2000-dis.c: Likewise.
 313         * iq2000-ibld.c: Likewise.
 314         * lm32-dis.c: Likewise.
 315         * lm32-ibld.c: Likewise.
 316         * m32c-dis.c: Likewise.
 317         * m32c-ibld.c: Likewise.
 318         * m32r-dis.c: Likewise.
 319         * m32r-ibld.c: Likewise.
 320         * mep-dis.c: Likewise.
 321         * mep-ibld.c: Likewise.
 322         * mt-dis.c: Likewise.
 323         * mt-ibld.c: Likewise.
 324         * or1k-dis.c: Likewise.
 325         * or1k-ibld.c: Likewise.
 326         * xc16x-dis.c: Likewise.
 327         * xc16x-ibld.c: Likewise.
 328         * xstormy16-dis.c: Likewise.
 329         * xstormy16-ibld.c: Likewise.
 330
 331 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 332
 333         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 334         (print_insn_): Handle instruction endian.
 335         * bpf-dis.c: Regenerate.
 336         * bpf-desc.c: Regenerate.
 337         * epiphany-dis.c: Likewise.
 338         * epiphany-desc.c: Likewise.
 339         * fr30-dis.c: Likewise.
 340         * fr30-desc.c: Likewise.
 341         * frv-dis.c: Likewise.
 342         * frv-desc.c: Likewise.
 343         * ip2k-dis.c: Likewise.
 344         * ip2k-desc.c: Likewise.
 345         * iq2000-dis.c: Likewise.
 346         * iq2000-desc.c: Likewise.
 347         * lm32-dis.c: Likewise.
 348         * lm32-desc.c: Likewise.
 349         * m32c-dis.c: Likewise.
 350         * m32c-desc.c: Likewise.
 351         * m32r-dis.c: Likewise.
 352         * m32r-desc.c: Likewise.
 353         * mep-dis.c: Likewise.
 354         * mep-desc.c: Likewise.
 355         * mt-dis.c: Likewise.
 356         * mt-desc.c: Likewise.
 357         * or1k-dis.c: Likewise.
 358         * or1k-desc.c: Likewise.
 359         * xc16x-dis.c: Likewise.
 360         * xc16x-desc.c: Likewise.
 361         * xstormy16-dis.c: Likewise.
 362         * xstormy16-desc.c: Likewise.
 363
 364 2020-06-03  Nick Clifton  <nickc@redhat.com>
 365
 366         * po/sr.po: Updated Serbian translation.
 367
 368 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 369
 370         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 371         (riscv_get_priv_spec_class): Likewise.
 372
 373 2020-06-01  Alan Modra  <amodra@gmail.com>
 374
 375         * bpf-desc.c: Regenerate.
 376
 377 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 378             David Faust <david.faust@oracle.com>
 379
 380         * bpf-desc.c: Regenerate.
 381         * bpf-opc.h: Likewise.
 382         * bpf-opc.c: Likewise.
 383         * bpf-dis.c: Likewise.
 384
 385 2020-05-28  Alan Modra  <amodra@gmail.com>
 386
 387         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 388         values.
 389
 390 2020-05-28  Alan Modra  <amodra@gmail.com>
 391
 392         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 393         immediates.
 394         (print_insn_ns32k): Revert last change.
 395
 396 2020-05-28  Nick Clifton  <nickc@redhat.com>
 397
 398         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 399         static.
 400
 401 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 402
 403         Fix extraction of signed constants in nios2 disassembler (again).
 404
 405         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 406         extractions of signed fields.
 407
 408 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 409
 410         * s390-opc.txt: Relocate vector load/store instructions with
 411         additional alignment parameter and change architecture level
 412         constraint from z14 to z13.
 413
 414 2020-05-21  Alan Modra  <amodra@gmail.com>
 415
 416         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 417         * sparc-dis.c: Likewise.
 418         * tic4x-dis.c: Likewise.
 419         * xtensa-dis.c: Likewise.
 420         * bpf-desc.c: Regenerate.
 421         * epiphany-desc.c: Regenerate.
 422         * fr30-desc.c: Regenerate.
 423         * frv-desc.c: Regenerate.
 424         * ip2k-desc.c: Regenerate.
 425         * iq2000-desc.c: Regenerate.
 426         * lm32-desc.c: Regenerate.
 427         * m32c-desc.c: Regenerate.
 428         * m32r-desc.c: Regenerate.
 429         * mep-asm.c: Regenerate.
 430         * mep-desc.c: Regenerate.
 431         * mt-desc.c: Regenerate.
 432         * or1k-desc.c: Regenerate.
 433         * xc16x-desc.c: Regenerate.
 434         * xstormy16-desc.c: Regenerate.
 435
 436 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 437
 438         * riscv-opc.c (riscv_ext_version_table): The table used to store
 439         all information about the supported spec and the corresponding ISA
 440         versions.  Currently, only Zicsr is supported to verify the
 441         correctness of Z sub extension settings.  Others will be supported
 442         in the future patches.
 443         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 444         classes and the corresponding strings.
 445         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 446         spec class by giving a ISA spec string.
 447         * riscv-opc.c (struct priv_spec_t): New structure.
 448         (struct priv_spec_t priv_specs): List for all supported privilege spec
 449         classes and the corresponding strings.
 450         (riscv_get_priv_spec_class): New function.  Get the corresponding
 451         privilege spec class by giving a spec string.
 452         (riscv_get_priv_spec_name): New function.  Get the corresponding
 453         privilege spec string by giving a CSR version class.
 454         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 455         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 456         according to the chosen version.  Build a hash table riscv_csr_hash to
 457         store the valid CSR for the chosen pirv verison.  Dump the direct
 458         CSR address rather than it's name if it is invalid.
 459         (parse_riscv_dis_option_without_args): New function.  Parse the options
 460         without arguments.
 461         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 462         parse the options without arguments first, and then handle the options
 463         with arguments.  Add the new option -Mpriv-spec, which has argument.
 464         * riscv-dis.c (print_riscv_disassembler_options): Add description
 465         about the new OBJDUMP option.
 466
 467 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 468
 469         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 470         WC values on POWER10 sync, dcbf  and wait instructions.
 471         (insert_pl, extract_pl): New functions.
 472         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 473         (LS3): New , 3-bit L for sync.
 474         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 475         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 476         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 477         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 478         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 479         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 480         <wait>: Enable PL operand on POWER10.
 481         <dcbf>: Enable L3OPT operand on POWER10.
 482         <sync>: Enable SC2 operand on POWER10.
 483
 484 2020-05-19  Stafford Horne  <shorne@gmail.com>
 485
 486         PR 25184
 487         * or1k-asm.c: Regenerate.
 488         * or1k-desc.c: Regenerate.
 489         * or1k-desc.h: Regenerate.
 490         * or1k-dis.c: Regenerate.
 491         * or1k-ibld.c: Regenerate.
 492         * or1k-opc.c: Regenerate.
 493         * or1k-opc.h: Regenerate.
 494         * or1k-opinst.c: Regenerate.
 495
 496 2020-05-11  Alan Modra  <amodra@gmail.com>
 497
 498         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 499         xsmaxcqp, xsmincqp.
 500
 501 2020-05-11  Alan Modra  <amodra@gmail.com>
 502
 503         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 504         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 505
 506 2020-05-11  Alan Modra  <amodra@gmail.com>
 507
 508         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 509
 510 2020-05-11  Alan Modra  <amodra@gmail.com>
 511
 512         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 513         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 514
 515 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 516
 517         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 518         mnemonics.
 519
 520 2020-05-11  Alan Modra  <amodra@gmail.com>
 521
 522         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 523         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 524         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 525         (prefix_opcodes): Add xxeval.
 526
 527 2020-05-11  Alan Modra  <amodra@gmail.com>
 528
 529         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 530         xxgenpcvwm, xxgenpcvdm.
 531
 532 2020-05-11  Alan Modra  <amodra@gmail.com>
 533
 534         * ppc-opc.c (MP, VXVAM_MASK): Define.
 535         (VXVAPS_MASK): Use VXVA_MASK.
 536         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 537         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 538         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 539         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 540
 541 2020-05-11  Alan Modra  <amodra@gmail.com>
 542             Peter Bergner  <bergner@linux.ibm.com>
 543
 544         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 545         New functions.
 546         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 547         YMSK2, XA6a, XA6ap, XB6a entries.
 548         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 549         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 550         (PPCVSX4): Define.
 551         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 552         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 553         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 554         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 555         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 556         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 557         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 558         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 559         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 560         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 561         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 562         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 563         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 564         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 565
 566 2020-05-11  Alan Modra  <amodra@gmail.com>
 567
 568         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 569         (insert_xts, extract_xts): New functions.
 570         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 571         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 572         (VXRC_MASK, VXSH_MASK): Define.
 573         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 574         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 575         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 576         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 577         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 578         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 579         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 580
 581 2020-05-11  Alan Modra  <amodra@gmail.com>
 582
 583         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 584         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 585         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 586         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 587         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 588
 589 2020-05-11  Alan Modra  <amodra@gmail.com>
 590
 591         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 592         (XTP, DQXP, DQXP_MASK): Define.
 593         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 594         (prefix_opcodes): Add plxvp and pstxvp.
 595
 596 2020-05-11  Alan Modra  <amodra@gmail.com>
 597
 598         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 599         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 600         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 601
 602 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 603
 604         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 605
 606 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 607
 608         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 609         (L1OPT): Define.
 610         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 611
 612 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 613
 614         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 615
 616 2020-05-11  Alan Modra  <amodra@gmail.com>
 617
 618         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 619
 620 2020-05-11  Alan Modra  <amodra@gmail.com>
 621
 622         * ppc-dis.c (ppc_opts): Add "power10" entry.
 623         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 624         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 625
 626 2020-05-11  Nick Clifton  <nickc@redhat.com>
 627
 628         * po/fr.po: Updated French translation.
 629
 630 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 631
 632         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 633         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 634         (operand_general_constraint_met_p): validate
 635         AARCH64_OPND_UNDEFINED.
 636         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 637         for FLD_imm16_2.
 638         * aarch64-asm-2.c: Regenerated.
 639         * aarch64-dis-2.c: Regenerated.
 640         * aarch64-opc-2.c: Regenerated.
 641
 642 2020-04-29  Nick Clifton  <nickc@redhat.com>
 643
 644         PR 22699
 645         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 646         and SETRC insns.
 647
 648 2020-04-29  Nick Clifton  <nickc@redhat.com>
 649
 650         * po/sv.po: Updated Swedish translation.
 651
 652 2020-04-29  Nick Clifton  <nickc@redhat.com>
 653
 654         PR 22699
 655         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 656         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 657         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 658         IMM0_8U case.
 659
 660 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 661
 662         PR 25848
 663         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 664         cmpi only on m68020up and cpu32.
 665
 666 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 667
 668         * aarch64-asm.c (aarch64_ins_none): New.
 669         * aarch64-asm.h (ins_none): New declaration.
 670         * aarch64-dis.c (aarch64_ext_none): New.
 671         * aarch64-dis.h (ext_none): New declaration.
 672         * aarch64-opc.c (aarch64_print_operand): Update case for
 673         AARCH64_OPND_BARRIER_PSB.
 674         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 675         (AARCH64_OPERANDS): Update inserter/extracter for
 676         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 677         * aarch64-asm-2.c: Regenerated.
 678         * aarch64-dis-2.c: Regenerated.
 679         * aarch64-opc-2.c: Regenerated.
 680
 681 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 682
 683         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 684         (aarch64_feature_ras, RAS): Likewise.
 685         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 686         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 687         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 688         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 689         * aarch64-asm-2.c: Regenerated.
 690         * aarch64-dis-2.c: Regenerated.
 691         * aarch64-opc-2.c: Regenerated.
 692
 693 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 694
 695         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 696         (print_insn_neon): Support disassembly of conditional
 697         instructions.
 698
 699 2020-02-16  David Faust  <david.faust@oracle.com>
 700
 701         * bpf-desc.c: Regenerate.
 702         * bpf-desc.h: Likewise.
 703         * bpf-opc.c: Regenerate.
 704         * bpf-opc.h: Likewise.
 705
 706 2020-04-07  Lili Cui  <lili.cui@intel.com>
 707
 708         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 709         (prefix_table): New instructions (see prefixes above).
 710         (rm_table): Likewise
 711         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 712         CPU_ANY_TSXLDTRK_FLAGS.
 713         (cpu_flags): Add CpuTSXLDTRK.
 714         * i386-opc.h (enum): Add CpuTSXLDTRK.
 715         (i386_cpu_flags): Add cputsxldtrk.
 716         * i386-opc.tbl: Add XSUSPLDTRK insns.
 717         * i386-init.h: Regenerate.
 718         * i386-tbl.h: Likewise.
 719
 720 2020-04-02  Lili Cui  <lili.cui@intel.com>
 721
 722         * i386-dis.c (prefix_table): New instructions serialize.
 723         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 724         CPU_ANY_SERIALIZE_FLAGS.
 725         (cpu_flags): Add CpuSERIALIZE.
 726         * i386-opc.h (enum): Add CpuSERIALIZE.
 727         (i386_cpu_flags): Add cpuserialize.
 728         * i386-opc.tbl: Add SERIALIZE insns.
 729         * i386-init.h: Regenerate.
 730         * i386-tbl.h: Likewise.
 731
 732 2020-03-26  Alan Modra  <amodra@gmail.com>
 733
 734         * disassemble.h (opcodes_assert): Declare.
 735         (OPCODES_ASSERT): Define.
 736         * disassemble.c: Don't include assert.h.  Include opintl.h.
 737         (opcodes_assert): New function.
 738         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 739         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 740         calculate maxlen.  Omit insn decoding when insn length exceeds
 741         maxlen.  Exit from nibble loop when looking for E, before
 742         accessing next data byte.  Move processing of E outside loop.
 743         Replace tests of maxlen in loop with assertions.
 744
 745 2020-03-26  Alan Modra  <amodra@gmail.com>
 746
 747         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 748
 749 2020-03-25  Alan Modra  <amodra@gmail.com>
 750
 751         * z80-dis.c (suffix): Init mybuf.
 752
 753 2020-03-22  Alan Modra  <amodra@gmail.com>
 754
 755         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 756         successflly read from section.
 757
 758 2020-03-22  Alan Modra  <amodra@gmail.com>
 759
 760         * arc-dis.c (find_format): Use ISO C string concatenation rather
 761         than line continuation within a string.  Don't access needs_limm
 762         before testing opcode != NULL.
 763
 764 2020-03-22  Alan Modra  <amodra@gmail.com>
 765
 766         * ns32k-dis.c (print_insn_arg): Update comment.
 767         (print_insn_ns32k): Reduce size of index_offset array, and
 768         initialize, passing -1 to print_insn_arg for args that are not
 769         an index.  Don't exit arg loop early.  Abort on bad arg number.
 770
 771 2020-03-22  Alan Modra  <amodra@gmail.com>
 772
 773         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 774         * s12z-opc.c: Formatting.
 775         (operands_f): Return an int.
 776         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 777         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 778         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 779         (exg_sex_discrim): Likewise.
 780         (create_immediate_operand, create_bitfield_operand),
 781         (create_register_operand_with_size, create_register_all_operand),
 782         (create_register_all16_operand, create_simple_memory_operand),
 783         (create_memory_operand, create_memory_auto_operand): Don't
 784         segfault on malloc failure.
 785         (z_ext24_decode): Return an int status, negative on fail, zero
 786         on success.
 787         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 788         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 789         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 790         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 791         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 792         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 793         (loop_primitive_decode, shift_decode, psh_pul_decode),
 794         (bit_field_decode): Similarly.
 795         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 796         to return value, update callers.
 797         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 798         Don't segfault on NULL operand.
 799         (decode_operation): Return OP_INVALID on first fail.
 800         (decode_s12z): Check all reads, returning -1 on fail.
 801
 802 2020-03-20  Alan Modra  <amodra@gmail.com>
 803
 804         * metag-dis.c (print_insn_metag): Don't ignore status from
 805         read_memory_func.
 806
 807 2020-03-20  Alan Modra  <amodra@gmail.com>
 808
 809         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 810         Initialize parts of buffer not written when handling a possible
 811         2-byte insn at end of section.  Don't attempt decoding of such
 812         an insn by the 4-byte machinery.
 813
 814 2020-03-20  Alan Modra  <amodra@gmail.com>
 815
 816         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 817         partially filled buffer.  Prevent lookup of 4-byte insns when
 818         only VLE 2-byte insns are possible due to section size.  Print
 819         ".word" rather than ".long" for 2-byte leftovers.
 820
 821 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 822
 823         PR 25641
 824         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 825
 826 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-dis.c (X86_64_0D): Rename to ...
 829         (X86_64_0E): ... this.
 830
 831 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 832
 833         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 834         * Makefile.in: Regenerated.
 835
 836 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 839         3-operand pseudos.
 840         * i386-tbl.h: Re-generate.
 841
 842 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 843
 844         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 845         vprot*, vpsha*, and vpshl*.
 846         * i386-tbl.h: Re-generate.
 847
 848 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 851         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 852         * i386-tbl.h: Re-generate.
 853
 854 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 857         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 858         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 859         * i386-tbl.h: Re-generate.
 860
 861 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-gen.c (struct template_arg, struct template_instance,
 864         struct template_param, struct template, templates,
 865         parse_template, expand_templates): New.
 866         (process_i386_opcodes): Various local variables moved to
 867         expand_templates. Call parse_template and expand_templates.
 868         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 869         * i386-tbl.h: Re-generate.
 870
 871 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 872
 873         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 874         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 875         register and memory source templates. Replace VexW= by VexW*
 876         where applicable.
 877         * i386-tbl.h: Re-generate.
 878
 879 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 880
 881         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 882         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 883         * i386-tbl.h: Re-generate.
 884
 885 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 886
 887         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 888         * i386-tbl.h: Re-generate.
 889
 890 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 891
 892         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 893         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 894         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 895         VexW0 on SSE2AVX variants.
 896         (vmovq): Drop NoRex64 from XMM/XMM variants.
 897         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 898         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 899         applicable use VexW0.
 900         * i386-tbl.h: Re-generate.
 901
 902 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 905         * i386-opc.h (Rex64): Delete.
 906         (struct i386_opcode_modifier): Remove rex64 field.
 907         * i386-opc.tbl (crc32): Drop Rex64.
 908         Replace Rex64 with Size64 everywhere else.
 909         * i386-tbl.h: Re-generate.
 910
 911 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-dis.c (OP_E_memory): Exclude recording of used address
 914         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 915         addressed memory operands for MPX insns.
 916
 917 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 920         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 921         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 922         (ptwrite): Split into non-64-bit and 64-bit forms.
 923         * i386-tbl.h: Re-generate.
 924
 925 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 926
 927         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 928         template.
 929         * i386-tbl.h: Re-generate.
 930
 931 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 932
 933         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 934         (prefix_table): Move vmmcall here. Add vmgexit.
 935         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 936         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 937         (cpu_flags): Add CpuSEV_ES entry.
 938         * i386-opc.h (CpuSEV_ES): New.
 939         (union i386_cpu_flags): Add cpusev_es field.
 940         * i386-opc.tbl (vmgexit): New.
 941         * i386-init.h, i386-tbl.h: Re-generate.
 942
 943 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 944
 945         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 946         with MnemonicSize.
 947         * i386-opc.h (IGNORESIZE): New.
 948         (DEFAULTSIZE): Likewise.
 949         (IgnoreSize): Removed.
 950         (DefaultSize): Likewise.
 951         (MnemonicSize): New.
 952         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 953         mnemonicsize.
 954         * i386-opc.tbl (IgnoreSize): New.
 955         (DefaultSize): Likewise.
 956         * i386-tbl.h: Regenerated.
 957
 958 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 959
 960         PR 25627
 961         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 962         instructions.
 963
 964 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 965
 966         PR gas/25622
 967         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 968         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 969         * i386-tbl.h: Regenerated.
 970
 971 2020-02-26  Alan Modra  <amodra@gmail.com>
 972
 973         * aarch64-asm.c: Indent labels correctly.
 974         * aarch64-dis.c: Likewise.
 975         * aarch64-gen.c: Likewise.
 976         * aarch64-opc.c: Likewise.
 977         * alpha-dis.c: Likewise.
 978         * i386-dis.c: Likewise.
 979         * nds32-asm.c: Likewise.
 980         * nfp-dis.c: Likewise.
 981         * visium-dis.c: Likewise.
 982
 983 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 984
 985         * arc-regs.h (int_vector_base): Make it available for all ARC
 986         CPUs.
 987
 988 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 989
 990         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 991         changed.
 992
 993 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 994
 995         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 996         c.mv/c.li if rs1 is zero.
 997
 998 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 999
1000         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1001         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1002         CPU_POPCNT_FLAGS.
1003         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1004         * i386-opc.h (CpuABM): Removed.
1005         (CpuPOPCNT): New.
1006         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1007         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1008         popcnt.  Remove CpuABM from lzcnt.
1009         * i386-init.h: Regenerated.
1010         * i386-tbl.h: Likewise.
1011
1012 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1015         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1016         VexW1 instead of open-coding them.
1017         * i386-tbl.h: Re-generate.
1018
1019 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl (AddrPrefixOpReg): Define.
1022         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1023         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1024         templates. Drop NoRex64.
1025         * i386-tbl.h: Re-generate.
1026
1027 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1028
1029         PR gas/6518
1030         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1031         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1032         into Intel syntax instance (with Unpsecified) and AT&T one
1033         (without).
1034         (vcvtneps2bf16): Likewise, along with folding the two so far
1035         separate ones.
1036         * i386-tbl.h: Re-generate.
1037
1038 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1039
1040         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1041         CPU_ANY_SSE4A_FLAGS.
1042
1043 2020-02-17  Alan Modra  <amodra@gmail.com>
1044
1045         * i386-gen.c (cpu_flag_init): Correct last change.
1046
1047 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1048
1049         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1050         CPU_ANY_SSE4_FLAGS.
1051
1052 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1053
1054         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1055         (movzx): Likewise.
1056
1057 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1058
1059         PR gas/25438
1060         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1061         destination for Cpu64-only variant.
1062         (movzx): Fold patterns.
1063         * i386-tbl.h: Re-generate.
1064
1065 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1066
1067         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1068         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1069         CPU_ANY_SSE4_FLAGS entry.
1070         * i386-init.h: Re-generate.
1071
1072 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1075         with Unspecified, making the present one AT&T syntax only.
1076         * i386-tbl.h: Re-generate.
1077
1078 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1079
1080         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1081         * i386-tbl.h: Re-generate.
1082
1083 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1084
1085         PR gas/24546
1086         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1087         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1088         Amd64 and Intel64 templates.
1089         (call, jmp): Likewise for far indirect variants. Dro
1090         Unspecified.
1091         * i386-tbl.h: Re-generate.
1092
1093 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1094
1095         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1096         * i386-opc.h (ShortForm): Delete.
1097         (struct i386_opcode_modifier): Remove shortform field.
1098         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1099         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1100         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1101         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1102         Drop ShortForm.
1103         * i386-tbl.h: Re-generate.
1104
1105 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1108         fucompi): Drop ShortForm from operand-less templates.
1109         * i386-tbl.h: Re-generate.
1110
1111 2020-02-11  Alan Modra  <amodra@gmail.com>
1112
1113         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1114         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1115         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1116         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1117         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1118
1119 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1120
1121         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1122         (cde_opcodes): Add VCX* instructions.
1123
1124 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1125             Matthew Malcomson  <matthew.malcomson@arm.com>
1126
1127         * arm-dis.c (struct cdeopcode32): New.
1128         (CDE_OPCODE): New macro.
1129         (cde_opcodes): New disassembly table.
1130         (regnames): New option to table.
1131         (cde_coprocs): New global variable.
1132         (print_insn_cde): New
1133         (print_insn_thumb32): Use print_insn_cde.
1134         (parse_arm_disassembler_options): Parse coprocN args.
1135
1136 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1137
1138         PR gas/25516
1139         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1140         with ISA64.
1141         * i386-opc.h (AMD64): Removed.
1142         (Intel64): Likewose.
1143         (AMD64): New.
1144         (INTEL64): Likewise.
1145         (INTEL64ONLY): Likewise.
1146         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1147         * i386-opc.tbl (Amd64): New.
1148         (Intel64): Likewise.
1149         (Intel64Only): Likewise.
1150         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1151         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1152         * i386-tbl.h: Regenerated.
1153
1154 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1155
1156         PR 25469
1157         * z80-dis.c: Add support for GBZ80 opcodes.
1158
1159 2020-02-04  Alan Modra  <amodra@gmail.com>
1160
1161         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1162
1163 2020-02-03  Alan Modra  <amodra@gmail.com>
1164
1165         * m32c-ibld.c: Regenerate.
1166
1167 2020-02-01  Alan Modra  <amodra@gmail.com>
1168
1169         * frv-ibld.c: Regenerate.
1170
1171 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1172
1173         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1174         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1175         (OP_E_memory): Replace xmm_mdq_mode case label by
1176         vex_scalar_w_dq_mode one.
1177         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1178
1179 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1182         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1183         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1184         (intel_operand_size): Drop vex_w_dq_mode case label.
1185
1186 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1187
1188         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1189         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1190
1191 2020-01-30  Alan Modra  <amodra@gmail.com>
1192
1193         * m32c-ibld.c: Regenerate.
1194
1195 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1196
1197         * bpf-opc.c: Regenerate.
1198
1199 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1200
1201         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1202         (dis386): Use them to replace C2/C3 table entries.
1203         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1204         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1205         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1206         * i386-tbl.h: Re-generate.
1207
1208 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1209
1210         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1211         forms.
1212         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1213         DefaultSize.
1214         * i386-tbl.h: Re-generate.
1215
1216 2020-01-30  Alan Modra  <amodra@gmail.com>
1217
1218         * tic4x-dis.c (tic4x_dp): Make unsigned.
1219
1220 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1221             Jan Beulich  <jbeulich@suse.com>
1222
1223         PR binutils/25445
1224         * i386-dis.c (MOVSXD_Fixup): New function.
1225         (movsxd_mode): New enum.
1226         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1227         (intel_operand_size): Handle movsxd_mode.
1228         (OP_E_register): Likewise.
1229         (OP_G): Likewise.
1230         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1231         register on movsxd.  Add movsxd with 16-bit destination register
1232         for AMD64 and Intel64 ISAs.
1233         * i386-tbl.h: Regenerated.
1234
1235 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1236
1237         PR 25403
1238         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1239         * aarch64-asm-2.c: Regenerate
1240         * aarch64-dis-2.c: Likewise.
1241         * aarch64-opc-2.c: Likewise.
1242
1243 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1244
1245         * i386-opc.tbl (sysret): Drop DefaultSize.
1246         * i386-tbl.h: Re-generate.
1247
1248 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1251         Dword.
1252         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1253         * i386-tbl.h: Re-generate.
1254
1255 2020-01-20  Nick Clifton  <nickc@redhat.com>
1256
1257         * po/de.po: Updated German translation.
1258         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1259         * po/uk.po: Updated Ukranian translation.
1260
1261 2020-01-20  Alan Modra  <amodra@gmail.com>
1262
1263         * hppa-dis.c (fput_const): Remove useless cast.
1264
1265 2020-01-20  Alan Modra  <amodra@gmail.com>
1266
1267         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1268
1269 2020-01-18  Nick Clifton  <nickc@redhat.com>
1270
1271         * configure: Regenerate.
1272         * po/opcodes.pot: Regenerate.
1273
1274 2020-01-18  Nick Clifton  <nickc@redhat.com>
1275
1276         Binutils 2.34 branch created.
1277
1278 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1279
1280         * opintl.h: Fix spelling error (seperate).
1281
1282 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1283
1284         * i386-opc.tbl: Add {vex} pseudo prefix.
1285         * i386-tbl.h: Regenerated.
1286
1287 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1288
1289         PR 25376
1290         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1291         (neon_opcodes): Likewise.
1292         (select_arm_features): Make sure we enable MVE bits when selecting
1293         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1294         any architecture.
1295
1296 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1297
1298         * i386-opc.tbl: Drop stale comment from XOP section.
1299
1300 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1301
1302         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1303         (extractps): Add VexWIG to SSE2AVX forms.
1304         * i386-tbl.h: Re-generate.
1305
1306 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1307
1308         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1309         Size64 from and use VexW1 on SSE2AVX forms.
1310         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1311         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1312         * i386-tbl.h: Re-generate.
1313
1314 2020-01-15  Alan Modra  <amodra@gmail.com>
1315
1316         * tic4x-dis.c (tic4x_version): Make unsigned long.
1317         (optab, optab_special, registernames): New file scope vars.
1318         (tic4x_print_register): Set up registernames rather than
1319         malloc'd registertable.
1320         (tic4x_disassemble): Delete optable and optable_special.  Use
1321         optab and optab_special instead.  Throw away old optab,
1322         optab_special and registernames when info->mach changes.
1323
1324 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1325
1326         PR 25377
1327         * z80-dis.c (suffix): Use .db instruction to generate double
1328         prefix.
1329
1330 2020-01-14  Alan Modra  <amodra@gmail.com>
1331
1332         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1333         values to unsigned before shifting.
1334
1335 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1336
1337         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1338         flow instructions.
1339         (print_insn_thumb16, print_insn_thumb32): Likewise.
1340         (print_insn): Initialize the insn info.
1341         * i386-dis.c (print_insn): Initialize the insn info fields, and
1342         detect jumps.
1343
1344 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1345
1346         * arc-opc.c (C_NE): Make it required.
1347
1348 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1349
1350         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1351         reserved register name.
1352
1353 2020-01-13  Alan Modra  <amodra@gmail.com>
1354
1355         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1356         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1357
1358 2020-01-13  Alan Modra  <amodra@gmail.com>
1359
1360         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1361         result of wasm_read_leb128 in a uint64_t and check that bits
1362         are not lost when copying to other locals.  Use uint32_t for
1363         most locals.  Use PRId64 when printing int64_t.
1364
1365 2020-01-13  Alan Modra  <amodra@gmail.com>
1366
1367         * score-dis.c: Formatting.
1368         * score7-dis.c: Formatting.
1369
1370 2020-01-13  Alan Modra  <amodra@gmail.com>
1371
1372         * score-dis.c (print_insn_score48): Use unsigned variables for
1373         unsigned values.  Don't left shift negative values.
1374         (print_insn_score32): Likewise.
1375         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1376
1377 2020-01-13  Alan Modra  <amodra@gmail.com>
1378
1379         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1380
1381 2020-01-13  Alan Modra  <amodra@gmail.com>
1382
1383         * fr30-ibld.c: Regenerate.
1384
1385 2020-01-13  Alan Modra  <amodra@gmail.com>
1386
1387         * xgate-dis.c (print_insn): Don't left shift signed value.
1388         (ripBits): Formatting, use 1u.
1389
1390 2020-01-10  Alan Modra  <amodra@gmail.com>
1391
1392         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1393         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1394
1395 2020-01-10  Alan Modra  <amodra@gmail.com>
1396
1397         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1398         and XRREG value earlier to avoid a shift with negative exponent.
1399         * m10200-dis.c (disassemble): Similarly.
1400
1401 2020-01-09  Nick Clifton  <nickc@redhat.com>
1402
1403         PR 25224
1404         * z80-dis.c (ld_ii_ii): Use correct cast.
1405
1406 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1407
1408         PR 25224
1409         * z80-dis.c (ld_ii_ii): Use character constant when checking
1410         opcode byte value.
1411
1412 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1413
1414         * i386-dis.c (SEP_Fixup): New.
1415         (SEP): Define.
1416         (dis386_twobyte): Use it for sysenter/sysexit.
1417         (enum x86_64_isa): Change amd64 enumerator to value 1.
1418         (OP_J): Compare isa64 against intel64 instead of amd64.
1419         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1420         forms.
1421         * i386-tbl.h: Re-generate.
1422
1423 2020-01-08  Alan Modra  <amodra@gmail.com>
1424
1425         * z8k-dis.c: Include libiberty.h
1426         (instr_data_s): Make max_fetched unsigned.
1427         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1428         Don't exceed byte_info bounds.
1429         (output_instr): Make num_bytes unsigned.
1430         (unpack_instr): Likewise for nibl_count and loop.
1431         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1432         idx unsigned.
1433         * z8k-opc.h: Regenerate.
1434
1435 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1436
1437         * arc-tbl.h (llock): Use 'LLOCK' as class.
1438         (llockd): Likewise.
1439         (scond): Use 'SCOND' as class.
1440         (scondd): Likewise.
1441         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1442         (scondd): Likewise.
1443
1444 2020-01-06  Alan Modra  <amodra@gmail.com>
1445
1446         * m32c-ibld.c: Regenerate.
1447
1448 2020-01-06  Alan Modra  <amodra@gmail.com>
1449
1450         PR 25344
1451         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1452         Peek at next byte to prevent recursion on repeated prefix bytes.
1453         Ensure uninitialised "mybuf" is not accessed.
1454         (print_insn_z80): Don't zero n_fetch and n_used here,..
1455         (print_insn_z80_buf): ..do it here instead.
1456
1457 2020-01-04  Alan Modra  <amodra@gmail.com>
1458
1459         * m32r-ibld.c: Regenerate.
1460
1461 2020-01-04  Alan Modra  <amodra@gmail.com>
1462
1463         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1464
1465 2020-01-04  Alan Modra  <amodra@gmail.com>
1466
1467         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1468
1469 2020-01-04  Alan Modra  <amodra@gmail.com>
1470
1471         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1472
1473 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1474
1475         * aarch64-tbl.h (aarch64_opcode_table): Use
1476         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1477
1478 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1479
1480         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1481         forms of SUDOT and USDOT.
1482
1483 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1484
1485         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1486         uzip{1,2}.
1487         * opcodes/aarch64-dis-2.c: Re-generate.
1488
1489 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1490
1491         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1492         FMMLA encoding.
1493         * opcodes/aarch64-dis-2.c: Re-generate.
1494
1495 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1496
1497         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1498
1499 2020-01-01  Alan Modra  <amodra@gmail.com>
1500
1501         Update year range in copyright notice of all files.
1502
1503 For older changes see ChangeLog-2019
1504 \f
1505 Copyright (C) 2020 Free Software Foundation, Inc.
1506
1507 Copying and distribution of this file, with or without modification,
1508 are permitted in any medium without royalty provided the copyright
1509 notice and this notice are preserved.
1510
1511 Local Variables:
1512 mode: change-log
1513 left-margin: 8
1514 fill-column: 74
1515 version-control: never
1516 End: