opcodes/ChangeLog

   1 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
   2
   3         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
   4         mnemonics.
   5
   6 2020-05-11  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
   9         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
  10         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
  11         (prefix_opcodes): Add xxeval.
  12
  13 2020-05-11  Alan Modra  <amodra@gmail.com>
  14
  15         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
  16         xxgenpcvwm, xxgenpcvdm.
  17
  18 2020-05-11  Alan Modra  <amodra@gmail.com>
  19
  20         * ppc-opc.c (MP, VXVAM_MASK): Define.
  21         (VXVAPS_MASK): Use VXVA_MASK.
  22         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
  23         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
  24         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
  25         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
  26
  27 2020-05-11  Alan Modra  <amodra@gmail.com>
  28             Peter Bergner  <bergner@linux.ibm.com>
  29
  30         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
  31         New functions.
  32         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
  33         YMSK2, XA6a, XA6ap, XB6a entries.
  34         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
  35         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
  36         (PPCVSX4): Define.
  37         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
  38         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
  39         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
  40         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
  41         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
  42         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
  43         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
  44         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
  45         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
  46         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
  47         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
  48         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
  49         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
  50         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
  51
  52 2020-05-11  Alan Modra  <amodra@gmail.com>
  53
  54         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
  55         (insert_xts, extract_xts): New functions.
  56         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
  57         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
  58         (VXRC_MASK, VXSH_MASK): Define.
  59         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
  60         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
  61         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
  62         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
  63         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
  64         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
  65         xxblendvh, xxblendvw, xxblendvd, xxpermx.
  66
  67 2020-05-11  Alan Modra  <amodra@gmail.com>
  68
  69         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
  70         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
  71         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
  72         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
  73         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
  74
  75 2020-05-11  Alan Modra  <amodra@gmail.com>
  76
  77         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
  78         (XTP, DQXP, DQXP_MASK): Define.
  79         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
  80         (prefix_opcodes): Add plxvp and pstxvp.
  81
  82 2020-05-11  Alan Modra  <amodra@gmail.com>
  83
  84         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
  85         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
  86         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
  87
  88 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  89
  90         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
  91
  92 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  93
  94         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
  95         (L1OPT): Define.
  96         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
  97
  98 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  99
 100         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 101
 102 2020-05-11  Alan Modra  <amodra@gmail.com>
 103
 104         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 105
 106 2020-05-11  Alan Modra  <amodra@gmail.com>
 107
 108         * ppc-dis.c (ppc_opts): Add "power10" entry.
 109         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 110         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 111
 112 2020-05-11  Nick Clifton  <nickc@redhat.com>
 113
 114         * po/fr.po: Updated French translation.
 115
 116 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 117
 118         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 119         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 120         (operand_general_constraint_met_p): validate
 121         AARCH64_OPND_UNDEFINED.
 122         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 123         for FLD_imm16_2.
 124         * aarch64-asm-2.c: Regenerated.
 125         * aarch64-dis-2.c: Regenerated.
 126         * aarch64-opc-2.c: Regenerated.
 127
 128 2020-04-29  Nick Clifton  <nickc@redhat.com>
 129
 130         PR 22699
 131         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 132         and SETRC insns.
 133
 134 2020-04-29  Nick Clifton  <nickc@redhat.com>
 135
 136         * po/sv.po: Updated Swedish translation.
 137
 138 2020-04-29  Nick Clifton  <nickc@redhat.com>
 139
 140         PR 22699
 141         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 142         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 143         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 144         IMM0_8U case.
 145
 146 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 147
 148         PR 25848
 149         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 150         cmpi only on m68020up and cpu32.
 151
 152 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 153
 154         * aarch64-asm.c (aarch64_ins_none): New.
 155         * aarch64-asm.h (ins_none): New declaration.
 156         * aarch64-dis.c (aarch64_ext_none): New.
 157         * aarch64-dis.h (ext_none): New declaration.
 158         * aarch64-opc.c (aarch64_print_operand): Update case for
 159         AARCH64_OPND_BARRIER_PSB.
 160         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 161         (AARCH64_OPERANDS): Update inserter/extracter for
 162         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 163         * aarch64-asm-2.c: Regenerated.
 164         * aarch64-dis-2.c: Regenerated.
 165         * aarch64-opc-2.c: Regenerated.
 166
 167 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 168
 169         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 170         (aarch64_feature_ras, RAS): Likewise.
 171         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 172         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 173         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 174         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 175         * aarch64-asm-2.c: Regenerated.
 176         * aarch64-dis-2.c: Regenerated.
 177         * aarch64-opc-2.c: Regenerated.
 178
 179 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 180
 181         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 182         (print_insn_neon): Support disassembly of conditional
 183         instructions.
 184
 185 2020-02-16  David Faust  <david.faust@oracle.com>
 186
 187         * bpf-desc.c: Regenerate.
 188         * bpf-desc.h: Likewise.
 189         * bpf-opc.c: Regenerate.
 190         * bpf-opc.h: Likewise.
 191
 192 2020-04-07  Lili Cui  <lili.cui@intel.com>
 193
 194         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 195         (prefix_table): New instructions (see prefixes above).
 196         (rm_table): Likewise
 197         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 198         CPU_ANY_TSXLDTRK_FLAGS.
 199         (cpu_flags): Add CpuTSXLDTRK.
 200         * i386-opc.h (enum): Add CpuTSXLDTRK.
 201         (i386_cpu_flags): Add cputsxldtrk.
 202         * i386-opc.tbl: Add XSUSPLDTRK insns.
 203         * i386-init.h: Regenerate.
 204         * i386-tbl.h: Likewise.
 205
 206 2020-04-02  Lili Cui  <lili.cui@intel.com>
 207
 208         * i386-dis.c (prefix_table): New instructions serialize.
 209         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 210         CPU_ANY_SERIALIZE_FLAGS.
 211         (cpu_flags): Add CpuSERIALIZE.
 212         * i386-opc.h (enum): Add CpuSERIALIZE.
 213         (i386_cpu_flags): Add cpuserialize.
 214         * i386-opc.tbl: Add SERIALIZE insns.
 215         * i386-init.h: Regenerate.
 216         * i386-tbl.h: Likewise.
 217
 218 2020-03-26  Alan Modra  <amodra@gmail.com>
 219
 220         * disassemble.h (opcodes_assert): Declare.
 221         (OPCODES_ASSERT): Define.
 222         * disassemble.c: Don't include assert.h.  Include opintl.h.
 223         (opcodes_assert): New function.
 224         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 225         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 226         calculate maxlen.  Omit insn decoding when insn length exceeds
 227         maxlen.  Exit from nibble loop when looking for E, before
 228         accessing next data byte.  Move processing of E outside loop.
 229         Replace tests of maxlen in loop with assertions.
 230
 231 2020-03-26  Alan Modra  <amodra@gmail.com>
 232
 233         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 234
 235 2020-03-25  Alan Modra  <amodra@gmail.com>
 236
 237         * z80-dis.c (suffix): Init mybuf.
 238
 239 2020-03-22  Alan Modra  <amodra@gmail.com>
 240
 241         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 242         successflly read from section.
 243
 244 2020-03-22  Alan Modra  <amodra@gmail.com>
 245
 246         * arc-dis.c (find_format): Use ISO C string concatenation rather
 247         than line continuation within a string.  Don't access needs_limm
 248         before testing opcode != NULL.
 249
 250 2020-03-22  Alan Modra  <amodra@gmail.com>
 251
 252         * ns32k-dis.c (print_insn_arg): Update comment.
 253         (print_insn_ns32k): Reduce size of index_offset array, and
 254         initialize, passing -1 to print_insn_arg for args that are not
 255         an index.  Don't exit arg loop early.  Abort on bad arg number.
 256
 257 2020-03-22  Alan Modra  <amodra@gmail.com>
 258
 259         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 260         * s12z-opc.c: Formatting.
 261         (operands_f): Return an int.
 262         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 263         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 264         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 265         (exg_sex_discrim): Likewise.
 266         (create_immediate_operand, create_bitfield_operand),
 267         (create_register_operand_with_size, create_register_all_operand),
 268         (create_register_all16_operand, create_simple_memory_operand),
 269         (create_memory_operand, create_memory_auto_operand): Don't
 270         segfault on malloc failure.
 271         (z_ext24_decode): Return an int status, negative on fail, zero
 272         on success.
 273         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 274         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 275         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 276         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 277         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 278         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 279         (loop_primitive_decode, shift_decode, psh_pul_decode),
 280         (bit_field_decode): Similarly.
 281         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 282         to return value, update callers.
 283         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 284         Don't segfault on NULL operand.
 285         (decode_operation): Return OP_INVALID on first fail.
 286         (decode_s12z): Check all reads, returning -1 on fail.
 287
 288 2020-03-20  Alan Modra  <amodra@gmail.com>
 289
 290         * metag-dis.c (print_insn_metag): Don't ignore status from
 291         read_memory_func.
 292
 293 2020-03-20  Alan Modra  <amodra@gmail.com>
 294
 295         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 296         Initialize parts of buffer not written when handling a possible
 297         2-byte insn at end of section.  Don't attempt decoding of such
 298         an insn by the 4-byte machinery.
 299
 300 2020-03-20  Alan Modra  <amodra@gmail.com>
 301
 302         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 303         partially filled buffer.  Prevent lookup of 4-byte insns when
 304         only VLE 2-byte insns are possible due to section size.  Print
 305         ".word" rather than ".long" for 2-byte leftovers.
 306
 307 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 308
 309         PR 25641
 310         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 311
 312 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-dis.c (X86_64_0D): Rename to ...
 315         (X86_64_0E): ... this.
 316
 317 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 320         * Makefile.in: Regenerated.
 321
 322 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 325         3-operand pseudos.
 326         * i386-tbl.h: Re-generate.
 327
 328 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 329
 330         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 331         vprot*, vpsha*, and vpshl*.
 332         * i386-tbl.h: Re-generate.
 333
 334 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 337         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 338         * i386-tbl.h: Re-generate.
 339
 340 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 341
 342         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 343         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 344         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 345         * i386-tbl.h: Re-generate.
 346
 347 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-gen.c (struct template_arg, struct template_instance,
 350         struct template_param, struct template, templates,
 351         parse_template, expand_templates): New.
 352         (process_i386_opcodes): Various local variables moved to
 353         expand_templates. Call parse_template and expand_templates.
 354         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 355         * i386-tbl.h: Re-generate.
 356
 357 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 360         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 361         register and memory source templates. Replace VexW= by VexW*
 362         where applicable.
 363         * i386-tbl.h: Re-generate.
 364
 365 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 368         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 369         * i386-tbl.h: Re-generate.
 370
 371 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 374         * i386-tbl.h: Re-generate.
 375
 376 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 379         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 380         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 381         VexW0 on SSE2AVX variants.
 382         (vmovq): Drop NoRex64 from XMM/XMM variants.
 383         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 384         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 385         applicable use VexW0.
 386         * i386-tbl.h: Re-generate.
 387
 388 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 391         * i386-opc.h (Rex64): Delete.
 392         (struct i386_opcode_modifier): Remove rex64 field.
 393         * i386-opc.tbl (crc32): Drop Rex64.
 394         Replace Rex64 with Size64 everywhere else.
 395         * i386-tbl.h: Re-generate.
 396
 397 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-dis.c (OP_E_memory): Exclude recording of used address
 400         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 401         addressed memory operands for MPX insns.
 402
 403 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 404
 405         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 406         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 407         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 408         (ptwrite): Split into non-64-bit and 64-bit forms.
 409         * i386-tbl.h: Re-generate.
 410
 411 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 412
 413         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 414         template.
 415         * i386-tbl.h: Re-generate.
 416
 417 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 420         (prefix_table): Move vmmcall here. Add vmgexit.
 421         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 422         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 423         (cpu_flags): Add CpuSEV_ES entry.
 424         * i386-opc.h (CpuSEV_ES): New.
 425         (union i386_cpu_flags): Add cpusev_es field.
 426         * i386-opc.tbl (vmgexit): New.
 427         * i386-init.h, i386-tbl.h: Re-generate.
 428
 429 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 432         with MnemonicSize.
 433         * i386-opc.h (IGNORESIZE): New.
 434         (DEFAULTSIZE): Likewise.
 435         (IgnoreSize): Removed.
 436         (DefaultSize): Likewise.
 437         (MnemonicSize): New.
 438         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 439         mnemonicsize.
 440         * i386-opc.tbl (IgnoreSize): New.
 441         (DefaultSize): Likewise.
 442         * i386-tbl.h: Regenerated.
 443
 444 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 445
 446         PR 25627
 447         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 448         instructions.
 449
 450 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         PR gas/25622
 453         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 454         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 455         * i386-tbl.h: Regenerated.
 456
 457 2020-02-26  Alan Modra  <amodra@gmail.com>
 458
 459         * aarch64-asm.c: Indent labels correctly.
 460         * aarch64-dis.c: Likewise.
 461         * aarch64-gen.c: Likewise.
 462         * aarch64-opc.c: Likewise.
 463         * alpha-dis.c: Likewise.
 464         * i386-dis.c: Likewise.
 465         * nds32-asm.c: Likewise.
 466         * nfp-dis.c: Likewise.
 467         * visium-dis.c: Likewise.
 468
 469 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 470
 471         * arc-regs.h (int_vector_base): Make it available for all ARC
 472         CPUs.
 473
 474 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 475
 476         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 477         changed.
 478
 479 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 480
 481         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 482         c.mv/c.li if rs1 is zero.
 483
 484 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 485
 486         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 487         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 488         CPU_POPCNT_FLAGS.
 489         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 490         * i386-opc.h (CpuABM): Removed.
 491         (CpuPOPCNT): New.
 492         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 493         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 494         popcnt.  Remove CpuABM from lzcnt.
 495         * i386-init.h: Regenerated.
 496         * i386-tbl.h: Likewise.
 497
 498 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 501         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 502         VexW1 instead of open-coding them.
 503         * i386-tbl.h: Re-generate.
 504
 505 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-opc.tbl (AddrPrefixOpReg): Define.
 508         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 509         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 510         templates. Drop NoRex64.
 511         * i386-tbl.h: Re-generate.
 512
 513 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 514
 515         PR gas/6518
 516         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 517         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 518         into Intel syntax instance (with Unpsecified) and AT&T one
 519         (without).
 520         (vcvtneps2bf16): Likewise, along with folding the two so far
 521         separate ones.
 522         * i386-tbl.h: Re-generate.
 523
 524 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 525
 526         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 527         CPU_ANY_SSE4A_FLAGS.
 528
 529 2020-02-17  Alan Modra  <amodra@gmail.com>
 530
 531         * i386-gen.c (cpu_flag_init): Correct last change.
 532
 533 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 534
 535         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 536         CPU_ANY_SSE4_FLAGS.
 537
 538 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 541         (movzx): Likewise.
 542
 543 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 544
 545         PR gas/25438
 546         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 547         destination for Cpu64-only variant.
 548         (movzx): Fold patterns.
 549         * i386-tbl.h: Re-generate.
 550
 551 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 554         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 555         CPU_ANY_SSE4_FLAGS entry.
 556         * i386-init.h: Re-generate.
 557
 558 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 561         with Unspecified, making the present one AT&T syntax only.
 562         * i386-tbl.h: Re-generate.
 563
 564 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 565
 566         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 567         * i386-tbl.h: Re-generate.
 568
 569 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 570
 571         PR gas/24546
 572         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 573         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 574         Amd64 and Intel64 templates.
 575         (call, jmp): Likewise for far indirect variants. Dro
 576         Unspecified.
 577         * i386-tbl.h: Re-generate.
 578
 579 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 582         * i386-opc.h (ShortForm): Delete.
 583         (struct i386_opcode_modifier): Remove shortform field.
 584         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 585         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 586         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 587         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 588         Drop ShortForm.
 589         * i386-tbl.h: Re-generate.
 590
 591 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 594         fucompi): Drop ShortForm from operand-less templates.
 595         * i386-tbl.h: Re-generate.
 596
 597 2020-02-11  Alan Modra  <amodra@gmail.com>
 598
 599         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 600         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 601         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 602         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 603         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 604
 605 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 606
 607         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 608         (cde_opcodes): Add VCX* instructions.
 609
 610 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 611             Matthew Malcomson  <matthew.malcomson@arm.com>
 612
 613         * arm-dis.c (struct cdeopcode32): New.
 614         (CDE_OPCODE): New macro.
 615         (cde_opcodes): New disassembly table.
 616         (regnames): New option to table.
 617         (cde_coprocs): New global variable.
 618         (print_insn_cde): New
 619         (print_insn_thumb32): Use print_insn_cde.
 620         (parse_arm_disassembler_options): Parse coprocN args.
 621
 622 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 623
 624         PR gas/25516
 625         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 626         with ISA64.
 627         * i386-opc.h (AMD64): Removed.
 628         (Intel64): Likewose.
 629         (AMD64): New.
 630         (INTEL64): Likewise.
 631         (INTEL64ONLY): Likewise.
 632         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 633         * i386-opc.tbl (Amd64): New.
 634         (Intel64): Likewise.
 635         (Intel64Only): Likewise.
 636         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 637         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 638         * i386-tbl.h: Regenerated.
 639
 640 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 641
 642         PR 25469
 643         * z80-dis.c: Add support for GBZ80 opcodes.
 644
 645 2020-02-04  Alan Modra  <amodra@gmail.com>
 646
 647         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 648
 649 2020-02-03  Alan Modra  <amodra@gmail.com>
 650
 651         * m32c-ibld.c: Regenerate.
 652
 653 2020-02-01  Alan Modra  <amodra@gmail.com>
 654
 655         * frv-ibld.c: Regenerate.
 656
 657 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 660         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 661         (OP_E_memory): Replace xmm_mdq_mode case label by
 662         vex_scalar_w_dq_mode one.
 663         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 664
 665 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 668         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 669         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 670         (intel_operand_size): Drop vex_w_dq_mode case label.
 671
 672 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 673
 674         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 675         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 676
 677 2020-01-30  Alan Modra  <amodra@gmail.com>
 678
 679         * m32c-ibld.c: Regenerate.
 680
 681 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 682
 683         * bpf-opc.c: Regenerate.
 684
 685 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 688         (dis386): Use them to replace C2/C3 table entries.
 689         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 690         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 691         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 692         * i386-tbl.h: Re-generate.
 693
 694 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 695
 696         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 697         forms.
 698         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 699         DefaultSize.
 700         * i386-tbl.h: Re-generate.
 701
 702 2020-01-30  Alan Modra  <amodra@gmail.com>
 703
 704         * tic4x-dis.c (tic4x_dp): Make unsigned.
 705
 706 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 707             Jan Beulich  <jbeulich@suse.com>
 708
 709         PR binutils/25445
 710         * i386-dis.c (MOVSXD_Fixup): New function.
 711         (movsxd_mode): New enum.
 712         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 713         (intel_operand_size): Handle movsxd_mode.
 714         (OP_E_register): Likewise.
 715         (OP_G): Likewise.
 716         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 717         register on movsxd.  Add movsxd with 16-bit destination register
 718         for AMD64 and Intel64 ISAs.
 719         * i386-tbl.h: Regenerated.
 720
 721 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 722
 723         PR 25403
 724         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 725         * aarch64-asm-2.c: Regenerate
 726         * aarch64-dis-2.c: Likewise.
 727         * aarch64-opc-2.c: Likewise.
 728
 729 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 730
 731         * i386-opc.tbl (sysret): Drop DefaultSize.
 732         * i386-tbl.h: Re-generate.
 733
 734 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 737         Dword.
 738         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 739         * i386-tbl.h: Re-generate.
 740
 741 2020-01-20  Nick Clifton  <nickc@redhat.com>
 742
 743         * po/de.po: Updated German translation.
 744         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 745         * po/uk.po: Updated Ukranian translation.
 746
 747 2020-01-20  Alan Modra  <amodra@gmail.com>
 748
 749         * hppa-dis.c (fput_const): Remove useless cast.
 750
 751 2020-01-20  Alan Modra  <amodra@gmail.com>
 752
 753         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 754
 755 2020-01-18  Nick Clifton  <nickc@redhat.com>
 756
 757         * configure: Regenerate.
 758         * po/opcodes.pot: Regenerate.
 759
 760 2020-01-18  Nick Clifton  <nickc@redhat.com>
 761
 762         Binutils 2.34 branch created.
 763
 764 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 765
 766         * opintl.h: Fix spelling error (seperate).
 767
 768 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-opc.tbl: Add {vex} pseudo prefix.
 771         * i386-tbl.h: Regenerated.
 772
 773 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 774
 775         PR 25376
 776         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 777         (neon_opcodes): Likewise.
 778         (select_arm_features): Make sure we enable MVE bits when selecting
 779         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 780         any architecture.
 781
 782 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 783
 784         * i386-opc.tbl: Drop stale comment from XOP section.
 785
 786 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 789         (extractps): Add VexWIG to SSE2AVX forms.
 790         * i386-tbl.h: Re-generate.
 791
 792 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 793
 794         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 795         Size64 from and use VexW1 on SSE2AVX forms.
 796         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 797         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 798         * i386-tbl.h: Re-generate.
 799
 800 2020-01-15  Alan Modra  <amodra@gmail.com>
 801
 802         * tic4x-dis.c (tic4x_version): Make unsigned long.
 803         (optab, optab_special, registernames): New file scope vars.
 804         (tic4x_print_register): Set up registernames rather than
 805         malloc'd registertable.
 806         (tic4x_disassemble): Delete optable and optable_special.  Use
 807         optab and optab_special instead.  Throw away old optab,
 808         optab_special and registernames when info->mach changes.
 809
 810 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 811
 812         PR 25377
 813         * z80-dis.c (suffix): Use .db instruction to generate double
 814         prefix.
 815
 816 2020-01-14  Alan Modra  <amodra@gmail.com>
 817
 818         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 819         values to unsigned before shifting.
 820
 821 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 822
 823         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 824         flow instructions.
 825         (print_insn_thumb16, print_insn_thumb32): Likewise.
 826         (print_insn): Initialize the insn info.
 827         * i386-dis.c (print_insn): Initialize the insn info fields, and
 828         detect jumps.
 829
 830 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 831
 832         * arc-opc.c (C_NE): Make it required.
 833
 834 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 835
 836         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 837         reserved register name.
 838
 839 2020-01-13  Alan Modra  <amodra@gmail.com>
 840
 841         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 842         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 843
 844 2020-01-13  Alan Modra  <amodra@gmail.com>
 845
 846         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 847         result of wasm_read_leb128 in a uint64_t and check that bits
 848         are not lost when copying to other locals.  Use uint32_t for
 849         most locals.  Use PRId64 when printing int64_t.
 850
 851 2020-01-13  Alan Modra  <amodra@gmail.com>
 852
 853         * score-dis.c: Formatting.
 854         * score7-dis.c: Formatting.
 855
 856 2020-01-13  Alan Modra  <amodra@gmail.com>
 857
 858         * score-dis.c (print_insn_score48): Use unsigned variables for
 859         unsigned values.  Don't left shift negative values.
 860         (print_insn_score32): Likewise.
 861         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 862
 863 2020-01-13  Alan Modra  <amodra@gmail.com>
 864
 865         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 866
 867 2020-01-13  Alan Modra  <amodra@gmail.com>
 868
 869         * fr30-ibld.c: Regenerate.
 870
 871 2020-01-13  Alan Modra  <amodra@gmail.com>
 872
 873         * xgate-dis.c (print_insn): Don't left shift signed value.
 874         (ripBits): Formatting, use 1u.
 875
 876 2020-01-10  Alan Modra  <amodra@gmail.com>
 877
 878         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 879         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 880
 881 2020-01-10  Alan Modra  <amodra@gmail.com>
 882
 883         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 884         and XRREG value earlier to avoid a shift with negative exponent.
 885         * m10200-dis.c (disassemble): Similarly.
 886
 887 2020-01-09  Nick Clifton  <nickc@redhat.com>
 888
 889         PR 25224
 890         * z80-dis.c (ld_ii_ii): Use correct cast.
 891
 892 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 893
 894         PR 25224
 895         * z80-dis.c (ld_ii_ii): Use character constant when checking
 896         opcode byte value.
 897
 898 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-dis.c (SEP_Fixup): New.
 901         (SEP): Define.
 902         (dis386_twobyte): Use it for sysenter/sysexit.
 903         (enum x86_64_isa): Change amd64 enumerator to value 1.
 904         (OP_J): Compare isa64 against intel64 instead of amd64.
 905         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 906         forms.
 907         * i386-tbl.h: Re-generate.
 908
 909 2020-01-08  Alan Modra  <amodra@gmail.com>
 910
 911         * z8k-dis.c: Include libiberty.h
 912         (instr_data_s): Make max_fetched unsigned.
 913         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 914         Don't exceed byte_info bounds.
 915         (output_instr): Make num_bytes unsigned.
 916         (unpack_instr): Likewise for nibl_count and loop.
 917         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 918         idx unsigned.
 919         * z8k-opc.h: Regenerate.
 920
 921 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 922
 923         * arc-tbl.h (llock): Use 'LLOCK' as class.
 924         (llockd): Likewise.
 925         (scond): Use 'SCOND' as class.
 926         (scondd): Likewise.
 927         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 928         (scondd): Likewise.
 929
 930 2020-01-06  Alan Modra  <amodra@gmail.com>
 931
 932         * m32c-ibld.c: Regenerate.
 933
 934 2020-01-06  Alan Modra  <amodra@gmail.com>
 935
 936         PR 25344
 937         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 938         Peek at next byte to prevent recursion on repeated prefix bytes.
 939         Ensure uninitialised "mybuf" is not accessed.
 940         (print_insn_z80): Don't zero n_fetch and n_used here,..
 941         (print_insn_z80_buf): ..do it here instead.
 942
 943 2020-01-04  Alan Modra  <amodra@gmail.com>
 944
 945         * m32r-ibld.c: Regenerate.
 946
 947 2020-01-04  Alan Modra  <amodra@gmail.com>
 948
 949         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 950
 951 2020-01-04  Alan Modra  <amodra@gmail.com>
 952
 953         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 954
 955 2020-01-04  Alan Modra  <amodra@gmail.com>
 956
 957         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 958
 959 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 960
 961         * aarch64-tbl.h (aarch64_opcode_table): Use
 962         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 963
 964 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 965
 966         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 967         forms of SUDOT and USDOT.
 968
 969 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 970
 971         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 972         uzip{1,2}.
 973         * opcodes/aarch64-dis-2.c: Re-generate.
 974
 975 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 976
 977         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 978         FMMLA encoding.
 979         * opcodes/aarch64-dis-2.c: Re-generate.
 980
 981 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 982
 983         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 984
 985 2020-01-01  Alan Modra  <amodra@gmail.com>
 986
 987         Update year range in copyright notice of all files.
 988
 989 For older changes see ChangeLog-2019
 990 \f
 991 Copyright (C) 2020 Free Software Foundation, Inc.
 992
 993 Copying and distribution of this file, with or without modification,
 994 are permitted in any medium without royalty provided the copyright
 995 notice and this notice are preserved.
 996
 997 Local Variables:
 998 mode: change-log
 999 left-margin: 8
1000 fill-column: 74
1001 version-control: never
1002 End: