opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2022 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm6_2,
  71   FLD_imm4,
  72   FLD_imm4_2,
  73   FLD_imm4_3,
  74   FLD_imm4_5,
  75   FLD_imm5,
  76   FLD_imm7,
  77   FLD_imm8,
  78   FLD_imm9,
  79   FLD_imm12,
  80   FLD_imm14,
  81   FLD_imm16,
  82   FLD_imm16_2,
  83   FLD_imm26,
  84   FLD_imms,
  85   FLD_immr,
  86   FLD_immb,
  87   FLD_immh,
  88   FLD_S_imm10,
  89   FLD_N,
  90   FLD_index,
  91   FLD_index2,
  92   FLD_sf,
  93   FLD_lse_sz,
  94   FLD_H,
  95   FLD_L,
  96   FLD_M,
  97   FLD_b5,
  98   FLD_b40,
  99   FLD_scale,
 100   FLD_SVE_M_4,
 101   FLD_SVE_M_14,
 102   FLD_SVE_M_16,
 103   FLD_SVE_N,
 104   FLD_SVE_Pd,
 105   FLD_SVE_Pg3,
 106   FLD_SVE_Pg4_5,
 107   FLD_SVE_Pg4_10,
 108   FLD_SVE_Pg4_16,
 109   FLD_SVE_Pm,
 110   FLD_SVE_Pn,
 111   FLD_SVE_Pt,
 112   FLD_SVE_Rm,
 113   FLD_SVE_Rn,
 114   FLD_SVE_Vd,
 115   FLD_SVE_Vm,
 116   FLD_SVE_Vn,
 117   FLD_SVE_Za_5,
 118   FLD_SVE_Za_16,
 119   FLD_SVE_Zd,
 120   FLD_SVE_Zm_5,
 121   FLD_SVE_Zm_16,
 122   FLD_SVE_Zn,
 123   FLD_SVE_Zt,
 124   FLD_SVE_i1,
 125   FLD_SVE_i3h,
 126   FLD_SVE_i3l,
 127   FLD_SVE_i3h2,
 128   FLD_SVE_i2h,
 129   FLD_SVE_imm3,
 130   FLD_SVE_imm4,
 131   FLD_SVE_imm5,
 132   FLD_SVE_imm5b,
 133   FLD_SVE_imm6,
 134   FLD_SVE_imm7,
 135   FLD_SVE_imm8,
 136   FLD_SVE_imm9,
 137   FLD_SVE_immr,
 138   FLD_SVE_imms,
 139   FLD_SVE_msz,
 140   FLD_SVE_pattern,
 141   FLD_SVE_prfop,
 142   FLD_SVE_rot1,
 143   FLD_SVE_rot2,
 144   FLD_SVE_rot3,
 145   FLD_SVE_sz,
 146   FLD_SVE_size,
 147   FLD_SVE_sz2,
 148   FLD_SVE_tsz,
 149   FLD_SVE_tszh,
 150   FLD_SVE_tszl_8,
 151   FLD_SVE_tszl_19,
 152   FLD_SVE_xs_14,
 153   FLD_SVE_xs_22,
 154   FLD_SME_ZAda_2b,
 155   FLD_SME_ZAda_3b,
 156   FLD_SME_size_10,
 157   FLD_SME_Q,
 158   FLD_SME_V,
 159   FLD_SME_Rv,
 160   FLD_SME_Pm,
 161   FLD_SME_zero_mask,
 162   FLD_SME_Rm,
 163   FLD_SME_i1,
 164   FLD_SME_tszh,
 165   FLD_SME_tszl,
 166   FLD_rotate1,
 167   FLD_rotate2,
 168   FLD_rotate3,
 169   FLD_SM3_imm2,
 170   FLD_sz,
 171   FLD_CRm_dsb_nxs,
 172   FLD_CSSC_imm8
 173 };
 174
 175 /* Field description.  */
 176 struct aarch64_field
 177 {
 178   int lsb;
 179   int width;
 180 };
 181
 182 typedef struct aarch64_field aarch64_field;
 183
 184 extern const aarch64_field fields[];
 185 \f
 186 /* Operand description.  */
 187
 188 struct aarch64_operand
 189 {
 190   enum aarch64_operand_class op_class;
 191
 192   /* Name of the operand code; used mainly for the purpose of internal
 193      debugging.  */
 194   const char *name;
 195
 196   unsigned int flags;
 197
 198   /* The associated instruction bit-fields; no operand has more than 4
 199      bit-fields */
 200   enum aarch64_field_kind fields[5];
 201
 202   /* Brief description */
 203   const char *desc;
 204 };
 205
 206 typedef struct aarch64_operand aarch64_operand;
 207
 208 extern const aarch64_operand aarch64_operands[];
 209
 210 enum err_type
 211 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 212                     bool, aarch64_operand_error *, aarch64_instr_sequence*);
 213
 214 /* Operand flags.  */
 215
 216 #define OPD_F_HAS_INSERTER      0x00000001
 217 #define OPD_F_HAS_EXTRACTOR     0x00000002
 218 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 219 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 220                                                    value by 2 to get the value
 221                                                    of an immediate operand.  */
 222 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 223 #define OPD_F_OD_MASK           0x000000e0      /* Operand-dependent data.  */
 224 #define OPD_F_OD_LSB            5
 225 #define OPD_F_NO_ZR             0x00000100      /* ZR index not allowed.  */
 226 #define OPD_F_SHIFT_BY_4        0x00000200      /* Need to left shift the field
 227                                                    value by 4 to get the value
 228                                                    of an immediate operand.  */
 229
 230
 231 /* Register flags.  */
 232
 233 #undef F_DEPRECATED
 234 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 235
 236 #undef F_ARCHEXT
 237 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 238
 239 #undef F_HASXT
 240 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 241                                      operand.  */
 242
 243 #undef F_REG_READ
 244 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 245                                      out of.  */
 246
 247 #undef F_REG_WRITE
 248 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 249                                      read from.  */
 250
 251 #undef F_REG_IN_CRM
 252 #define F_REG_IN_CRM    (1 << 5)  /* Register extra encoding in CRm.  */
 253
 254 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
 255    Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
 256    In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
 257    macros to encode and decode CRm encoding.
 258 */
 259 #define PSTATE_ENCODE_CRM(val) (val << 6)
 260 #define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f)
 261
 262 #undef F_IMM_IN_CRM
 263 #define F_IMM_IN_CRM    (1 << 10)  /* Immediate extra encoding in CRm.  */
 264
 265 /* Also CRm may contain, in addition to <pstatefield> immediate.
 266    E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode
 267    immediate mask.
 268 */
 269 #define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11)
 270 #define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f)
 271
 272 /* Helper macro to ENCODE CRm and its immediate.  */
 273 #define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \
 274         (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
 275          | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
 276
 277 /* Bits [15, 18] contain the maximum value for an immediate MSR.  */
 278 #define F_REG_MAX_VALUE(X) ((X) << 15)
 279 #define F_GET_REG_MAX_VALUE(X) (((X) >> 15) & 0x0f)
 280
 281 /* HINT operand flags.  */
 282 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 283
 284 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 285 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 286 #define HINT_FLAG(val) (val >> 8)
 287 #define HINT_VAL(val) (val & 0xff)
 288
 289 static inline bool
 290 operand_has_inserter (const aarch64_operand *operand)
 291 {
 292   return (operand->flags & OPD_F_HAS_INSERTER) != 0;
 293 }
 294
 295 static inline bool
 296 operand_has_extractor (const aarch64_operand *operand)
 297 {
 298   return (operand->flags & OPD_F_HAS_EXTRACTOR) != 0;
 299 }
 300
 301 static inline bool
 302 operand_need_sign_extension (const aarch64_operand *operand)
 303 {
 304   return (operand->flags & OPD_F_SEXT) != 0;
 305 }
 306
 307 static inline bool
 308 operand_need_shift_by_two (const aarch64_operand *operand)
 309 {
 310   return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
 311 }
 312
 313 static inline bool
 314 operand_need_shift_by_four (const aarch64_operand *operand)
 315 {
 316   return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
 317 }
 318
 319 static inline bool
 320 operand_maybe_stack_pointer (const aarch64_operand *operand)
 321 {
 322   return (operand->flags & OPD_F_MAYBE_SP) != 0;
 323 }
 324
 325 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 326 static inline unsigned int
 327 get_operand_specific_data (const aarch64_operand *operand)
 328 {
 329   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 330 }
 331
 332 /* Return the width of field number N of operand *OPERAND.  */
 333 static inline unsigned
 334 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 335 {
 336   assert (operand->fields[n] != FLD_NIL);
 337   return fields[operand->fields[n]].width;
 338 }
 339
 340 /* Return the total width of the operand *OPERAND.  */
 341 static inline unsigned
 342 get_operand_fields_width (const aarch64_operand *operand)
 343 {
 344   int i = 0;
 345   unsigned width = 0;
 346   while (operand->fields[i] != FLD_NIL)
 347     width += fields[operand->fields[i++]].width;
 348   assert (width > 0 && width < 32);
 349   return width;
 350 }
 351
 352 static inline const aarch64_operand *
 353 get_operand_from_code (enum aarch64_opnd code)
 354 {
 355   return aarch64_operands + code;
 356 }
 357 \f
 358 /* Operand qualifier and operand constraint checking.  */
 359
 360 int aarch64_match_operands_constraint (aarch64_inst *,
 361                                        aarch64_operand_error *);
 362
 363 /* Operand qualifier related functions.  */
 364 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 365 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 366 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 367 int aarch64_find_best_match (const aarch64_inst *,
 368                              const aarch64_opnd_qualifier_seq_t *,
 369                              int, aarch64_opnd_qualifier_t *);
 370
 371 static inline void
 372 reset_operand_qualifier (aarch64_inst *inst, int idx)
 373 {
 374   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 375   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 376 }
 377 \f
 378 /* Inline functions operating on instruction bit-field(s).  */
 379
 380 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 381
 382 static inline aarch64_insn
 383 gen_mask (int width)
 384 {
 385   return ((aarch64_insn) 1 << width) - 1;
 386 }
 387
 388 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 389 static inline int
 390 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 391 {
 392   const aarch64_field *field = &fields[kind];
 393   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 394     return 0;
 395   ret->lsb = field->lsb + lsb_rel;
 396   ret->width = width;
 397   return 1;
 398 }
 399
 400 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 401    of the opcode.  */
 402
 403 static inline void
 404 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 405                 aarch64_insn value, aarch64_insn mask)
 406 {
 407   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 408           && field->lsb + field->width <= 32);
 409   value &= gen_mask (field->width);
 410   value <<= field->lsb;
 411   /* In some opcodes, field can be part of the base opcode, e.g. the size
 412      field in FADD.  The following helps avoid corrupt the base opcode.  */
 413   value &= ~mask;
 414   *code |= value;
 415 }
 416
 417 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 418    mask of the opcode.  */
 419
 420 static inline aarch64_insn
 421 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 422                  aarch64_insn mask)
 423 {
 424   aarch64_insn value;
 425   /* Clear any bit that is a part of the base opcode.  */
 426   code &= ~mask;
 427   value = (code >> field->lsb) & gen_mask (field->width);
 428   return value;
 429 }
 430
 431 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 432    of the opcode.  */
 433
 434 static inline void
 435 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 436               aarch64_insn value, aarch64_insn mask)
 437 {
 438   insert_field_2 (&fields[kind], code, value, mask);
 439 }
 440
 441 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 442    base mask of the opcode.  */
 443
 444 static inline aarch64_insn
 445 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 446                aarch64_insn mask)
 447 {
 448   return extract_field_2 (&fields[kind], code, mask);
 449 }
 450
 451 extern aarch64_insn
 452 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 453 \f
 454 /* Inline functions selecting operand to do the encoding/decoding for a
 455    certain instruction bit-field.  */
 456
 457 /* Select the operand to do the encoding/decoding of the 'sf' field.
 458    The heuristic-based rule is that the result operand is respected more.  */
 459
 460 static inline int
 461 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 462 {
 463   int idx = -1;
 464   if (aarch64_get_operand_class (opcode->operands[0])
 465       == AARCH64_OPND_CLASS_INT_REG)
 466     /* normal case.  */
 467     idx = 0;
 468   else if (aarch64_get_operand_class (opcode->operands[1])
 469            == AARCH64_OPND_CLASS_INT_REG)
 470     /* e.g. float2fix.  */
 471     idx = 1;
 472   else
 473     { assert (0); abort (); }
 474   return idx;
 475 }
 476
 477 /* Select the operand to do the encoding/decoding of the 'type' field in
 478    the floating-point instructions.
 479    The heuristic-based rule is that the source operand is respected more.  */
 480
 481 static inline int
 482 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 483 {
 484   int idx;
 485   if (aarch64_get_operand_class (opcode->operands[1])
 486       == AARCH64_OPND_CLASS_FP_REG)
 487     /* normal case.  */
 488     idx = 1;
 489   else if (aarch64_get_operand_class (opcode->operands[0])
 490            == AARCH64_OPND_CLASS_FP_REG)
 491     /* e.g. float2fix.  */
 492     idx = 0;
 493   else
 494     { assert (0); abort (); }
 495   return idx;
 496 }
 497
 498 /* Select the operand to do the encoding/decoding of the 'size' field in
 499    the AdvSIMD scalar instructions.
 500    The heuristic-based rule is that the destination operand is respected
 501    more.  */
 502
 503 static inline int
 504 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 505 {
 506   int src_size = 0, dst_size = 0;
 507   if (aarch64_get_operand_class (opcode->operands[0])
 508       == AARCH64_OPND_CLASS_SISD_REG)
 509     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 510   if (aarch64_get_operand_class (opcode->operands[1])
 511       == AARCH64_OPND_CLASS_SISD_REG)
 512     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 513   if (src_size == dst_size && src_size == 0)
 514     { assert (0); abort (); }
 515   /* When the result is not a sisd register or it is a long operantion.  */
 516   if (dst_size == 0 || dst_size == src_size << 1)
 517     return 1;
 518   else
 519     return 0;
 520 }
 521
 522 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 523    the AdvSIMD instructions.  */
 524
 525 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 526 \f
 527 /* Miscellaneous.  */
 528
 529 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 530 enum aarch64_modifier_kind
 531 aarch64_get_operand_modifier_from_value (aarch64_insn, bool);
 532
 533
 534 bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
 535 bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 536 int aarch64_shrink_expanded_imm8 (uint64_t);
 537
 538 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 539 static inline void
 540 copy_operand_info (aarch64_inst *inst, int dst, int src)
 541 {
 542   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 543           && src < AARCH64_MAX_OPND_NUM);
 544   memcpy (&inst->operands[dst], &inst->operands[src],
 545           sizeof (aarch64_opnd_info));
 546   inst->operands[dst].idx = dst;
 547 }
 548
 549 /* A primitive log caculator.  */
 550
 551 static inline unsigned int
 552 get_logsz (unsigned int size)
 553 {
 554   const unsigned char ls[16] =
 555     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 556   if (size > 16)
 557     {
 558       assert (0);
 559       return -1;
 560     }
 561   assert (ls[size - 1] != (unsigned char)-1);
 562   return ls[size - 1];
 563 }
 564
 565 #endif /* OPCODES_AARCH64_OPC_H */