opcodes/bpf-opc.c

   1 /* bpf-opc.c - BPF opcodes.
   2    Copyright (C) 2023 Free Software Foundation, Inc.
   3
   4    Contributed by Oracle Inc.
   5
   6    This file is part of the GNU binutils.
   7
   8    This is free software; you can redistribute them and/or modify them
   9    under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    This program is distributed in the hope that it will be useful, but
  14    WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16    General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "config.h"
  23 #include <stdlib.h>
  24 #include "opcode/bpf.h"
  25
  26 /* Note that the entries in the opcodes table below are accessed
  27    sequentially when matching instructions per opcode, and also when
  28    parsing.  Please take care to keep the entries sorted
  29    accordingly!  */
  30
  31 const struct bpf_opcode bpf_opcodes[] =
  32 {
  33   /* id, normal, pseudoc, version, mask, opcodes */
  34
  35   /* ALU instructions.  */
  36   {BPF_INSN_ADDR, "add%W%dr , %sr", "%dr += %sr",
  37    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_X},
  38   {BPF_INSN_ADDI, "add%W%dr , %i32", "%dr += %i32",
  39    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_K},
  40   {BPF_INSN_SUBR, "sub%W%dr , %sr", "%dr -= %sr",
  41    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_X},
  42   {BPF_INSN_SUBI, "sub%W%dr , %i32", "%dr -= %i32",
  43    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_K},
  44   {BPF_INSN_MULR, "mul%W%dr , %sr", "%dr *= %sr",
  45    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_X},
  46   {BPF_INSN_MULI, "mul%W%dr , %i32", "%dr *= %i32",
  47    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_K},
  48   {BPF_INSN_SDIVR, "sdiv%W%dr, %sr", "%dr s/= %sr",
  49    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
  50   {BPF_INSN_SDIVI, "sdiv%W%dr , %i32","%dr s/= %i32",
  51    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
  52   {BPF_INSN_SMODR, "smod%W%dr , %sr", "%dr s%%= %sr",
  53    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
  54   {BPF_INSN_SMODI, "smod%W%dr , %i32", "%dr s%%= %i32",
  55    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
  56   {BPF_INSN_DIVR, "div%W%dr , %sr", "%dr /= %sr",
  57    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X},
  58   {BPF_INSN_DIVI, "div%W%dr , %i32", "%dr /= %i32",
  59    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K},
  60   {BPF_INSN_MODR, "mod%W%dr , %sr", "%dr %%= %sr",
  61    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X},
  62   {BPF_INSN_MODI, "mod%W%dr , %i32", "%dr %%= %i32",
  63    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K},
  64   {BPF_INSN_ORR, "or%W%dr , %sr", "%dr |= %sr",
  65    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_X},
  66   {BPF_INSN_ORI, "or%W%dr , %i32", "%dr |= %i32",
  67    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_K},
  68   {BPF_INSN_ANDR, "and%W%dr , %sr", "%dr &= %sr",
  69    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_X},
  70   {BPF_INSN_ANDI, "and%W%dr , %i32", "%dr &= %i32",
  71    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_K},
  72   {BPF_INSN_XORR, "xor%W%dr , %sr", "%dr ^= %sr",
  73    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_X},
  74   {BPF_INSN_XORI, "xor%W%dr , %i32", "%dr ^= %i32",
  75    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_K},
  76   {BPF_INSN_NEGR, "neg%W%dr, %sr", "%dr = - %sr",
  77    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_X},
  78   {BPF_INSN_NEGI, "neg%W%dr , %i32", "%dr = -%W%i32",
  79    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_K},
  80   {BPF_INSN_LSHR, "lsh%W%dr , %sr", "%dr <<= %sr",
  81    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_X},
  82   {BPF_INSN_LSHI, "lsh%W%dr , %i32", "%dr <<= %i32",
  83    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_K},
  84   {BPF_INSN_RSHR, "rsh%W%dr , %sr", "%dr >>= %sr",
  85    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_X},
  86   {BPF_INSN_RSHI, "rsh%W%dr , %i32", "%dr >>= %i32",
  87    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_K},
  88   {BPF_INSN_ARSHR, "arsh%W%dr , %sr", "%dr%ws>>= %sr",
  89    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X},
  90   {BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>= %i32",
  91    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K},
  92   {BPF_INSN_MOVS8R, "movs%W%dr , %sr , 8", "%dr%ws=%w( i8 )%w%sr",
  93    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
  94   {BPF_INSN_MOVS16R, "movs%W%dr , %sr , 16", "%dr%ws=%w( i16 )%w%sr",
  95    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
  96   {BPF_INSN_MOVS32R, "movs%W%dr , %sr , 32", "%dr%ws=%w( i32 )%w%sr",
  97    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
  98   {BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr = %sr",
  99    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X},
 100   {BPF_INSN_MOVI, "mov%W%dr , %i32", "%dr = %i32",
 101    BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_K},
 102
 103   /* ALU32 instructions.  */
 104   {BPF_INSN_ADD32R, "add32%W%dr , %sr", "%dw += %sw",
 105    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_X},
 106   {BPF_INSN_ADD32I, "add32%W%dr , %i32", "%dw += %i32",
 107    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_K},
 108   {BPF_INSN_SUB32R, "sub32%W%dr , %sr", "%dw -= %sw",
 109    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_X},
 110   {BPF_INSN_SUB32I, "sub32%W%dr , %i32", "%dw -= %i32",
 111    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_K},
 112   {BPF_INSN_MUL32R, "mul32%W%dr , %sr", "%dw *= %sw",
 113    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_X},
 114   {BPF_INSN_MUL32I, "mul32%W%dr , %i32", "%dw *= %i32",
 115    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_K},
 116   {BPF_INSN_SDIV32R, "sdiv32%W%dr , %sr", "%dw s/= %sw",
 117    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
 118   {BPF_INSN_SDIV32I, "sdiv32%W%dr , %i32", "%dw s/= %i32",
 119    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
 120   {BPF_INSN_SMOD32R, "smod32%W%dr , %sr", "%dw s%%= %sw",
 121    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
 122   {BPF_INSN_SMOD32I, "smod32%W%dr , %i32", "%dw s%%= %i32",
 123    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
 124   {BPF_INSN_DIV32R, "div32%W%dr , %sr", "%dw /= %sw",
 125    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X},
 126   {BPF_INSN_DIV32I, "div32%W%dr , %i32", "%dw /= %i32",
 127    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K},
 128   {BPF_INSN_MOD32R, "mod32%W%dr , %sr", "%dw %%= %sw",
 129    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X},
 130   {BPF_INSN_MOD32I, "mod32%W%dr , %i32", "%dw %%= %i32",
 131    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K},
 132   {BPF_INSN_OR32R, "or32%W%dr , %sr",  "%dw |= %sw",
 133    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_X},
 134   {BPF_INSN_OR32I, "or32%W%dr , %i32", "%dw |= %i32",
 135    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_K},
 136   {BPF_INSN_AND32R, "and32%W%dr , %sr", "%dw &= %sw",
 137    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_X},
 138   {BPF_INSN_AND32I, "and32%W%dr , %i32", "%dw &= %i32",
 139    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_K},
 140   {BPF_INSN_XOR32R, "xor32%W%dr , %sr", "%dw ^= %sw",
 141    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_X},
 142   {BPF_INSN_XOR32I, "xor32%W%dr , %i32", "%dw ^= %i32",
 143    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_K},
 144   {BPF_INSN_NEG32R, "neg32%W%dr , %sr", "%dw = - %sw",
 145    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_X},
 146   {BPF_INSN_NEG32I, "neg32%W%dr , %i32", "%dw = -%W%i32",
 147    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_K},
 148   {BPF_INSN_LSH32R, "lsh32%W%dr , %sr", "%dw <<= %sw",
 149    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_X},
 150   {BPF_INSN_LSH32I, "lsh32%W%dr , %i32", "%dw <<= %i32",
 151    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_K},
 152   {BPF_INSN_RSH32R, "rsh32%W%dr , %sr", "%dw >>= %sw",
 153    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_X},
 154   {BPF_INSN_RSH32I, "rsh32%W%dr , %i32", "%dw >>= %i32",
 155    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_K},
 156   {BPF_INSN_ARSH32R, "arsh32%W%dr , %sr", "%dw%ws>>= %sw",
 157    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X},
 158   {BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>= %i32",
 159    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K},
 160   {BPF_INSN_MOVS328R, "movs32%W%dr , %sr , 8", "%dw%ws=%w( i8 )%w%sw",
 161    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8},
 162   {BPF_INSN_MOVS3216R, "movs32%W%dr , %sr , 16", "%dw%ws=%w( i16 )%w%sw",
 163    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16},
 164   {BPF_INSN_MOVS3232R, "movs32%W%dr , %sr , 32", "%dw%ws=%w( i32 )%w%sw",
 165    BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32},
 166   {BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw = %sw",
 167    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X},
 168   {BPF_INSN_MOV32I, "mov32%W%dr , %i32", "%dw = %i32",
 169    BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_K},
 170
 171   /* Endianness conversion instructions.  */
 172   {BPF_INSN_ENDLE16, "endle%W%dr , 16", "%dr = le16%w%dr",
 173    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END16},
 174   {BPF_INSN_ENDLE32, "endle%W%dr , 32", "%dr = le32%w%dr",
 175    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END32},
 176   {BPF_INSN_ENDLE64, "endle%W%dr , 64", "%dr = le64%w%dr",
 177    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END64},
 178   {BPF_INSN_ENDBE16, "endbe%W%dr , 16", "%dr = be16%w%dr",
 179    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END16},
 180   {BPF_INSN_ENDBE32, "endbe%W%dr , 32", "%dr = be32%w%dr",
 181    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END32},
 182   {BPF_INSN_ENDBE64, "endbe%W%dr , 64", "%dr = be64%w%dr",
 183    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END64},
 184
 185   /* 64-bit load instruction.  */
 186   {BPF_INSN_LDDW, "lddw%W%dr , %i64", "%dr = %i64%wll",
 187    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IMM},
 188
 189   /* Indirect load instructions, designed to be used in socket
 190      filters.  */
 191   {BPF_INSN_LDINDB, "ldindb%W%sr , %i32", "r0 = * ( u8 * ) skb [ %sr %I32 ]",
 192    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_IND},
 193   {BPF_INSN_LDINDH, "ldindh%W%sr , %i32", "r0 = * ( u16 * ) skb [ %sr %I32 ]",
 194    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_IND},
 195   {BPF_INSN_LDINDW, "ldindw%W%sr , %i32", "r0 = * ( u32 * ) skb [ %sr %I32 ]",
 196    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_IND},
 197   {BPF_INSN_LDINDDW, "ldinddw%W%sr , %i32", "r0 = * ( u64 * ) skb [ %sr %I32 ]",
 198    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IND},
 199
 200   /* Absolute load instructions, designed to be used in socket filters.  */
 201   {BPF_INSN_LDABSB, "ldabsb%W%i32", "r0 = * ( u8 * ) skb [ %i32 ]",
 202    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_ABS},
 203   {BPF_INSN_LDABSH, "ldabsh%W%i32", "r0 = * ( u16 * ) skb [ %i32 ]",
 204    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_ABS},
 205   {BPF_INSN_LDABSW, "ldabsw%W%i32", "r0 = * ( u32 * ) skb [ %i32 ]",
 206    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_ABS},
 207   {BPF_INSN_LDABSDW, "ldabsdw%W%i32", "r0 = * ( u64 * ) skb [ %i32 ]",
 208    BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_ABS},
 209
 210   /* Generic load instructions (to register.)  */
 211   {BPF_INSN_LDXB, "ldxb%W%dr , [ %sr %o16 ]", "%dr = * ( u8 * ) ( %sr %o16 )",
 212    BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM},
 213   {BPF_INSN_LDXH, "ldxh%W%dr , [ %sr %o16 ]", "%dr = * ( u16 * ) ( %sr %o16 )",
 214    BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM},
 215   {BPF_INSN_LDXW, "ldxw%W%dr , [ %sr %o16 ]", "%dr = * ( u32 * ) ( %sr %o16 )",
 216    BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},
 217   {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )",
 218    BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},
 219
 220   /* Generic store instructions (from register.)  */
 221   {BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sr",
 222    BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM},
 223   {BPF_INSN_STXHR, "stxh%W[ %dr %o16 ] , %sr", "* ( u16 * ) ( %dr %o16 ) = %sr",
 224    BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_H|BPF_MODE_MEM},
 225   {BPF_INSN_STXWR, "stxw%W[ %dr %o16 ], %sr", "* ( u32 * ) ( %dr %o16 ) = %sr",
 226    BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_MEM},
 227   {BPF_INSN_STXDWR, "stxdw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) = %sr",
 228    BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_MEM},
 229
 230   /* Generic store instructions (from 32-bit immediate.)  */
 231   {BPF_INSN_STXBI, "stb%W[ %dr %o16 ] , %i32", "* ( u8 * ) ( %dr %o16 ) = %i32",
 232    BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_B|BPF_MODE_MEM},
 233   {BPF_INSN_STXHI, "sth%W[ %dr %o16 ] , %i32", "* ( u16 * ) ( %dr %o16 ) = %i32",
 234    BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_H|BPF_MODE_MEM},
 235   {BPF_INSN_STXWI, "stw%W[ %dr %o16 ] , %i32", "* ( u32 * ) ( %dr %o16 ) = %i32",
 236    BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_W|BPF_MODE_MEM},
 237   {BPF_INSN_STXDWI, "stdw%W[ %dr %o16 ] , %i32", "* ( u64 * ) ( %dr %o16 ) = %i32",
 238    BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_DW|BPF_MODE_MEM},
 239
 240   /* Compare-and-jump instructions (reg OP reg).  */
 241   {BPF_INSN_JAR, "ja%W%d16", "goto%w%d16",
 242    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JA|BPF_SRC_K},
 243   {BPF_INSN_JEQR, "jeq%W%dr , %sr , %d16", "if%w%dr == %sr%wgoto%w%d16",
 244    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_X},
 245   {BPF_INSN_JGTR, "jgt%W%dr , %sr , %d16", "if%w%dr > %sr%wgoto%w%d16",
 246    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_X},
 247   {BPF_INSN_JSGTR, "jsgt%W%dr, %sr , %d16", "if%w%dr s> %sr%wgoto%w%d16",
 248       BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_X},
 249   {BPF_INSN_JGER, "jge%W%dr , %sr , %d16", "if%w%dr >= %sr%wgoto%w%d16",
 250    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_X},
 251   {BPF_INSN_JSGER, "jsge%W%dr , %sr , %d16", "if%w%dr s>= %sr%wgoto%w%d16",
 252    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_X},
 253   {BPF_INSN_JLTR, "jlt%W%dr , %sr , %d16", "if%w%dr < %sr%wgoto%w%d16",
 254    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_X},
 255   {BPF_INSN_JSLTR, "jslt%W%dr , %sr , %d16", "if%w%dr s< %sr%wgoto%w%d16",
 256    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_X},
 257   {BPF_INSN_JLER, "jle%W%dr , %sr , %d16", "if%w%dr <= %sr%wgoto%w%d16",
 258    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_X},
 259   {BPF_INSN_JSLER, "jsle%W%dr , %sr , %d16", "if%w%dr s<= %sr%wgoto%w%d16",
 260    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_X},
 261   {BPF_INSN_JSETR, "jset%W%dr , %sr , %d16", "if%w%dr & %sr%wgoto%w%d16",
 262    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_X},
 263   {BPF_INSN_JNER, "jne%W%dr , %sr , %d16", "if%w%dr != %sr%wgoto%w%d16",
 264    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_X},
 265   {BPF_INSN_CALLR, "call%W%dr", "callx%w%dr",
 266    BPF_XBPF, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X},
 267   {BPF_INSN_CALL, "call%W%d32", "call%w%d32",
 268    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_K},
 269   {BPF_INSN_EXIT, "exit", "exit",
 270    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_EXIT|BPF_SRC_K},
 271
 272   /* Compare-and-jump instructions (reg OP imm).  */
 273   {BPF_INSN_JEQI, "jeq%W%dr , %i32 , %d16", "if%w%dr == %i32%wgoto%w%d16",
 274    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_K},
 275   {BPF_INSN_JGTI, "jgt%W%dr , %i32 , %d16", "if%w%dr > %i32%wgoto%w%d16",
 276    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_K},
 277   {BPF_INSN_JSGTI, "jsgt%W%dr, %i32 , %d16", "if%w%dr s> %i32%wgoto%w%d16",
 278       BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_K},
 279   {BPF_INSN_JGEI, "jge%W%dr , %i32 , %d16", "if%w%dr >= %i32%wgoto%w%d16",
 280    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_K},
 281   {BPF_INSN_JSGEI, "jsge%W%dr , %i32 , %d16", "if%w%dr s>= %i32%wgoto%w%d16",
 282    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_K},
 283   {BPF_INSN_JLTI, "jlt%W%dr , %i32 , %d16", "if%w%dr < %i32%wgoto%w%d16",
 284    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_K},
 285   {BPF_INSN_JSLTI, "jslt%W%dr , %i32, %d16", "if%w%dr s< %i32%wgoto%w%d16",
 286    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_K},
 287   {BPF_INSN_JLEI, "jle%W%dr , %i32 , %d16", "if%w%dr <= %i32%wgoto%w%d16",
 288    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_K},
 289   {BPF_INSN_JSLEI, "jsle%W%dr , %i32 , %d16", "if%w%dr s<= %i32%wgoto%w%d16",
 290    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_K},
 291   {BPF_INSN_JSETI, "jset%W%dr , %i32 , %d16", "if%w%dr & %i32%wgoto%w%d16",
 292    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_K},
 293   {BPF_INSN_JNEI, "jne%W%dr , %i32 , %d16", "if%w%dr != %i32%wgoto%w%d16",
 294    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_K},
 295
 296   /* 32-bit compare-and-jump instructions (reg OP reg).  */
 297   {BPF_INSN_JEQ32R, "jeq32%W%dr , %sr , %d16", "if%w%dw == %sw%wgoto%w%d16",
 298    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_X},
 299   {BPF_INSN_JGT32R, "jgt32%W%dr , %sr , %d16", "if%w%dw > %sw%wgoto%w%d16",
 300    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_X},
 301   {BPF_INSN_JSGT32R, "jsgt32%W%dr, %sr , %d16", "if%w%dw s> %sw%wgoto%w%d16",
 302    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_X},
 303   {BPF_INSN_JGE32R, "jge32%W%dr , %sr , %d16", "if%w%dw >= %sw%wgoto%w%d16",
 304    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_X},
 305   {BPF_INSN_JSGE32R, "jsge32%W%dr , %sr , %d16", "if%w%dw s>= %sw%wgoto%w%d16",
 306    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_X},
 307   {BPF_INSN_JLT32R, "jlt32%W%dr , %sr , %d16", "if%w%dw < %sw%wgoto%w%d16",
 308    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_X},
 309   {BPF_INSN_JSLT32R, "jslt32%W%dr , %sr , %d16", "if%w%dw s< %sw%wgoto%w%d16",
 310    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_X},
 311   {BPF_INSN_JLE32R, "jle32%W%dr , %sr , %d16", "if%w%dw <= %sw%wgoto%w%d16",
 312    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_X},
 313   {BPF_INSN_JSLE32R, "jsle32%W%dr , %sr , %d16", "if%w%dw s<= %sw%wgoto%w%d16",
 314    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_X},
 315   {BPF_INSN_JSET32R, "jset32%W%dr , %sr , %d16", "if%w%dw & %sw%wgoto%w%d16",
 316    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_X},
 317   {BPF_INSN_JNE32R, "jne32%W%dr , %sr , %d16", "if%w%dw != %sw%wgoto%w%d16",
 318    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_X},
 319
 320   /* 32-bit compare-and-jump instructions (reg OP imm).  */
 321   {BPF_INSN_JEQ32I, "jeq32%W%dr , %i32 , %d16", "if%w%dw == %i32%wgoto%w%d16",
 322    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_K},
 323   {BPF_INSN_JGT32I, "jgt32%W%dr , %i32 , %d16", "if%w%dw > %i32%wgoto%w%d16",
 324    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_K},
 325   {BPF_INSN_JSGT32I, "jsgt32%W%dr, %i32 , %d16", "if%w%dw s> %i32%wgoto%w%d16",
 326    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_K},
 327   {BPF_INSN_JGE32I, "jge32%W%dr , %i32 , %d16", "if%w%dw >= %i32%wgoto%w%d16",
 328    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_K},
 329   {BPF_INSN_JSGE32I, "jsge32%W%dr , %i32 , %d16", "if%w%dw s>= %i32%wgoto%w%d16",
 330    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_K},
 331   {BPF_INSN_JLT32I, "jlt32%W%dr , %i32 , %d16", "if%w%dw < %i32%wgoto%w%d16",
 332    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_K},
 333   {BPF_INSN_JSLT32I, "jslt32%W%dr , %i32, %d16", "if%w%dw s< %i32%wgoto%w%d16",
 334    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_K},
 335   {BPF_INSN_JLE32I, "jle32%W%dr , %i32 , %d16", "if%w%dw <= %i32%wgoto%w%d16",
 336    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_K},
 337   {BPF_INSN_JSLE32I, "jsle32%W%dr , %i32 , %d16", "if%w%dw s<= %i32%wgoto%w%d16",
 338    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_K},
 339   {BPF_INSN_JSET32I, "jset32%W%dr , %i32 , %d16", "if%w%dw & %i32%wgoto%w%d16",
 340    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_K},
 341   {BPF_INSN_JNE32I, "jne32%W%dr , %i32 , %d16", "if%w%dw != %i32%wgoto%w%d16",
 342    BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_K},
 343
 344   /* Atomic instructions.  */
 345   {BPF_INSN_AADD, "aadd%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
 346    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
 347   {BPF_INSN_AOR, "aor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) |= %sr",
 348    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
 349   {BPF_INSN_AAND, "aand%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) &= %sr",
 350    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
 351   {BPF_INSN_AXOR, "axor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) ^= %sr",
 352    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
 353
 354   /* Atomic instructions with fetching.  */
 355   {BPF_INSN_AFADD, "afadd%W[ %dr %o16 ] , %sr", "???",
 356    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
 357   {BPF_INSN_AFOR, "afor%W[ %dr %o16 ] , %sr", "???",
 358    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
 359   {BPF_INSN_AFAND, "afand%W[ %dr %o16 ] , %sr", "???",
 360    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
 361   {BPF_INSN_AFXOR, "afxor%W[ %dr %o16 ] , %sr", "???",
 362    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
 363
 364   /* Atomic instructions (32-bit.) */
 365   {BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) += %sr",
 366    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
 367   {BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) |= %sr",
 368    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
 369   {BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) &= %sr",
 370    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
 371   {BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) ^= %sr",
 372    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
 373
 374   /* Atomic instructions with fetching (32-bit.) */
 375   {BPF_INSN_AFADD32, "afadd32 %W[ %dr %o16 ] , %sr", "???",
 376    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
 377   {BPF_INSN_AFOR32, "afor32%W[ %dr %o16 ] , %sr", "???",
 378    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
 379   {BPF_INSN_AFAND32, "afand32%W[ %dr %o16 ] , %sr", "???",
 380    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
 381   {BPF_INSN_AFXOR32, "afxor32%W[ %dr %o16 ] , %sr", "???",
 382    BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
 383
 384   /* Old versions of aadd and aadd32.  */
 385   {BPF_INSN_AADD, "xadddw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
 386    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
 387   {BPF_INSN_AADD32, "xaddw%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) += %sr",
 388    BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
 389
 390   /* the brkpt instruction is used by the BPF simulator and it doesn't
 391      really belong to the BPF instruction set.  */
 392   {BPF_INSN_BRKPT, "brkpt", "brkpt",
 393    BPF_XBPF, BPF_CODE, BPF_CLASS_ALU|BPF_SRC_X|BPF_CODE_NEG},
 394
 395   /* Sentinel.  */
 396   {BPF_NOINSN, NULL, NULL, 0, 0UL, 0UL},
 397 };
 398
 399 static bpf_insn_word
 400 bpf_handle_endianness (bpf_insn_word word, enum bpf_endian endian)
 401 {
 402   if (endian == BPF_ENDIAN_LITTLE)
 403     {
 404       /* Endianness groups: 8 | 4 | 4 | 16 | 32  */
 405
 406       bpf_insn_word code = (word >> 56) & 0xff;
 407       bpf_insn_word dst = (word >> 48) & 0xf;
 408       bpf_insn_word src = (word >> 52) & 0xf;
 409       bpf_insn_word offset16 = (word >> 32) & 0xffff;
 410       bpf_insn_word imm32 = word & 0xffffffff;
 411
 412       return ((code << 56)
 413               | dst << 52
 414               | src << 48
 415               | (offset16 & 0xff) << 40
 416               | ((offset16 >> 8) & 0xff) << 32
 417               | (imm32 & 0xff) << 24
 418               | ((imm32 >> 8) & 0xff) << 16
 419               | ((imm32 >> 16) & 0xff) << 8
 420               | ((imm32 >> 24) & 0xff));
 421     }
 422
 423   return word;
 424 }
 425
 426 const struct bpf_opcode *
 427 bpf_match_insn (bpf_insn_word word,
 428                 enum bpf_endian endian,
 429                 int version)
 430 {
 431   unsigned int i = 0;
 432
 433   while (bpf_opcodes[i].normal != NULL)
 434     {
 435       bpf_insn_word cword
 436         = bpf_handle_endianness (word, endian);
 437
 438       /* Attempt match using mask and opcodes.  */
 439       if (bpf_opcodes[i].version <= version
 440           && (cword & bpf_opcodes[i].mask) == bpf_opcodes[i].opcode)
 441         return &bpf_opcodes[i];
 442       i++;
 443     }
 444
 445   /* No maching instruction found.  */
 446   return NULL;
 447 }
 448
 449 uint8_t
 450 bpf_extract_src (bpf_insn_word word, enum bpf_endian endian)
 451 {
 452   word = bpf_handle_endianness (word, endian);
 453   return (uint8_t) ((word >> 48) & 0xf);
 454 }
 455
 456 uint8_t
 457 bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian)
 458 {
 459   word = bpf_handle_endianness (word, endian);
 460   return (uint8_t) ((word >> 52) & 0xf);
 461 }
 462
 463 int16_t
 464 bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian)
 465 {
 466   word = bpf_handle_endianness (word, endian);
 467   return (int16_t) ((word >> 32) & 0xffff);
 468 }
 469
 470 int32_t
 471 bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian)
 472 {
 473   word = bpf_handle_endianness (word, endian);
 474   return (int32_t) (word & 0xffffffff);
 475 }
 476
 477 int64_t
 478 bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,
 479                    enum bpf_endian endian)
 480 {
 481   word1 = bpf_handle_endianness (word1, endian);
 482   word2 = bpf_handle_endianness (word2, endian);
 483   return (int64_t) (((word2 & 0xffffffff) << 32) | (word1 & 0xffffffff));
 484 }
 485
 486 const struct bpf_opcode *
 487 bpf_get_opcode (unsigned int index)
 488 {
 489   unsigned int i = 0;
 490
 491   while (bpf_opcodes[i].normal != NULL && i < index)
 492     ++i;
 493   return (bpf_opcodes[i].normal == NULL
 494           ? NULL
 495           : &bpf_opcodes[i]);
 496 }