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* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that
[thirdparty/binutils-gdb.git] / opcodes / fr30-opc.c
1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
5
6 Copyright (C) 1998 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "ansidecl.h"
27 #include "libiberty.h"
28 #include "bfd.h"
29 #include "symcat.h"
30 #include "fr30-opc.h"
31 #include "opintl.h"
32
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
35
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
38
39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
40 static unsigned int asm_hash_insn PARAMS ((const char *));
41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
43
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
51
52 The result is a pointer to the insn table entry, or NULL if the instruction
53 wasn't recognized. */
54
55 const CGEN_INSN *
56 fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
57 CGEN_OPCODE_DESC od;
58 const CGEN_INSN *insn;
59 CGEN_INSN_BYTES insn_value;
60 int length;
61 CGEN_FIELDS *fields;
62 int alias_p;
63 {
64 unsigned char buf[CGEN_MAX_INSN_SIZE];
65 unsigned char *bufp;
66 CGEN_INSN_INT base_insn;
67 #if CGEN_INT_INSN_P
68 CGEN_EXTRACT_INFO *info = NULL;
69 #else
70 CGEN_EXTRACT_INFO ex_info;
71 CGEN_EXTRACT_INFO *info = &ex_info;
72 #endif
73
74 #if CGEN_INT_INSN_P
75 cgen_put_insn_value (od, buf, length, insn_value);
76 bufp = buf;
77 base_insn = insn_value; /*???*/
78 #else
79 ex_info.dis_info = NULL;
80 ex_info.insn_bytes = insn_value;
81 ex_info.valid = -1;
82 base_insn = cgen_get_insn_value (od, buf, length);
83 bufp = insn_value;
84 #endif
85
86 if (!insn)
87 {
88 const CGEN_INSN_LIST *insn_list;
89
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
92
93 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
94 while (insn_list != NULL)
95 {
96 insn = insn_list->insn;
97
98 if (alias_p
99 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
100 {
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
103 extract handler. */
104 if ((base_insn & CGEN_INSN_BASE_MASK (insn))
105 == CGEN_INSN_BASE_VALUE (insn))
106 {
107 /* ??? 0 is passed for `pc' */
108 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
109 base_insn, fields,
110 (bfd_vma) 0);
111 if (elength > 0)
112 {
113 /* sanity check */
114 if (length != 0 && length != elength)
115 abort ();
116 return insn;
117 }
118 }
119 }
120
121 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
122 }
123 }
124 else
125 {
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
127 if (! alias_p
128 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
129 abort ();
130 /* Sanity check: length must be correct. */
131 if (length != CGEN_INSN_BITSIZE (insn))
132 abort ();
133
134 /* ??? 0 is passed for `pc' */
135 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
136 (bfd_vma) 0);
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
139 if (length == 0)
140 abort ();
141 return insn;
142 }
143
144 return NULL;
145 }
146
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
149 in. */
150
151 void
152 fr30_cgen_get_insn_operands (od, insn, fields, indices)
153 CGEN_OPCODE_DESC od;
154 const CGEN_INSN * insn;
155 const CGEN_FIELDS * fields;
156 int *indices;
157 {
158 const CGEN_OPERAND_INSTANCE *opinst;
159 int i;
160
161 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
162 opinst != NULL
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
164 ++i, ++opinst)
165 {
166 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
167 if (op == NULL)
168 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
169 else
170 indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
171 fields);
172 }
173 }
174
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
176 isn't known.
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
179
180 The result is the insn table entry or NULL if the instruction wasn't
181 recognized. */
182
183 const CGEN_INSN *
184 fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
185 CGEN_OPCODE_DESC od;
186 const CGEN_INSN *insn;
187 CGEN_INSN_BYTES insn_value;
188 int length;
189 int *indices;
190 {
191 CGEN_FIELDS fields;
192
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
196 insn != NULL);
197 if (! insn)
198 return NULL;
199
200 fr30_cgen_get_insn_operands (od, insn, &fields, indices);
201 return insn;
202 }
203 /* Attributes. */
204
205 static const CGEN_ATTR_ENTRY bool_attr[] =
206 {
207 { "#f", 0 },
208 { "#t", 1 },
209 { 0, 0 }
210 };
211
212 static const CGEN_ATTR_ENTRY MACH_attr[] =
213 {
214 { "base", MACH_BASE },
215 { "fr30", MACH_FR30 },
216 { "max", MACH_MAX },
217 { 0, 0 }
218 };
219
220 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
221 {
222 { "MACH", & MACH_attr[0] },
223 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
224 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
225 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
226 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
227 { "RESERVED", &bool_attr[0], &bool_attr[0] },
228 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
229 { 0, 0, 0 }
230 };
231
232 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
233 {
234 { "MACH", & MACH_attr[0] },
235 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
236 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
237 { "SIGNED", &bool_attr[0], &bool_attr[0] },
238 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
239 { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
240 { "PC", &bool_attr[0], &bool_attr[0] },
241 { "PROFILE", &bool_attr[0], &bool_attr[0] },
242 { 0, 0, 0 }
243 };
244
245 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
246 {
247 { "MACH", & MACH_attr[0] },
248 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
249 { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
250 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
251 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
252 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
253 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
254 { "RELAX", &bool_attr[0], &bool_attr[0] },
255 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
256 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
257 { 0, 0, 0 }
258 };
259
260 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
261 {
262 { "MACH", & MACH_attr[0] },
263 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
264 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
265 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
266 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
267 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
268 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
269 { "RELAX", &bool_attr[0], &bool_attr[0] },
270 { "ALIAS", &bool_attr[0], &bool_attr[0] },
271 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
272 { "PBB", &bool_attr[0], &bool_attr[0] },
273 { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
274 { 0, 0, 0 }
275 };
276
277 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
278 {
279 { "r0", 0 },
280 { "r1", 1 },
281 { "r2", 2 },
282 { "r3", 3 },
283 { "r4", 4 },
284 { "r5", 5 },
285 { "r6", 6 },
286 { "r7", 7 },
287 { "r8", 8 },
288 { "r9", 9 },
289 { "r10", 10 },
290 { "r11", 11 },
291 { "r12", 12 },
292 { "r13", 13 },
293 { "r14", 14 },
294 { "r15", 15 },
295 { "ac", 13 },
296 { "fp", 14 },
297 { "sp", 15 }
298 };
299
300 CGEN_KEYWORD fr30_cgen_opval_h_gr =
301 {
302 & fr30_cgen_opval_h_gr_entries[0],
303 19
304 };
305
306 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
307 {
308 { "cr0", 0 },
309 { "cr1", 1 },
310 { "cr2", 2 },
311 { "cr3", 3 },
312 { "cr4", 4 },
313 { "cr5", 5 },
314 { "cr6", 6 },
315 { "cr7", 7 },
316 { "cr8", 8 },
317 { "cr9", 9 },
318 { "cr10", 10 },
319 { "cr11", 11 },
320 { "cr12", 12 },
321 { "cr13", 13 },
322 { "cr14", 14 },
323 { "cr15", 15 }
324 };
325
326 CGEN_KEYWORD fr30_cgen_opval_h_cr =
327 {
328 & fr30_cgen_opval_h_cr_entries[0],
329 16
330 };
331
332 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
333 {
334 { "tbr", 0 },
335 { "rp", 1 },
336 { "ssp", 2 },
337 { "usp", 3 },
338 { "mdh", 4 },
339 { "mdl", 5 }
340 };
341
342 CGEN_KEYWORD fr30_cgen_opval_h_dr =
343 {
344 & fr30_cgen_opval_h_dr_entries[0],
345 6
346 };
347
348 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
349 {
350 { "ps", 0 }
351 };
352
353 CGEN_KEYWORD fr30_cgen_opval_h_ps =
354 {
355 & fr30_cgen_opval_h_ps_entries[0],
356 1
357 };
358
359 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
360 {
361 { "r13", 0 }
362 };
363
364 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
365 {
366 & fr30_cgen_opval_h_r13_entries[0],
367 1
368 };
369
370 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
371 {
372 { "r14", 0 }
373 };
374
375 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
376 {
377 & fr30_cgen_opval_h_r14_entries[0],
378 1
379 };
380
381 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
382 {
383 { "r15", 0 }
384 };
385
386 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
387 {
388 & fr30_cgen_opval_h_r15_entries[0],
389 1
390 };
391
392
393 /* The hardware table. */
394
395 #define HW_ENT(n) fr30_cgen_hw_entries[n]
396 static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
397 {
398 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
399 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
400 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
401 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
402 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
403 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
404 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
405 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
406 { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
407 { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
408 { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
409 { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
410 { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
411 { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
412 { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
413 { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
414 { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
415 { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
416 { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
417 { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
418 { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
419 { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
420 { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
421 { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
422 { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
423 { 0 }
424 };
425
426 /* The instruction field table. */
427
428 static const CGEN_IFLD fr30_cgen_ifld_table[] =
429 {
430 { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
431 { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
432 { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
433 { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
434 { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
435 { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
436 { FR30_F_CC, "f-cc", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
437 { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
438 { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
439 { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
440 { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
441 { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
442 { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
443 { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
444 { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
445 { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
446 { FR30_F_U4, "f-u4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
447 { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
448 { FR30_F_I4, "f-i4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
449 { FR30_F_M4, "f-m4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
450 { FR30_F_U8, "f-u8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
451 { FR30_F_I8, "f-i8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
452 { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
453 { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
454 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
455 { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
456 { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
457 { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
458 { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
459 { FR30_F_S10, "f-s10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
460 { FR30_F_U10, "f-u10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
461 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
462 { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
463 { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
464 { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
465 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
466 { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
467 { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
468 { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
469 { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
470 { 0 }
471 };
472
473 /* The operand table. */
474
475 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
476 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
477
478 const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
479 {
480 /* pc: program counter */
481 { "pc", & HW_ENT (HW_H_PC), 0, 0,
482 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
483 /* Ri: destination register */
484 { "Ri", & HW_ENT (HW_H_GR), 12, 4,
485 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
486 /* Rj: source register */
487 { "Rj", & HW_ENT (HW_H_GR), 8, 4,
488 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
489 /* Ric: target register coproc insn */
490 { "Ric", & HW_ENT (HW_H_GR), 12, 4,
491 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
492 /* Rjc: source register coproc insn */
493 { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
494 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
495 /* CRi: coprocessor register */
496 { "CRi", & HW_ENT (HW_H_CR), 12, 4,
497 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
498 /* CRj: coprocessor register */
499 { "CRj", & HW_ENT (HW_H_CR), 8, 4,
500 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
501 /* Rs1: dedicated register */
502 { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
503 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
504 /* Rs2: dedicated register */
505 { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
506 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
507 /* R13: General Register 13 */
508 { "R13", & HW_ENT (HW_H_R13), 0, 0,
509 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
510 /* R14: General Register 14 */
511 { "R14", & HW_ENT (HW_H_R14), 0, 0,
512 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
513 /* R15: General Register 15 */
514 { "R15", & HW_ENT (HW_H_R15), 0, 0,
515 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
516 /* ps: Program Status register */
517 { "ps", & HW_ENT (HW_H_PS), 0, 0,
518 { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
519 /* u4: 4 bit unsigned immediate */
520 { "u4", & HW_ENT (HW_H_UINT), 8, 4,
521 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
522 /* u4c: 4 bit unsigned immediate */
523 { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
524 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
525 /* u8: 8 bit unsigned immediate */
526 { "u8", & HW_ENT (HW_H_UINT), 8, 8,
527 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
528 /* i8: 8 bit unsigned immediate */
529 { "i8", & HW_ENT (HW_H_UINT), 4, 8,
530 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
531 /* udisp6: 6 bit unsigned immediate */
532 { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
533 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
534 /* disp8: 8 bit signed immediate */
535 { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
536 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
537 /* disp9: 9 bit signed immediate */
538 { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
539 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
540 /* disp10: 10 bit signed immediate */
541 { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
542 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
543 /* s10: 10 bit signed immediate */
544 { "s10", & HW_ENT (HW_H_SINT), 8, 8,
545 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
546 /* u10: 10 bit unsigned immediate */
547 { "u10", & HW_ENT (HW_H_UINT), 8, 8,
548 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
549 /* i32: 32 bit immediate */
550 { "i32", & HW_ENT (HW_H_UINT), 0, 32,
551 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
552 /* m4: 4 bit negative immediate */
553 { "m4", & HW_ENT (HW_H_SINT), 8, 4,
554 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
555 /* i20: 20 bit immediate */
556 { "i20", & HW_ENT (HW_H_UINT), 0, 20,
557 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { (1<<MACH_BASE) } } },
558 /* dir8: 8 bit direct address */
559 { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
560 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
561 /* dir9: 9 bit direct address */
562 { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
563 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
564 /* dir10: 10 bit direct address */
565 { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
566 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
567 /* label9: 9 bit pc relative address */
568 { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
569 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
570 /* label12: 12 bit pc relative address */
571 { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
572 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
573 /* reglist_low_ld: 8 bit register mask for ldm */
574 { "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8,
575 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
576 /* reglist_hi_ld: 8 bit register mask for ldm */
577 { "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8,
578 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
579 /* reglist_low_st: 8 bit register mask for ldm */
580 { "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8,
581 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
582 /* reglist_hi_st: 8 bit register mask for ldm */
583 { "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8,
584 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
585 /* cc: condition codes */
586 { "cc", & HW_ENT (HW_H_UINT), 4, 4,
587 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
588 /* ccc: coprocessor calc */
589 { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
590 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
591 /* nbit: negative bit */
592 { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
593 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
594 /* vbit: overflow bit */
595 { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
596 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
597 /* zbit: zero bit */
598 { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
599 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
600 /* cbit: carry bit */
601 { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
602 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
603 /* ibit: interrupt bit */
604 { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
605 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
606 /* sbit: stack bit */
607 { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
608 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
609 /* tbit: trace trap bit */
610 { "tbit", & HW_ENT (HW_H_TBIT), 0, 0,
611 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
612 /* d0bit: division 0 bit */
613 { "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0,
614 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
615 /* d1bit: division 1 bit */
616 { "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0,
617 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
618 /* ccr: condition code bits */
619 { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
620 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
621 /* scr: system condition bits */
622 { "scr", & HW_ENT (HW_H_SCR), 0, 0,
623 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
624 /* ilm: interrupt level mask */
625 { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
626 { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
627 };
628
629 /* Instruction formats. */
630
631 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
632
633 static const CGEN_IFMT fmt_empty = {
634 0, 0, 0x0, { 0 }
635 };
636
637 static const CGEN_IFMT fmt_add = {
638 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
639 };
640
641 static const CGEN_IFMT fmt_addi = {
642 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
643 };
644
645 static const CGEN_IFMT fmt_add2 = {
646 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
647 };
648
649 static const CGEN_IFMT fmt_addc = {
650 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
651 };
652
653 static const CGEN_IFMT fmt_addn = {
654 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
655 };
656
657 static const CGEN_IFMT fmt_addni = {
658 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
659 };
660
661 static const CGEN_IFMT fmt_addn2 = {
662 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
663 };
664
665 static const CGEN_IFMT fmt_cmp = {
666 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
667 };
668
669 static const CGEN_IFMT fmt_cmpi = {
670 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
671 };
672
673 static const CGEN_IFMT fmt_cmp2 = {
674 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
675 };
676
677 static const CGEN_IFMT fmt_and = {
678 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
679 };
680
681 static const CGEN_IFMT fmt_andm = {
682 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
683 };
684
685 static const CGEN_IFMT fmt_andh = {
686 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
687 };
688
689 static const CGEN_IFMT fmt_andb = {
690 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
691 };
692
693 static const CGEN_IFMT fmt_bandl = {
694 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
695 };
696
697 static const CGEN_IFMT fmt_btstl = {
698 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
699 };
700
701 static const CGEN_IFMT fmt_mul = {
702 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
703 };
704
705 static const CGEN_IFMT fmt_mulu = {
706 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
707 };
708
709 static const CGEN_IFMT fmt_mulh = {
710 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
711 };
712
713 static const CGEN_IFMT fmt_div0s = {
714 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
715 };
716
717 static const CGEN_IFMT fmt_div0u = {
718 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
719 };
720
721 static const CGEN_IFMT fmt_div1 = {
722 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
723 };
724
725 static const CGEN_IFMT fmt_div2 = {
726 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
727 };
728
729 static const CGEN_IFMT fmt_div3 = {
730 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
731 };
732
733 static const CGEN_IFMT fmt_div4s = {
734 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
735 };
736
737 static const CGEN_IFMT fmt_lsl = {
738 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
739 };
740
741 static const CGEN_IFMT fmt_lsli = {
742 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
743 };
744
745 static const CGEN_IFMT fmt_ldi8 = {
746 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
747 };
748
749 static const CGEN_IFMT fmt_ldi20 = {
750 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
751 };
752
753 static const CGEN_IFMT fmt_ldi32 = {
754 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
755 };
756
757 static const CGEN_IFMT fmt_ld = {
758 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
759 };
760
761 static const CGEN_IFMT fmt_lduh = {
762 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
763 };
764
765 static const CGEN_IFMT fmt_ldub = {
766 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
767 };
768
769 static const CGEN_IFMT fmt_ldr13 = {
770 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
771 };
772
773 static const CGEN_IFMT fmt_ldr13uh = {
774 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
775 };
776
777 static const CGEN_IFMT fmt_ldr13ub = {
778 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
779 };
780
781 static const CGEN_IFMT fmt_ldr14 = {
782 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
783 };
784
785 static const CGEN_IFMT fmt_ldr14uh = {
786 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
787 };
788
789 static const CGEN_IFMT fmt_ldr14ub = {
790 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
791 };
792
793 static const CGEN_IFMT fmt_ldr15 = {
794 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
795 };
796
797 static const CGEN_IFMT fmt_ldr15gr = {
798 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
799 };
800
801 static const CGEN_IFMT fmt_ldr15dr = {
802 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
803 };
804
805 static const CGEN_IFMT fmt_ldr15ps = {
806 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
807 };
808
809 static const CGEN_IFMT fmt_st = {
810 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
811 };
812
813 static const CGEN_IFMT fmt_sth = {
814 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
815 };
816
817 static const CGEN_IFMT fmt_stb = {
818 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
819 };
820
821 static const CGEN_IFMT fmt_str13 = {
822 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
823 };
824
825 static const CGEN_IFMT fmt_str13h = {
826 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
827 };
828
829 static const CGEN_IFMT fmt_str13b = {
830 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
831 };
832
833 static const CGEN_IFMT fmt_str14 = {
834 16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
835 };
836
837 static const CGEN_IFMT fmt_str14h = {
838 16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
839 };
840
841 static const CGEN_IFMT fmt_str14b = {
842 16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
843 };
844
845 static const CGEN_IFMT fmt_str15 = {
846 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
847 };
848
849 static const CGEN_IFMT fmt_str15gr = {
850 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
851 };
852
853 static const CGEN_IFMT fmt_str15dr = {
854 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
855 };
856
857 static const CGEN_IFMT fmt_str15ps = {
858 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
859 };
860
861 static const CGEN_IFMT fmt_mov = {
862 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
863 };
864
865 static const CGEN_IFMT fmt_movdr = {
866 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
867 };
868
869 static const CGEN_IFMT fmt_movps = {
870 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
871 };
872
873 static const CGEN_IFMT fmt_mov2dr = {
874 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
875 };
876
877 static const CGEN_IFMT fmt_mov2ps = {
878 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
879 };
880
881 static const CGEN_IFMT fmt_jmp = {
882 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
883 };
884
885 static const CGEN_IFMT fmt_callr = {
886 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
887 };
888
889 static const CGEN_IFMT fmt_call = {
890 16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
891 };
892
893 static const CGEN_IFMT fmt_ret = {
894 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
895 };
896
897 static const CGEN_IFMT fmt_int = {
898 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
899 };
900
901 static const CGEN_IFMT fmt_inte = {
902 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
903 };
904
905 static const CGEN_IFMT fmt_reti = {
906 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
907 };
908
909 static const CGEN_IFMT fmt_brad = {
910 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
911 };
912
913 static const CGEN_IFMT fmt_beqd = {
914 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
915 };
916
917 static const CGEN_IFMT fmt_bcd = {
918 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
919 };
920
921 static const CGEN_IFMT fmt_bnd = {
922 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
923 };
924
925 static const CGEN_IFMT fmt_bvd = {
926 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
927 };
928
929 static const CGEN_IFMT fmt_bltd = {
930 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
931 };
932
933 static const CGEN_IFMT fmt_bled = {
934 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
935 };
936
937 static const CGEN_IFMT fmt_blsd = {
938 16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
939 };
940
941 static const CGEN_IFMT fmt_dmovr13 = {
942 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
943 };
944
945 static const CGEN_IFMT fmt_dmovr13h = {
946 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
947 };
948
949 static const CGEN_IFMT fmt_dmovr13b = {
950 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
951 };
952
953 static const CGEN_IFMT fmt_dmovr13pi = {
954 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
955 };
956
957 static const CGEN_IFMT fmt_dmovr13pih = {
958 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
959 };
960
961 static const CGEN_IFMT fmt_dmovr13pib = {
962 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
963 };
964
965 static const CGEN_IFMT fmt_dmovr15pi = {
966 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
967 };
968
969 static const CGEN_IFMT fmt_dmov2r13 = {
970 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
971 };
972
973 static const CGEN_IFMT fmt_dmov2r13h = {
974 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
975 };
976
977 static const CGEN_IFMT fmt_dmov2r13b = {
978 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
979 };
980
981 static const CGEN_IFMT fmt_dmov2r13pi = {
982 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
983 };
984
985 static const CGEN_IFMT fmt_dmov2r13pih = {
986 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
987 };
988
989 static const CGEN_IFMT fmt_dmov2r13pib = {
990 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
991 };
992
993 static const CGEN_IFMT fmt_dmov2r15pd = {
994 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
995 };
996
997 static const CGEN_IFMT fmt_ldres = {
998 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
999 };
1000
1001 static const CGEN_IFMT fmt_copop = {
1002 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
1003 };
1004
1005 static const CGEN_IFMT fmt_copld = {
1006 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
1007 };
1008
1009 static const CGEN_IFMT fmt_copst = {
1010 16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
1011 };
1012
1013 static const CGEN_IFMT fmt_nop = {
1014 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1015 };
1016
1017 static const CGEN_IFMT fmt_andccr = {
1018 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1019 };
1020
1021 static const CGEN_IFMT fmt_stilm = {
1022 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
1023 };
1024
1025 static const CGEN_IFMT fmt_addsp = {
1026 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
1027 };
1028
1029 static const CGEN_IFMT fmt_extsb = {
1030 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1031 };
1032
1033 static const CGEN_IFMT fmt_extub = {
1034 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1035 };
1036
1037 static const CGEN_IFMT fmt_extsh = {
1038 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1039 };
1040
1041 static const CGEN_IFMT fmt_extuh = {
1042 16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
1043 };
1044
1045 static const CGEN_IFMT fmt_ldm0 = {
1046 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 }
1047 };
1048
1049 static const CGEN_IFMT fmt_ldm1 = {
1050 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 }
1051 };
1052
1053 static const CGEN_IFMT fmt_stm0 = {
1054 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 }
1055 };
1056
1057 static const CGEN_IFMT fmt_stm1 = {
1058 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 }
1059 };
1060
1061 static const CGEN_IFMT fmt_enter = {
1062 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
1063 };
1064
1065 static const CGEN_IFMT fmt_leave = {
1066 16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
1067 };
1068
1069 static const CGEN_IFMT fmt_xchb = {
1070 16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
1071 };
1072
1073 #undef F
1074
1075 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1076 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1077 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1078
1079 /* The instruction table.
1080 This is currently non-static because the simulator accesses it
1081 directly. */
1082
1083 const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
1084 {
1085 /* Special null first entry.
1086 A `num' value of zero is thus invalid.
1087 Also, the special `invalid' insn resides here. */
1088 { { 0 }, 0 },
1089 /* add $Rj,$Ri */
1090 {
1091 { 1, 1, 1, 1 },
1092 FR30_INSN_ADD, "add", "add",
1093 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1094 & fmt_add, { 0xa600 },
1095 (PTR) 0,
1096 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1097 },
1098 /* add $u4,$Ri */
1099 {
1100 { 1, 1, 1, 1 },
1101 FR30_INSN_ADDI, "addi", "add",
1102 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1103 & fmt_addi, { 0xa400 },
1104 (PTR) 0,
1105 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1106 },
1107 /* add2 $m4,$Ri */
1108 {
1109 { 1, 1, 1, 1 },
1110 FR30_INSN_ADD2, "add2", "add2",
1111 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1112 & fmt_add2, { 0xa500 },
1113 (PTR) 0,
1114 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1115 },
1116 /* addc $Rj,$Ri */
1117 {
1118 { 1, 1, 1, 1 },
1119 FR30_INSN_ADDC, "addc", "addc",
1120 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1121 & fmt_addc, { 0xa700 },
1122 (PTR) 0,
1123 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1124 },
1125 /* addn $Rj,$Ri */
1126 {
1127 { 1, 1, 1, 1 },
1128 FR30_INSN_ADDN, "addn", "addn",
1129 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1130 & fmt_addn, { 0xa200 },
1131 (PTR) 0,
1132 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1133 },
1134 /* addn $u4,$Ri */
1135 {
1136 { 1, 1, 1, 1 },
1137 FR30_INSN_ADDNI, "addni", "addn",
1138 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1139 & fmt_addni, { 0xa000 },
1140 (PTR) 0,
1141 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1142 },
1143 /* addn2 $m4,$Ri */
1144 {
1145 { 1, 1, 1, 1 },
1146 FR30_INSN_ADDN2, "addn2", "addn2",
1147 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1148 & fmt_addn2, { 0xa100 },
1149 (PTR) 0,
1150 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1151 },
1152 /* sub $Rj,$Ri */
1153 {
1154 { 1, 1, 1, 1 },
1155 FR30_INSN_SUB, "sub", "sub",
1156 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1157 & fmt_add, { 0xac00 },
1158 (PTR) 0,
1159 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1160 },
1161 /* subc $Rj,$Ri */
1162 {
1163 { 1, 1, 1, 1 },
1164 FR30_INSN_SUBC, "subc", "subc",
1165 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1166 & fmt_addc, { 0xad00 },
1167 (PTR) 0,
1168 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1169 },
1170 /* subn $Rj,$Ri */
1171 {
1172 { 1, 1, 1, 1 },
1173 FR30_INSN_SUBN, "subn", "subn",
1174 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1175 & fmt_addn, { 0xae00 },
1176 (PTR) 0,
1177 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1178 },
1179 /* cmp $Rj,$Ri */
1180 {
1181 { 1, 1, 1, 1 },
1182 FR30_INSN_CMP, "cmp", "cmp",
1183 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1184 & fmt_cmp, { 0xaa00 },
1185 (PTR) 0,
1186 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1187 },
1188 /* cmp $u4,$Ri */
1189 {
1190 { 1, 1, 1, 1 },
1191 FR30_INSN_CMPI, "cmpi", "cmp",
1192 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1193 & fmt_cmpi, { 0xa800 },
1194 (PTR) 0,
1195 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1196 },
1197 /* cmp2 $m4,$Ri */
1198 {
1199 { 1, 1, 1, 1 },
1200 FR30_INSN_CMP2, "cmp2", "cmp2",
1201 { { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
1202 & fmt_cmp2, { 0xa900 },
1203 (PTR) 0,
1204 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1205 },
1206 /* and $Rj,$Ri */
1207 {
1208 { 1, 1, 1, 1 },
1209 FR30_INSN_AND, "and", "and",
1210 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1211 & fmt_and, { 0x8200 },
1212 (PTR) 0,
1213 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1214 },
1215 /* or $Rj,$Ri */
1216 {
1217 { 1, 1, 1, 1 },
1218 FR30_INSN_OR, "or", "or",
1219 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1220 & fmt_and, { 0x9200 },
1221 (PTR) 0,
1222 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1223 },
1224 /* eor $Rj,$Ri */
1225 {
1226 { 1, 1, 1, 1 },
1227 FR30_INSN_EOR, "eor", "eor",
1228 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1229 & fmt_and, { 0x9a00 },
1230 (PTR) 0,
1231 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1232 },
1233 /* and $Rj,@$Ri */
1234 {
1235 { 1, 1, 1, 1 },
1236 FR30_INSN_ANDM, "andm", "and",
1237 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1238 & fmt_andm, { 0x8400 },
1239 (PTR) 0,
1240 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1241 },
1242 /* andh $Rj,@$Ri */
1243 {
1244 { 1, 1, 1, 1 },
1245 FR30_INSN_ANDH, "andh", "andh",
1246 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1247 & fmt_andh, { 0x8500 },
1248 (PTR) 0,
1249 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1250 },
1251 /* andb $Rj,@$Ri */
1252 {
1253 { 1, 1, 1, 1 },
1254 FR30_INSN_ANDB, "andb", "andb",
1255 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1256 & fmt_andb, { 0x8600 },
1257 (PTR) 0,
1258 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1259 },
1260 /* or $Rj,@$Ri */
1261 {
1262 { 1, 1, 1, 1 },
1263 FR30_INSN_ORM, "orm", "or",
1264 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1265 & fmt_andm, { 0x9400 },
1266 (PTR) 0,
1267 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1268 },
1269 /* orh $Rj,@$Ri */
1270 {
1271 { 1, 1, 1, 1 },
1272 FR30_INSN_ORH, "orh", "orh",
1273 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1274 & fmt_andh, { 0x9500 },
1275 (PTR) 0,
1276 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1277 },
1278 /* orb $Rj,@$Ri */
1279 {
1280 { 1, 1, 1, 1 },
1281 FR30_INSN_ORB, "orb", "orb",
1282 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1283 & fmt_andb, { 0x9600 },
1284 (PTR) 0,
1285 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1286 },
1287 /* eor $Rj,@$Ri */
1288 {
1289 { 1, 1, 1, 1 },
1290 FR30_INSN_EORM, "eorm", "eor",
1291 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1292 & fmt_andm, { 0x9c00 },
1293 (PTR) 0,
1294 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1295 },
1296 /* eorh $Rj,@$Ri */
1297 {
1298 { 1, 1, 1, 1 },
1299 FR30_INSN_EORH, "eorh", "eorh",
1300 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1301 & fmt_andh, { 0x9d00 },
1302 (PTR) 0,
1303 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1304 },
1305 /* eorb $Rj,@$Ri */
1306 {
1307 { 1, 1, 1, 1 },
1308 FR30_INSN_EORB, "eorb", "eorb",
1309 { { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
1310 & fmt_andb, { 0x9e00 },
1311 (PTR) 0,
1312 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1313 },
1314 /* bandl $u4,@$Ri */
1315 {
1316 { 1, 1, 1, 1 },
1317 FR30_INSN_BANDL, "bandl", "bandl",
1318 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1319 & fmt_bandl, { 0x8000 },
1320 (PTR) 0,
1321 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1322 },
1323 /* borl $u4,@$Ri */
1324 {
1325 { 1, 1, 1, 1 },
1326 FR30_INSN_BORL, "borl", "borl",
1327 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1328 & fmt_bandl, { 0x9000 },
1329 (PTR) 0,
1330 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1331 },
1332 /* beorl $u4,@$Ri */
1333 {
1334 { 1, 1, 1, 1 },
1335 FR30_INSN_BEORL, "beorl", "beorl",
1336 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1337 & fmt_bandl, { 0x9800 },
1338 (PTR) 0,
1339 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1340 },
1341 /* bandh $u4,@$Ri */
1342 {
1343 { 1, 1, 1, 1 },
1344 FR30_INSN_BANDH, "bandh", "bandh",
1345 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1346 & fmt_bandl, { 0x8100 },
1347 (PTR) 0,
1348 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1349 },
1350 /* borh $u4,@$Ri */
1351 {
1352 { 1, 1, 1, 1 },
1353 FR30_INSN_BORH, "borh", "borh",
1354 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1355 & fmt_bandl, { 0x9100 },
1356 (PTR) 0,
1357 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1358 },
1359 /* beorh $u4,@$Ri */
1360 {
1361 { 1, 1, 1, 1 },
1362 FR30_INSN_BEORH, "beorh", "beorh",
1363 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1364 & fmt_bandl, { 0x9900 },
1365 (PTR) 0,
1366 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1367 },
1368 /* btstl $u4,@$Ri */
1369 {
1370 { 1, 1, 1, 1 },
1371 FR30_INSN_BTSTL, "btstl", "btstl",
1372 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1373 & fmt_btstl, { 0x8800 },
1374 (PTR) 0,
1375 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1376 },
1377 /* btsth $u4,@$Ri */
1378 {
1379 { 1, 1, 1, 1 },
1380 FR30_INSN_BTSTH, "btsth", "btsth",
1381 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
1382 & fmt_btstl, { 0x8900 },
1383 (PTR) 0,
1384 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1385 },
1386 /* mul $Rj,$Ri */
1387 {
1388 { 1, 1, 1, 1 },
1389 FR30_INSN_MUL, "mul", "mul",
1390 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1391 & fmt_mul, { 0xaf00 },
1392 (PTR) 0,
1393 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1394 },
1395 /* mulu $Rj,$Ri */
1396 {
1397 { 1, 1, 1, 1 },
1398 FR30_INSN_MULU, "mulu", "mulu",
1399 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1400 & fmt_mulu, { 0xab00 },
1401 (PTR) 0,
1402 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1403 },
1404 /* mulh $Rj,$Ri */
1405 {
1406 { 1, 1, 1, 1 },
1407 FR30_INSN_MULH, "mulh", "mulh",
1408 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1409 & fmt_mulh, { 0xbf00 },
1410 (PTR) 0,
1411 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1412 },
1413 /* muluh $Rj,$Ri */
1414 {
1415 { 1, 1, 1, 1 },
1416 FR30_INSN_MULUH, "muluh", "muluh",
1417 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1418 & fmt_mulh, { 0xbb00 },
1419 (PTR) 0,
1420 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1421 },
1422 /* div0s $Ri */
1423 {
1424 { 1, 1, 1, 1 },
1425 FR30_INSN_DIV0S, "div0s", "div0s",
1426 { { MNEM, ' ', OP (RI), 0 } },
1427 & fmt_div0s, { 0x9740 },
1428 (PTR) 0,
1429 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1430 },
1431 /* div0u $Ri */
1432 {
1433 { 1, 1, 1, 1 },
1434 FR30_INSN_DIV0U, "div0u", "div0u",
1435 { { MNEM, ' ', OP (RI), 0 } },
1436 & fmt_div0u, { 0x9750 },
1437 (PTR) 0,
1438 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1439 },
1440 /* div1 $Ri */
1441 {
1442 { 1, 1, 1, 1 },
1443 FR30_INSN_DIV1, "div1", "div1",
1444 { { MNEM, ' ', OP (RI), 0 } },
1445 & fmt_div1, { 0x9760 },
1446 (PTR) 0,
1447 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1448 },
1449 /* div2 $Ri */
1450 {
1451 { 1, 1, 1, 1 },
1452 FR30_INSN_DIV2, "div2", "div2",
1453 { { MNEM, ' ', OP (RI), 0 } },
1454 & fmt_div2, { 0x9770 },
1455 (PTR) 0,
1456 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1457 },
1458 /* div3 */
1459 {
1460 { 1, 1, 1, 1 },
1461 FR30_INSN_DIV3, "div3", "div3",
1462 { { MNEM, 0 } },
1463 & fmt_div3, { 0x9f60 },
1464 (PTR) 0,
1465 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1466 },
1467 /* div4s */
1468 {
1469 { 1, 1, 1, 1 },
1470 FR30_INSN_DIV4S, "div4s", "div4s",
1471 { { MNEM, 0 } },
1472 & fmt_div4s, { 0x9f70 },
1473 (PTR) 0,
1474 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1475 },
1476 /* lsl $Rj,$Ri */
1477 {
1478 { 1, 1, 1, 1 },
1479 FR30_INSN_LSL, "lsl", "lsl",
1480 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1481 & fmt_lsl, { 0xb600 },
1482 (PTR) 0,
1483 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1484 },
1485 /* lsl $u4,$Ri */
1486 {
1487 { 1, 1, 1, 1 },
1488 FR30_INSN_LSLI, "lsli", "lsl",
1489 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1490 & fmt_lsli, { 0xb400 },
1491 (PTR) 0,
1492 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1493 },
1494 /* lsl2 $u4,$Ri */
1495 {
1496 { 1, 1, 1, 1 },
1497 FR30_INSN_LSL2, "lsl2", "lsl2",
1498 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1499 & fmt_lsli, { 0xb500 },
1500 (PTR) 0,
1501 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1502 },
1503 /* lsr $Rj,$Ri */
1504 {
1505 { 1, 1, 1, 1 },
1506 FR30_INSN_LSR, "lsr", "lsr",
1507 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1508 & fmt_lsl, { 0xb200 },
1509 (PTR) 0,
1510 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1511 },
1512 /* lsr $u4,$Ri */
1513 {
1514 { 1, 1, 1, 1 },
1515 FR30_INSN_LSRI, "lsri", "lsr",
1516 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1517 & fmt_lsli, { 0xb000 },
1518 (PTR) 0,
1519 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1520 },
1521 /* lsr2 $u4,$Ri */
1522 {
1523 { 1, 1, 1, 1 },
1524 FR30_INSN_LSR2, "lsr2", "lsr2",
1525 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1526 & fmt_lsli, { 0xb100 },
1527 (PTR) 0,
1528 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1529 },
1530 /* asr $Rj,$Ri */
1531 {
1532 { 1, 1, 1, 1 },
1533 FR30_INSN_ASR, "asr", "asr",
1534 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1535 & fmt_lsl, { 0xba00 },
1536 (PTR) 0,
1537 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1538 },
1539 /* asr $u4,$Ri */
1540 {
1541 { 1, 1, 1, 1 },
1542 FR30_INSN_ASRI, "asri", "asr",
1543 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1544 & fmt_lsli, { 0xb800 },
1545 (PTR) 0,
1546 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1547 },
1548 /* asr2 $u4,$Ri */
1549 {
1550 { 1, 1, 1, 1 },
1551 FR30_INSN_ASR2, "asr2", "asr2",
1552 { { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
1553 & fmt_lsli, { 0xb900 },
1554 (PTR) 0,
1555 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1556 },
1557 /* ldi:8 $i8,$Ri */
1558 {
1559 { 1, 1, 1, 1 },
1560 FR30_INSN_LDI8, "ldi8", "ldi:8",
1561 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
1562 & fmt_ldi8, { 0xc000 },
1563 (PTR) 0,
1564 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1565 },
1566 /* ldi:20 $i20,$Ri */
1567 {
1568 { 1, 1, 1, 1 },
1569 FR30_INSN_LDI20, "ldi20", "ldi:20",
1570 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
1571 & fmt_ldi20, { 0x9b00 },
1572 (PTR) 0,
1573 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1574 },
1575 /* ldi:32 $i32,$Ri */
1576 {
1577 { 1, 1, 1, 1 },
1578 FR30_INSN_LDI32, "ldi32", "ldi:32",
1579 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
1580 & fmt_ldi32, { 0x9f80 },
1581 (PTR) 0,
1582 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1583 },
1584 /* ld @$Rj,$Ri */
1585 {
1586 { 1, 1, 1, 1 },
1587 FR30_INSN_LD, "ld", "ld",
1588 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1589 & fmt_ld, { 0x400 },
1590 (PTR) 0,
1591 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1592 },
1593 /* lduh @$Rj,$Ri */
1594 {
1595 { 1, 1, 1, 1 },
1596 FR30_INSN_LDUH, "lduh", "lduh",
1597 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1598 & fmt_lduh, { 0x500 },
1599 (PTR) 0,
1600 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1601 },
1602 /* ldub @$Rj,$Ri */
1603 {
1604 { 1, 1, 1, 1 },
1605 FR30_INSN_LDUB, "ldub", "ldub",
1606 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
1607 & fmt_ldub, { 0x600 },
1608 (PTR) 0,
1609 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1610 },
1611 /* ld @($R13,$Rj),$Ri */
1612 {
1613 { 1, 1, 1, 1 },
1614 FR30_INSN_LDR13, "ldr13", "ld",
1615 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1616 & fmt_ldr13, { 0x0 },
1617 (PTR) 0,
1618 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1619 },
1620 /* lduh @($R13,$Rj),$Ri */
1621 {
1622 { 1, 1, 1, 1 },
1623 FR30_INSN_LDR13UH, "ldr13uh", "lduh",
1624 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1625 & fmt_ldr13uh, { 0x100 },
1626 (PTR) 0,
1627 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1628 },
1629 /* ldub @($R13,$Rj),$Ri */
1630 {
1631 { 1, 1, 1, 1 },
1632 FR30_INSN_LDR13UB, "ldr13ub", "ldub",
1633 { { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
1634 & fmt_ldr13ub, { 0x200 },
1635 (PTR) 0,
1636 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1637 },
1638 /* ld @($R14,$disp10),$Ri */
1639 {
1640 { 1, 1, 1, 1 },
1641 FR30_INSN_LDR14, "ldr14", "ld",
1642 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
1643 & fmt_ldr14, { 0x2000 },
1644 (PTR) 0,
1645 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1646 },
1647 /* lduh @($R14,$disp9),$Ri */
1648 {
1649 { 1, 1, 1, 1 },
1650 FR30_INSN_LDR14UH, "ldr14uh", "lduh",
1651 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
1652 & fmt_ldr14uh, { 0x4000 },
1653 (PTR) 0,
1654 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1655 },
1656 /* ldub @($R14,$disp8),$Ri */
1657 {
1658 { 1, 1, 1, 1 },
1659 FR30_INSN_LDR14UB, "ldr14ub", "ldub",
1660 { { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
1661 & fmt_ldr14ub, { 0x6000 },
1662 (PTR) 0,
1663 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1664 },
1665 /* ld @($R15,$udisp6),$Ri */
1666 {
1667 { 1, 1, 1, 1 },
1668 FR30_INSN_LDR15, "ldr15", "ld",
1669 { { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
1670 & fmt_ldr15, { 0x300 },
1671 (PTR) 0,
1672 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1673 },
1674 /* ld @$R15+,$Ri */
1675 {
1676 { 1, 1, 1, 1 },
1677 FR30_INSN_LDR15GR, "ldr15gr", "ld",
1678 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
1679 & fmt_ldr15gr, { 0x700 },
1680 (PTR) 0,
1681 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1682 },
1683 /* ld @$R15+,$Rs2 */
1684 {
1685 { 1, 1, 1, 1 },
1686 FR30_INSN_LDR15DR, "ldr15dr", "ld",
1687 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
1688 & fmt_ldr15dr, { 0x780 },
1689 (PTR) 0,
1690 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1691 },
1692 /* ld @$R15+,$ps */
1693 {
1694 { 1, 1, 1, 1 },
1695 FR30_INSN_LDR15PS, "ldr15ps", "ld",
1696 { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
1697 & fmt_ldr15ps, { 0x790 },
1698 (PTR) 0,
1699 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
1700 },
1701 /* st $Ri,@$Rj */
1702 {
1703 { 1, 1, 1, 1 },
1704 FR30_INSN_ST, "st", "st",
1705 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1706 & fmt_st, { 0x1400 },
1707 (PTR) 0,
1708 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1709 },
1710 /* sth $Ri,@$Rj */
1711 {
1712 { 1, 1, 1, 1 },
1713 FR30_INSN_STH, "sth", "sth",
1714 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1715 & fmt_sth, { 0x1500 },
1716 (PTR) 0,
1717 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1718 },
1719 /* stb $Ri,@$Rj */
1720 {
1721 { 1, 1, 1, 1 },
1722 FR30_INSN_STB, "stb", "stb",
1723 { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
1724 & fmt_stb, { 0x1600 },
1725 (PTR) 0,
1726 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1727 },
1728 /* st $Ri,@($R13,$Rj) */
1729 {
1730 { 1, 1, 1, 1 },
1731 FR30_INSN_STR13, "str13", "st",
1732 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1733 & fmt_str13, { 0x1000 },
1734 (PTR) 0,
1735 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1736 },
1737 /* sth $Ri,@($R13,$Rj) */
1738 {
1739 { 1, 1, 1, 1 },
1740 FR30_INSN_STR13H, "str13h", "sth",
1741 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1742 & fmt_str13h, { 0x1100 },
1743 (PTR) 0,
1744 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1745 },
1746 /* stb $Ri,@($R13,$Rj) */
1747 {
1748 { 1, 1, 1, 1 },
1749 FR30_INSN_STR13B, "str13b", "stb",
1750 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
1751 & fmt_str13b, { 0x1200 },
1752 (PTR) 0,
1753 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1754 },
1755 /* st $Ri,@($R14,$disp10) */
1756 {
1757 { 1, 1, 1, 1 },
1758 FR30_INSN_STR14, "str14", "st",
1759 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
1760 & fmt_str14, { 0x3000 },
1761 (PTR) 0,
1762 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1763 },
1764 /* sth $Ri,@($R14,$disp9) */
1765 {
1766 { 1, 1, 1, 1 },
1767 FR30_INSN_STR14H, "str14h", "sth",
1768 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
1769 & fmt_str14h, { 0x5000 },
1770 (PTR) 0,
1771 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1772 },
1773 /* stb $Ri,@($R14,$disp8) */
1774 {
1775 { 1, 1, 1, 1 },
1776 FR30_INSN_STR14B, "str14b", "stb",
1777 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
1778 & fmt_str14b, { 0x7000 },
1779 (PTR) 0,
1780 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1781 },
1782 /* st $Ri,@($R15,$udisp6) */
1783 {
1784 { 1, 1, 1, 1 },
1785 FR30_INSN_STR15, "str15", "st",
1786 { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
1787 & fmt_str15, { 0x1300 },
1788 (PTR) 0,
1789 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1790 },
1791 /* st $Ri,@-$R15 */
1792 {
1793 { 1, 1, 1, 1 },
1794 FR30_INSN_STR15GR, "str15gr", "st",
1795 { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
1796 & fmt_str15gr, { 0x1700 },
1797 (PTR) 0,
1798 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1799 },
1800 /* st $Rs2,@-$R15 */
1801 {
1802 { 1, 1, 1, 1 },
1803 FR30_INSN_STR15DR, "str15dr", "st",
1804 { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
1805 & fmt_str15dr, { 0x1780 },
1806 (PTR) 0,
1807 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1808 },
1809 /* st $ps,@-$R15 */
1810 {
1811 { 1, 1, 1, 1 },
1812 FR30_INSN_STR15PS, "str15ps", "st",
1813 { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
1814 & fmt_str15ps, { 0x1790 },
1815 (PTR) 0,
1816 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1817 },
1818 /* mov $Rj,$Ri */
1819 {
1820 { 1, 1, 1, 1 },
1821 FR30_INSN_MOV, "mov", "mov",
1822 { { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
1823 & fmt_mov, { 0x8b00 },
1824 (PTR) 0,
1825 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1826 },
1827 /* mov $Rs1,$Ri */
1828 {
1829 { 1, 1, 1, 1 },
1830 FR30_INSN_MOVDR, "movdr", "mov",
1831 { { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
1832 & fmt_movdr, { 0xb700 },
1833 (PTR) 0,
1834 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1835 },
1836 /* mov $ps,$Ri */
1837 {
1838 { 1, 1, 1, 1 },
1839 FR30_INSN_MOVPS, "movps", "mov",
1840 { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
1841 & fmt_movps, { 0x1710 },
1842 (PTR) 0,
1843 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1844 },
1845 /* mov $Ri,$Rs1 */
1846 {
1847 { 1, 1, 1, 1 },
1848 FR30_INSN_MOV2DR, "mov2dr", "mov",
1849 { { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
1850 & fmt_mov2dr, { 0xb300 },
1851 (PTR) 0,
1852 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1853 },
1854 /* mov $Ri,$ps */
1855 {
1856 { 1, 1, 1, 1 },
1857 FR30_INSN_MOV2PS, "mov2ps", "mov",
1858 { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
1859 & fmt_mov2ps, { 0x710 },
1860 (PTR) 0,
1861 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1862 },
1863 /* jmp @$Ri */
1864 {
1865 { 1, 1, 1, 1 },
1866 FR30_INSN_JMP, "jmp", "jmp",
1867 { { MNEM, ' ', '@', OP (RI), 0 } },
1868 & fmt_jmp, { 0x9700 },
1869 (PTR) 0,
1870 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1871 },
1872 /* jmp:d @$Ri */
1873 {
1874 { 1, 1, 1, 1 },
1875 FR30_INSN_JMPD, "jmpd", "jmp:d",
1876 { { MNEM, ' ', '@', OP (RI), 0 } },
1877 & fmt_jmp, { 0x9f00 },
1878 (PTR) 0,
1879 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1880 },
1881 /* call @$Ri */
1882 {
1883 { 1, 1, 1, 1 },
1884 FR30_INSN_CALLR, "callr", "call",
1885 { { MNEM, ' ', '@', OP (RI), 0 } },
1886 & fmt_callr, { 0x9710 },
1887 (PTR) 0,
1888 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1889 },
1890 /* call:d @$Ri */
1891 {
1892 { 1, 1, 1, 1 },
1893 FR30_INSN_CALLRD, "callrd", "call:d",
1894 { { MNEM, ' ', '@', OP (RI), 0 } },
1895 & fmt_callr, { 0x9f10 },
1896 (PTR) 0,
1897 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1898 },
1899 /* call $label12 */
1900 {
1901 { 1, 1, 1, 1 },
1902 FR30_INSN_CALL, "call", "call",
1903 { { MNEM, ' ', OP (LABEL12), 0 } },
1904 & fmt_call, { 0xd000 },
1905 (PTR) 0,
1906 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1907 },
1908 /* call:d $label12 */
1909 {
1910 { 1, 1, 1, 1 },
1911 FR30_INSN_CALLD, "calld", "call:d",
1912 { { MNEM, ' ', OP (LABEL12), 0 } },
1913 & fmt_call, { 0xd800 },
1914 (PTR) 0,
1915 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1916 },
1917 /* ret */
1918 {
1919 { 1, 1, 1, 1 },
1920 FR30_INSN_RET, "ret", "ret",
1921 { { MNEM, 0 } },
1922 & fmt_ret, { 0x9720 },
1923 (PTR) 0,
1924 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1925 },
1926 /* ret:d */
1927 {
1928 { 1, 1, 1, 1 },
1929 FR30_INSN_RET_D, "ret:d", "ret:d",
1930 { { MNEM, 0 } },
1931 & fmt_ret, { 0x9f20 },
1932 (PTR) 0,
1933 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1934 },
1935 /* int $u8 */
1936 {
1937 { 1, 1, 1, 1 },
1938 FR30_INSN_INT, "int", "int",
1939 { { MNEM, ' ', OP (U8), 0 } },
1940 & fmt_int, { 0x1f00 },
1941 (PTR) 0,
1942 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1943 },
1944 /* inte */
1945 {
1946 { 1, 1, 1, 1 },
1947 FR30_INSN_INTE, "inte", "inte",
1948 { { MNEM, 0 } },
1949 & fmt_inte, { 0x9f30 },
1950 (PTR) 0,
1951 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1952 },
1953 /* reti */
1954 {
1955 { 1, 1, 1, 1 },
1956 FR30_INSN_RETI, "reti", "reti",
1957 { { MNEM, 0 } },
1958 & fmt_reti, { 0x9730 },
1959 (PTR) 0,
1960 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
1961 },
1962 /* bra:d $label9 */
1963 {
1964 { 1, 1, 1, 1 },
1965 FR30_INSN_BRAD, "brad", "bra:d",
1966 { { MNEM, ' ', OP (LABEL9), 0 } },
1967 & fmt_brad, { 0xf000 },
1968 (PTR) 0,
1969 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1970 },
1971 /* bra $label9 */
1972 {
1973 { 1, 1, 1, 1 },
1974 FR30_INSN_BRA, "bra", "bra",
1975 { { MNEM, ' ', OP (LABEL9), 0 } },
1976 & fmt_brad, { 0xe000 },
1977 (PTR) 0,
1978 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1979 },
1980 /* bno:d $label9 */
1981 {
1982 { 1, 1, 1, 1 },
1983 FR30_INSN_BNOD, "bnod", "bno:d",
1984 { { MNEM, ' ', OP (LABEL9), 0 } },
1985 & fmt_brad, { 0xf100 },
1986 (PTR) 0,
1987 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
1988 },
1989 /* bno $label9 */
1990 {
1991 { 1, 1, 1, 1 },
1992 FR30_INSN_BNO, "bno", "bno",
1993 { { MNEM, ' ', OP (LABEL9), 0 } },
1994 & fmt_brad, { 0xe100 },
1995 (PTR) 0,
1996 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1997 },
1998 /* beq:d $label9 */
1999 {
2000 { 1, 1, 1, 1 },
2001 FR30_INSN_BEQD, "beqd", "beq:d",
2002 { { MNEM, ' ', OP (LABEL9), 0 } },
2003 & fmt_beqd, { 0xf200 },
2004 (PTR) 0,
2005 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2006 },
2007 /* beq $label9 */
2008 {
2009 { 1, 1, 1, 1 },
2010 FR30_INSN_BEQ, "beq", "beq",
2011 { { MNEM, ' ', OP (LABEL9), 0 } },
2012 & fmt_beqd, { 0xe200 },
2013 (PTR) 0,
2014 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2015 },
2016 /* bne:d $label9 */
2017 {
2018 { 1, 1, 1, 1 },
2019 FR30_INSN_BNED, "bned", "bne:d",
2020 { { MNEM, ' ', OP (LABEL9), 0 } },
2021 & fmt_beqd, { 0xf300 },
2022 (PTR) 0,
2023 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2024 },
2025 /* bne $label9 */
2026 {
2027 { 1, 1, 1, 1 },
2028 FR30_INSN_BNE, "bne", "bne",
2029 { { MNEM, ' ', OP (LABEL9), 0 } },
2030 & fmt_beqd, { 0xe300 },
2031 (PTR) 0,
2032 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2033 },
2034 /* bc:d $label9 */
2035 {
2036 { 1, 1, 1, 1 },
2037 FR30_INSN_BCD, "bcd", "bc:d",
2038 { { MNEM, ' ', OP (LABEL9), 0 } },
2039 & fmt_bcd, { 0xf400 },
2040 (PTR) 0,
2041 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2042 },
2043 /* bc $label9 */
2044 {
2045 { 1, 1, 1, 1 },
2046 FR30_INSN_BC, "bc", "bc",
2047 { { MNEM, ' ', OP (LABEL9), 0 } },
2048 & fmt_bcd, { 0xe400 },
2049 (PTR) 0,
2050 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2051 },
2052 /* bnc:d $label9 */
2053 {
2054 { 1, 1, 1, 1 },
2055 FR30_INSN_BNCD, "bncd", "bnc:d",
2056 { { MNEM, ' ', OP (LABEL9), 0 } },
2057 & fmt_bcd, { 0xf500 },
2058 (PTR) 0,
2059 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2060 },
2061 /* bnc $label9 */
2062 {
2063 { 1, 1, 1, 1 },
2064 FR30_INSN_BNC, "bnc", "bnc",
2065 { { MNEM, ' ', OP (LABEL9), 0 } },
2066 & fmt_bcd, { 0xe500 },
2067 (PTR) 0,
2068 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2069 },
2070 /* bn:d $label9 */
2071 {
2072 { 1, 1, 1, 1 },
2073 FR30_INSN_BND, "bnd", "bn:d",
2074 { { MNEM, ' ', OP (LABEL9), 0 } },
2075 & fmt_bnd, { 0xf600 },
2076 (PTR) 0,
2077 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2078 },
2079 /* bn $label9 */
2080 {
2081 { 1, 1, 1, 1 },
2082 FR30_INSN_BN, "bn", "bn",
2083 { { MNEM, ' ', OP (LABEL9), 0 } },
2084 & fmt_bnd, { 0xe600 },
2085 (PTR) 0,
2086 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2087 },
2088 /* bp:d $label9 */
2089 {
2090 { 1, 1, 1, 1 },
2091 FR30_INSN_BPD, "bpd", "bp:d",
2092 { { MNEM, ' ', OP (LABEL9), 0 } },
2093 & fmt_bnd, { 0xf700 },
2094 (PTR) 0,
2095 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2096 },
2097 /* bp $label9 */
2098 {
2099 { 1, 1, 1, 1 },
2100 FR30_INSN_BP, "bp", "bp",
2101 { { MNEM, ' ', OP (LABEL9), 0 } },
2102 & fmt_bnd, { 0xe700 },
2103 (PTR) 0,
2104 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2105 },
2106 /* bv:d $label9 */
2107 {
2108 { 1, 1, 1, 1 },
2109 FR30_INSN_BVD, "bvd", "bv:d",
2110 { { MNEM, ' ', OP (LABEL9), 0 } },
2111 & fmt_bvd, { 0xf800 },
2112 (PTR) 0,
2113 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2114 },
2115 /* bv $label9 */
2116 {
2117 { 1, 1, 1, 1 },
2118 FR30_INSN_BV, "bv", "bv",
2119 { { MNEM, ' ', OP (LABEL9), 0 } },
2120 & fmt_bvd, { 0xe800 },
2121 (PTR) 0,
2122 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2123 },
2124 /* bnv:d $label9 */
2125 {
2126 { 1, 1, 1, 1 },
2127 FR30_INSN_BNVD, "bnvd", "bnv:d",
2128 { { MNEM, ' ', OP (LABEL9), 0 } },
2129 & fmt_bvd, { 0xf900 },
2130 (PTR) 0,
2131 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2132 },
2133 /* bnv $label9 */
2134 {
2135 { 1, 1, 1, 1 },
2136 FR30_INSN_BNV, "bnv", "bnv",
2137 { { MNEM, ' ', OP (LABEL9), 0 } },
2138 & fmt_bvd, { 0xe900 },
2139 (PTR) 0,
2140 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2141 },
2142 /* blt:d $label9 */
2143 {
2144 { 1, 1, 1, 1 },
2145 FR30_INSN_BLTD, "bltd", "blt:d",
2146 { { MNEM, ' ', OP (LABEL9), 0 } },
2147 & fmt_bltd, { 0xfa00 },
2148 (PTR) 0,
2149 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2150 },
2151 /* blt $label9 */
2152 {
2153 { 1, 1, 1, 1 },
2154 FR30_INSN_BLT, "blt", "blt",
2155 { { MNEM, ' ', OP (LABEL9), 0 } },
2156 & fmt_bltd, { 0xea00 },
2157 (PTR) 0,
2158 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2159 },
2160 /* bge:d $label9 */
2161 {
2162 { 1, 1, 1, 1 },
2163 FR30_INSN_BGED, "bged", "bge:d",
2164 { { MNEM, ' ', OP (LABEL9), 0 } },
2165 & fmt_bltd, { 0xfb00 },
2166 (PTR) 0,
2167 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2168 },
2169 /* bge $label9 */
2170 {
2171 { 1, 1, 1, 1 },
2172 FR30_INSN_BGE, "bge", "bge",
2173 { { MNEM, ' ', OP (LABEL9), 0 } },
2174 & fmt_bltd, { 0xeb00 },
2175 (PTR) 0,
2176 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2177 },
2178 /* ble:d $label9 */
2179 {
2180 { 1, 1, 1, 1 },
2181 FR30_INSN_BLED, "bled", "ble:d",
2182 { { MNEM, ' ', OP (LABEL9), 0 } },
2183 & fmt_bled, { 0xfc00 },
2184 (PTR) 0,
2185 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2186 },
2187 /* ble $label9 */
2188 {
2189 { 1, 1, 1, 1 },
2190 FR30_INSN_BLE, "ble", "ble",
2191 { { MNEM, ' ', OP (LABEL9), 0 } },
2192 & fmt_bled, { 0xec00 },
2193 (PTR) 0,
2194 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2195 },
2196 /* bgt:d $label9 */
2197 {
2198 { 1, 1, 1, 1 },
2199 FR30_INSN_BGTD, "bgtd", "bgt:d",
2200 { { MNEM, ' ', OP (LABEL9), 0 } },
2201 & fmt_bled, { 0xfd00 },
2202 (PTR) 0,
2203 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2204 },
2205 /* bgt $label9 */
2206 {
2207 { 1, 1, 1, 1 },
2208 FR30_INSN_BGT, "bgt", "bgt",
2209 { { MNEM, ' ', OP (LABEL9), 0 } },
2210 & fmt_bled, { 0xed00 },
2211 (PTR) 0,
2212 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2213 },
2214 /* bls:d $label9 */
2215 {
2216 { 1, 1, 1, 1 },
2217 FR30_INSN_BLSD, "blsd", "bls:d",
2218 { { MNEM, ' ', OP (LABEL9), 0 } },
2219 & fmt_blsd, { 0xfe00 },
2220 (PTR) 0,
2221 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2222 },
2223 /* bls $label9 */
2224 {
2225 { 1, 1, 1, 1 },
2226 FR30_INSN_BLS, "bls", "bls",
2227 { { MNEM, ' ', OP (LABEL9), 0 } },
2228 & fmt_blsd, { 0xee00 },
2229 (PTR) 0,
2230 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2231 },
2232 /* bhi:d $label9 */
2233 {
2234 { 1, 1, 1, 1 },
2235 FR30_INSN_BHID, "bhid", "bhi:d",
2236 { { MNEM, ' ', OP (LABEL9), 0 } },
2237 & fmt_blsd, { 0xff00 },
2238 (PTR) 0,
2239 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
2240 },
2241 /* bhi $label9 */
2242 {
2243 { 1, 1, 1, 1 },
2244 FR30_INSN_BHI, "bhi", "bhi",
2245 { { MNEM, ' ', OP (LABEL9), 0 } },
2246 & fmt_blsd, { 0xef00 },
2247 (PTR) 0,
2248 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
2249 },
2250 /* dmov $R13,@$dir10 */
2251 {
2252 { 1, 1, 1, 1 },
2253 FR30_INSN_DMOVR13, "dmovr13", "dmov",
2254 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
2255 & fmt_dmovr13, { 0x1800 },
2256 (PTR) 0,
2257 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2258 },
2259 /* dmovh $R13,@$dir9 */
2260 {
2261 { 1, 1, 1, 1 },
2262 FR30_INSN_DMOVR13H, "dmovr13h", "dmovh",
2263 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
2264 & fmt_dmovr13h, { 0x1900 },
2265 (PTR) 0,
2266 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2267 },
2268 /* dmovb $R13,@$dir8 */
2269 {
2270 { 1, 1, 1, 1 },
2271 FR30_INSN_DMOVR13B, "dmovr13b", "dmovb",
2272 { { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
2273 & fmt_dmovr13b, { 0x1a00 },
2274 (PTR) 0,
2275 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2276 },
2277 /* dmov @$R13+,@$dir10 */
2278 {
2279 { 1, 1, 1, 1 },
2280 FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov",
2281 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
2282 & fmt_dmovr13pi, { 0x1c00 },
2283 (PTR) 0,
2284 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2285 },
2286 /* dmovh @$R13+,@$dir9 */
2287 {
2288 { 1, 1, 1, 1 },
2289 FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh",
2290 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
2291 & fmt_dmovr13pih, { 0x1d00 },
2292 (PTR) 0,
2293 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2294 },
2295 /* dmovb @$R13+,@$dir8 */
2296 {
2297 { 1, 1, 1, 1 },
2298 FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb",
2299 { { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
2300 & fmt_dmovr13pib, { 0x1e00 },
2301 (PTR) 0,
2302 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2303 },
2304 /* dmov @$R15+,@$dir10 */
2305 {
2306 { 1, 1, 1, 1 },
2307 FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov",
2308 { { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
2309 & fmt_dmovr15pi, { 0x1b00 },
2310 (PTR) 0,
2311 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2312 },
2313 /* dmov @$dir10,$R13 */
2314 {
2315 { 1, 1, 1, 1 },
2316 FR30_INSN_DMOV2R13, "dmov2r13", "dmov",
2317 { { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
2318 & fmt_dmov2r13, { 0x800 },
2319 (PTR) 0,
2320 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2321 },
2322 /* dmovh @$dir9,$R13 */
2323 {
2324 { 1, 1, 1, 1 },
2325 FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh",
2326 { { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
2327 & fmt_dmov2r13h, { 0x900 },
2328 (PTR) 0,
2329 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2330 },
2331 /* dmovb @$dir8,$R13 */
2332 {
2333 { 1, 1, 1, 1 },
2334 FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb",
2335 { { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
2336 & fmt_dmov2r13b, { 0xa00 },
2337 (PTR) 0,
2338 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2339 },
2340 /* dmov @$dir10,@$R13+ */
2341 {
2342 { 1, 1, 1, 1 },
2343 FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov",
2344 { { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
2345 & fmt_dmov2r13pi, { 0xc00 },
2346 (PTR) 0,
2347 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2348 },
2349 /* dmovh @$dir9,@$R13+ */
2350 {
2351 { 1, 1, 1, 1 },
2352 FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh",
2353 { { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
2354 & fmt_dmov2r13pih, { 0xd00 },
2355 (PTR) 0,
2356 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2357 },
2358 /* dmovb @$dir8,@$R13+ */
2359 {
2360 { 1, 1, 1, 1 },
2361 FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb",
2362 { { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
2363 & fmt_dmov2r13pib, { 0xe00 },
2364 (PTR) 0,
2365 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2366 },
2367 /* dmov @$dir10,@-$R15 */
2368 {
2369 { 1, 1, 1, 1 },
2370 FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov",
2371 { { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
2372 & fmt_dmov2r15pd, { 0xb00 },
2373 (PTR) 0,
2374 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2375 },
2376 /* ldres @$Ri+,$u4 */
2377 {
2378 { 1, 1, 1, 1 },
2379 FR30_INSN_LDRES, "ldres", "ldres",
2380 { { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
2381 & fmt_ldres, { 0xbc00 },
2382 (PTR) 0,
2383 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2384 },
2385 /* stres $u4,@$Ri+ */
2386 {
2387 { 1, 1, 1, 1 },
2388 FR30_INSN_STRES, "stres", "stres",
2389 { { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
2390 & fmt_ldres, { 0xbd00 },
2391 (PTR) 0,
2392 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2393 },
2394 /* copop $u4c,$ccc,$CRj,$CRi */
2395 {
2396 { 1, 1, 1, 1 },
2397 FR30_INSN_COPOP, "copop", "copop",
2398 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
2399 & fmt_copop, { 0x9fc0 },
2400 (PTR) 0,
2401 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2402 },
2403 /* copld $u4c,$ccc,$Rjc,$CRi */
2404 {
2405 { 1, 1, 1, 1 },
2406 FR30_INSN_COPLD, "copld", "copld",
2407 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
2408 & fmt_copld, { 0x9fd0 },
2409 (PTR) 0,
2410 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2411 },
2412 /* copst $u4c,$ccc,$CRj,$Ric */
2413 {
2414 { 1, 1, 1, 1 },
2415 FR30_INSN_COPST, "copst", "copst",
2416 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2417 & fmt_copst, { 0x9fe0 },
2418 (PTR) 0,
2419 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2420 },
2421 /* copsv $u4c,$ccc,$CRj,$Ric */
2422 {
2423 { 1, 1, 1, 1 },
2424 FR30_INSN_COPSV, "copsv", "copsv",
2425 { { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
2426 & fmt_copst, { 0x9ff0 },
2427 (PTR) 0,
2428 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2429 },
2430 /* nop */
2431 {
2432 { 1, 1, 1, 1 },
2433 FR30_INSN_NOP, "nop", "nop",
2434 { { MNEM, 0 } },
2435 & fmt_nop, { 0x9fa0 },
2436 (PTR) 0,
2437 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2438 },
2439 /* andccr $u8 */
2440 {
2441 { 1, 1, 1, 1 },
2442 FR30_INSN_ANDCCR, "andccr", "andccr",
2443 { { MNEM, ' ', OP (U8), 0 } },
2444 & fmt_andccr, { 0x8300 },
2445 (PTR) 0,
2446 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2447 },
2448 /* orccr $u8 */
2449 {
2450 { 1, 1, 1, 1 },
2451 FR30_INSN_ORCCR, "orccr", "orccr",
2452 { { MNEM, ' ', OP (U8), 0 } },
2453 & fmt_andccr, { 0x9300 },
2454 (PTR) 0,
2455 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2456 },
2457 /* stilm $u8 */
2458 {
2459 { 1, 1, 1, 1 },
2460 FR30_INSN_STILM, "stilm", "stilm",
2461 { { MNEM, ' ', OP (U8), 0 } },
2462 & fmt_stilm, { 0x8700 },
2463 (PTR) 0,
2464 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2465 },
2466 /* addsp $s10 */
2467 {
2468 { 1, 1, 1, 1 },
2469 FR30_INSN_ADDSP, "addsp", "addsp",
2470 { { MNEM, ' ', OP (S10), 0 } },
2471 & fmt_addsp, { 0xa300 },
2472 (PTR) 0,
2473 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2474 },
2475 /* extsb $Ri */
2476 {
2477 { 1, 1, 1, 1 },
2478 FR30_INSN_EXTSB, "extsb", "extsb",
2479 { { MNEM, ' ', OP (RI), 0 } },
2480 & fmt_extsb, { 0x9780 },
2481 (PTR) 0,
2482 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2483 },
2484 /* extub $Ri */
2485 {
2486 { 1, 1, 1, 1 },
2487 FR30_INSN_EXTUB, "extub", "extub",
2488 { { MNEM, ' ', OP (RI), 0 } },
2489 & fmt_extub, { 0x9790 },
2490 (PTR) 0,
2491 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2492 },
2493 /* extsh $Ri */
2494 {
2495 { 1, 1, 1, 1 },
2496 FR30_INSN_EXTSH, "extsh", "extsh",
2497 { { MNEM, ' ', OP (RI), 0 } },
2498 & fmt_extsh, { 0x97a0 },
2499 (PTR) 0,
2500 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2501 },
2502 /* extuh $Ri */
2503 {
2504 { 1, 1, 1, 1 },
2505 FR30_INSN_EXTUH, "extuh", "extuh",
2506 { { MNEM, ' ', OP (RI), 0 } },
2507 & fmt_extuh, { 0x97b0 },
2508 (PTR) 0,
2509 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2510 },
2511 /* ldm0 ($reglist_low_ld) */
2512 {
2513 { 1, 1, 1, 1 },
2514 FR30_INSN_LDM0, "ldm0", "ldm0",
2515 { { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } },
2516 & fmt_ldm0, { 0x8c00 },
2517 (PTR) 0,
2518 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2519 },
2520 /* ldm1 ($reglist_hi_ld) */
2521 {
2522 { 1, 1, 1, 1 },
2523 FR30_INSN_LDM1, "ldm1", "ldm1",
2524 { { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } },
2525 & fmt_ldm1, { 0x8d00 },
2526 (PTR) 0,
2527 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2528 },
2529 /* stm0 ($reglist_low_st) */
2530 {
2531 { 1, 1, 1, 1 },
2532 FR30_INSN_STM0, "stm0", "stm0",
2533 { { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } },
2534 & fmt_stm0, { 0x8e00 },
2535 (PTR) 0,
2536 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2537 },
2538 /* stm1 ($reglist_hi_st) */
2539 {
2540 { 1, 1, 1, 1 },
2541 FR30_INSN_STM1, "stm1", "stm1",
2542 { { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } },
2543 & fmt_stm1, { 0x8f00 },
2544 (PTR) 0,
2545 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2546 },
2547 /* enter $u10 */
2548 {
2549 { 1, 1, 1, 1 },
2550 FR30_INSN_ENTER, "enter", "enter",
2551 { { MNEM, ' ', OP (U10), 0 } },
2552 & fmt_enter, { 0xf00 },
2553 (PTR) 0,
2554 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2555 },
2556 /* leave */
2557 {
2558 { 1, 1, 1, 1 },
2559 FR30_INSN_LEAVE, "leave", "leave",
2560 { { MNEM, 0 } },
2561 & fmt_leave, { 0x9f90 },
2562 (PTR) 0,
2563 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2564 },
2565 /* xchb @$Rj,$Ri */
2566 {
2567 { 1, 1, 1, 1 },
2568 FR30_INSN_XCHB, "xchb", "xchb",
2569 { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
2570 & fmt_xchb, { 0x8a00 },
2571 (PTR) 0,
2572 { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
2573 },
2574 };
2575
2576 #undef A
2577 #undef MNEM
2578 #undef OP
2579
2580 static const CGEN_INSN_TABLE insn_table =
2581 {
2582 & fr30_cgen_insn_table_entries[0],
2583 sizeof (CGEN_INSN),
2584 MAX_INSNS,
2585 NULL
2586 };
2587
2588 /* Formats for ALIAS macro-insns. */
2589
2590 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
2591
2592 static const CGEN_IFMT fmt_ldi8m = {
2593 16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
2594 };
2595
2596 static const CGEN_IFMT fmt_ldi20m = {
2597 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
2598 };
2599
2600 static const CGEN_IFMT fmt_ldi32m = {
2601 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
2602 };
2603
2604 #undef F
2605
2606 /* Each non-simple macro entry points to an array of expansion possibilities. */
2607
2608 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2609 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2610 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2611
2612 /* The macro instruction table. */
2613
2614 static const CGEN_INSN macro_insn_table_entries[] =
2615 {
2616 /* ldi8 $i8,$Ri */
2617 {
2618 { 1, 1, 1, 1 },
2619 -1, "ldi8m", "ldi8",
2620 { { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
2621 & fmt_ldi8m, { 0xc000 },
2622 (PTR) 0,
2623 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
2624 },
2625 /* ldi20 $i20,$Ri */
2626 {
2627 { 1, 1, 1, 1 },
2628 -1, "ldi20m", "ldi20",
2629 { { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
2630 & fmt_ldi20m, { 0x9b00 },
2631 (PTR) 0,
2632 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
2633 },
2634 /* ldi32 $i32,$Ri */
2635 {
2636 { 1, 1, 1, 1 },
2637 -1, "ldi32m", "ldi32",
2638 { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
2639 & fmt_ldi32m, { 0x9f80 },
2640 (PTR) 0,
2641 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
2642 },
2643 };
2644
2645 #undef A
2646 #undef MNEM
2647 #undef OP
2648
2649 static const CGEN_INSN_TABLE macro_insn_table =
2650 {
2651 & macro_insn_table_entries[0],
2652 sizeof (CGEN_INSN),
2653 (sizeof (macro_insn_table_entries) /
2654 sizeof (macro_insn_table_entries[0])),
2655 NULL
2656 };
2657
2658 static void
2659 init_tables ()
2660 {
2661 }
2662
2663 /* Return non-zero if INSN is to be added to the hash table.
2664 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2665
2666 static int
2667 asm_hash_insn_p (insn)
2668 const CGEN_INSN * insn;
2669 {
2670 return CGEN_ASM_HASH_P (insn);
2671 }
2672
2673 static int
2674 dis_hash_insn_p (insn)
2675 const CGEN_INSN * insn;
2676 {
2677 /* If building the hash table and the NO-DIS attribute is present,
2678 ignore. */
2679 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2680 return 0;
2681 return CGEN_DIS_HASH_P (insn);
2682 }
2683
2684 /* The result is the hash value of the insn.
2685 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
2686
2687 static unsigned int
2688 asm_hash_insn (mnem)
2689 const char * mnem;
2690 {
2691 return CGEN_ASM_HASH (mnem);
2692 }
2693
2694 /* BUF is a pointer to the insn's bytes in target order.
2695 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2696 host order. */
2697
2698 static unsigned int
2699 dis_hash_insn (buf, value)
2700 const char * buf;
2701 CGEN_INSN_INT value;
2702 {
2703 return CGEN_DIS_HASH (buf, value);
2704 }
2705
2706 /* Initialize an opcode table and return a descriptor.
2707 It's much like opening a file, and must be the first function called. */
2708
2709 CGEN_OPCODE_DESC
2710 fr30_cgen_opcode_open (mach, endian)
2711 int mach;
2712 enum cgen_endian endian;
2713 {
2714 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2715 static int init_p;
2716
2717 if (! init_p)
2718 {
2719 init_tables ();
2720 init_p = 1;
2721 }
2722
2723 memset (table, 0, sizeof (*table));
2724
2725 CGEN_OPCODE_MACH (table) = mach;
2726 CGEN_OPCODE_ENDIAN (table) = endian;
2727 /* FIXME: for the sparc case we can determine insn-endianness statically.
2728 The worry here is where both data and insn endian can be independently
2729 chosen, in which case this function will need another argument.
2730 Actually, will want to allow for more arguments in the future anyway. */
2731 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
2732
2733 CGEN_OPCODE_HW_LIST (table) = & fr30_cgen_hw_entries[0];
2734
2735 CGEN_OPCODE_IFLD_TABLE (table) = & fr30_cgen_ifld_table[0];
2736
2737 CGEN_OPCODE_OPERAND_TABLE (table) = & fr30_cgen_operand_table[0];
2738
2739 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2740
2741 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2742
2743 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2744 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2745 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2746
2747 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2748 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2749 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2750
2751 return (CGEN_OPCODE_DESC) table;
2752 }
2753
2754 /* Close an opcode table. */
2755
2756 void
2757 fr30_cgen_opcode_close (desc)
2758 CGEN_OPCODE_DESC desc;
2759 {
2760 free (desc);
2761 }
2762
2763 /* Getting values from cgen_fields is handled by a collection of functions.
2764 They are distinguished by the type of the VALUE argument they return.
2765 TODO: floating point, inlining support, remove cases where result type
2766 not appropriate. */
2767
2768 int
2769 fr30_cgen_get_int_operand (opindex, fields)
2770 int opindex;
2771 const CGEN_FIELDS * fields;
2772 {
2773 int value;
2774
2775 switch (opindex)
2776 {
2777 case FR30_OPERAND_RI :
2778 value = fields->f_Ri;
2779 break;
2780 case FR30_OPERAND_RJ :
2781 value = fields->f_Rj;
2782 break;
2783 case FR30_OPERAND_RIC :
2784 value = fields->f_Ric;
2785 break;
2786 case FR30_OPERAND_RJC :
2787 value = fields->f_Rjc;
2788 break;
2789 case FR30_OPERAND_CRI :
2790 value = fields->f_CRi;
2791 break;
2792 case FR30_OPERAND_CRJ :
2793 value = fields->f_CRj;
2794 break;
2795 case FR30_OPERAND_RS1 :
2796 value = fields->f_Rs1;
2797 break;
2798 case FR30_OPERAND_RS2 :
2799 value = fields->f_Rs2;
2800 break;
2801 case FR30_OPERAND_R13 :
2802 value = fields->f_nil;
2803 break;
2804 case FR30_OPERAND_R14 :
2805 value = fields->f_nil;
2806 break;
2807 case FR30_OPERAND_R15 :
2808 value = fields->f_nil;
2809 break;
2810 case FR30_OPERAND_PS :
2811 value = fields->f_nil;
2812 break;
2813 case FR30_OPERAND_U4 :
2814 value = fields->f_u4;
2815 break;
2816 case FR30_OPERAND_U4C :
2817 value = fields->f_u4c;
2818 break;
2819 case FR30_OPERAND_U8 :
2820 value = fields->f_u8;
2821 break;
2822 case FR30_OPERAND_I8 :
2823 value = fields->f_i8;
2824 break;
2825 case FR30_OPERAND_UDISP6 :
2826 value = fields->f_udisp6;
2827 break;
2828 case FR30_OPERAND_DISP8 :
2829 value = fields->f_disp8;
2830 break;
2831 case FR30_OPERAND_DISP9 :
2832 value = fields->f_disp9;
2833 break;
2834 case FR30_OPERAND_DISP10 :
2835 value = fields->f_disp10;
2836 break;
2837 case FR30_OPERAND_S10 :
2838 value = fields->f_s10;
2839 break;
2840 case FR30_OPERAND_U10 :
2841 value = fields->f_u10;
2842 break;
2843 case FR30_OPERAND_I32 :
2844 value = fields->f_i32;
2845 break;
2846 case FR30_OPERAND_M4 :
2847 value = fields->f_m4;
2848 break;
2849 case FR30_OPERAND_I20 :
2850 value = fields->f_i20;
2851 break;
2852 case FR30_OPERAND_DIR8 :
2853 value = fields->f_dir8;
2854 break;
2855 case FR30_OPERAND_DIR9 :
2856 value = fields->f_dir9;
2857 break;
2858 case FR30_OPERAND_DIR10 :
2859 value = fields->f_dir10;
2860 break;
2861 case FR30_OPERAND_LABEL9 :
2862 value = fields->f_rel9;
2863 break;
2864 case FR30_OPERAND_LABEL12 :
2865 value = fields->f_rel12;
2866 break;
2867 case FR30_OPERAND_REGLIST_LOW_LD :
2868 value = fields->f_reglist_low_ld;
2869 break;
2870 case FR30_OPERAND_REGLIST_HI_LD :
2871 value = fields->f_reglist_hi_ld;
2872 break;
2873 case FR30_OPERAND_REGLIST_LOW_ST :
2874 value = fields->f_reglist_low_st;
2875 break;
2876 case FR30_OPERAND_REGLIST_HI_ST :
2877 value = fields->f_reglist_hi_st;
2878 break;
2879 case FR30_OPERAND_CC :
2880 value = fields->f_cc;
2881 break;
2882 case FR30_OPERAND_CCC :
2883 value = fields->f_ccc;
2884 break;
2885
2886 default :
2887 /* xgettext:c-format */
2888 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
2889 opindex);
2890 abort ();
2891 }
2892
2893 return value;
2894 }
2895
2896 bfd_vma
2897 fr30_cgen_get_vma_operand (opindex, fields)
2898 int opindex;
2899 const CGEN_FIELDS * fields;
2900 {
2901 bfd_vma value;
2902
2903 switch (opindex)
2904 {
2905 case FR30_OPERAND_RI :
2906 value = fields->f_Ri;
2907 break;
2908 case FR30_OPERAND_RJ :
2909 value = fields->f_Rj;
2910 break;
2911 case FR30_OPERAND_RIC :
2912 value = fields->f_Ric;
2913 break;
2914 case FR30_OPERAND_RJC :
2915 value = fields->f_Rjc;
2916 break;
2917 case FR30_OPERAND_CRI :
2918 value = fields->f_CRi;
2919 break;
2920 case FR30_OPERAND_CRJ :
2921 value = fields->f_CRj;
2922 break;
2923 case FR30_OPERAND_RS1 :
2924 value = fields->f_Rs1;
2925 break;
2926 case FR30_OPERAND_RS2 :
2927 value = fields->f_Rs2;
2928 break;
2929 case FR30_OPERAND_R13 :
2930 value = fields->f_nil;
2931 break;
2932 case FR30_OPERAND_R14 :
2933 value = fields->f_nil;
2934 break;
2935 case FR30_OPERAND_R15 :
2936 value = fields->f_nil;
2937 break;
2938 case FR30_OPERAND_PS :
2939 value = fields->f_nil;
2940 break;
2941 case FR30_OPERAND_U4 :
2942 value = fields->f_u4;
2943 break;
2944 case FR30_OPERAND_U4C :
2945 value = fields->f_u4c;
2946 break;
2947 case FR30_OPERAND_U8 :
2948 value = fields->f_u8;
2949 break;
2950 case FR30_OPERAND_I8 :
2951 value = fields->f_i8;
2952 break;
2953 case FR30_OPERAND_UDISP6 :
2954 value = fields->f_udisp6;
2955 break;
2956 case FR30_OPERAND_DISP8 :
2957 value = fields->f_disp8;
2958 break;
2959 case FR30_OPERAND_DISP9 :
2960 value = fields->f_disp9;
2961 break;
2962 case FR30_OPERAND_DISP10 :
2963 value = fields->f_disp10;
2964 break;
2965 case FR30_OPERAND_S10 :
2966 value = fields->f_s10;
2967 break;
2968 case FR30_OPERAND_U10 :
2969 value = fields->f_u10;
2970 break;
2971 case FR30_OPERAND_I32 :
2972 value = fields->f_i32;
2973 break;
2974 case FR30_OPERAND_M4 :
2975 value = fields->f_m4;
2976 break;
2977 case FR30_OPERAND_I20 :
2978 value = fields->f_i20;
2979 break;
2980 case FR30_OPERAND_DIR8 :
2981 value = fields->f_dir8;
2982 break;
2983 case FR30_OPERAND_DIR9 :
2984 value = fields->f_dir9;
2985 break;
2986 case FR30_OPERAND_DIR10 :
2987 value = fields->f_dir10;
2988 break;
2989 case FR30_OPERAND_LABEL9 :
2990 value = fields->f_rel9;
2991 break;
2992 case FR30_OPERAND_LABEL12 :
2993 value = fields->f_rel12;
2994 break;
2995 case FR30_OPERAND_REGLIST_LOW_LD :
2996 value = fields->f_reglist_low_ld;
2997 break;
2998 case FR30_OPERAND_REGLIST_HI_LD :
2999 value = fields->f_reglist_hi_ld;
3000 break;
3001 case FR30_OPERAND_REGLIST_LOW_ST :
3002 value = fields->f_reglist_low_st;
3003 break;
3004 case FR30_OPERAND_REGLIST_HI_ST :
3005 value = fields->f_reglist_hi_st;
3006 break;
3007 case FR30_OPERAND_CC :
3008 value = fields->f_cc;
3009 break;
3010 case FR30_OPERAND_CCC :
3011 value = fields->f_ccc;
3012 break;
3013
3014 default :
3015 /* xgettext:c-format */
3016 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3017 opindex);
3018 abort ();
3019 }
3020
3021 return value;
3022 }
3023
3024 /* Stuffing values in cgen_fields is handled by a collection of functions.
3025 They are distinguished by the type of the VALUE argument they accept.
3026 TODO: floating point, inlining support, remove cases where argument type
3027 not appropriate. */
3028
3029 void
3030 fr30_cgen_set_int_operand (opindex, fields, value)
3031 int opindex;
3032 CGEN_FIELDS * fields;
3033 int value;
3034 {
3035 switch (opindex)
3036 {
3037 case FR30_OPERAND_RI :
3038 fields->f_Ri = value;
3039 break;
3040 case FR30_OPERAND_RJ :
3041 fields->f_Rj = value;
3042 break;
3043 case FR30_OPERAND_RIC :
3044 fields->f_Ric = value;
3045 break;
3046 case FR30_OPERAND_RJC :
3047 fields->f_Rjc = value;
3048 break;
3049 case FR30_OPERAND_CRI :
3050 fields->f_CRi = value;
3051 break;
3052 case FR30_OPERAND_CRJ :
3053 fields->f_CRj = value;
3054 break;
3055 case FR30_OPERAND_RS1 :
3056 fields->f_Rs1 = value;
3057 break;
3058 case FR30_OPERAND_RS2 :
3059 fields->f_Rs2 = value;
3060 break;
3061 case FR30_OPERAND_R13 :
3062 fields->f_nil = value;
3063 break;
3064 case FR30_OPERAND_R14 :
3065 fields->f_nil = value;
3066 break;
3067 case FR30_OPERAND_R15 :
3068 fields->f_nil = value;
3069 break;
3070 case FR30_OPERAND_PS :
3071 fields->f_nil = value;
3072 break;
3073 case FR30_OPERAND_U4 :
3074 fields->f_u4 = value;
3075 break;
3076 case FR30_OPERAND_U4C :
3077 fields->f_u4c = value;
3078 break;
3079 case FR30_OPERAND_U8 :
3080 fields->f_u8 = value;
3081 break;
3082 case FR30_OPERAND_I8 :
3083 fields->f_i8 = value;
3084 break;
3085 case FR30_OPERAND_UDISP6 :
3086 fields->f_udisp6 = value;
3087 break;
3088 case FR30_OPERAND_DISP8 :
3089 fields->f_disp8 = value;
3090 break;
3091 case FR30_OPERAND_DISP9 :
3092 fields->f_disp9 = value;
3093 break;
3094 case FR30_OPERAND_DISP10 :
3095 fields->f_disp10 = value;
3096 break;
3097 case FR30_OPERAND_S10 :
3098 fields->f_s10 = value;
3099 break;
3100 case FR30_OPERAND_U10 :
3101 fields->f_u10 = value;
3102 break;
3103 case FR30_OPERAND_I32 :
3104 fields->f_i32 = value;
3105 break;
3106 case FR30_OPERAND_M4 :
3107 fields->f_m4 = value;
3108 break;
3109 case FR30_OPERAND_I20 :
3110 fields->f_i20 = value;
3111 break;
3112 case FR30_OPERAND_DIR8 :
3113 fields->f_dir8 = value;
3114 break;
3115 case FR30_OPERAND_DIR9 :
3116 fields->f_dir9 = value;
3117 break;
3118 case FR30_OPERAND_DIR10 :
3119 fields->f_dir10 = value;
3120 break;
3121 case FR30_OPERAND_LABEL9 :
3122 fields->f_rel9 = value;
3123 break;
3124 case FR30_OPERAND_LABEL12 :
3125 fields->f_rel12 = value;
3126 break;
3127 case FR30_OPERAND_REGLIST_LOW_LD :
3128 fields->f_reglist_low_ld = value;
3129 break;
3130 case FR30_OPERAND_REGLIST_HI_LD :
3131 fields->f_reglist_hi_ld = value;
3132 break;
3133 case FR30_OPERAND_REGLIST_LOW_ST :
3134 fields->f_reglist_low_st = value;
3135 break;
3136 case FR30_OPERAND_REGLIST_HI_ST :
3137 fields->f_reglist_hi_st = value;
3138 break;
3139 case FR30_OPERAND_CC :
3140 fields->f_cc = value;
3141 break;
3142 case FR30_OPERAND_CCC :
3143 fields->f_ccc = value;
3144 break;
3145
3146 default :
3147 /* xgettext:c-format */
3148 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3149 opindex);
3150 abort ();
3151 }
3152 }
3153
3154 void
3155 fr30_cgen_set_vma_operand (opindex, fields, value)
3156 int opindex;
3157 CGEN_FIELDS * fields;
3158 bfd_vma value;
3159 {
3160 switch (opindex)
3161 {
3162 case FR30_OPERAND_RI :
3163 fields->f_Ri = value;
3164 break;
3165 case FR30_OPERAND_RJ :
3166 fields->f_Rj = value;
3167 break;
3168 case FR30_OPERAND_RIC :
3169 fields->f_Ric = value;
3170 break;
3171 case FR30_OPERAND_RJC :
3172 fields->f_Rjc = value;
3173 break;
3174 case FR30_OPERAND_CRI :
3175 fields->f_CRi = value;
3176 break;
3177 case FR30_OPERAND_CRJ :
3178 fields->f_CRj = value;
3179 break;
3180 case FR30_OPERAND_RS1 :
3181 fields->f_Rs1 = value;
3182 break;
3183 case FR30_OPERAND_RS2 :
3184 fields->f_Rs2 = value;
3185 break;
3186 case FR30_OPERAND_R13 :
3187 fields->f_nil = value;
3188 break;
3189 case FR30_OPERAND_R14 :
3190 fields->f_nil = value;
3191 break;
3192 case FR30_OPERAND_R15 :
3193 fields->f_nil = value;
3194 break;
3195 case FR30_OPERAND_PS :
3196 fields->f_nil = value;
3197 break;
3198 case FR30_OPERAND_U4 :
3199 fields->f_u4 = value;
3200 break;
3201 case FR30_OPERAND_U4C :
3202 fields->f_u4c = value;
3203 break;
3204 case FR30_OPERAND_U8 :
3205 fields->f_u8 = value;
3206 break;
3207 case FR30_OPERAND_I8 :
3208 fields->f_i8 = value;
3209 break;
3210 case FR30_OPERAND_UDISP6 :
3211 fields->f_udisp6 = value;
3212 break;
3213 case FR30_OPERAND_DISP8 :
3214 fields->f_disp8 = value;
3215 break;
3216 case FR30_OPERAND_DISP9 :
3217 fields->f_disp9 = value;
3218 break;
3219 case FR30_OPERAND_DISP10 :
3220 fields->f_disp10 = value;
3221 break;
3222 case FR30_OPERAND_S10 :
3223 fields->f_s10 = value;
3224 break;
3225 case FR30_OPERAND_U10 :
3226 fields->f_u10 = value;
3227 break;
3228 case FR30_OPERAND_I32 :
3229 fields->f_i32 = value;
3230 break;
3231 case FR30_OPERAND_M4 :
3232 fields->f_m4 = value;
3233 break;
3234 case FR30_OPERAND_I20 :
3235 fields->f_i20 = value;
3236 break;
3237 case FR30_OPERAND_DIR8 :
3238 fields->f_dir8 = value;
3239 break;
3240 case FR30_OPERAND_DIR9 :
3241 fields->f_dir9 = value;
3242 break;
3243 case FR30_OPERAND_DIR10 :
3244 fields->f_dir10 = value;
3245 break;
3246 case FR30_OPERAND_LABEL9 :
3247 fields->f_rel9 = value;
3248 break;
3249 case FR30_OPERAND_LABEL12 :
3250 fields->f_rel12 = value;
3251 break;
3252 case FR30_OPERAND_REGLIST_LOW_LD :
3253 fields->f_reglist_low_ld = value;
3254 break;
3255 case FR30_OPERAND_REGLIST_HI_LD :
3256 fields->f_reglist_hi_ld = value;
3257 break;
3258 case FR30_OPERAND_REGLIST_LOW_ST :
3259 fields->f_reglist_low_st = value;
3260 break;
3261 case FR30_OPERAND_REGLIST_HI_ST :
3262 fields->f_reglist_hi_st = value;
3263 break;
3264 case FR30_OPERAND_CC :
3265 fields->f_cc = value;
3266 break;
3267 case FR30_OPERAND_CCC :
3268 fields->f_ccc = value;
3269 break;
3270
3271 default :
3272 /* xgettext:c-format */
3273 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3274 opindex);
3275 abort ();
3276 }
3277 }
3278
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