1 /* mmix-opc.c -- MMIX opcode table
2 Copyright (C) 2001-2022 Free Software Foundation, Inc.
3 Written by Hans-Peter Nilsson (hp@bitrange.com)
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include "opcode/mmix.h"
26 /* Register-name-table for special registers. */
27 const struct mmix_spec_reg mmix_spec_regs
[] =
29 /* Keep rJ at top; it's the most frequently used one. */
65 /* Opcode-table. In order to cut down on redundant contents, we use helper
68 /* All bits in the opcode-byte are significant. Add "| ..." expressions
71 #define O(m) ((unsigned long) (m) << 24UL), ((~(unsigned long) (m) & 255) << 24)
73 /* Bits 7..1 of the opcode are significant. */
75 #define Z(m) ((unsigned long) (m) << 24), ((~(unsigned long) (m) & 254) << 24)
77 /* For easier overview of the table. */
78 #define N mmix_type_normal
79 #define B mmix_type_branch
80 #define C mmix_type_condbranch
81 #define MB mmix_type_memaccess_byte
82 #define MW mmix_type_memaccess_wyde
83 #define MT mmix_type_memaccess_tetra
84 #define MO mmix_type_memaccess_octa
85 #define M mmix_type_memaccess_block
86 #define J mmix_type_jsr
87 #define P mmix_type_pseudo
89 #define OP(y) XCONCAT2 (mmix_operands_,y)
91 /* Groups of instructions specified here must, if all are matching the
92 same instruction, be consecutive, in order more-specific to
93 less-specific match. */
95 const struct mmix_opcode mmix_opcodes
[] =
97 {"trap", O (0), OP (xyz_opt
), J
},
98 {"fcmp", O (1), OP (regs
), N
},
99 {"flot", Z (8), OP (roundregs_z
), N
},
101 {"fun", O (2), OP (regs
), N
},
102 {"feql", O (3), OP (regs
), N
},
103 {"flotu", Z (10), OP (roundregs_z
), N
},
105 {"fadd", O (4), OP (regs
), N
},
106 {"fix", O (5), OP (roundregs
), N
},
107 {"sflot", Z (12), OP (roundregs_z
), N
},
109 {"fsub", O (6), OP (regs
), N
},
110 {"fixu", O (7), OP (roundregs
), N
},
111 {"sflotu", Z (14), OP (roundregs_z
), N
},
113 {"fmul", O (16), OP (regs
), N
},
114 {"fcmpe", O (17), OP (regs
), N
},
115 {"mul", Z (24), OP (regs_z
), N
},
117 {"fune", O (18), OP (regs
), N
},
118 {"feqle", O (19), OP (regs
), N
},
119 {"mulu", Z (26), OP (regs_z
), N
},
121 {"fdiv", O (20), OP (regs
), N
},
122 {"fsqrt", O (21), OP (roundregs
), N
},
123 {"div", Z (28), OP (regs_z
), N
},
125 {"frem", O (22), OP (regs
), N
},
126 {"fint", O (23), OP (roundregs
), N
},
127 {"divu", Z (30), OP (regs_z
), N
},
129 {"add", Z (0x20), OP (regs_z
), N
},
130 {"2addu", Z (0x28), OP (regs_z
), N
},
132 {"addu", Z (0x22), OP (regs_z
), N
},
133 /* Synonym for ADDU. Put after ADDU, since we don't prefer it for
134 disassembly. It's supposed to be used for addresses, so we make it
135 a memory block reference for purposes of assembly. */
136 {"lda", Z (0x22), OP (regs_z_opt
), M
},
137 {"4addu", Z (0x2a), OP (regs_z
), N
},
139 {"sub", Z (0x24), OP (regs_z
), N
},
140 {"8addu", Z (0x2c), OP (regs_z
), N
},
142 {"subu", Z (0x26), OP (regs_z
), N
},
143 {"16addu", Z (0x2e), OP (regs_z
), N
},
145 {"cmp", Z (0x30), OP (regs_z
), N
},
146 {"sl", Z (0x38), OP (regs_z
), N
},
148 {"cmpu", Z (0x32), OP (regs_z
), N
},
149 {"slu", Z (0x3a), OP (regs_z
), N
},
151 {"neg", Z (0x34), OP (neg
), N
},
152 {"sr", Z (0x3c), OP (regs_z
), N
},
154 {"negu", Z (0x36), OP (neg
), N
},
155 {"sru", Z (0x3e), OP (regs_z
), N
},
157 {"bn", Z (0x40), OP (regaddr
), C
},
158 {"bnn", Z (0x48), OP (regaddr
), C
},
160 {"bz", Z (0x42), OP (regaddr
), C
},
161 {"bnz", Z (0x4a), OP (regaddr
), C
},
163 {"bp", Z (0x44), OP (regaddr
), C
},
164 {"bnp", Z (0x4c), OP (regaddr
), C
},
166 {"bod", Z (0x46), OP (regaddr
), C
},
167 {"bev", Z (0x4e), OP (regaddr
), C
},
169 {"pbn", Z (0x50), OP (regaddr
), C
},
170 {"pbnn", Z (0x58), OP (regaddr
), C
},
172 {"pbz", Z (0x52), OP (regaddr
), C
},
173 {"pbnz", Z (0x5a), OP (regaddr
), C
},
175 {"pbp", Z (0x54), OP (regaddr
), C
},
176 {"pbnp", Z (0x5c), OP (regaddr
), C
},
178 {"pbod", Z (0x56), OP (regaddr
), C
},
179 {"pbev", Z (0x5e), OP (regaddr
), C
},
181 {"csn", Z (0x60), OP (regs_z
), N
},
182 {"csnn", Z (0x68), OP (regs_z
), N
},
184 {"csz", Z (0x62), OP (regs_z
), N
},
185 {"csnz", Z (0x6a), OP (regs_z
), N
},
187 {"csp", Z (0x64), OP (regs_z
), N
},
188 {"csnp", Z (0x6c), OP (regs_z
), N
},
190 {"csod", Z (0x66), OP (regs_z
), N
},
191 {"csev", Z (0x6e), OP (regs_z
), N
},
193 {"zsn", Z (0x70), OP (regs_z
), N
},
194 {"zsnn", Z (0x78), OP (regs_z
), N
},
196 {"zsz", Z (0x72), OP (regs_z
), N
},
197 {"zsnz", Z (0x7a), OP (regs_z
), N
},
199 {"zsp", Z (0x74), OP (regs_z
), N
},
200 {"zsnp", Z (0x7c), OP (regs_z
), N
},
202 {"zsod", Z (0x76), OP (regs_z
), N
},
203 {"zsev", Z (0x7e), OP (regs_z
), N
},
205 {"ldb", Z (0x80), OP (regs_z_opt
), MB
},
206 {"ldt", Z (0x88), OP (regs_z_opt
), MT
},
208 {"ldbu", Z (0x82), OP (regs_z_opt
), MB
},
209 {"ldtu", Z (0x8a), OP (regs_z_opt
), MT
},
211 {"ldw", Z (0x84), OP (regs_z_opt
), MW
},
212 {"ldo", Z (0x8c), OP (regs_z_opt
), MO
},
214 {"ldwu", Z (0x86), OP (regs_z_opt
), MW
},
215 {"ldou", Z (0x8e), OP (regs_z_opt
), MO
},
217 {"ldsf", Z (0x90), OP (regs_z_opt
), MT
},
219 /* This doesn't seem to access memory, just the TLB. */
220 {"ldvts", Z (0x98), OP (regs_z_opt
), M
},
222 {"ldht", Z (0x92), OP (regs_z_opt
), MT
},
224 /* Neither does this per-se. */
225 {"preld", Z (0x9a), OP (x_regs_z
), N
},
227 {"cswap", Z (0x94), OP (regs_z_opt
), MO
},
228 {"prego", Z (0x9c), OP (x_regs_z
), N
},
230 {"ldunc", Z (0x96), OP (regs_z_opt
), MO
},
231 {"go", Z (GO_INSN_BYTE
),
234 {"stb", Z (0xa0), OP (regs_z_opt
), MB
},
235 {"stt", Z (0xa8), OP (regs_z_opt
), MT
},
237 {"stbu", Z (0xa2), OP (regs_z_opt
), MB
},
238 {"sttu", Z (0xaa), OP (regs_z_opt
), MT
},
240 {"stw", Z (0xa4), OP (regs_z_opt
), MW
},
241 {"sto", Z (0xac), OP (regs_z_opt
), MO
},
243 {"stwu", Z (0xa6), OP (regs_z_opt
), MW
},
244 {"stou", Z (0xae), OP (regs_z_opt
), MO
},
246 {"stsf", Z (0xb0), OP (regs_z_opt
), MT
},
247 {"syncd", Z (0xb8), OP (x_regs_z
), M
},
249 {"stht", Z (0xb2), OP (regs_z_opt
), MT
},
250 {"prest", Z (0xba), OP (x_regs_z
), M
},
252 {"stco", Z (0xb4), OP (x_regs_z
), MO
},
253 {"syncid", Z (0xbc), OP (x_regs_z
), M
},
255 {"stunc", Z (0xb6), OP (regs_z_opt
), MO
},
256 {"pushgo", Z (PUSHGO_INSN_BYTE
),
259 /* Synonym for OR with a zero Z. */
261 | 0xff, OP (set
), N
},
263 {"or", Z (0xc0), OP (regs_z
), N
},
264 {"and", Z (0xc8), OP (regs_z
), N
},
266 {"orn", Z (0xc2), OP (regs_z
), N
},
267 {"andn", Z (0xca), OP (regs_z
), N
},
269 {"nor", Z (0xc4), OP (regs_z
), N
},
270 {"nand", Z (0xcc), OP (regs_z
), N
},
272 {"xor", Z (0xc6), OP (regs_z
), N
},
273 {"nxor", Z (0xce), OP (regs_z
), N
},
275 {"bdif", Z (0xd0), OP (regs_z
), N
},
276 {"mux", Z (0xd8), OP (regs_z
), N
},
278 {"wdif", Z (0xd2), OP (regs_z
), N
},
279 {"sadd", Z (0xda), OP (regs_z
), N
},
281 {"tdif", Z (0xd4), OP (regs_z
), N
},
282 {"mor", Z (0xdc), OP (regs_z
), N
},
284 {"odif", Z (0xd6), OP (regs_z
), N
},
285 {"mxor", Z (0xde), OP (regs_z
), N
},
287 {"seth", O (0xe0), OP (reg_yz
), N
},
288 {"setmh", O (0xe1), OP (reg_yz
), N
},
289 {"orh", O (0xe8), OP (reg_yz
), N
},
290 {"ormh", O (0xe9), OP (reg_yz
), N
},
292 {"setml", O (0xe2), OP (reg_yz
), N
},
293 {"setl", O (SETL_INSN_BYTE
),
295 {"orml", O (0xea), OP (reg_yz
), N
},
296 {"orl", O (0xeb), OP (reg_yz
), N
},
298 {"inch", O (INCH_INSN_BYTE
),
300 {"incmh", O (INCMH_INSN_BYTE
),
302 {"andnh", O (0xec), OP (reg_yz
), N
},
303 {"andnmh", O (0xed), OP (reg_yz
), N
},
305 {"incml", O (INCML_INSN_BYTE
),
307 {"incl", O (0xe7), OP (reg_yz
), N
},
308 {"andnml", O (0xee), OP (reg_yz
), N
},
309 {"andnl", O (0xef), OP (reg_yz
), N
},
311 {"jmp", Z (0xf0), OP (jmp
), B
},
312 {"pop", O (0xf8), OP (pop
), B
},
314 | 0xffff00, OP (resume
), B
},
316 {"pushj", Z (0xf2), OP (pushj
), J
},
318 | 0xffff, OP (save
), M
},
320 | 0xffff00, OP (unsave
), M
},
322 {"geta", Z (0xf4), OP (regaddr
), N
},
323 {"sync", O (0xfc), OP (sync
), N
},
324 {"swym", O (SWYM_INSN_BYTE
),
327 {"put", Z (0xf6) | 0xff00, OP (put
), N
},
328 {"get", O (0xfe) | 0xffe0, OP (get
), N
},
329 {"trip", O (0xff), OP (xyz_opt
), J
},
331 /* We have mmixal pseudos in the ordinary instruction table so we can
332 avoid the "set" vs. ".set" ambiguity that would be the effect if we
333 had pseudos handled "normally" and defined NO_PSEUDO_DOT.
335 Note that IS and GREG are handled fully by md_start_line_hook, so
337 {"loc", ~0, ~0, OP (loc
), P
},
338 {"prefix", ~0, ~0, OP (prefix
), P
},
339 {"byte", ~0, ~0, OP (byte
), P
},
340 {"wyde", ~0, ~0, OP (wyde
), P
},
341 {"tetra", ~0, ~0, OP (tetra
), P
},
342 {"octa", ~0, ~0, OP (octa
), P
},
343 {"local", ~0, ~0, OP (local
), P
},
344 {"bspec", ~0, ~0, OP (bspec
), P
},
345 {"espec", ~0, ~0, OP (espec
), P
},
347 {NULL
, ~0, ~0, OP (none
), N
}
projects / thirdparty / binutils-gdb.git / blob