opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "dis-asm.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29
  30 /* This file provides several disassembler functions, all of which use
  31    the disassembler interface defined in dis-asm.h.  Several functions
  32    are provided because this file handles disassembly for the PowerPC
  33    in both big and little endian mode and also for the POWER (RS/6000)
  34    chip.  */
  35 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  36                                ppc_cpu_t);
  37
  38 struct dis_private
  39 {
  40   /* Stash the result of parsing disassembler_options here.  */
  41   ppc_cpu_t dialect;
  42 } private;
  43
  44 #define POWERPC_DIALECT(INFO) \
  45   (((struct dis_private *) ((INFO)->private_data))->dialect)
  46
  47 struct ppc_mopt {
  48   const char *opt;
  49   ppc_cpu_t cpu;
  50   ppc_cpu_t sticky;
  51 };
  52
  53 struct ppc_mopt ppc_opts[] = {
  54   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  55     0 },
  56   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  57     0 },
  58   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  59                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  60     0 },
  61   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  62                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  63     0 },
  64   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
  65                 | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  66     0 },
  67   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  68     0 },
  69   { "603",     PPC_OPCODE_PPC,
  70     0 },
  71   { "604",     PPC_OPCODE_PPC,
  72     0 },
  73   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  74     0 },
  75   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  76     0 },
  77   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  78     0 },
  79   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
  80     0 },
  81   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  82     0 },
  83   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
  84     , 0 },
  85   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
  86     0 },
  87   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
  88     0 },
  89   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
  90     0 },
  91   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
  92                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
  93                 | PPC_OPCODE_A2),
  94     0 },
  95   { "altivec", PPC_OPCODE_PPC,
  96     PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 },
  97   { "any",     0,
  98     PPC_OPCODE_ANY },
  99   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 100     0 },
 101   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 102     0 },
 103   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 104                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 105     0 },
 106   { "com",     PPC_OPCODE_COMMON,
 107     0 },
 108   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 109                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 110                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 111                 | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
 112     PPC_OPCODE_VLE },
 113   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 114     0 },
 115   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 116                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 117                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 118                 | PPC_OPCODE_E500),
 119     0 },
 120   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 121                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 122                 | PPC_OPCODE_E500MC),
 123     0 },
 124   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 125                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 126                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 127                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 128     0 },
 129   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 130                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 131                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 132                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 133                 | PPC_OPCODE_POWER7),
 134     0 },
 135   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 136                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 137                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 138                 | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
 139                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 140     0 },
 141   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 142                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 143                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 144                 | PPC_OPCODE_E500),
 145     0 },
 146   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 147     0 },
 148   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 149     0 },
 150   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 151                 | PPC_OPCODE_POWER5),
 152     0 },
 153   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 154                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 155     0 },
 156   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 157                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 158                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 159     0 },
 160   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 161                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 162                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 163                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 164     0 },
 165   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 166                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 167                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 168                 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
 169                 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
 170     0 },
 171   { "ppc",     PPC_OPCODE_PPC,
 172     0 },
 173   { "ppc32",   PPC_OPCODE_PPC,
 174     0 },
 175   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 176     0 },
 177   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 178     0 },
 179   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 180     0 },
 181   { "pwr",     PPC_OPCODE_POWER,
 182     0 },
 183   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 184     0 },
 185   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 186     0 },
 187   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 188                 | PPC_OPCODE_POWER5),
 189     0 },
 190   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 191                 | PPC_OPCODE_POWER5),
 192     0 },
 193   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 194                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 195     0 },
 196   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 197                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 198                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 199     0 },
 200   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 201                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 202                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
 203                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
 204     0 },
 205   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 206                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 207                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 208                 | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
 209                 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
 210     0 },
 211   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 212     0 },
 213   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 214     PPC_OPCODE_SPE },
 215   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 216                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 217     0 },
 218   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
 219                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 220                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 221                 | PPC_OPCODE_E500),
 222     PPC_OPCODE_VLE },
 223   { "vsx",     PPC_OPCODE_PPC,
 224     PPC_OPCODE_VSX | PPC_OPCODE_VSX3 },
 225   { "htm",     PPC_OPCODE_PPC,
 226     PPC_OPCODE_HTM },
 227 };
 228
 229 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 230 static ppc_cpu_t
 231 get_powerpc_dialect (struct disassemble_info *info)
 232 {
 233   ppc_cpu_t dialect = 0;
 234
 235   dialect = POWERPC_DIALECT (info);
 236
 237   /* Disassemble according to the section headers flags for VLE-mode.  */
 238   if (dialect & PPC_OPCODE_VLE
 239       && info->section != NULL && info->section->owner != NULL
 240       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 241       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 242       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 243     return dialect;
 244   else
 245     return dialect & ~ PPC_OPCODE_VLE;
 246 }
 247
 248 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 249
 250 ppc_cpu_t
 251 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 252 {
 253   unsigned int i;
 254
 255   for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 256     if (strcmp (ppc_opts[i].opt, arg) == 0)
 257       {
 258         if (ppc_opts[i].sticky)
 259           {
 260             *sticky |= ppc_opts[i].sticky;
 261             if ((ppc_cpu & ~*sticky) != 0)
 262               break;
 263           }
 264         ppc_cpu = ppc_opts[i].cpu;
 265         break;
 266       }
 267   if (i >= sizeof (ppc_opts) / sizeof (ppc_opts[0]))
 268     return 0;
 269
 270   ppc_cpu |= *sticky;
 271   return ppc_cpu;
 272 }
 273
 274 /* Determine which set of machines to disassemble for.  */
 275
 276 static void
 277 powerpc_init_dialect (struct disassemble_info *info)
 278 {
 279   ppc_cpu_t dialect = 0;
 280   ppc_cpu_t sticky = 0;
 281   char *arg;
 282   struct dis_private *priv = calloc (sizeof (*priv), 1);
 283
 284   if (priv == NULL)
 285     priv = &private;
 286
 287   switch (info->mach)
 288     {
 289     case bfd_mach_ppc_403:
 290     case bfd_mach_ppc_403gc:
 291       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 292       break;
 293     case bfd_mach_ppc_405:
 294       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 295       break;
 296     case bfd_mach_ppc_601:
 297       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 298       break;
 299     case bfd_mach_ppc_a35:
 300     case bfd_mach_ppc_rs64ii:
 301     case bfd_mach_ppc_rs64iii:
 302       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 303       break;
 304     case bfd_mach_ppc_e500:
 305       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 306       break;
 307     case bfd_mach_ppc_e500mc:
 308       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 309       break;
 310     case bfd_mach_ppc_e500mc64:
 311       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 312       break;
 313     case bfd_mach_ppc_e5500:
 314       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 315       break;
 316     case bfd_mach_ppc_e6500:
 317       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 318       break;
 319     case bfd_mach_ppc_titan:
 320       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 321       break;
 322     case bfd_mach_ppc_vle:
 323       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 324       break;
 325     default:
 326       dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
 327     }
 328
 329   arg = info->disassembler_options;
 330   while (arg != NULL)
 331     {
 332       ppc_cpu_t new_cpu = 0;
 333       char *end = strchr (arg, ',');
 334
 335       if (end != NULL)
 336         *end = 0;
 337
 338       if ((new_cpu = ppc_parse_cpu (dialect, &sticky, arg)) != 0)
 339         dialect = new_cpu;
 340       else if (strcmp (arg, "32") == 0)
 341         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 342       else if (strcmp (arg, "64") == 0)
 343         dialect |= PPC_OPCODE_64;
 344       else
 345         fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), arg);
 346
 347       if (end != NULL)
 348         *end++ = ',';
 349       arg = end;
 350     }
 351
 352   info->private_data = priv;
 353   POWERPC_DIALECT(info) = dialect;
 354 }
 355
 356 #define PPC_OPCD_SEGS 64
 357 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
 358 #define VLE_OPCD_SEGS 32
 359 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
 360
 361 /* Calculate opcode table indices to speed up disassembly,
 362    and init dialect.  */
 363
 364 void
 365 disassemble_init_powerpc (struct disassemble_info *info)
 366 {
 367   int i;
 368   unsigned short last;
 369
 370   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 371     {
 372
 373       i = powerpc_num_opcodes;
 374       while (--i >= 0)
 375         {
 376           unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
 377
 378           powerpc_opcd_indices[op] = i;
 379         }
 380
 381       last = powerpc_num_opcodes;
 382       for (i = PPC_OPCD_SEGS; i > 0; --i)
 383         {
 384           if (powerpc_opcd_indices[i] == 0)
 385             powerpc_opcd_indices[i] = last;
 386           last = powerpc_opcd_indices[i];
 387         }
 388
 389       i = vle_num_opcodes;
 390       while (--i >= 0)
 391         {
 392           unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
 393           unsigned seg = VLE_OP_TO_SEG (op);
 394
 395           vle_opcd_indices[seg] = i;
 396         }
 397
 398       last = vle_num_opcodes;
 399       for (i = VLE_OPCD_SEGS; i > 0; --i)
 400         {
 401           if (vle_opcd_indices[i] == 0)
 402             vle_opcd_indices[i] = last;
 403           last = vle_opcd_indices[i];
 404         }
 405     }
 406
 407   if (info->arch == bfd_arch_powerpc)
 408     powerpc_init_dialect (info);
 409 }
 410
 411 /* Print a big endian PowerPC instruction.  */
 412
 413 int
 414 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 415 {
 416   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 417 }
 418
 419 /* Print a little endian PowerPC instruction.  */
 420
 421 int
 422 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 423 {
 424   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 425 }
 426
 427 /* Print a POWER (RS/6000) instruction.  */
 428
 429 int
 430 print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
 431 {
 432   return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
 433 }
 434
 435 /* Extract the operand value from the PowerPC or POWER instruction.  */
 436
 437 static long
 438 operand_value_powerpc (const struct powerpc_operand *operand,
 439                        unsigned long insn, ppc_cpu_t dialect)
 440 {
 441   long value;
 442   int invalid;
 443   /* Extract the value from the instruction.  */
 444   if (operand->extract)
 445     value = (*operand->extract) (insn, dialect, &invalid);
 446   else
 447     {
 448       if (operand->shift >= 0)
 449         value = (insn >> operand->shift) & operand->bitm;
 450       else
 451         value = (insn << -operand->shift) & operand->bitm;
 452       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 453         {
 454           /* BITM is always some number of zeros followed by some
 455              number of ones, followed by some number of zeros.  */
 456           unsigned long top = operand->bitm;
 457           /* top & -top gives the rightmost 1 bit, so this
 458              fills in any trailing zeros.  */
 459           top |= (top & -top) - 1;
 460           top &= ~(top >> 1);
 461           value = (value ^ top) - top;
 462         }
 463     }
 464
 465   return value;
 466 }
 467
 468 /* Determine whether the optional operand(s) should be printed.  */
 469
 470 static int
 471 skip_optional_operands (const unsigned char *opindex,
 472                         unsigned long insn, ppc_cpu_t dialect)
 473 {
 474   const struct powerpc_operand *operand;
 475
 476   for (; *opindex != 0; opindex++)
 477     {
 478       operand = &powerpc_operands[*opindex];
 479       if ((operand->flags & PPC_OPERAND_NEXT) != 0
 480           || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
 481               && operand_value_powerpc (operand, insn, dialect) !=
 482                  ppc_optional_operand_value (operand)))
 483         return 0;
 484     }
 485
 486   return 1;
 487 }
 488
 489 /* Find a match for INSN in the opcode table, given machine DIALECT.
 490    A DIALECT of -1 is special, matching all machine opcode variations.  */
 491
 492 static const struct powerpc_opcode *
 493 lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
 494 {
 495   const struct powerpc_opcode *opcode;
 496   const struct powerpc_opcode *opcode_end;
 497   unsigned long op;
 498
 499   /* Get the major opcode of the instruction.  */
 500   op = PPC_OP (insn);
 501
 502   /* Find the first match in the opcode table for this major opcode.  */
 503   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 504   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 505        opcode < opcode_end;
 506        ++opcode)
 507     {
 508       const unsigned char *opindex;
 509       const struct powerpc_operand *operand;
 510       int invalid;
 511
 512       if ((insn & opcode->mask) != opcode->opcode
 513           || (dialect != (ppc_cpu_t) -1
 514               && ((opcode->flags & dialect) == 0
 515                   || (opcode->deprecated & dialect) != 0)))
 516         continue;
 517
 518       /* Check validity of operands.  */
 519       invalid = 0;
 520       for (opindex = opcode->operands; *opindex != 0; opindex++)
 521         {
 522           operand = powerpc_operands + *opindex;
 523           if (operand->extract)
 524             (*operand->extract) (insn, dialect, &invalid);
 525         }
 526       if (invalid)
 527         continue;
 528
 529       return opcode;
 530     }
 531
 532   return NULL;
 533 }
 534
 535 /* Find a match for INSN in the VLE opcode table.  */
 536
 537 static const struct powerpc_opcode *
 538 lookup_vle (unsigned long insn)
 539 {
 540   const struct powerpc_opcode *opcode;
 541   const struct powerpc_opcode *opcode_end;
 542   unsigned op, seg;
 543
 544   op = PPC_OP (insn);
 545   if (op >= 0x20 && op <= 0x37)
 546     {
 547       /* This insn has a 4-bit opcode.  */
 548       op &= 0x3c;
 549     }
 550   seg = VLE_OP_TO_SEG (op);
 551
 552   /* Find the first match in the opcode table for this major opcode.  */
 553   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 554   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 555        opcode < opcode_end;
 556        ++opcode)
 557     {
 558       unsigned long table_opcd = opcode->opcode;
 559       unsigned long table_mask = opcode->mask;
 560       bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
 561       unsigned long insn2;
 562       const unsigned char *opindex;
 563       const struct powerpc_operand *operand;
 564       int invalid;
 565
 566       insn2 = insn;
 567       if (table_op_is_short)
 568         insn2 >>= 16;
 569       if ((insn2 & table_mask) != table_opcd)
 570         continue;
 571
 572       /* Check validity of operands.  */
 573       invalid = 0;
 574       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 575         {
 576           operand = powerpc_operands + *opindex;
 577           if (operand->extract)
 578             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 579         }
 580       if (invalid)
 581         continue;
 582
 583       return opcode;
 584     }
 585
 586   return NULL;
 587 }
 588
 589 /* Print a PowerPC or POWER instruction.  */
 590
 591 static int
 592 print_insn_powerpc (bfd_vma memaddr,
 593                     struct disassemble_info *info,
 594                     int bigendian,
 595                     ppc_cpu_t dialect)
 596 {
 597   bfd_byte buffer[4];
 598   int status;
 599   unsigned long insn;
 600   const struct powerpc_opcode *opcode;
 601   bfd_boolean insn_is_short;
 602
 603   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 604   if (status != 0)
 605     {
 606       /* The final instruction may be a 2-byte VLE insn.  */
 607       if ((dialect & PPC_OPCODE_VLE) != 0)
 608         {
 609           /* Clear buffer so unused bytes will not have garbage in them.  */
 610           buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
 611           status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 612           if (status != 0)
 613             {
 614               (*info->memory_error_func) (status, memaddr, info);
 615               return -1;
 616             }
 617         }
 618       else
 619         {
 620           (*info->memory_error_func) (status, memaddr, info);
 621           return -1;
 622         }
 623     }
 624
 625   if (bigendian)
 626     insn = bfd_getb32 (buffer);
 627   else
 628     insn = bfd_getl32 (buffer);
 629
 630   /* Get the major opcode of the insn.  */
 631   opcode = NULL;
 632   insn_is_short = FALSE;
 633   if ((dialect & PPC_OPCODE_VLE) != 0)
 634     {
 635       opcode = lookup_vle (insn);
 636       if (opcode != NULL)
 637         insn_is_short = PPC_OP_SE_VLE(opcode->mask);
 638     }
 639   if (opcode == NULL)
 640     opcode = lookup_powerpc (insn, dialect);
 641   if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
 642     opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
 643
 644   if (opcode != NULL)
 645     {
 646       const unsigned char *opindex;
 647       const struct powerpc_operand *operand;
 648       int need_comma;
 649       int need_paren;
 650       int skip_optional;
 651
 652       if (opcode->operands[0] != 0)
 653         (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
 654       else
 655         (*info->fprintf_func) (info->stream, "%s", opcode->name);
 656
 657       if (insn_is_short)
 658         /* The operands will be fetched out of the 16-bit instruction.  */
 659         insn >>= 16;
 660
 661       /* Now extract and print the operands.  */
 662       need_comma = 0;
 663       need_paren = 0;
 664       skip_optional = -1;
 665       for (opindex = opcode->operands; *opindex != 0; opindex++)
 666         {
 667           long value;
 668
 669           operand = powerpc_operands + *opindex;
 670
 671           /* Operands that are marked FAKE are simply ignored.  We
 672              already made sure that the extract function considered
 673              the instruction to be valid.  */
 674           if ((operand->flags & PPC_OPERAND_FAKE) != 0)
 675             continue;
 676
 677           /* If all of the optional operands have the value zero,
 678              then don't print any of them.  */
 679           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 680             {
 681               if (skip_optional < 0)
 682                 skip_optional = skip_optional_operands (opindex, insn,
 683                                                         dialect);
 684               if (skip_optional)
 685                 continue;
 686             }
 687
 688           value = operand_value_powerpc (operand, insn, dialect);
 689
 690           if (need_comma)
 691             {
 692               (*info->fprintf_func) (info->stream, ",");
 693               need_comma = 0;
 694             }
 695
 696           /* Print the operand as directed by the flags.  */
 697           if ((operand->flags & PPC_OPERAND_GPR) != 0
 698               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
 699             (*info->fprintf_func) (info->stream, "r%ld", value);
 700           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
 701             (*info->fprintf_func) (info->stream, "f%ld", value);
 702           else if ((operand->flags & PPC_OPERAND_VR) != 0)
 703             (*info->fprintf_func) (info->stream, "v%ld", value);
 704           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 705             (*info->fprintf_func) (info->stream, "vs%ld", value);
 706           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
 707             (*info->print_address_func) (memaddr + value, info);
 708           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
 709             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
 710           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
 711             (*info->fprintf_func) (info->stream, "fsl%ld", value);
 712           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
 713             (*info->fprintf_func) (info->stream, "fcr%ld", value);
 714           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 715             (*info->fprintf_func) (info->stream, "%ld", value);
 716           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
 717                    && (((dialect & PPC_OPCODE_PPC) != 0)
 718                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 719             (*info->fprintf_func) (info->stream, "cr%ld", value);
 720           else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
 721                    && (((dialect & PPC_OPCODE_PPC) != 0)
 722                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 723             {
 724               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
 725               int cr;
 726               int cc;
 727
 728               cr = value >> 2;
 729               if (cr != 0)
 730                 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
 731               cc = value & 3;
 732               (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 733             }
 734           else
 735             (*info->fprintf_func) (info->stream, "%d", (int) value);
 736
 737           if (need_paren)
 738             {
 739               (*info->fprintf_func) (info->stream, ")");
 740               need_paren = 0;
 741             }
 742
 743           if ((operand->flags & PPC_OPERAND_PARENS) == 0)
 744             need_comma = 1;
 745           else
 746             {
 747               (*info->fprintf_func) (info->stream, "(");
 748               need_paren = 1;
 749             }
 750         }
 751
 752       /* We have found and printed an instruction.
 753          If it was a short VLE instruction we have more to do.  */
 754       if (insn_is_short)
 755         {
 756           memaddr += 2;
 757           return 2;
 758         }
 759       else
 760         /* Otherwise, return.  */
 761         return 4;
 762     }
 763
 764   /* We could not find a match.  */
 765   (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
 766
 767   return 4;
 768 }
 769
 770 void
 771 print_ppc_disassembler_options (FILE *stream)
 772 {
 773   unsigned int i, col;
 774
 775   fprintf (stream, _("\n\
 776 The following PPC specific disassembler options are supported for use with\n\
 777 the -M switch:\n"));
 778
 779   for (col = 0, i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++)
 780     {
 781       col += fprintf (stream, " %s,", ppc_opts[i].opt);
 782       if (col > 66)
 783         {
 784           fprintf (stream, "\n");
 785           col = 0;
 786         }
 787     }
 788   fprintf (stream, " 32, 64\n");
 789 }