sim/aarch64/ChangeLog

   1 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * aclocal.m4, configure: Regenerate.
   4
   5 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * configure: Regenerate.
   8
   9 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
  10
  11         * cpustate.c: Include sim-signal.h.
  12         * memory.c, simulator.c: Likewise.
  13
  14 2021-06-17  Mike Frysinger  <vapier@gentoo.org>
  15
  16         * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
  17         * aclocal.m4, configure: Regenerate.
  18
  19 2021-06-16  Mike Frysinger  <vapier@gentoo.org>
  20
  21         * configure: Regenerate.
  22
  23 2021-06-16  Mike Frysinger  <vapier@gentoo.org>
  24
  25         * configure: Regenerate.
  26         * config.in: Removed.
  27
  28 2021-06-15  Mike Frysinger  <vapier@gentoo.org>
  29
  30         * config.in, configure: Regenerate.
  31
  32 2021-06-14  Mike Frysinger  <vapier@gentoo.org>
  33
  34         * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
  35         * configure: Regenerate.
  36
  37 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  38
  39         * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
  40         * interp.c (sim_open): Set current_alignment.
  41
  42 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  43
  44         * aclocal.m4, config.in, configure: Regenerate.
  45
  46 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  47
  48         * config.in, configure: Regenerate.
  49
  50 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
  51
  52         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
  53
  54 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
  55
  56         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
  57         (struct sim_state): Delete.
  58
  59 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  60
  61         * cpustate.c: Include defs.h.
  62         * interp.c: Replace config.h include with defs.h.
  63         * memory.c, simulator.c: Likewise.
  64         * cpustate.h, simulator.h: Delete config.h include.
  65
  66 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  67
  68         * config.in, configure: Regenerate.
  69
  70 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
  71
  72         * cpustate.h: Update include path.
  73         * interp.c: Likewise.
  74
  75 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
  76
  77         * configure: Regenerate.
  78
  79 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  80
  81         * config.in, configure: Regenerate.
  82
  83 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  84
  85         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
  86         (aarch64_set_FP_double, aarch64_set_FP_long_double,
  87         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  88
  89 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  90
  91         * simulator.c (do_fcvtzu): Change UL to ULL.
  92
  93 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
  94
  95         * aclocal.m4, config.in, configure: Regenerate.
  96
  97 2021-04-22  Tom Tromey  <tom@tromey.com>
  98
  99         * configure, config.in: Rebuild.
 100
 101 2021-04-22  Tom Tromey  <tom@tromey.com>
 102
 103         * configure: Rebuild.
 104
 105 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
 106
 107         * aclocal.m4: Regenerate.
 108
 109 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
 110
 111         * configure: Regenerate.
 112
 113 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
 114
 115         * configure: Regenerate.
 116
 117 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
 118
 119         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
 120
 121 2021-04-07  Jim Wilson  <jimw@sifive.com>
 122
 123         PR sim/27483
 124         * simulator.c (set_flags_for_add32): Compare uresult against
 125         itself.  Compare sresult against itself.
 126
 127 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
 128
 129         * aclocal.m4, configure: Regenerate.
 130
 131 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
 132
 133         * configure: Regenerate.
 134
 135 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
 136
 137         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
 138         * aclocal.m4, configure: Regenerate.
 139
 140 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
 141
 142         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
 143         * aclocal.m4, configure: Regenerate.
 144
 145 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
 146
 147         * configure: Regenerate.
 148
 149 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
 150
 151         * config.in, configure: Regenerate.
 152
 153 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
 154
 155         * configure: Regenerate.
 156
 157 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
 158
 159         * configure: Regenerate.
 160
 161 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
 162
 163         * configure: Regenerate.
 164
 165 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
 166
 167         PR sim/25318
 168         * simulator.c (blr): Read destination register before calling
 169         aarch64_save_LR.
 170
 171 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 172
 173         * cpustate.c: Add 'libiberty.h' include.
 174         * interp.c: Add 'sim-assert.h' include.
 175
 176 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 177
 178         * configure: Regenerate.
 179
 180 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 181
 182         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 183         registers based on structure size.
 184         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 185         (LD1_1): Replace with call to vec_load.
 186         (vec_store): Add new M argument.  Rewrite to iterate over registers
 187         based on structure size.
 188         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 189         (ST1_1): Replace with call to vec_store.
 190
 191 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 192
 193         * simulator.c (do_vec_FCVTL): New.
 194         (do_vec_op1): Call do_vec_FCVTL.
 195
 196         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 197         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 198         (do_scalar_vec): Add calls to new functions.
 199
 200 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 201
 202         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 203         flag check.
 204
 205 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 206
 207         * simulator.c (mul64hi): Shift carry left by 32.
 208         (smulh): Change signum to negate.  If negate, invert result, and add
 209         carry bit if low part of multiply result is zero.
 210
 211 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 212
 213         * simulator.c (do_vec_SMOV_into_scalar): New.
 214         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 215         Rewritten.
 216         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 217         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 218         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 219         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 220
 221         * simulator.c (popcount): New.
 222         (do_vec_CNT): New.
 223         (do_vec_op1): Add do_vec_CNT call.
 224
 225 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 226
 227         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 228         with type set to input type size.
 229         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 230
 231 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 232
 233         * simulator.c (do_vec_MLA): Rewrite switch body.
 234
 235         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 236         2.  Move test_false if inside loop.  Fix logic for computing result
 237         stored to vd.
 238
 239         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 240         (do_vec_LDn_single, do_vec_STn_single): New.
 241         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 242         loop over nregs using new var n.  Add n times size to address in loop.
 243         Add n to vd in loop.
 244         (do_vec_load_store): Add comment for instruction bit 24.  New var
 245         single to hold instruction bit 24.  Add new code to use single.  Move
 246         ldnr support inside single if statements.  Fix ldnr register counts
 247         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 248
 249 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 250
 251         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 252
 253 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 254
 255         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 256         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 257         case 3, call HALT_UNALLOC unconditionally.
 258         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 259         i + 2.  Delete if on bias, change index to i + bias * X.
 260
 261 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 262
 263         * simulator.c (do_vec_UZP): Rewrite.
 264
 265 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 266
 267         * cpustate.c: Include math.h.
 268         (aarch64_set_FP_float): Use signbit to check for signed zero.
 269         (aarch64_set_FP_double): Likewise.
 270         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 271         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 272         args same size as third arg.
 273         (fmaxnm): Use isnan instead of fpclassify.
 274         (fminnm, dmaxnm, dminnm): Likewise.
 275         (do_vec_MLS): Reverse order of subtraction operands.
 276         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 277         aarch64_get_FP_float to get source register contents.
 278         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 279         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 280         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 281         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 282         raise_exception calls.
 283
 284 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 285
 286         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 287         Add comment to document NaN issue.
 288         (set_flags_for_double_compare): Likewise.
 289
 290 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 291
 292         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 293         (set_flags_for_add64): Replace with a modified copy of
 294         set_flags_for_sub64.
 295
 296 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 297
 298         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 299         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 300
 301 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 302
 303         * simulator.c (fsturs): Switch use of rn and st variables.
 304         (fsturd, fsturq): Likewise
 305
 306 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 307
 308         * interp.c: Include bfd.h.
 309         (symcount, symtab, aarch64_get_sym_value): Delete.
 310         (remove_useless_symbols): Change count type to long.
 311         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 312         and symtab local variables.
 313         (sim_create_inferior): Delete storage.  Replace symbol code
 314         with a call to trace_load_symbols.
 315         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 316         includes.
 317         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 318         trace_sym_value.
 319         * memory.h: Delete bfd.h include.
 320         (mem_add_blk): Delete unused prototype.
 321         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 322         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 323         (aarch64_get_sym_value): Delete.
 324
 325 2016-08-12  Nick Clifton  <nickc@redhat.com>
 326
 327         * simulator.c (aarch64_step): Revert pervious delta.
 328         (aarch64_run): Call sim_events_tick after each
 329         instruction is simulated, and if necessary call
 330         sim_events_process.
 331         * simulator.h: Revert previous delta.
 332
 333 2016-08-11  Nick Clifton  <nickc@redhat.com>
 334
 335         * interp.c (sim_create_inferior): Allow for being called with a
 336         NULL abfd parameter.  If a bfd is provided, initialise the sim
 337         with that start address.
 338         * simulator.c (HALT_NYI): Just print out the numeric value of the
 339         instruction when not tracing.
 340         (aarch64_step): Change from static to global.
 341         * simulator.h: Add a prototype for aarch64_step().
 342
 343 2016-07-27  Alan Modra  <amodra@gmail.com>
 344
 345         * memory.c: Don't include libbfd.h.
 346
 347 2016-07-21  Nick Clifton  <nickc@redhat.com>
 348
 349         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 350
 351 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 352
 353         * cpustate.h: Include config.h.
 354         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 355         use anonymous structs to align members.
 356         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 357         endian_le2h_4 to read instruction from pc.
 358
 359 2016-05-06  Nick Clifton  <nickc@redhat.com>
 360
 361         * simulator.c (do_FMLA_by_element): New function.
 362         (do_vec_op2): Call it.
 363
 364 2016-04-27  Nick Clifton  <nickc@redhat.com>
 365
 366         * simulator.c: Add TRACE_DECODE statements to all emulation
 367         functions.
 368
 369 2016-03-30  Nick Clifton  <nickc@redhat.com>
 370
 371         * cpustate.c (aarch64_set_reg_s32): New function.
 372         (aarch64_set_reg_u32): New function.
 373         (aarch64_get_FP_half): Place half precision value into the correct
 374         slot of the union.
 375         (aarch64_set_FP_half): Likewise.
 376         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 377         aarch64_set_reg_u32.
 378         * memory.c (FETCH_FUNC): Cast the read value to the access type
 379         before converting it to the return type.  Rename to FETCH_FUNC64.
 380         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 381         accesses.  Use for 32-bit memory access functions.
 382         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 383         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 384         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 385         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 386         (ldrh32_abs): Store 32 bit value not 64-bits.
 387         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 388         (do_vec_MOV_immediate): Fix computation of val.
 389         (do_vec_MVNI): Likewise.
 390         (DO_VEC_WIDENING_MUL): New macro.
 391         (do_vec_mull): Use new macro.
 392         (do_vec_mul): Use new macro.
 393         (do_vec_MLA): Read values before writing.
 394         (do_vec_xtl): Likewise.
 395         (do_vec_SSHL): Select correct shift value.
 396         (do_vec_USHL): Likewise.
 397         (do_scalar_UCVTF): New function.
 398         (do_scalar_vec): Call new function.
 399         (store_pair_u64): Treat reads of SP as reads of XZR.
 400
 401 2016-03-29  Nick Clifton  <nickc@redhat.com>
 402
 403         * cpustate.c: Remove space after asterisk in function parameters.
 404         * decode.h (greg): Delete unused function.
 405         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 406         * simulator.c: Use INSTR macro in more places.
 407         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 408         Remove extraneous whitespace.
 409
 410 2016-03-23  Nick Clifton  <nickc@redhat.com>
 411
 412         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 413         register as a half precision floating point number.
 414         (aarch64_set_FP_half): New function.  Similar, but for setting
 415         a half precision register.
 416         (aarch64_get_thread_id): New function.  Returns the value of the
 417         CPU's TPIDR register.
 418         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 419         floating point control register.
 420         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 421         register.
 422         * cpustate.h: Add prototypes for new functions.
 423         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 424         * memory.c: Use unaligned core access functions for all memory
 425         reads and writes.
 426         * simulator.c (HALT_NYI): Generate an error message if tracing
 427         will not tell the user why the simulator is halting.
 428         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 429         (INSTR): New time-saver macro.
 430         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 431         offset.
 432         (fldrh_abs): New function.  Likewise for 16-bit values.
 433         (do_vec_SSHL): Allow for negative shift values.
 434         (do_vec_USHL): Likewise.
 435         (do_vec_SHL): Correct computation of shift amount.
 436         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 437         shifts and computation of shift value.
 438         (clz): New function.  Counts leading zero bits.
 439         (do_vec_CLZ): New function.  Implements CLZ (vector).
 440         (do_vec_MOV_element): Call do_vec_CLZ.
 441         (dexSimpleFPCondCompare): Implement.
 442         (do_FCVT_half_to_single): New function.  Implements one of the
 443         FCVT operations.
 444         (do_FCVT_half_to_double): New function.  Likewise.
 445         (do_FCVT_single_to_half): New function.  Likewise.
 446         (do_FCVT_double_to_half): New function.  Likewise.
 447         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 448         (do_scalar_SHL): Handle negative shifts.
 449         (do_scalar_shift): Handle SSHR.
 450         (do_scalar_USHL): New function.
 451         (do_double_add): Simplify to just performing a double precision
 452         add operation.  Move remaining code into...
 453         (do_scalar_vec): ... New function.
 454         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 455         functions.
 456         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 457         registers.
 458         (system_set): New function.
 459         (do_MSR_immediate): New function.  Stub for now.
 460         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 461         instruction.
 462         (do_SYS): New function.  Stub for now,
 463         (dexSystem): Call new functions.
 464
 465 2016-03-18  Nick Clifton  <nickc@redhat.com>
 466
 467         * cpustate.c: Remove spurious spaces from TRACE strings.
 468         Print hex equivalents of floats and doubles.
 469         Check element number against array size when accessing vector
 470         registers.
 471         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 472         element index.
 473         (SET_VEC_ELEMENT): Likewise.
 474         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 475
 476         * memory.c: Trace memory reads when --trace-memory is enabled.
 477         Remove float and double load and store functions.
 478         * memory.h (aarch64_get_mem_float): Delete prototype.
 479         (aarch64_get_mem_double): Likewise.
 480         (aarch64_set_mem_float): Likewise.
 481         (aarch64_set_mem_double): Likewise.
 482         * simulator (IS_SET): Always return either 0 or 1.
 483         (IS_CLEAR): Likewise.
 484         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 485         and doubles using 64-bit memory accesses.
 486         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 487         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 488         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 489         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 490         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 491         (do_vec_MUL_by_element): New function.
 492         (do_vec_op2): Call do_vec_MUL_by_element.
 493         (do_scalar_NEG): New function.
 494         (do_double_add): Call do_scalar_NEG.
 495
 496 2016-03-03  Nick Clifton  <nickc@redhat.com>
 497
 498         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 499         (CondCompare): Swap interpretation of bit 30.
 500         (DO_ADDP): Delete macro.
 501         (do_vec_ADDP): Copy source registers before starting to update
 502         destination register.
 503         (do_vec_FADDP): Likewise.
 504         (do_vec_load_store): Fix computation of sizeof_operation.
 505         (rbit64): Fix type of constant.
 506         (aarch64_step): When displaying insn value, display all 32 bits.
 507
 508 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 509
 510         * config.in, configure: Regenerate.
 511
 512 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 513
 514         * configure: Regenerate.
 515
 516 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 517
 518         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 519         * configure: Regenerate.
 520
 521 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 522
 523         * configure: Regenerate.
 524
 525 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 526
 527         * configure: Regenerate.
 528
 529 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 530
 531         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 532         * configure: Regenerate.
 533
 534 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 535
 536         * configure: Regenerate.
 537
 538 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 539
 540         * configure: Regenerate.
 541
 542 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 543
 544         * config.in, configure: Regenerate.
 545
 546 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 547
 548         * interp.c (sim_create_inferior): Mark argv and env const.
 549         (sim_open): Mark argv const.
 550
 551 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 552
 553         * interp.c: Delete dis-asm.h include.
 554         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 555         (sim_create_inferior): Delete disassemble init logic.
 556         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 557         (sim_open): Delete sim_add_option_table call.
 558         * memory.c (mem_error): Delete disas check.
 559         * simulator.c: Delete dis-asm.h include.
 560         (disas): Delete.
 561         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 562         (HALT_NYI): Likewise.
 563         (handle_halt): Delete disas call.
 564         (aarch64_step): Replace disas logic with TRACE_DISASM.
 565         * simulator.h: Delete dis-asm.h include.
 566         (aarch64_print_insn): Delete.
 567
 568 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 569
 570         * simulator.c (MAX, MIN): Delete.
 571         (do_vec_maxv): Change MAX to max and MIN to min.
 572         (do_vec_fminmaxV): Likewise.
 573
 574 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 575
 576         * simulator.c: Remove syscall.h include.
 577
 578 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 579
 580         * configure: Regenerate.
 581
 582 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 583
 584         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 585         * configure: Regenerate.
 586
 587 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 588
 589         * configure: Regenerate.
 590
 591 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 592
 593         * interp.c (sim_dis_read): Change private_data to application_data.
 594         (sim_create_inferior): Likewise.
 595
 596 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 597
 598         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 599
 600 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 601
 602         * config.in, configure: Regenerate.
 603
 604 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 605
 606         * interp.c (sim_create_inferior): Update comment and argv check.
 607
 608 2015-12-14  Nick Clifton  <nickc@redhat.com>
 609
 610         * simulator.c (system_get): New function.  Provides read
 611         access to the dczid system register.
 612         (do_mrs): New function - implements the MRS instruction.
 613         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 614         unimplemented system instructions.
 615
 616 2015-11-24  Nick Clifton  <nickc@redhat.com>
 617
 618         * configure.ac: New configure template.
 619         * aclocal.m4: Generate.
 620         * config.in: Generate.
 621         * configure: Generate.
 622         * cpustate.c: New file - functions for accessing AArch64 registers.
 623         * cpustate.h: New header.
 624         * decode.h: New header.
 625         * interp.c: New file - interface between GDB and simulator.
 626         * Makefile.in: New makefile template.
 627         * memory.c: New file - functions for simulating aarch64 memory
 628         accesses.
 629         * memory.h: New header.
 630         * sim-main.h: New header.
 631         * simulator.c: New file - aarch64 simulator functions.
 632         * simulator.h: New header.