sim/arm/armemu.h

   1 /*  armemu.h -- ARMulator emulation macros:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 2 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, write to the Free Software
  16     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  17
  18 extern ARMword isize;
  19
  20 /***************************************************************************\
  21 *                           Condition code values                           *
  22 \***************************************************************************/
  23
  24 #define EQ 0
  25 #define NE 1
  26 #define CS 2
  27 #define CC 3
  28 #define MI 4
  29 #define PL 5
  30 #define VS 6
  31 #define VC 7
  32 #define HI 8
  33 #define LS 9
  34 #define GE 10
  35 #define LT 11
  36 #define GT 12
  37 #define LE 13
  38 #define AL 14
  39 #define NV 15
  40
  41 /***************************************************************************\
  42 *                               Shift Opcodes                               *
  43 \***************************************************************************/
  44
  45 #define LSL 0
  46 #define LSR 1
  47 #define ASR 2
  48 #define ROR 3
  49
  50 /***************************************************************************\
  51 *               Macros to twiddle the status flags and mode                 *
  52 \***************************************************************************/
  53
  54 #define NBIT ((unsigned)1L << 31)
  55 #define ZBIT (1L << 30)
  56 #define CBIT (1L << 29)
  57 #define VBIT (1L << 28)
  58 #define IBIT (1L << 7)
  59 #define FBIT (1L << 6)
  60 #define IFBITS (3L << 6)
  61 #define R15IBIT (1L << 27)
  62 #define R15FBIT (1L << 26)
  63 #define R15IFBITS (3L << 26)
  64
  65 #define POS(i) ( (~(i)) >> 31 )
  66 #define NEG(i) ( (i) >> 31 )
  67
  68 #ifdef MODET /* Thumb support */
  69 /* ??? This bit is actually in the low order bit of the PC in the hardware.
  70    It isn't clear if the simulator needs to model that or not.  */
  71 #define TBIT (1L << 5)
  72 #define TFLAG state->TFlag
  73 #define SETT state->TFlag = 1
  74 #define CLEART state->TFlag = 0
  75 #define ASSIGNT(res) state->TFlag = res
  76 #endif
  77
  78 #define NFLAG state->NFlag
  79 #define SETN state->NFlag = 1
  80 #define CLEARN state->NFlag = 0
  81 #define ASSIGNN(res) state->NFlag = res
  82
  83 #define ZFLAG state->ZFlag
  84 #define SETZ state->ZFlag = 1
  85 #define CLEARZ state->ZFlag = 0
  86 #define ASSIGNZ(res) state->ZFlag = res
  87
  88 #define CFLAG state->CFlag
  89 #define SETC state->CFlag = 1
  90 #define CLEARC state->CFlag = 0
  91 #define ASSIGNC(res) state->CFlag = res
  92
  93 #define VFLAG state->VFlag
  94 #define SETV state->VFlag = 1
  95 #define CLEARV state->VFlag = 0
  96 #define ASSIGNV(res) state->VFlag = res
  97
  98 #define IFLAG (state->IFFlags >> 1)
  99 #define FFLAG (state->IFFlags & 1)
 100 #define IFFLAGS state->IFFlags
 101 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
 102 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
 103
 104 #define CCBITS (0xf0000000L)
 105 #define INTBITS (0xc0L)
 106
 107 #if defined MODET && defined MODE32
 108 #define PCBITS (0xffffffffL)
 109 #else
 110 #define PCBITS (0xfffffffcL)
 111 #endif
 112
 113 #define MODEBITS (0x1fL)
 114 #define R15INTBITS (3L << 26)
 115
 116 #if defined MODET && defined MODE32
 117 #define R15PCBITS (0x03ffffffL)
 118 #else
 119 #define R15PCBITS (0x03fffffcL)
 120 #endif
 121
 122 #define R15PCMODEBITS (0x03ffffffL)
 123 #define R15MODEBITS (0x3L)
 124
 125 #ifdef MODE32
 126 #define PCMASK PCBITS
 127 #define PCWRAP(pc) (pc)
 128 #else
 129 #define PCMASK R15PCBITS
 130 #define PCWRAP(pc) ((pc) & R15PCBITS)
 131 #endif
 132
 133 #define PC (state->Reg[15] & PCMASK)
 134 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
 135 #define R15INT (state->Reg[15] & R15INTBITS)
 136 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
 137 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
 138 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
 139 #define R15PC (state->Reg[15] & R15PCBITS)
 140 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
 141 #define R15MODE (state->Reg[15] & R15MODEBITS)
 142
 143 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
 144 #define EINT (IFFLAGS << 6)
 145 #define ER15INT (IFFLAGS << 26)
 146 #define EMODE (state->Mode)
 147
 148 #ifdef MODET
 149 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
 150 #else
 151 #define CPSR (ECC | EINT | EMODE)
 152 #endif
 153
 154 #ifdef MODE32
 155 #define PATCHR15
 156 #else
 157 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
 158 #endif
 159
 160 #define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
 161 #define SETPSR(d,s) d = (s) & (ARMword)(CCBITS | INTBITS | MODEBITS)
 162 #define SETINTMODE(d,s) d = ((d) & CCBITS) | ((s) & (INTBITS | MODEBITS))
 163 #define SETCC(d,s) d = ((d) & (INTBITS | MODEBITS)) | ((s) & CCBITS)
 164 #define SETR15PSR(s) if (state->Mode == USER26MODE) { \
 165                         state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
 166                         ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
 167                         ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
 168                         ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
 169                         ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
 170                         } \
 171                      else { \
 172                         state->Reg[15] = R15PC | (s) & (CCBITS | R15INTBITS | R15MODEBITS) ; \
 173                         ARMul_R15Altered(state) ; \
 174                         }
 175 #define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
 176
 177 #ifndef MODE32
 178 #define VECTORS 0x20
 179 #define LEGALADDR 0x03ffffff
 180 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
 181 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
 182 #endif
 183
 184 #define INTERNALABORT(address) if (address < VECTORS) \
 185                                   state->Aborted = ARMul_DataAbortV ; \
 186                                else \
 187                                   state->Aborted = ARMul_AddrExceptnV ;
 188
 189 #ifdef MODE32
 190 #define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
 191 #else
 192 #define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
 193                      ARMul_Abort(state,ARMul_AddrExceptnV) ; \
 194                   else \
 195                      ARMul_Abort(state,ARMul_DataAbortV)
 196 #endif
 197 #define CPTAKEABORT if (!state->Aborted) \
 198                        ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
 199                     else if (state->Aborted == ARMul_AddrExceptnV) \
 200                        ARMul_Abort(state,ARMul_AddrExceptnV) ; \
 201                     else \
 202                        ARMul_Abort(state,ARMul_DataAbortV)
 203
 204
 205 /***************************************************************************\
 206 *               Different ways to start the next instruction                *
 207 \***************************************************************************/
 208
 209 #define SEQ 0
 210 #define NONSEQ 1
 211 #define PCINCEDSEQ 2
 212 #define PCINCEDNONSEQ 3
 213 #define PRIMEPIPE 4
 214 #define RESUME 8
 215
 216 #define NORMALCYCLE state->NextInstr = 0
 217 #define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */
 218 #define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
 219                       state->NextInstr = (state->NextInstr & 0xff) | 2
 220 #define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
 221                       state->NextInstr |= 3
 222 #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
 223               state->NextInstr |= 2
 224 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
 225
 226 /***************************************************************************\
 227 *                          Cycle based emulation                            *
 228 \***************************************************************************/
 229
 230 #define OUTPUTCP(i,a,b)
 231 #define NCYCLE
 232 #define SCYCLE
 233 #define ICYCLE
 234 #define CCYCLE
 235 #define NEXTCYCLE(c)
 236
 237 /***************************************************************************\
 238 *                 States of the cycle based state machine                   *
 239 \***************************************************************************/
 240
 241
 242 /***************************************************************************\
 243 *                 Macros to extract parts of instructions                   *
 244 \***************************************************************************/
 245
 246 #define DESTReg (BITS(12,15))
 247 #define LHSReg (BITS(16,19))
 248 #define RHSReg (BITS(0,3))
 249
 250 #define DEST (state->Reg[DESTReg])
 251
 252 #ifdef MODE32
 253 #ifdef MODET
 254 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
 255 #else
 256 #define LHS (state->Reg[LHSReg])
 257 #endif
 258 #else
 259 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
 260 #endif
 261
 262 #define MULDESTReg (BITS(16,19))
 263 #define MULLHSReg (BITS(0,3))
 264 #define MULRHSReg (BITS(8,11))
 265 #define MULACCReg (BITS(12,15))
 266
 267 #define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
 268 #define DPSImmRHS temp = BITS(0,11) ; \
 269                   rhs = ARMul_ImmedTable[temp] ; \
 270                   if (temp > 255) /* there was a shift */ \
 271                      ASSIGNC(rhs >> 31) ;
 272
 273 #ifdef MODE32
 274 #define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
 275                                   : GetDPRegRHS(state, instr))
 276 #define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
 277                                    : GetDPSRegRHS(state, instr))
 278 #else
 279 #define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
 280                                   : GetDPRegRHS(state, instr))
 281 #define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
 282                                    : GetDPSRegRHS(state, instr))
 283 #endif
 284
 285 #define LSBase state->Reg[LHSReg]
 286 #define LSImmRHS (BITS(0,11))
 287
 288 #ifdef MODE32
 289 #define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
 290                                   : GetLSRegRHS(state, instr))
 291 #else
 292 #define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
 293                                   : GetLSRegRHS(state, instr))
 294 #endif
 295
 296 #define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
 297                     (ARMword)ARMul_BitList[BITS(8,15)] )
 298 #define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
 299                       (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
 300
 301 #define SWAPSRC (state->Reg[RHSReg])
 302
 303 #define LSCOff (BITS(0,7) << 2)
 304 #define CPNum BITS(8,11)
 305
 306 /***************************************************************************\
 307 *                    Macro to rotate n right by b bits                      *
 308 \***************************************************************************/
 309
 310 #define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))
 311
 312 /***************************************************************************\
 313 *                 Macros to store results of instructions                   *
 314 \***************************************************************************/
 315
 316 #define WRITEDEST(d) if (DESTReg==15) \
 317                         WriteR15(state, d) ; \
 318                      else \
 319                           DEST = d
 320
 321 #define WRITESDEST(d) if (DESTReg == 15) \
 322                          WriteSR15(state, d) ; \
 323                       else { \
 324                          DEST = d ; \
 325                          ARMul_NegZero(state, d) ; \
 326                          }
 327
 328 #define BYTETOBUS(data) ((data & 0xff) | \
 329                         ((data & 0xff) << 8) | \
 330                         ((data & 0xff) << 16) | \
 331                         ((data & 0xff) << 24))
 332 #define BUSTOBYTE(address,data) \
 333            if (state->bigendSig) \
 334               temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
 335            else \
 336               temp = (data >> ((address & 3) << 3)) & 0xff
 337
 338 #define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
 339 #define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
 340 #define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
 341 #define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
 342
 343 #define POSBRANCH ((instr & 0x7fffff) << 2)
 344 #define NEGBRANCH (0xff000000 | ((instr & 0xffffff) << 2))
 345
 346 /***************************************************************************\
 347 *                          Values for Emulate                               *
 348 \***************************************************************************/
 349
 350 #define STOP            0 /* stop */
 351 #define CHANGEMODE      1 /* change mode */
 352 #define ONCE            2 /* execute just one interation */
 353 #define RUN             3 /* continuous execution */
 354
 355 /***************************************************************************\
 356 *                      Stuff that is shared across modes                    *
 357 \***************************************************************************/
 358
 359 extern ARMword ARMul_Emulate26(ARMul_State *state) ;
 360 extern ARMword ARMul_Emulate32(ARMul_State *state) ;
 361 extern unsigned ARMul_MultTable[] ; /* Number of I cycles for a mult */
 362 extern ARMword ARMul_ImmedTable[] ; /* immediate DP LHS values */
 363 extern char ARMul_BitList[] ; /* number of bits in a byte table */
 364 extern void ARMul_Abort26(ARMul_State *state, ARMword) ;
 365 extern void ARMul_Abort32(ARMul_State *state, ARMword) ;
 366 extern unsigned ARMul_NthReg(ARMword instr,unsigned number) ;
 367 extern void ARMul_MSRCpsr(ARMul_State *state, ARMword instr, ARMword rhs) ;
 368 extern void ARMul_NegZero(ARMul_State *state, ARMword result) ;
 369 extern void ARMul_AddCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
 370 extern void ARMul_AddOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
 371 extern void ARMul_SubCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
 372 extern void ARMul_SubOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
 373 extern void ARMul_CPSRAltered(ARMul_State *state) ;
 374 extern void ARMul_R15Altered(ARMul_State *state) ;
 375 extern ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode) ;
 376 extern unsigned ARMul_NthReg(ARMword instr, unsigned number) ;
 377 extern void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address) ;
 378 extern void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address) ;
 379 extern void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source) ;
 380 extern ARMword ARMul_MRC(ARMul_State *state,ARMword instr) ;
 381 extern void ARMul_CDP(ARMul_State *state,ARMword instr) ;
 382 extern unsigned IntPending(ARMul_State *state) ;
 383 extern ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data) ;
 384 #define EVENTLISTSIZE 1024L
 385
 386 /* Thumb support: */
 387
 388 typedef enum {
 389   t_undefined,  /* undefined Thumb instruction */
 390   t_decoded,    /* instruction decoded to ARM equivalent */
 391   t_branch      /* Thumb branch (already processed) */
 392 } tdstate;
 393
 394 extern tdstate ARMul_ThumbDecode(ARMul_State *state,ARMword pc,ARMword tinstr, ARMword *ainstr);
 395
 396 /***************************************************************************\
 397 *                      Macros to scrutinize instructions                    *
 398 \***************************************************************************/
 399
 400
 401 #define UNDEF_Test
 402 #define UNDEF_Shift
 403 #define UNDEF_MSRPC
 404 #define UNDEF_MRSPC
 405 #define UNDEF_MULPCDest
 406 #define UNDEF_MULDestEQOp1
 407 #define UNDEF_LSRBPC
 408 #define UNDEF_LSRBaseEQOffWb
 409 #define UNDEF_LSRBaseEQDestWb
 410 #define UNDEF_LSRPCBaseWb
 411 #define UNDEF_LSRPCOffWb
 412 #define UNDEF_LSMNoRegs
 413 #define UNDEF_LSMPCBase
 414 #define UNDEF_LSMUserBankWb
 415 #define UNDEF_LSMBaseInListWb
 416 #define UNDEF_SWPPC
 417 #define UNDEF_CoProHS
 418 #define UNDEF_MCRPC
 419 #define UNDEF_LSCPCBaseWb
 420 #define UNDEF_UndefNotBounced
 421 #define UNDEF_ShortInt
 422 #define UNDEF_IllegalMode
 423 #define UNDEF_Prog32SigChange
 424 #define UNDEF_Data32SigChange
 425