sim/arm/armos.c

   1 /*  armos.c -- ARMulator OS interface:  ARM6 Instruction Emulator.
   2     Copyright (C) 1994 Advanced RISC Machines Ltd.
   3
   4     This program is free software; you can redistribute it and/or modify
   5     it under the terms of the GNU General Public License as published by
   6     the Free Software Foundation; either version 3 of the License, or
   7     (at your option) any later version.
   8
   9     This program is distributed in the hope that it will be useful,
  10     but WITHOUT ANY WARRANTY; without even the implied warranty of
  11     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12     GNU General Public License for more details.
  13
  14     You should have received a copy of the GNU General Public License
  15     along with this program; if not, see <http://www.gnu.org/licenses/>. */
  16
  17 /* This file contains a model of Demon, ARM Ltd's Debug Monitor,
  18    including all the SWI's required to support the C library. The code in
  19    it is not really for the faint-hearted (especially the abort handling
  20    code), but it is a complete example. Defining NOOS will disable all the
  21    fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
  22    0x11 to halt the emulator.  */
  23
  24 /* This must come before any other includes.  */
  25 #include "defs.h"
  26
  27 #include "ansidecl.h"
  28 #include "libiberty.h"
  29
  30 #include <time.h>
  31 #include <errno.h>
  32 #include <limits.h>
  33 #include <string.h>
  34 #include <unistd.h>             /* For SEEK_SET etc.  */
  35
  36 #include "armdefs.h"
  37 #include "armos.h"
  38 #include "armemu.h"
  39
  40 #ifndef NOOS
  41 #ifndef VALIDATE
  42 /* #ifndef ASIM */
  43 #include "armfpe.h"
  44 /* #endif */
  45 #endif
  46 #endif
  47
  48 /* For RDIError_BreakpointReached.  */
  49 #include "dbg_rdi.h"
  50
  51 #include "sim/callback.h"
  52 extern host_callback *sim_callback;
  53
  54 extern unsigned ARMul_OSInit       (ARMul_State *);
  55 extern unsigned ARMul_OSHandleSWI  (ARMul_State *, ARMword);
  56
  57 #ifndef FOPEN_MAX
  58 #define FOPEN_MAX 64
  59 #endif
  60 #ifndef PATH_MAX
  61 #define PATH_MAX 1024
  62 #endif
  63
  64 /* OS private Information.  */
  65
  66 struct OSblock
  67 {
  68   ARMword ErrorNo;
  69 };
  70
  71 /* Bit mask of enabled SWI implementations.  */
  72 unsigned int swi_mask = -1;
  73
  74
  75 static ARMword softvectorcode[] =
  76 {
  77   /* Installed instructions:
  78        swi    tidyexception + event;
  79        mov    lr, pc;
  80        ldmia  fp, {fp, pc};
  81        swi    generateexception  + event.  */
  82   0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
  83   0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
  84   0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
  85   0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */
  86   0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */
  87   0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */
  88   0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */
  89   0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */
  90   0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */
  91   0xe1a0f00e                    /* Default handler */
  92 };
  93
  94 /* Time for the Operating System to initialise itself.  */
  95
  96 unsigned
  97 ARMul_OSInit (ARMul_State * state)
  98 {
  99 #ifndef NOOS
 100 #ifndef VALIDATE
 101   ARMword instr, i, j;
 102   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 103
 104   if (state->OSptr == NULL)
 105     {
 106       state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
 107       if (state->OSptr == NULL)
 108         {
 109           perror ("OS Memory");
 110           exit (15);
 111         }
 112     }
 113
 114   OSptr = (struct OSblock *) state->OSptr;
 115   state->Reg[13] = ADDRSUPERSTACK;                      /* Set up a stack for the current mode...  */
 116   ARMul_SetReg (state, SVC32MODE,   13, ADDRSUPERSTACK);/* ...and for supervisor mode...  */
 117   ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode...  */
 118   ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode...  */
 119   ARMul_SetReg (state, SYSTEMMODE,  13, ADDRSUPERSTACK);/* ...and for system mode.  */
 120   instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8);           /* Load pc from soft vector */
 121
 122   for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
 123     /* Write hardware vectors.  */
 124     ARMul_WriteWord (state, i, instr);
 125
 126   SWI_vector_installed = 0;
 127
 128   for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
 129     {
 130       ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
 131       ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
 132                        SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
 133     }
 134
 135   for (i = 0; i < sizeof (softvectorcode); i += 4)
 136     ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
 137
 138   ARMul_ConsolePrint (state, ", Demon 1.01");
 139
 140 /* #ifndef ASIM */
 141
 142   /* Install FPE.  */
 143   for (i = 0; i < fpesize; i += 4)
 144     /* Copy the code.  */
 145     ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
 146
 147   /* Scan backwards from the end of the code.  */
 148   for (i = FPESTART + fpesize;; i -= 4)
 149     {
 150       /* When we reach the marker value, break out of
 151          the loop, leaving i pointing at the maker.  */
 152       if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
 153         break;
 154
 155       /* If necessary, reverse the error strings.  */
 156       if (state->bigendSig && j < 0x80000000)
 157         {
 158           /* It's part of the string so swap it.  */
 159           j = ((j >> 0x18) & 0x000000ff) |
 160             ((j >> 0x08) & 0x0000ff00) |
 161             ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
 162           ARMul_WriteWord (state, i, j);
 163         }
 164     }
 165
 166   /* Copy old illegal instr vector.  */
 167   ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));
 168   /* Install new vector.  */
 169   ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
 170   ARMul_ConsolePrint (state, ", FPE");
 171
 172 /* #endif  ASIM */
 173 #endif /* VALIDATE */
 174 #endif /* NOOS */
 175
 176   /* Intel do not want DEMON SWI support.  */
 177    if (state->is_XScale)
 178     swi_mask = SWI_MASK_ANGEL;
 179
 180    return TRUE;
 181 }
 182
 183 /* These are libgloss defines, but seem to be common across all supported ARM
 184    targets at the moment.  These should get moved to the callback open_map.  */
 185 #define TARGET_O_BINARY 0
 186 #define TARGET_O_APPEND 0x8
 187 #define TARGET_O_CREAT 0x200
 188 #define TARGET_O_RDONLY 0x0
 189 #define TARGET_O_RDWR 0x2
 190 #define TARGET_O_TRUNC 0x400
 191 #define TARGET_O_WRONLY 0x1
 192
 193 static const int translate_open_mode[] =
 194 {
 195   TARGET_O_RDONLY,              /* "r"   */
 196   TARGET_O_RDONLY + TARGET_O_BINARY,    /* "rb"  */
 197   TARGET_O_RDWR,                /* "r+"  */
 198   TARGET_O_RDWR + TARGET_O_BINARY,              /* "r+b" */
 199   TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC,    /* "w"   */
 200   TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC,  /* "wb"  */
 201   TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC,      /* "w+"  */
 202   TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC,    /* "w+b" */
 203   TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT,   /* "a"   */
 204   TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab"  */
 205   TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT,     /* "a+"  */
 206   TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT    /* "a+b" */
 207 };
 208
 209 static void
 210 SWIWrite0 (ARMul_State * state, ARMword addr)
 211 {
 212   ARMword temp;
 213   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 214
 215   while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
 216     {
 217       char buffer = temp;
 218       /* Note - we cannot just cast 'temp' to a (char *) here,
 219          since on a big-endian host the byte value will end
 220          up in the wrong place and a nul character will be printed.  */
 221       (void) sim_callback->write_stdout (sim_callback, & buffer, 1);
 222     }
 223
 224   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 225 }
 226
 227 static void
 228 WriteCommandLineTo (ARMul_State * state, ARMword addr)
 229 {
 230   ARMword temp;
 231   char *cptr = state->CommandLine;
 232
 233   if (cptr == NULL)
 234     cptr = "\0";
 235   do
 236     {
 237       temp = (ARMword) * cptr++;
 238       ARMul_SafeWriteByte (state, addr++, temp);
 239     }
 240   while (temp != 0);
 241 }
 242
 243 static int
 244 ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
 245 {
 246   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 247   char *p = buf;
 248
 249   while (n--)
 250     if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
 251       return 0;
 252   OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
 253   state->Reg[0] = -1;
 254   return -1;
 255 }
 256
 257 static void
 258 SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
 259 {
 260   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 261   char buf[PATH_MAX];
 262   int flags;
 263
 264   if (ReadFileName (state, buf, name, sizeof buf) == -1)
 265     return;
 266
 267   /* Now we need to decode the Demon open mode.  */
 268   if (SWIflags >= ARRAY_SIZE (translate_open_mode))
 269     flags = 0;
 270   else
 271     flags = translate_open_mode[SWIflags];
 272
 273   /* Filename ":tt" is special: it denotes stdin/out.  */
 274   if (strcmp (buf, ":tt") == 0)
 275     {
 276       if (flags == TARGET_O_RDONLY) /* opening tty "r" */
 277         state->Reg[0] = 0;      /* stdin */
 278       else
 279         state->Reg[0] = 1;      /* stdout */
 280     }
 281   else
 282     {
 283       state->Reg[0] = sim_callback->open (sim_callback, buf, flags);
 284       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 285     }
 286 }
 287
 288 static void
 289 SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
 290 {
 291   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 292   int res;
 293   int i;
 294   char *local = malloc (len);
 295
 296   if (local == NULL)
 297     {
 298       sim_callback->printf_filtered
 299         (sim_callback,
 300          "sim: Unable to read 0x%lx bytes - out of memory\n",
 301          (long)len);
 302       return;
 303     }
 304
 305   res = sim_callback->read (sim_callback, f, local, len);
 306   if (res > 0)
 307     for (i = 0; i < res; i++)
 308       ARMul_SafeWriteByte (state, ptr + i, local[i]);
 309
 310   free (local);
 311   state->Reg[0] = res == -1 ? -1 : len - res;
 312   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 313 }
 314
 315 static void
 316 SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
 317 {
 318   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 319   int res;
 320   ARMword i;
 321   char *local = malloc (len);
 322
 323   if (local == NULL)
 324     {
 325       sim_callback->printf_filtered
 326         (sim_callback,
 327          "sim: Unable to write 0x%lx bytes - out of memory\n",
 328          (long) len);
 329       return;
 330     }
 331
 332   for (i = 0; i < len; i++)
 333     local[i] = ARMul_SafeReadByte (state, ptr + i);
 334
 335   res = sim_callback->write (sim_callback, f, local, len);
 336   state->Reg[0] = res == -1 ? -1 : len - res;
 337   free (local);
 338
 339   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 340 }
 341
 342 static void
 343 SWIflen (ARMul_State * state, ARMword fh)
 344 {
 345   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 346   ARMword addr;
 347
 348   if (fh > FOPEN_MAX)
 349     {
 350       OSptr->ErrorNo = EBADF;
 351       state->Reg[0] = -1L;
 352       return;
 353     }
 354
 355   addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR);
 356
 357   state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END);
 358   (void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET);
 359
 360   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 361 }
 362
 363 static void
 364 SWIremove (ARMul_State * state, ARMword path)
 365 {
 366   char buf[PATH_MAX];
 367
 368   if (ReadFileName (state, buf, path, sizeof buf) != -1)
 369     {
 370       struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 371       state->Reg[0] = sim_callback->unlink (sim_callback, buf);
 372       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 373     }
 374 }
 375
 376 static void
 377 SWIrename (ARMul_State * state, ARMword old, ARMword new)
 378 {
 379   char oldbuf[PATH_MAX], newbuf[PATH_MAX];
 380
 381   if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
 382       && ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
 383     {
 384       struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 385       state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
 386       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 387     }
 388 }
 389
 390 /* The emulator calls this routine when a SWI instruction is encuntered.
 391    The parameter passed is the SWI number (lower 24 bits of the instruction).  */
 392
 393 unsigned
 394 ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
 395 {
 396   struct OSblock * OSptr = (struct OSblock *) state->OSptr;
 397   int              unhandled = FALSE;
 398
 399   switch (number)
 400     {
 401     case SWI_Read:
 402       if (swi_mask & SWI_MASK_DEMON)
 403         SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
 404       else
 405         unhandled = TRUE;
 406       break;
 407
 408     case SWI_Write:
 409       if (swi_mask & SWI_MASK_DEMON)
 410         SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
 411       else
 412         unhandled = TRUE;
 413       break;
 414
 415     case SWI_Open:
 416       if (swi_mask & SWI_MASK_DEMON)
 417         SWIopen (state, state->Reg[0], state->Reg[1]);
 418       else
 419         unhandled = TRUE;
 420       break;
 421
 422     case SWI_Clock:
 423       if (swi_mask & SWI_MASK_DEMON)
 424         {
 425           /* Return number of centi-seconds.  */
 426           state->Reg[0] =
 427 #ifdef CLOCKS_PER_SEC
 428             (CLOCKS_PER_SEC >= 100)
 429             ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
 430             : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
 431 #else
 432           /* Presume unix... clock() returns microseconds.  */
 433           (ARMword) (clock () / 10000);
 434 #endif
 435           OSptr->ErrorNo = errno;
 436         }
 437       else
 438         unhandled = TRUE;
 439       break;
 440
 441     case SWI_Time:
 442       if (swi_mask & SWI_MASK_DEMON)
 443         {
 444           state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
 445           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 446         }
 447       else
 448         unhandled = TRUE;
 449       break;
 450
 451     case SWI_Close:
 452       if (swi_mask & SWI_MASK_DEMON)
 453         {
 454           state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]);
 455           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 456         }
 457       else
 458         unhandled = TRUE;
 459       break;
 460
 461     case SWI_Flen:
 462       if (swi_mask & SWI_MASK_DEMON)
 463         SWIflen (state, state->Reg[0]);
 464       else
 465         unhandled = TRUE;
 466       break;
 467
 468     case SWI_Exit:
 469       if (swi_mask & SWI_MASK_DEMON)
 470         state->Emulate = FALSE;
 471       else
 472         unhandled = TRUE;
 473       break;
 474
 475     case SWI_Seek:
 476       if (swi_mask & SWI_MASK_DEMON)
 477         {
 478           /* We must return non-zero for failure.  */
 479           state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET);
 480           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 481         }
 482       else
 483         unhandled = TRUE;
 484       break;
 485
 486     case SWI_WriteC:
 487       if (swi_mask & SWI_MASK_DEMON)
 488         {
 489           char tmp = state->Reg[0];
 490           (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
 491           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 492         }
 493       else
 494         unhandled = TRUE;
 495       break;
 496
 497     case SWI_Write0:
 498       if (swi_mask & SWI_MASK_DEMON)
 499         SWIWrite0 (state, state->Reg[0]);
 500       else
 501         unhandled = TRUE;
 502       break;
 503
 504     case SWI_GetErrno:
 505       if (swi_mask & SWI_MASK_DEMON)
 506         state->Reg[0] = OSptr->ErrorNo;
 507       else
 508         unhandled = TRUE;
 509       break;
 510
 511     case SWI_GetEnv:
 512       if (swi_mask & SWI_MASK_DEMON)
 513         {
 514           state->Reg[0] = ADDRCMDLINE;
 515           if (state->MemSize)
 516             state->Reg[1] = state->MemSize;
 517           else
 518             state->Reg[1] = ADDRUSERSTACK;
 519
 520           WriteCommandLineTo (state, state->Reg[0]);
 521         }
 522       else
 523         unhandled = TRUE;
 524       break;
 525
 526     case SWI_Breakpoint:
 527       state->EndCondition = RDIError_BreakpointReached;
 528       state->Emulate = FALSE;
 529       break;
 530
 531     case SWI_Remove:
 532       if (swi_mask & SWI_MASK_DEMON)
 533         SWIremove (state, state->Reg[0]);
 534       else
 535         unhandled = TRUE;
 536       break;
 537
 538     case SWI_Rename:
 539       if (swi_mask & SWI_MASK_DEMON)
 540         SWIrename (state, state->Reg[0], state->Reg[1]);
 541       else
 542         unhandled = TRUE;
 543       break;
 544
 545     case SWI_IsTTY:
 546       if (swi_mask & SWI_MASK_DEMON)
 547         {
 548           state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
 549           OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 550         }
 551       else
 552         unhandled = TRUE;
 553       break;
 554
 555       /* Handle Angel SWIs as well as Demon ones.  */
 556     case AngelSWI_ARM:
 557     case AngelSWI_Thumb:
 558       if (swi_mask & SWI_MASK_ANGEL)
 559         {
 560           ARMword addr;
 561           ARMword temp;
 562
 563           /* R1 is almost always a parameter block.  */
 564           addr = state->Reg[1];
 565           /* R0 is a reason code.  */
 566           switch (state->Reg[0])
 567             {
 568             case -1:
 569               /* This can happen when a SWI is interrupted (eg receiving a
 570                  ctrl-C whilst processing SWIRead()).  The SWI will complete
 571                  returning -1 in r0 to the caller.  If GDB is then used to
 572                  resume the system call the reason code will now be -1.  */
 573               return TRUE;
 574
 575               /* Unimplemented reason codes.  */
 576             case AngelSWI_Reason_ReadC:
 577             case AngelSWI_Reason_TmpNam:
 578             case AngelSWI_Reason_System:
 579             case AngelSWI_Reason_EnterSVC:
 580             default:
 581               state->Emulate = FALSE;
 582               return FALSE;
 583
 584             case AngelSWI_Reason_Clock:
 585               /* Return number of centi-seconds.  */
 586               state->Reg[0] =
 587 #ifdef CLOCKS_PER_SEC
 588                 (CLOCKS_PER_SEC >= 100)
 589                 ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
 590                 : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
 591 #else
 592               /* Presume unix... clock() returns microseconds.  */
 593               (ARMword) (clock () / 10000);
 594 #endif
 595               OSptr->ErrorNo = errno;
 596               break;
 597
 598             case AngelSWI_Reason_Time:
 599               state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
 600               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 601               break;
 602
 603             case AngelSWI_Reason_WriteC:
 604               {
 605                 char tmp = ARMul_SafeReadByte (state, addr);
 606                 (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
 607                 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 608                 break;
 609               }
 610
 611             case AngelSWI_Reason_Write0:
 612               SWIWrite0 (state, addr);
 613               break;
 614
 615             case AngelSWI_Reason_Close:
 616               state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
 617               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 618               break;
 619
 620             case AngelSWI_Reason_Seek:
 621               state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
 622                                                          ARMul_ReadWord (state, addr + 4),
 623                                                          SEEK_SET);
 624               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 625               break;
 626
 627             case AngelSWI_Reason_FLen:
 628               SWIflen (state, ARMul_ReadWord (state, addr));
 629               break;
 630
 631             case AngelSWI_Reason_GetCmdLine:
 632               WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
 633               break;
 634
 635             case AngelSWI_Reason_HeapInfo:
 636               /* R1 is a pointer to a pointer.  */
 637               addr = ARMul_ReadWord (state, addr);
 638
 639               /* Pick up the right memory limit.  */
 640               if (state->MemSize)
 641                 temp = state->MemSize;
 642               else
 643                 temp = ADDRUSERSTACK;
 644
 645               ARMul_WriteWord (state, addr, 0);         /* Heap base.  */
 646               ARMul_WriteWord (state, addr + 4, temp);  /* Heap limit.  */
 647               ARMul_WriteWord (state, addr + 8, temp);  /* Stack base.  */
 648               ARMul_WriteWord (state, addr + 12, temp); /* Stack limit.  */
 649               break;
 650
 651             case AngelSWI_Reason_ReportException:
 652               if (state->Reg[1] == ADP_Stopped_ApplicationExit)
 653                 state->Reg[0] = 0;
 654               else
 655                 state->Reg[0] = -1;
 656               state->Emulate = FALSE;
 657               break;
 658
 659             case ADP_Stopped_ApplicationExit:
 660               state->Reg[0] = 0;
 661               state->Emulate = FALSE;
 662               break;
 663
 664             case ADP_Stopped_RunTimeError:
 665               state->Reg[0] = -1;
 666               state->Emulate = FALSE;
 667               break;
 668
 669             case AngelSWI_Reason_Errno:
 670               state->Reg[0] = OSptr->ErrorNo;
 671               break;
 672
 673             case AngelSWI_Reason_Open:
 674               SWIopen (state,
 675                        ARMul_ReadWord (state, addr),
 676                        ARMul_ReadWord (state, addr + 4));
 677               break;
 678
 679             case AngelSWI_Reason_Read:
 680               SWIread (state,
 681                        ARMul_ReadWord (state, addr),
 682                        ARMul_ReadWord (state, addr + 4),
 683                        ARMul_ReadWord (state, addr + 8));
 684               break;
 685
 686             case AngelSWI_Reason_Write:
 687               SWIwrite (state,
 688                         ARMul_ReadWord (state, addr),
 689                         ARMul_ReadWord (state, addr + 4),
 690                         ARMul_ReadWord (state, addr + 8));
 691               break;
 692
 693             case AngelSWI_Reason_IsTTY:
 694               state->Reg[0] = sim_callback->isatty (sim_callback,
 695                                                     ARMul_ReadWord (state, addr));
 696               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 697               break;
 698
 699             case AngelSWI_Reason_Remove:
 700               SWIremove (state,
 701                          ARMul_ReadWord (state, addr));
 702
 703             case AngelSWI_Reason_Rename:
 704               SWIrename (state,
 705                          ARMul_ReadWord (state, addr),
 706                          ARMul_ReadWord (state, addr + 4));
 707             }
 708         }
 709       else
 710         unhandled = TRUE;
 711       break;
 712
 713       /* The following SWIs are generated by the softvectorcode[]
 714          installed by default by the simulator.  */
 715     case 0x91: /* Undefined Instruction.  */
 716       {
 717         ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
 718
 719         sim_callback->printf_filtered
 720           (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x.  Stopping.\n",
 721            ARMul_ReadWord (state, addr), addr);
 722         state->EndCondition = RDIError_SoftwareInterrupt;
 723         state->Emulate = FALSE;
 724         return FALSE;
 725       }
 726
 727     case 0x90: /* Reset.  */
 728     case 0x92: /* SWI.  */
 729       /* These two can be safely ignored.  */
 730       break;
 731
 732     case 0x93: /* Prefetch Abort.  */
 733     case 0x94: /* Data Abort.  */
 734     case 0x95: /* Address Exception.  */
 735     case 0x96: /* IRQ.  */
 736     case 0x97: /* FIQ.  */
 737     case 0x98: /* Error.  */
 738       unhandled = TRUE;
 739       break;
 740
 741     case -1:
 742       /* This can happen when a SWI is interrupted (eg receiving a
 743          ctrl-C whilst processing SWIRead()).  The SWI will complete
 744          returning -1 in r0 to the caller.  If GDB is then used to
 745          resume the system call the reason code will now be -1.  */
 746       return TRUE;
 747
 748     case 0x180001: /* RedBoot's Syscall SWI in ARM mode.  */
 749       if (swi_mask & SWI_MASK_REDBOOT)
 750         {
 751           switch (state->Reg[0])
 752             {
 753               /* These numbers are defined in libgloss/syscall.h
 754                  but the simulator should not be dependend upon
 755                  libgloss being installed.  */
 756             case 1:  /* Exit.  */
 757               state->Emulate = FALSE;
 758               /* Copy exit code into r0.  */
 759               state->Reg[0] = state->Reg[1];
 760               break;
 761
 762             case 2:  /* Open.  */
 763               SWIopen (state, state->Reg[1], state->Reg[2]);
 764               break;
 765
 766             case 3:  /* Close.  */
 767               state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
 768               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 769               break;
 770
 771             case 4:  /* Read.  */
 772               SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
 773               break;
 774
 775             case 5:  /* Write.  */
 776               SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
 777               break;
 778
 779             case 6:  /* Lseek.  */
 780               state->Reg[0] = sim_callback->lseek (sim_callback,
 781                                                    state->Reg[1],
 782                                                    state->Reg[2],
 783                                                    state->Reg[3]);
 784               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 785               break;
 786
 787             case 17: /* Utime.  */
 788               state->Reg[0] = state->Reg[1] = (ARMword) sim_callback->time (sim_callback);
 789               OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 790               break;
 791
 792             case 7:  /* Unlink.  */
 793             case 8:  /* Getpid.  */
 794             case 9:  /* Kill.  */
 795             case 10: /* Fstat.  */
 796             case 11: /* Sbrk.  */
 797             case 12: /* Argvlen.  */
 798             case 13: /* Argv.  */
 799             case 14: /* ChDir.  */
 800             case 15: /* Stat.  */
 801             case 16: /* Chmod.  */
 802             case 18: /* Time.  */
 803               sim_callback->printf_filtered
 804                 (sim_callback,
 805                  "sim: unhandled RedBoot syscall `%d' encountered - "
 806                  "returning ENOSYS\n",
 807                  state->Reg[0]);
 808               state->Reg[0] = -1;
 809               OSptr->ErrorNo = cb_host_to_target_errno
 810                 (sim_callback, ENOSYS);
 811               break;
 812             case 1001: /* Meminfo. */
 813               {
 814                 ARMword totmem = state->Reg[1],
 815                         topmem = state->Reg[2];
 816                 ARMword stack = state->MemSize > 0
 817                   ? state->MemSize : ADDRUSERSTACK;
 818                 if (totmem != 0)
 819                   ARMul_WriteWord (state, totmem, stack);
 820                 if (topmem != 0)
 821                   ARMul_WriteWord (state, topmem, stack);
 822                 state->Reg[0] = 0;
 823                 break;
 824               }
 825
 826             default:
 827               sim_callback->printf_filtered
 828                 (sim_callback,
 829                  "sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
 830                  state->Reg[0]);
 831               return FALSE;
 832             }
 833           break;
 834         }
 835
 836     default:
 837       unhandled = TRUE;
 838     }
 839
 840   if (unhandled)
 841     {
 842       if (SWI_vector_installed)
 843         {
 844           ARMword cpsr;
 845           ARMword i_size;
 846
 847           cpsr = ARMul_GetCPSR (state);
 848           i_size = INSN_SIZE;
 849
 850           ARMul_SetSPSR (state, SVC32MODE, cpsr);
 851
 852           cpsr &= ~0xbf;
 853           cpsr |= SVC32MODE | 0x80;
 854           ARMul_SetCPSR (state, cpsr);
 855
 856           state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
 857           state->NextInstr            = RESUME;
 858           state->Reg[15]              = state->pc = ARMSWIV;
 859           FLUSHPIPE;
 860         }
 861       else
 862         {
 863           sim_callback->printf_filtered
 864             (sim_callback,
 865              "sim: unknown SWI encountered - %x - ignoring\n",
 866              number);
 867           return FALSE;
 868         }
 869     }
 870
 871   return TRUE;
 872 }