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1 /* Blackfin Event Vector Table (EVT) model.
2
3 Copyright (C) 2010-2014 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include "sim-main.h"
24 #include "devices.h"
25 #include "dv-bfin_cec.h"
26 #include "dv-bfin_evt.h"
27
28 struct bfin_evt
29 {
30 bu32 base;
31
32 /* Order after here is important -- matches hardware MMR layout. */
33 bu32 evt[16];
34 };
35 #define mmr_base() offsetof(struct bfin_evt, evt[0])
36 #define mmr_offset(mmr) (offsetof(struct bfin_evt, mmr) - mmr_base())
37
38 static const char * const mmr_names[] =
39 {
40 "EVT0", "EVT1", "EVT2", "EVT3", "EVT4", "EVT5", "EVT6", "EVT7", "EVT8",
41 "EVT9", "EVT10", "EVT11", "EVT12", "EVT13", "EVT14", "EVT15",
42 };
43 #define mmr_name(off) mmr_names[(off) / 4]
44
45 static unsigned
46 bfin_evt_io_write_buffer (struct hw *me, const void *source,
47 int space, address_word addr, unsigned nr_bytes)
48 {
49 struct bfin_evt *evt = hw_data (me);
50 bu32 mmr_off;
51 bu32 value;
52
53 value = dv_load_4 (source);
54 mmr_off = addr - evt->base;
55
56 HW_TRACE_WRITE ();
57
58 evt->evt[mmr_off / 4] = value;
59
60 return nr_bytes;
61 }
62
63 static unsigned
64 bfin_evt_io_read_buffer (struct hw *me, void *dest,
65 int space, address_word addr, unsigned nr_bytes)
66 {
67 struct bfin_evt *evt = hw_data (me);
68 bu32 mmr_off;
69 bu32 value;
70
71 mmr_off = addr - evt->base;
72
73 HW_TRACE_READ ();
74
75 value = evt->evt[mmr_off / 4];
76
77 dv_store_4 (dest, value);
78
79 return nr_bytes;
80 }
81
82 static void
83 attach_bfin_evt_regs (struct hw *me, struct bfin_evt *evt)
84 {
85 address_word attach_address;
86 int attach_space;
87 unsigned attach_size;
88 reg_property_spec reg;
89
90 if (hw_find_property (me, "reg") == NULL)
91 hw_abort (me, "Missing \"reg\" property");
92
93 if (!hw_find_reg_array_property (me, "reg", 0, &reg))
94 hw_abort (me, "\"reg\" property must contain three addr/size entries");
95
96 hw_unit_address_to_attach_address (hw_parent (me),
97 &reg.address,
98 &attach_space, &attach_address, me);
99 hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
100
101 if (attach_size != BFIN_COREMMR_EVT_SIZE)
102 hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_EVT_SIZE);
103
104 hw_attach_address (hw_parent (me),
105 0, attach_space, attach_address, attach_size, me);
106
107 evt->base = attach_address;
108 }
109
110 static void
111 bfin_evt_finish (struct hw *me)
112 {
113 struct bfin_evt *evt;
114
115 evt = HW_ZALLOC (me, struct bfin_evt);
116
117 set_hw_data (me, evt);
118 set_hw_io_read_buffer (me, bfin_evt_io_read_buffer);
119 set_hw_io_write_buffer (me, bfin_evt_io_write_buffer);
120
121 attach_bfin_evt_regs (me, evt);
122 }
123
124 const struct hw_descriptor dv_bfin_evt_descriptor[] =
125 {
126 {"bfin_evt", bfin_evt_finish,},
127 {NULL, NULL},
128 };
129
130 #define EVT_STATE(cpu) DV_STATE_CACHED (cpu, evt)
131
132 void
133 cec_set_evt (SIM_CPU *cpu, int ivg, bu32 handler_addr)
134 {
135 if (ivg > IVG15 || ivg < 0)
136 sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
137
138 EVT_STATE (cpu)->evt[ivg] = handler_addr;
139 }
140
141 bu32
142 cec_get_evt (SIM_CPU *cpu, int ivg)
143 {
144 if (ivg > IVG15 || ivg < 0)
145 sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
146
147 return EVT_STATE (cpu)->evt[ivg];
148 }
149
150 bu32
151 cec_get_reset_evt (SIM_CPU *cpu)
152 {
153 /* XXX: This should tail into the model to get via BMODE pins. */
154 return 0xef000000;
155 }