sim/bfin/dv-bfin_mmu.c

   1 /* Blackfin Memory Management Unit (MMU) model.
   2
   3    Copyright (C) 2010-2011 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22
  23 #include "sim-main.h"
  24 #include "sim-options.h"
  25 #include "devices.h"
  26 #include "dv-bfin_mmu.h"
  27 #include "dv-bfin_cec.h"
  28
  29 /* XXX: Should this really be two blocks of registers ?  PRM describes
  30         these as two Content Addressable Memory (CAM) blocks.  */
  31
  32 struct bfin_mmu
  33 {
  34   bu32 base;
  35
  36   /* Order after here is important -- matches hardware MMR layout.  */
  37   bu32 sram_base_address;
  38
  39   bu32 dmem_control, dcplb_fault_status, dcplb_fault_addr;
  40   char _dpad0[0x100 - 0x0 - (4 * 4)];
  41   bu32 dcplb_addr[16];
  42   char _dpad1[0x200 - 0x100 - (4 * 16)];
  43   bu32 dcplb_data[16];
  44   char _dpad2[0x300 - 0x200 - (4 * 16)];
  45   bu32 dtest_command;
  46   char _dpad3[0x400 - 0x300 - (4 * 1)];
  47   bu32 dtest_data[2];
  48
  49   char _dpad4[0x1000 - 0x400 - (4 * 2)];
  50
  51   bu32 idk;     /* Filler MMR; hardware simply ignores.  */
  52   bu32 imem_control, icplb_fault_status, icplb_fault_addr;
  53   char _ipad0[0x100 - 0x0 - (4 * 4)];
  54   bu32 icplb_addr[16];
  55   char _ipad1[0x200 - 0x100 - (4 * 16)];
  56   bu32 icplb_data[16];
  57   char _ipad2[0x300 - 0x200 - (4 * 16)];
  58   bu32 itest_command;
  59   char _ipad3[0x400 - 0x300 - (4 * 1)];
  60   bu32 itest_data[2];
  61 };
  62 #define mmr_base()      offsetof(struct bfin_mmu, sram_base_address)
  63 #define mmr_offset(mmr) (offsetof(struct bfin_mmu, mmr) - mmr_base())
  64 #define mmr_idx(mmr)    (mmr_offset (mmr) / 4)
  65
  66 static const char * const mmr_names[BFIN_COREMMR_MMU_SIZE / 4] = {
  67   "SRAM_BASE_ADDRESS", "DMEM_CONTROL", "DCPLB_FAULT_STATUS", "DCPLB_FAULT_ADDR",
  68   [mmr_idx (dcplb_addr[0])] = "DCPLB_ADDR0",
  69   "DCPLB_ADDR1", "DCPLB_ADDR2", "DCPLB_ADDR3", "DCPLB_ADDR4", "DCPLB_ADDR5",
  70   "DCPLB_ADDR6", "DCPLB_ADDR7", "DCPLB_ADDR8", "DCPLB_ADDR9", "DCPLB_ADDR10",
  71   "DCPLB_ADDR11", "DCPLB_ADDR12", "DCPLB_ADDR13", "DCPLB_ADDR14", "DCPLB_ADDR15",
  72   [mmr_idx (dcplb_data[0])] = "DCPLB_DATA0",
  73   "DCPLB_DATA1", "DCPLB_DATA2", "DCPLB_DATA3", "DCPLB_DATA4", "DCPLB_DATA5",
  74   "DCPLB_DATA6", "DCPLB_DATA7", "DCPLB_DATA8", "DCPLB_DATA9", "DCPLB_DATA10",
  75   "DCPLB_DATA11", "DCPLB_DATA12", "DCPLB_DATA13", "DCPLB_DATA14", "DCPLB_DATA15",
  76   [mmr_idx (dtest_command)] = "DTEST_COMMAND",
  77   [mmr_idx (dtest_data[0])] = "DTEST_DATA0", "DTEST_DATA1",
  78   [mmr_idx (imem_control)] = "IMEM_CONTROL", "ICPLB_FAULT_STATUS", "ICPLB_FAULT_ADDR",
  79   [mmr_idx (icplb_addr[0])] = "ICPLB_ADDR0",
  80   "ICPLB_ADDR1", "ICPLB_ADDR2", "ICPLB_ADDR3", "ICPLB_ADDR4", "ICPLB_ADDR5",
  81   "ICPLB_ADDR6", "ICPLB_ADDR7", "ICPLB_ADDR8", "ICPLB_ADDR9", "ICPLB_ADDR10",
  82   "ICPLB_ADDR11", "ICPLB_ADDR12", "ICPLB_ADDR13", "ICPLB_ADDR14", "ICPLB_ADDR15",
  83   [mmr_idx (icplb_data[0])] = "ICPLB_DATA0",
  84   "ICPLB_DATA1", "ICPLB_DATA2", "ICPLB_DATA3", "ICPLB_DATA4", "ICPLB_DATA5",
  85   "ICPLB_DATA6", "ICPLB_DATA7", "ICPLB_DATA8", "ICPLB_DATA9", "ICPLB_DATA10",
  86   "ICPLB_DATA11", "ICPLB_DATA12", "ICPLB_DATA13", "ICPLB_DATA14", "ICPLB_DATA15",
  87   [mmr_idx (itest_command)] = "ITEST_COMMAND",
  88   [mmr_idx (itest_data[0])] = "ITEST_DATA0", "ITEST_DATA1",
  89 };
  90 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
  91
  92 static bool bfin_mmu_skip_cplbs = false;
  93
  94 static unsigned
  95 bfin_mmu_io_write_buffer (struct hw *me, const void *source,
  96                           int space, address_word addr, unsigned nr_bytes)
  97 {
  98   struct bfin_mmu *mmu = hw_data (me);
  99   bu32 mmr_off;
 100   bu32 value;
 101   bu32 *valuep;
 102
 103   value = dv_load_4 (source);
 104
 105   mmr_off = addr - mmu->base;
 106   valuep = (void *)((unsigned long)mmu + mmr_base() + mmr_off);
 107
 108   HW_TRACE_WRITE ();
 109
 110   switch (mmr_off)
 111     {
 112     case mmr_offset(dmem_control):
 113     case mmr_offset(imem_control):
 114       /* XXX: IMC/DMC bit should add/remove L1 cache regions ...  */
 115     case mmr_offset(dtest_data[0]) ... mmr_offset(dtest_data[1]):
 116     case mmr_offset(itest_data[0]) ... mmr_offset(itest_data[1]):
 117     case mmr_offset(dcplb_addr[0]) ... mmr_offset(dcplb_addr[15]):
 118     case mmr_offset(dcplb_data[0]) ... mmr_offset(dcplb_data[15]):
 119     case mmr_offset(icplb_addr[0]) ... mmr_offset(icplb_addr[15]):
 120     case mmr_offset(icplb_data[0]) ... mmr_offset(icplb_data[15]):
 121       *valuep = value;
 122       break;
 123     case mmr_offset(sram_base_address):
 124     case mmr_offset(dcplb_fault_status):
 125     case mmr_offset(dcplb_fault_addr):
 126     case mmr_offset(idk):
 127     case mmr_offset(icplb_fault_status):
 128     case mmr_offset(icplb_fault_addr):
 129       /* Discard writes to these.  */
 130       break;
 131     case mmr_offset(itest_command):
 132       /* XXX: Not supported atm.  */
 133       if (value)
 134         hw_abort (me, "ITEST_COMMAND unimplemented");
 135       break;
 136     case mmr_offset(dtest_command):
 137       /* Access L1 memory indirectly.  */
 138       *valuep = value;
 139       if (value)
 140         {
 141           bu32 addr = mmu->sram_base_address   |
 142             ((value >> (26 - 11)) & (1 << 11)) | /* addr bit 11 (Way0/Way1)   */
 143             ((value >> (24 - 21)) & (1 << 21)) | /* addr bit 21 (Data/Inst)   */
 144             ((value >> (23 - 15)) & (1 << 15)) | /* addr bit 15 (Data Bank)   */
 145             ((value >> (16 - 12)) & (3 << 12)) | /* addr bits 13:12 (Subbank) */
 146             (value & 0x47F8);                    /* addr bits 14 & 10:3       */
 147
 148           if (!(value & TEST_DATA_ARRAY))
 149             hw_abort (me, "DTEST_COMMAND tag array unimplemented");
 150           if (value & 0xfa7cb801)
 151             hw_abort (me, "DTEST_COMMAND bits undefined");
 152
 153           if (value & TEST_WRITE)
 154             sim_write (hw_system (me), addr, (void *)mmu->dtest_data, 8);
 155           else
 156             sim_read (hw_system (me), addr, (void *)mmu->dtest_data, 8);
 157         }
 158       break;
 159     default:
 160       dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
 161       break;
 162     }
 163
 164   return nr_bytes;
 165 }
 166
 167 static unsigned
 168 bfin_mmu_io_read_buffer (struct hw *me, void *dest,
 169                          int space, address_word addr, unsigned nr_bytes)
 170 {
 171   struct bfin_mmu *mmu = hw_data (me);
 172   bu32 mmr_off;
 173   bu32 *valuep;
 174
 175   mmr_off = addr - mmu->base;
 176   valuep = (void *)((unsigned long)mmu + mmr_base() + mmr_off);
 177
 178   HW_TRACE_READ ();
 179
 180   switch (mmr_off)
 181     {
 182     case mmr_offset(dmem_control):
 183     case mmr_offset(imem_control):
 184     case mmr_offset(dtest_command):
 185     case mmr_offset(dtest_data[0]) ... mmr_offset(dtest_data[2]):
 186     case mmr_offset(itest_command):
 187     case mmr_offset(itest_data[0]) ... mmr_offset(itest_data[2]):
 188       /* XXX: should do something here.  */
 189     case mmr_offset(dcplb_addr[0]) ... mmr_offset(dcplb_addr[15]):
 190     case mmr_offset(dcplb_data[0]) ... mmr_offset(dcplb_data[15]):
 191     case mmr_offset(icplb_addr[0]) ... mmr_offset(icplb_addr[15]):
 192     case mmr_offset(icplb_data[0]) ... mmr_offset(icplb_data[15]):
 193     case mmr_offset(sram_base_address):
 194     case mmr_offset(dcplb_fault_status):
 195     case mmr_offset(dcplb_fault_addr):
 196     case mmr_offset(idk):
 197     case mmr_offset(icplb_fault_status):
 198     case mmr_offset(icplb_fault_addr):
 199       dv_store_4 (dest, *valuep);
 200       break;
 201     default:
 202       while (1) /* Core MMRs -> exception -> doesn't return.  */
 203         dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
 204       break;
 205     }
 206
 207   return nr_bytes;
 208 }
 209
 210 static void
 211 attach_bfin_mmu_regs (struct hw *me, struct bfin_mmu *mmu)
 212 {
 213   address_word attach_address;
 214   int attach_space;
 215   unsigned attach_size;
 216   reg_property_spec reg;
 217
 218   if (hw_find_property (me, "reg") == NULL)
 219     hw_abort (me, "Missing \"reg\" property");
 220
 221   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 222     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 223
 224   hw_unit_address_to_attach_address (hw_parent (me),
 225                                      &reg.address,
 226                                      &attach_space, &attach_address, me);
 227   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 228
 229   if (attach_size != BFIN_COREMMR_MMU_SIZE)
 230     hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_MMU_SIZE);
 231
 232   hw_attach_address (hw_parent (me),
 233                      0, attach_space, attach_address, attach_size, me);
 234
 235   mmu->base = attach_address;
 236 }
 237
 238 static void
 239 bfin_mmu_finish (struct hw *me)
 240 {
 241   struct bfin_mmu *mmu;
 242
 243   mmu = HW_ZALLOC (me, struct bfin_mmu);
 244
 245   set_hw_data (me, mmu);
 246   set_hw_io_read_buffer (me, bfin_mmu_io_read_buffer);
 247   set_hw_io_write_buffer (me, bfin_mmu_io_write_buffer);
 248
 249   attach_bfin_mmu_regs (me, mmu);
 250
 251   /* Initialize the MMU.  */
 252   mmu->sram_base_address = 0xff800000 - 0;
 253                            /*(4 * 1024 * 1024 * CPU_INDEX (hw_system_cpu (me)));*/
 254   mmu->dmem_control = 0x00000001;
 255   mmu->imem_control = 0x00000001;
 256 }
 257
 258 const struct hw_descriptor dv_bfin_mmu_descriptor[] = {
 259   {"bfin_mmu", bfin_mmu_finish,},
 260   {NULL, NULL},
 261 };
 262 \f
 263 /* Device option parsing.  */
 264
 265 static DECLARE_OPTION_HANDLER (bfin_mmu_option_handler);
 266
 267 enum {
 268   OPTION_MMU_SKIP_TABLES = OPTION_START,
 269 };
 270
 271 const OPTION bfin_mmu_options[] =
 272 {
 273   { {"mmu-skip-cplbs", no_argument, NULL, OPTION_MMU_SKIP_TABLES },
 274       '\0', NULL, "Skip parsing of CPLB tables (big speed increase)",
 275       bfin_mmu_option_handler, NULL },
 276
 277   { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
 278 };
 279
 280 static SIM_RC
 281 bfin_mmu_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
 282                          char *arg, int is_command)
 283 {
 284   switch (opt)
 285     {
 286     case OPTION_MMU_SKIP_TABLES:
 287       bfin_mmu_skip_cplbs = true;
 288       return SIM_RC_OK;
 289
 290     default:
 291       sim_io_eprintf (sd, "Unknown Blackfin MMU option %d\n", opt);
 292       return SIM_RC_FAIL;
 293     }
 294 }
 295 \f
 296 #define MMU_STATE(cpu) DV_STATE_CACHED (cpu, mmu)
 297
 298 static void
 299 _mmu_log_ifault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 pc, bool supv)
 300 {
 301   mmu->icplb_fault_addr = pc;
 302   mmu->icplb_fault_status = supv << 17;
 303 }
 304
 305 void
 306 mmu_log_ifault (SIM_CPU *cpu)
 307 {
 308   _mmu_log_ifault (cpu, MMU_STATE (cpu), PCREG, cec_get_ivg (cpu) >= 0);
 309 }
 310
 311 static void
 312 _mmu_log_fault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 addr, bool write,
 313                 bool inst, bool miss, bool supv, bool dag1, bu32 faults)
 314 {
 315   bu32 *fault_status, *fault_addr;
 316
 317   /* No logging in non-OS mode.  */
 318   if (!mmu)
 319     return;
 320
 321   fault_status = inst ? &mmu->icplb_fault_status : &mmu->dcplb_fault_status;
 322   fault_addr = inst ? &mmu->icplb_fault_addr : &mmu->dcplb_fault_addr;
 323   /* ICPLB regs always get updated.  */
 324   if (!inst)
 325     _mmu_log_ifault (cpu, mmu, PCREG, supv);
 326
 327   *fault_addr = addr;
 328   *fault_status =
 329         (miss << 19) |
 330         (dag1 << 18) |
 331         (supv << 17) |
 332         (write << 16) |
 333         faults;
 334 }
 335
 336 static void
 337 _mmu_process_fault (SIM_CPU *cpu, struct bfin_mmu *mmu, bu32 addr, bool write,
 338                     bool inst, bool unaligned, bool miss, bool supv, bool dag1)
 339 {
 340   int excp;
 341
 342   /* See order in mmu_check_addr() */
 343   if (unaligned)
 344     excp = inst ? VEC_MISALI_I : VEC_MISALI_D;
 345   else if (addr >= BFIN_SYSTEM_MMR_BASE)
 346     excp = VEC_ILL_RES;
 347   else if (!mmu)
 348     excp = inst ? VEC_CPLB_I_M : VEC_CPLB_M;
 349   else
 350     {
 351       /* Misses are hardware errors.  */
 352       cec_hwerr (cpu, HWERR_EXTERN_ADDR);
 353       return;
 354     }
 355
 356   _mmu_log_fault (cpu, mmu, addr, write, inst, miss, supv, dag1, 0);
 357   cec_exception (cpu, excp);
 358 }
 359
 360 void
 361 mmu_process_fault (SIM_CPU *cpu, bu32 addr, bool write, bool inst,
 362                    bool unaligned, bool miss)
 363 {
 364   SIM_DESC sd = CPU_STATE (cpu);
 365   struct bfin_mmu *mmu;
 366
 367   if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
 368     mmu = NULL;
 369   else
 370     mmu = MMU_STATE (cpu);
 371
 372   _mmu_process_fault (cpu, mmu, addr, write, inst, unaligned, miss,
 373                       cec_is_supervisor_mode (cpu),
 374                       BFIN_CPU_STATE.multi_pc == PCREG + 6);
 375 }
 376
 377 /* Return values:
 378     -2: no known problems
 379     -1: valid
 380      0: miss
 381      1: protection violation
 382      2: multiple hits
 383      3: unaligned
 384      4: miss; hwerr  */
 385 static int
 386 mmu_check_implicit_addr (SIM_CPU *cpu, bu32 addr, bool inst, int size,
 387                          bool supv, bool dag1)
 388 {
 389   bool l1 = ((addr & 0xFF000000) == 0xFF000000);
 390   bu32 amask = (addr & 0xFFF00000);
 391
 392   if (addr & (size - 1))
 393     return 3;
 394
 395   /* MMRs may never be executable or accessed from usermode.  */
 396   if (addr >= BFIN_SYSTEM_MMR_BASE)
 397     {
 398       if (inst)
 399         return 0;
 400       else if (!supv || dag1)
 401         return 1;
 402       else
 403         return -1;
 404     }
 405   else if (inst)
 406     {
 407       /* Some regions are not executable.  */
 408       /* XXX: Should this be in the model data ?  Core B 561 ?  */
 409       if (l1)
 410         return (amask == 0xFFA00000) ? -1 : 1;
 411     }
 412   else
 413     {
 414       /* Some regions are not readable.  */
 415       /* XXX: Should this be in the model data ?  Core B 561 ?  */
 416       if (l1)
 417         return (amask != 0xFFA00000) ? -1 : 4;
 418     }
 419
 420   return -2;
 421 }
 422
 423 /* Exception order per the PRM (first has highest):
 424      Inst Multiple CPLB Hits
 425      Inst Misaligned Access
 426      Inst Protection Violation
 427      Inst CPLB Miss
 428   Only the alignment matters in non-OS mode though.  */
 429 static int
 430 _mmu_check_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst, int size)
 431 {
 432   SIM_DESC sd = CPU_STATE (cpu);
 433   struct bfin_mmu *mmu;
 434   bu32 *fault_status, *fault_addr, *mem_control, *cplb_addr, *cplb_data;
 435   bu32 faults;
 436   bool supv, do_excp, dag1;
 437   int i, hits;
 438
 439   supv = cec_is_supervisor_mode (cpu);
 440   dag1 = (BFIN_CPU_STATE.multi_pc == PCREG + 6);
 441
 442   if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT || bfin_mmu_skip_cplbs)
 443     {
 444       int ret = mmu_check_implicit_addr (cpu, addr, inst, size, supv, dag1);
 445       /* Valid hits and misses are OK in non-OS envs.  */
 446       if (ret < 0)
 447         return 0;
 448       _mmu_process_fault (cpu, NULL, addr, write, inst, (ret == 3), false, supv, dag1);
 449     }
 450
 451   mmu = MMU_STATE (cpu);
 452   fault_status = inst ? &mmu->icplb_fault_status : &mmu->dcplb_fault_status;
 453   fault_addr = inst ? &mmu->icplb_fault_addr : &mmu->dcplb_fault_addr;
 454   mem_control = inst ? &mmu->imem_control : &mmu->dmem_control;
 455   cplb_addr = inst ? &mmu->icplb_addr[0] : &mmu->dcplb_addr[0];
 456   cplb_data = inst ? &mmu->icplb_data[0] : &mmu->dcplb_data[0];
 457
 458   faults = 0;
 459   hits = 0;
 460   do_excp = false;
 461
 462   /* CPLBs disabled -> little to do.  */
 463   if (!(*mem_control & ENCPLB))
 464     {
 465       hits = 1;
 466       goto implicit_check;
 467     }
 468
 469   /* Check all the CPLBs first.  */
 470   for (i = 0; i < 16; ++i)
 471     {
 472       const bu32 pages[4] = { 0x400, 0x1000, 0x100000, 0x400000 };
 473       bu32 addr_lo, addr_hi;
 474
 475       /* Skip invalid entries.  */
 476       if (!(cplb_data[i] & CPLB_VALID))
 477         continue;
 478
 479       /* See if this entry covers this address.  */
 480       addr_lo = cplb_addr[i];
 481       addr_hi = cplb_addr[i] + pages[(cplb_data[i] & PAGE_SIZE) >> 16];
 482       if (addr < addr_lo || addr >= addr_hi)
 483         continue;
 484
 485       ++hits;
 486       faults |= (1 << i);
 487       if (write)
 488         {
 489           if (!supv && !(cplb_data[i] & CPLB_USER_WR))
 490             do_excp = true;
 491           if (supv && !(cplb_data[i] & CPLB_SUPV_WR))
 492             do_excp = true;
 493           if ((cplb_data[i] & (CPLB_WT | CPLB_L1_CHBL | CPLB_DIRTY)) == CPLB_L1_CHBL)
 494             do_excp = true;
 495         }
 496       else
 497         {
 498           if (!supv && !(cplb_data[i] & CPLB_USER_RD))
 499             do_excp = true;
 500         }
 501     }
 502
 503   /* Handle default/implicit CPLBs.  */
 504   if (!do_excp && hits < 2)
 505     {
 506       int ihits;
 507  implicit_check:
 508       ihits = mmu_check_implicit_addr (cpu, addr, inst, size, supv, dag1);
 509       switch (ihits)
 510         {
 511         /* No faults and one match -> good to go.  */
 512         case -1: return 0;
 513         case -2:
 514           if (hits == 1)
 515             return 0;
 516           break;
 517         case 4:
 518           cec_hwerr (cpu, HWERR_EXTERN_ADDR);
 519           return 0;
 520         default:
 521           hits = ihits;
 522         }
 523     }
 524   else
 525     /* Normalize hit count so hits==2 is always multiple hit exception.  */
 526     hits = MIN (2, hits);
 527
 528   _mmu_log_fault (cpu, mmu, addr, write, inst, hits == 0, supv, dag1, faults);
 529
 530   if (inst)
 531     {
 532       int iexcps[] = { VEC_CPLB_I_M, VEC_CPLB_I_VL, VEC_CPLB_I_MHIT, VEC_MISALI_I };
 533       return iexcps[hits];
 534     }
 535   else
 536     {
 537       int dexcps[] = { VEC_CPLB_M, VEC_CPLB_VL, VEC_CPLB_MHIT, VEC_MISALI_D };
 538       return dexcps[hits];
 539     }
 540 }
 541
 542 void
 543 mmu_check_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst, int size)
 544 {
 545   int excp = _mmu_check_addr (cpu, addr, write, inst, size);
 546   if (excp)
 547     cec_exception (cpu, excp);
 548 }
 549
 550 void
 551 mmu_check_cache_addr (SIM_CPU *cpu, bu32 addr, bool write, bool inst)
 552 {
 553   bu32 cacheaddr;
 554   int excp;
 555
 556   cacheaddr = addr & ~(BFIN_L1_CACHE_BYTES - 1);
 557   excp = _mmu_check_addr (cpu, cacheaddr, write, inst, BFIN_L1_CACHE_BYTES);
 558   if (excp == 0)
 559     return;
 560
 561   /* Most exceptions are ignored with cache funcs.  */
 562   /* XXX: Not sure if we should be ignoring CPLB misses.  */
 563   if (inst)
 564     {
 565       if (excp == VEC_CPLB_I_VL)
 566         return;
 567     }
 568   else
 569     {
 570       if (excp == VEC_CPLB_VL)
 571         return;
 572     }
 573   cec_exception (cpu, excp);
 574 }