sim/bfin/dv-bfin_twi.c

   1 /* Blackfin Two Wire Interface (TWI) model
   2
   3    Copyright (C) 2010-2013 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22
  23 #include "sim-main.h"
  24 #include "devices.h"
  25 #include "dv-bfin_twi.h"
  26
  27 /* XXX: This is merely a stub.  */
  28
  29 struct bfin_twi
  30 {
  31   /* This top portion matches common dv_bfin struct.  */
  32   bu32 base;
  33   struct hw *dma_master;
  34   bool acked;
  35
  36   struct hw_event *handler;
  37   char saved_byte;
  38   int saved_count;
  39
  40   bu16 xmt_fifo, rcv_fifo;
  41
  42   /* Order after here is important -- matches hardware MMR layout.  */
  43   bu16 BFIN_MMR_16(clkdiv);
  44   bu16 BFIN_MMR_16(control);
  45   bu16 BFIN_MMR_16(slave_ctl);
  46   bu16 BFIN_MMR_16(slave_stat);
  47   bu16 BFIN_MMR_16(slave_addr);
  48   bu16 BFIN_MMR_16(master_ctl);
  49   bu16 BFIN_MMR_16(master_stat);
  50   bu16 BFIN_MMR_16(master_addr);
  51   bu16 BFIN_MMR_16(int_stat);
  52   bu16 BFIN_MMR_16(int_mask);
  53   bu16 BFIN_MMR_16(fifo_ctl);
  54   bu16 BFIN_MMR_16(fifo_stat);
  55   bu32 _pad0[20];
  56   bu16 BFIN_MMR_16(xmt_data8);
  57   bu16 BFIN_MMR_16(xmt_data16);
  58   bu16 BFIN_MMR_16(rcv_data8);
  59   bu16 BFIN_MMR_16(rcv_data16);
  60 };
  61 #define mmr_base()      offsetof(struct bfin_twi, clkdiv)
  62 #define mmr_offset(mmr) (offsetof(struct bfin_twi, mmr) - mmr_base())
  63 #define mmr_idx(mmr)    (mmr_offset (mmr) / 4)
  64
  65 static const char * const mmr_names[] =
  66 {
  67   "TWI_CLKDIV", "TWI_CONTROL", "TWI_SLAVE_CTL", "TWI_SLAVE_STAT",
  68   "TWI_SLAVE_ADDR", "TWI_MASTER_CTL", "TWI_MASTER_STAT", "TWI_MASTER_ADDR",
  69   "TWI_INT_STAT", "TWI_INT_MASK", "TWI_FIFO_CTL", "TWI_FIFO_STAT",
  70   [mmr_idx (xmt_data8)] = "TWI_XMT_DATA8", "TWI_XMT_DATA16", "TWI_RCV_DATA8",
  71   "TWI_RCV_DATA16",
  72 };
  73 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
  74
  75 static unsigned
  76 bfin_twi_io_write_buffer (struct hw *me, const void *source, int space,
  77                           address_word addr, unsigned nr_bytes)
  78 {
  79   struct bfin_twi *twi = hw_data (me);
  80   bu32 mmr_off;
  81   bu32 value;
  82   bu16 *valuep;
  83
  84   value = dv_load_2 (source);
  85   mmr_off = addr - twi->base;
  86   valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off);
  87
  88   HW_TRACE_WRITE ();
  89
  90   dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
  91
  92   switch (mmr_off)
  93     {
  94     case mmr_offset(clkdiv):
  95     case mmr_offset(control):
  96     case mmr_offset(slave_ctl):
  97     case mmr_offset(slave_addr):
  98     case mmr_offset(master_ctl):
  99     case mmr_offset(master_addr):
 100     case mmr_offset(int_mask):
 101     case mmr_offset(fifo_ctl):
 102       *valuep = value;
 103       break;
 104     case mmr_offset(int_stat):
 105       dv_w1c_2 (valuep, value, -1);
 106       break;
 107     case mmr_offset(master_stat):
 108       dv_w1c_2 (valuep, value, BUFWRERR | BUFRDERR | DNAK | ANAK | LOSTARB);
 109       break;
 110     case mmr_offset(slave_stat):
 111     case mmr_offset(fifo_stat):
 112     case mmr_offset(rcv_data8):
 113     case mmr_offset(rcv_data16):
 114       /* These are all RO.  XXX: Does these throw error ?  */
 115       break;
 116     case mmr_offset(xmt_data8):
 117       value &= 0xff;
 118     case mmr_offset(xmt_data16):
 119       twi->xmt_fifo = value;
 120       break;
 121     default:
 122       dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
 123       break;
 124     }
 125
 126   return nr_bytes;
 127 }
 128
 129 static unsigned
 130 bfin_twi_io_read_buffer (struct hw *me, void *dest, int space,
 131                          address_word addr, unsigned nr_bytes)
 132 {
 133   struct bfin_twi *twi = hw_data (me);
 134   bu32 mmr_off;
 135   bu16 *valuep;
 136
 137   mmr_off = addr - twi->base;
 138   valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off);
 139
 140   HW_TRACE_READ ();
 141
 142   dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
 143
 144   switch (mmr_off)
 145     {
 146     case mmr_offset(clkdiv):
 147     case mmr_offset(control):
 148     case mmr_offset(slave_ctl):
 149     case mmr_offset(slave_stat):
 150     case mmr_offset(slave_addr):
 151     case mmr_offset(master_ctl):
 152     case mmr_offset(master_stat):
 153     case mmr_offset(master_addr):
 154     case mmr_offset(int_stat):
 155     case mmr_offset(int_mask):
 156     case mmr_offset(fifo_ctl):
 157     case mmr_offset(fifo_stat):
 158       dv_store_2 (dest, *valuep);
 159       break;
 160     case mmr_offset(rcv_data8):
 161     case mmr_offset(rcv_data16):
 162       dv_store_2 (dest, twi->rcv_fifo);
 163       break;
 164     case mmr_offset(xmt_data8):
 165     case mmr_offset(xmt_data16):
 166       /* These always read as 0.  */
 167       dv_store_2 (dest, 0);
 168       break;
 169     default:
 170       dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
 171       break;
 172     }
 173
 174   return nr_bytes;
 175 }
 176
 177 static const struct hw_port_descriptor bfin_twi_ports[] =
 178 {
 179   { "stat", 0, 0, output_port, },
 180   { NULL, 0, 0, 0, },
 181 };
 182
 183 static void
 184 attach_bfin_twi_regs (struct hw *me, struct bfin_twi *twi)
 185 {
 186   address_word attach_address;
 187   int attach_space;
 188   unsigned attach_size;
 189   reg_property_spec reg;
 190
 191   if (hw_find_property (me, "reg") == NULL)
 192     hw_abort (me, "Missing \"reg\" property");
 193
 194   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 195     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 196
 197   hw_unit_address_to_attach_address (hw_parent (me),
 198                                      &reg.address,
 199                                      &attach_space, &attach_address, me);
 200   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 201
 202   if (attach_size != BFIN_MMR_TWI_SIZE)
 203     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_TWI_SIZE);
 204
 205   hw_attach_address (hw_parent (me),
 206                      0, attach_space, attach_address, attach_size, me);
 207
 208   twi->base = attach_address;
 209 }
 210
 211 static void
 212 bfin_twi_finish (struct hw *me)
 213 {
 214   struct bfin_twi *twi;
 215
 216   twi = HW_ZALLOC (me, struct bfin_twi);
 217
 218   set_hw_data (me, twi);
 219   set_hw_io_read_buffer (me, bfin_twi_io_read_buffer);
 220   set_hw_io_write_buffer (me, bfin_twi_io_write_buffer);
 221   set_hw_ports (me, bfin_twi_ports);
 222
 223   attach_bfin_twi_regs (me, twi);
 224 }
 225
 226 const struct hw_descriptor dv_bfin_twi_descriptor[] =
 227 {
 228   {"bfin_twi", bfin_twi_finish,},
 229   {NULL, NULL},
 230 };