sim/bfin/dv-bfin_uart.h

   1 /* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
   2    For "old style" UARTs on BF53x/etc... parts.
   3
   4    Copyright (C) 2010-2013 Free Software Foundation, Inc.
   5    Contributed by Analog Devices, Inc.
   6
   7    This file is part of simulators.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef DV_BFIN_UART_H
  23 #define DV_BFIN_UART_H
  24
  25 struct bfin_uart;
  26 bu16 bfin_uart_get_next_byte (struct hw *, bu16, bu16, bool *fresh);
  27 bu16 bfin_uart_write_byte (struct hw *, bu16, bu16);
  28 bu16 bfin_uart_get_status (struct hw *);
  29 unsigned bfin_uart_write_buffer (struct hw *, const unsigned char *, unsigned);
  30 unsigned bfin_uart_read_buffer (struct hw *, unsigned char *, unsigned);
  31 void bfin_uart_reschedule (struct hw *);
  32
  33 /* UART_LCR */
  34 #define DLAB    (1 << 7)
  35
  36 /* UART_LSR */
  37 #define TFI     (1 << 7)
  38 #define TEMT    (1 << 6)
  39 #define THRE    (1 << 5)
  40 #define BI      (1 << 4)
  41 #define FE      (1 << 3)
  42 #define PE      (1 << 2)
  43 #define OE      (1 << 1)
  44 #define DR      (1 << 0)
  45
  46 /* UART_IER */
  47 #define ERBFI   (1 << 0)
  48 #define ETBEI   (1 << 1)
  49 #define ELSI    (1 << 2)
  50
  51 /* UART_MCR */
  52 #define XOFF            (1 << 0)
  53 #define MRTS            (1 << 1)
  54 #define RFIT            (1 << 2)
  55 #define RFRT            (1 << 3)
  56 #define LOOP_ENA        (1 << 4)
  57 #define FCPOL           (1 << 5)
  58 #define ARTS            (1 << 6)
  59 #define ACTS            (1 << 7)
  60
  61 #endif