sim/common/cgen-engine.h

   1 /* Engine header for Cpu tools GENerated simulators.
   2    Copyright (C) 1998-2014 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This file is included by ${cpu}.h.
  21    It needs CGEN_INSN_WORD which is defined by ${cpu}.h.
  22    ??? A lot of this could be moved to genmloop.sh to be put in eng.h
  23    and thus remove some conditional compilation.  We'd still need
  24    CGEN_INSN_WORD though.  */
  25
  26 /* Semantic functions come in six versions on two axes:
  27    fast/full-featured, and using one of the simple/scache/compilation engines.
  28    A full featured simulator is always provided.  --enable-sim-fast includes
  29    support for fast execution by duplicating the semantic code but leaving
  30    out all features like tracing and profiling.
  31    Using the scache is selected with --enable-sim-scache.  */
  32 /* FIXME: --enable-sim-fast not implemented yet.  */
  33 /* FIXME: undecided how to handle WITH_SCACHE_PBB.  */
  34
  35 /* There are several styles of engines, all generally supported by the
  36    same code:
  37
  38    WITH_SCACHE && WITH_SCACHE_PBB - pseudo-basic-block scaching
  39    WITH_SCACHE && !WITH_SCACHE_PBB - scaching on an insn by insn basis
  40    !WITH_SCACHE - simple engine: fetch an insn, execute an insn
  41
  42    The !WITH_SCACHE case can also be broken up into two flavours:
  43    extract the fields of the insn into an ARGBUF struct, or defer the
  44    extraction to the semantic handler.  The former can be viewed as the
  45    WITH_SCACHE case with a cache size of 1 (thus there's no need for a
  46    WITH_EXTRACTION macro).  The WITH_SCACHE case always extracts the fields
  47    into an ARGBUF struct.  */
  48
  49 #ifndef CGEN_ENGINE_H
  50 #define CGEN_ENGINE_H
  51
  52 /* Instruction field support macros.  */
  53
  54 #define EXTRACT_MSB0_SINT(val, total, start, length) \
  55 (((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \
  56  >> ((sizeof (INT) * 8) - (length)))
  57 #define EXTRACT_MSB0_UINT(val, total, start, length) \
  58 (((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \
  59  >> ((sizeof (UINT) * 8) - (length)))
  60
  61 #define EXTRACT_LSB0_SINT(val, total, start, length) \
  62 (((INT) (val) << ((sizeof (INT) * 8) - (start) - 1)) \
  63  >> ((sizeof (INT) * 8) - (length)))
  64 #define EXTRACT_LSB0_UINT(val, total, start, length) \
  65 (((UINT) (val) << ((sizeof (UINT) * 8) - (start) - 1)) \
  66  >> ((sizeof (UINT) * 8) - (length)))
  67
  68 #define EXTRACT_MSB0_LGSINT(val, total, start, length) \
  69 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (total) + (start))) \
  70  >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
  71 #define EXTRACT_MSB0_LGUINT(val, total, start, length) \
  72 (((CGEN_INSN_UINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (total) + (start))) \
  73  >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
  74
  75 #define EXTRACT_LSB0_LGSINT(val, total, start, length) \
  76 (((CGEN_INSN_LGSINT) (val) << ((sizeof (CGEN_INSN_LGSINT) * 8) - (start) - 1)) \
  77  >> ((sizeof (CGEN_INSN_LGSINT) * 8) - (length)))
  78 #define EXTRACT_LSB0_LGUINT(val, total, start, length) \
  79 (((CGEN_INSN_LGUINT) (val) << ((sizeof (CGEN_INSN_LGUINT) * 8) - (start) - 1)) \
  80  >> ((sizeof (CGEN_INSN_LGUINT) * 8) - (length)))
  81 \f
  82 /* Semantic routines.  */
  83
  84 /* Type of the machine generated extraction fns.  */
  85 /* ??? No longer used.  */
  86 typedef void (EXTRACT_FN) (SIM_CPU *, IADDR, CGEN_INSN_WORD, ARGBUF *);
  87
  88 /* Type of the machine generated semantic fns.  */
  89
  90 #if WITH_SCACHE
  91
  92 /* Instruction fields are extracted into ARGBUF before calling the
  93    semantic routine.  */
  94 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
  95 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *);
  96 #else
  97 typedef SEM_PC (SEMANTIC_FN) (SIM_CPU *, SEM_ARG);
  98 #endif
  99
 100 #else
 101
 102 /* Result of semantic routines is a status indicator (wip).  */
 103 typedef unsigned int SEM_STATUS;
 104
 105 /* Instruction fields are extracted by the semantic routine.
 106    ??? TODO: multi word insns.  */
 107 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_GENWRITE
 108 typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, PAREXEC *, CGEN_INSN_WORD);
 109 #else
 110 typedef SEM_STATUS (SEMANTIC_FN) (SIM_CPU *, SEM_ARG, CGEN_INSN_WORD);
 111 #endif
 112
 113 #endif
 114
 115 /* In the ARGBUF struct, a pointer to the semantic routine for the insn.  */
 116
 117 union sem {
 118 #if ! WITH_SEM_SWITCH_FULL
 119   SEMANTIC_FN *sem_full;
 120 #endif
 121 #if ! WITH_SEM_SWITCH_FAST
 122   SEMANTIC_FN *sem_fast;
 123 #endif
 124 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 125 #ifdef __GNUC__
 126   void *sem_case;
 127 #else
 128   int sem_case;
 129 #endif
 130 #endif
 131 };
 132
 133 /* Set the appropriate semantic handler in ABUF.  */
 134
 135 #if WITH_SEM_SWITCH_FULL
 136 #ifdef __GNUC__
 137 #define SEM_SET_FULL_CODE(abuf, idesc) \
 138   do { (abuf)->semantic.sem_case = (idesc)->sem_full_lab; } while (0)
 139 #else
 140 #define SEM_SET_FULL_CODE(abuf, idesc) \
 141   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 142 #endif
 143 #else
 144 #define SEM_SET_FULL_CODE(abuf, idesc) \
 145   do { (abuf)->semantic.sem_full = (idesc)->sem_full; } while (0)
 146 #endif
 147
 148 #if WITH_SEM_SWITCH_FAST
 149 #ifdef __GNUC__
 150 #define SEM_SET_FAST_CODE(abuf, idesc) \
 151   do { (abuf)->semantic.sem_case = (idesc)->sem_fast_lab; } while (0)
 152 #else
 153 #define SEM_SET_FAST_CODE(abuf, idesc) \
 154   do { (abuf)->semantic.sem_case = (idesc)->num; } while (0)
 155 #endif
 156 #else
 157 #define SEM_SET_FAST_CODE(abuf, idesc) \
 158   do { (abuf)->semantic.sem_fast = (idesc)->sem_fast; } while (0)
 159 #endif
 160
 161 #define SEM_SET_CODE(abuf, idesc, fast_p) \
 162 do { \
 163   if (fast_p) \
 164     SEM_SET_FAST_CODE ((abuf), (idesc)); \
 165   else \
 166     SEM_SET_FULL_CODE ((abuf), (idesc)); \
 167 } while (0)
 168 \f
 169 /* Return non-zero if IDESC is a conditional or unconditional CTI.  */
 170
 171 #define IDESC_CTI_P(idesc) \
 172      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
 173        & (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \
 174           | CGEN_ATTR_MASK (CGEN_INSN_UNCOND_CTI))) \
 175       != 0)
 176
 177 /* Return non-zero if IDESC is a skip insn.  */
 178
 179 #define IDESC_SKIP_P(idesc) \
 180      ((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) \
 181        & CGEN_ATTR_MASK (CGEN_INSN_SKIP_CTI)) \
 182       != 0)
 183
 184 /* Return pointer to ARGBUF given ptr to SCACHE.  */
 185 #define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf)
 186
 187 #if WITH_SCACHE
 188
 189 #define CIA_ADDR(cia) (cia)
 190
 191 #if WITH_SCACHE_PBB
 192
 193 /* Return the scache pointer of the current insn.  */
 194 #define SEM_SEM_ARG(vpc, sc) (vpc)
 195
 196 /* Return the virtual pc of the next insn to execute
 197    (assuming this isn't a cti or the branch isn't taken).  */
 198 #define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1)
 199
 200 /* Update the instruction counter.  */
 201 #define PBB_UPDATE_INSN_COUNT(cpu,sc) \
 202   (CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count)
 203
 204 /* Do not append a `;' to invocations of this.
 205    npc,br_type are for communication between the cti insn and cti-chain.  */
 206 #define SEM_BRANCH_INIT \
 207   IADDR npc = 0; /* assign a value for -Wall */ \
 208   SEM_BRANCH_TYPE br_type = SEM_BRANCH_UNTAKEN;
 209
 210 /* SEM_IN_SWITCH is defined at the top of the mainloop.c files
 211    generated by genmloop.sh.  It exists so generated semantic code needn't
 212    care whether it's being put in a switch or in a function.  */
 213 #ifdef SEM_IN_SWITCH
 214 #define SEM_BRANCH_FINI(pcvar) \
 215 do { \
 216   pbb_br_npc = npc; \
 217   pbb_br_type = br_type; \
 218 } while (0)
 219 #else /* 1 semantic function per instruction */
 220 #define SEM_BRANCH_FINI(pcvar) \
 221 do { \
 222   CPU_PBB_BR_NPC (current_cpu) = npc; \
 223   CPU_PBB_BR_TYPE (current_cpu) = br_type; \
 224 } while (0)
 225 #endif
 226
 227 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
 228 do { \
 229   npc = (newval); \
 230   br_type = SEM_BRANCH_CACHEABLE; \
 231 } while (0)
 232
 233 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 234 do { \
 235   npc = (newval); \
 236   br_type = SEM_BRANCH_UNCACHEABLE; \
 237 } while (0)
 238
 239 #define SEM_SKIP_COMPILE(cpu, sc, skip) \
 240 do { \
 241   SEM_ARGBUF (sc) -> skip_count = (skip); \
 242 } while (0)
 243
 244 #define SEM_SKIP_INSN(cpu, sc, vpcvar) \
 245 do { \
 246   (vpcvar) += SEM_ARGBUF (sc) -> skip_count; \
 247 } while (0)
 248
 249 #else /* ! WITH_SCACHE_PBB */
 250
 251 #define SEM_SEM_ARG(vpc, sc) (sc)
 252
 253 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 254
 255 /* ??? May wish to move taken_p out of here and make it explicit.  */
 256 #define SEM_BRANCH_INIT \
 257   int taken_p = 0;
 258
 259 #ifndef TARGET_SEM_BRANCH_FINI
 260 #define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
 261 #endif
 262 #define SEM_BRANCH_FINI(pcvar) \
 263   do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
 264
 265 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
 266 do { \
 267   (pcvar) = (newval); \
 268   taken_p = 1; \
 269 } while (0)
 270
 271 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
 272 do { \
 273   (pcvar) = (newval); \
 274   taken_p = 1; \
 275 } while (0)
 276
 277 #endif /* ! WITH_SCACHE_PBB */
 278
 279 #else /* ! WITH_SCACHE */
 280
 281 /* This is the "simple" engine case.  */
 282
 283 #define CIA_ADDR(cia) (cia)
 284
 285 #define SEM_SEM_ARG(vpc, sc) (sc)
 286
 287 #define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
 288
 289 #define SEM_BRANCH_INIT \
 290   int taken_p = 0;
 291
 292 #define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \
 293 do { \
 294   (pcvar) = (newval); \
 295   taken_p = 1; \
 296 } while (0)
 297
 298 #define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \
 299 do { \
 300   (pcvar) = (newval); \
 301   taken_p = 1; \
 302 } while (0)
 303
 304 /* Finish off branch insns.
 305    The target must define TARGET_SEM_BRANCH_FINI.
 306    ??? This can probably go away when define-execute is finished.  */
 307 #define SEM_BRANCH_FINI(pcvar, bool_attrs) \
 308   do { TARGET_SEM_BRANCH_FINI ((pcvar), (bool_attrs), taken_p); } while (0)
 309
 310 /* Finish off non-branch insns.
 311    The target must define TARGET_SEM_NBRANCH_FINI.
 312    ??? This can probably go away when define-execute is finished.  */
 313 #define SEM_NBRANCH_FINI(pcvar, bool_attrs) \
 314   do { TARGET_SEM_NBRANCH_FINI ((pcvar), (bool_attrs)); } while (0)
 315
 316 #endif /* ! WITH_SCACHE */
 317 \f
 318 /* Instruction information.  */
 319
 320 /* Sanity check, at most one of these may be true.  */
 321 #if WITH_PARALLEL_READ + WITH_PARALLEL_WRITE + WITH_PARALLEL_GENWRITE > 1
 322 #error "At most one of WITH_PARALLEL_{READ,WRITE,GENWRITE} can be true."
 323 #endif
 324
 325 /* Compile time computable instruction data.  */
 326
 327 struct insn_sem {
 328   /* The instruction type (a number that identifies each insn over the
 329      entire architecture).  */
 330   CGEN_INSN_TYPE type;
 331
 332   /* Index in IDESC table.  */
 333   int index;
 334
 335   /* Semantic format number.  */
 336   int sfmt;
 337
 338 #if HAVE_PARALLEL_INSNS && ! WITH_PARALLEL_ONLY
 339   /* Index in IDESC table of parallel handler.  */
 340   int par_index;
 341 #endif
 342
 343 #if WITH_PARALLEL_READ
 344   /* Index in IDESC table of read handler.  */
 345   int read_index;
 346 #endif
 347
 348 #if WITH_PARALLEL_WRITE
 349   /* Index in IDESC table of writeback handler.  */
 350   int write_index;
 351 #endif
 352 };
 353
 354 /* Entry in semantic function table.
 355    This information is copied to the insn descriptor table at run-time.  */
 356
 357 struct sem_fn_desc {
 358   /* Index in IDESC table.  */
 359   int index;
 360
 361   /* Function to perform the semantics of the insn.  */
 362   SEMANTIC_FN *fn;
 363 };
 364
 365 /* Run-time computed instruction descriptor.  */
 366
 367 struct idesc {
 368 #if WITH_SEM_SWITCH_FAST
 369 #ifdef __GNUC__
 370   void *sem_fast_lab;
 371 #else
 372   /* nothing needed, switch's on `num' member */
 373 #endif
 374 #else
 375   SEMANTIC_FN *sem_fast;
 376 #endif
 377
 378 #if WITH_SEM_SWITCH_FULL
 379 #ifdef __GNUC__
 380   void *sem_full_lab;
 381 #else
 382   /* nothing needed, switch's on `num' member */
 383 #endif
 384 #else
 385   SEMANTIC_FN *sem_full;
 386 #endif
 387
 388   /* Parallel support.  */
 389 #if HAVE_PARALLEL_INSNS && (! WITH_PARALLEL_ONLY || (WITH_PARALLEL_ONLY && ! WITH_PARALLEL_GENWRITE))
 390   /* Pointer to parallel handler if serial insn.
 391      Pointer to readahead/writeback handler if parallel insn.  */
 392   struct idesc *par_idesc;
 393 #endif
 394
 395   /* Instruction number (index in IDESC table, profile table).
 396      Also used to switch on in non-gcc semantic switches.  */
 397   int num;
 398
 399   /* Semantic format id.  */
 400   int sfmt;
 401
 402   /* instruction data (name, attributes, size, etc.) */
 403   const CGEN_INSN *idata;
 404
 405   /* instruction attributes, copied from `idata' for speed */
 406   const CGEN_INSN_ATTR_TYPE *attrs;
 407
 408   /* instruction length in bytes, copied from `idata' for speed */
 409   int length;
 410
 411   /* profiling/modelling support */
 412   const INSN_TIMING *timing;
 413 };
 414 \f
 415 /* Tracing/profiling.  */
 416
 417 /* Return non-zero if a before/after handler is needed.
 418    When tracing/profiling a selected range there's no need to slow
 419    down simulation of the other insns (except to get more accurate data!).
 420
 421    ??? May wish to profile all insns if doing insn tracing, or to
 422    get more accurate cycle data.
 423
 424    First test ANY_P so we avoid a potentially expensive HIT_P call
 425    [if there are lots of address ranges].  */
 426
 427 #define PC_IN_TRACE_RANGE_P(cpu, pc) \
 428   (TRACE_ANY_P (cpu) \
 429    && ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc)))
 430 #define PC_IN_PROFILE_RANGE_P(cpu, pc) \
 431   (PROFILE_ANY_P (cpu) \
 432    && ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc)))
 433
 434 #endif /* CGEN_ENGINE_H */