sim/common/cgen-par.c

   1 /* Simulator parallel routines for CGEN simulators (and maybe others).
   2    Copyright (C) 1999 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of the GNU instruction set simulator.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #include "sim-main.h"
  22 #include "cgen-mem.h"
  23 #include "cgen-par.h"
  24
  25 /* Functions required by the cgen interface.  These functions add various
  26    kinds of writes to the write queue.  */
  27 void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
  28 {
  29   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  30   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  31   element->kind = CGEN_QI_WRITE;
  32   element->kinds.qi_write.target = target;
  33   element->kinds.qi_write.value  = value;
  34 }
  35
  36 void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
  37 {
  38   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  39   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  40   element->kind = CGEN_SI_WRITE;
  41   element->kinds.si_write.target = target;
  42   element->kinds.si_write.value  = value;
  43 }
  44
  45 void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
  46 {
  47   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  48   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  49   element->kind = CGEN_SF_WRITE;
  50   element->kinds.sf_write.target = target;
  51   element->kinds.sf_write.value  = value;
  52 }
  53
  54 void sim_queue_pc_write (SIM_CPU *cpu, USI value)
  55 {
  56   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  57   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  58   element->kind = CGEN_PC_WRITE;
  59   element->kinds.pc_write.value = value;
  60 }
  61
  62 void sim_queue_fn_si_write (
  63   SIM_CPU *cpu,
  64   void (*write_function)(SIM_CPU *cpu, UINT, USI),
  65   UINT regno,
  66   SI value
  67 )
  68 {
  69   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  70   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  71   element->kind = CGEN_FN_SI_WRITE;
  72   element->kinds.fn_si_write.function = write_function;
  73   element->kinds.fn_si_write.regno = regno;
  74   element->kinds.fn_si_write.value = value;
  75 }
  76
  77 void sim_queue_fn_di_write (
  78   SIM_CPU *cpu,
  79   void (*write_function)(SIM_CPU *cpu, UINT, DI),
  80   UINT regno,
  81   DI value
  82 )
  83 {
  84   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
  85   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
  86   element->kind = CGEN_FN_DI_WRITE;
  87   element->kinds.fn_di_write.function = write_function;
  88   element->kinds.fn_di_write.regno = regno;
  89   element->kinds.fn_di_write.value = value;
  90 }
  91
  92 void sim_queue_fn_df_write (
  93   SIM_CPU *cpu,
  94   void (*write_function)(SIM_CPU *cpu, UINT, DI),
  95   UINT regno,
  96   DF value
  97 )
  98 {
  99   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 100   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 101   element->kind = CGEN_FN_DF_WRITE;
 102   element->kinds.fn_df_write.function = write_function;
 103   element->kinds.fn_df_write.regno = regno;
 104   element->kinds.fn_df_write.value = value;
 105 }
 106
 107 void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
 108 {
 109   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 110   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 111   element->kind = CGEN_MEM_QI_WRITE;
 112   element->kinds.mem_qi_write.address = address;
 113   element->kinds.mem_qi_write.value   = value;
 114 }
 115
 116 void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
 117 {
 118   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 119   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 120   element->kind = CGEN_MEM_HI_WRITE;
 121   element->kinds.mem_hi_write.address = address;
 122   element->kinds.mem_hi_write.value   = value;
 123 }
 124
 125 void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
 126 {
 127   CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
 128   CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
 129   element->kind = CGEN_MEM_SI_WRITE;
 130   element->kinds.mem_si_write.address = address;
 131   element->kinds.mem_si_write.value   = value;
 132 }
 133
 134 /* Execute a write stored on the write queue.  */
 135 void
 136 cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
 137 {
 138   IADDR pc;
 139   switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
 140     {
 141     case CGEN_QI_WRITE:
 142       *item->kinds.qi_write.target = item->kinds.qi_write.value;
 143       break;
 144     case CGEN_SI_WRITE:
 145       *item->kinds.si_write.target = item->kinds.si_write.value;
 146       break;
 147     case CGEN_SF_WRITE:
 148       *item->kinds.sf_write.target = item->kinds.sf_write.value;
 149       break;
 150     case CGEN_PC_WRITE:
 151       CPU_PC_SET (cpu, item->kinds.pc_write.value);
 152       break;
 153     case CGEN_FN_SI_WRITE:
 154       item->kinds.fn_si_write.function (cpu,
 155                                         item->kinds.fn_si_write.regno,
 156                                         item->kinds.fn_si_write.value);
 157       break;
 158     case CGEN_FN_DI_WRITE:
 159       item->kinds.fn_di_write.function (cpu,
 160                                         item->kinds.fn_di_write.regno,
 161                                         item->kinds.fn_di_write.value);
 162       break;
 163     case CGEN_FN_DF_WRITE:
 164       item->kinds.fn_df_write.function (cpu,
 165                                         item->kinds.fn_df_write.regno,
 166                                         item->kinds.fn_df_write.value);
 167       break;
 168     case CGEN_MEM_QI_WRITE:
 169       pc = CPU_PC_GET (cpu);
 170       SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
 171                 item->kinds.mem_qi_write.value);
 172       break;
 173     case CGEN_MEM_HI_WRITE:
 174       pc = CPU_PC_GET (cpu);
 175       SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
 176                 item->kinds.mem_hi_write.value);
 177       break;
 178     case CGEN_MEM_SI_WRITE:
 179       pc = CPU_PC_GET (cpu);
 180       SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
 181                 item->kinds.mem_si_write.value);
 182       break;
 183     default:
 184       break; /* FIXME: for now....print message later.  */
 185     }
 186 }
 187
 188 /* Utilities for the write queue.  */
 189 CGEN_WRITE_QUEUE_ELEMENT *
 190 cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
 191 {
 192   abort (); /* FIXME: for now....print message later.  */
 193   return 0;
 194 }