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1 /* This file is part of the program psim.
2
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18
19 */
20
21
22 #ifndef SIM_CORE_C
23 #define SIM_CORE_C
24
25 #include "sim-main.h"
26 #include "sim-assert.h"
27
28 #if (WITH_HW)
29 #include "sim-hw.h"
30 #endif
31
32 #if (WITH_DEVICES)
33 /* TODO: create sim/common/device.h */
34 void device_error (device *me, char* message, ...);
35 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
36 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
37 #endif
38
39 /* "core" module install handler.
40
41 This is called via sim_module_install to install the "core"
42 subsystem into the simulator. */
43
44 #if EXTERN_SIM_CORE_P
45 static MODULE_INIT_FN sim_core_init;
46 static MODULE_UNINSTALL_FN sim_core_uninstall;
47 #endif
48
49 #if EXTERN_SIM_CORE_P
50 SIM_RC
51 sim_core_install (SIM_DESC sd)
52 {
53 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
54
55 /* establish the other handlers */
56 sim_module_add_uninstall_fn (sd, sim_core_uninstall);
57 sim_module_add_init_fn (sd, sim_core_init);
58
59 /* establish any initial data structures - none */
60 return SIM_RC_OK;
61 }
62 #endif
63
64
65 /* Uninstall the "core" subsystem from the simulator. */
66
67 #if EXTERN_SIM_CORE_P
68 static void
69 sim_core_uninstall (SIM_DESC sd)
70 {
71 sim_core *core = STATE_CORE(sd);
72 unsigned map;
73 /* blow away any mappings */
74 for (map = 0; map < nr_maps; map++) {
75 sim_core_mapping *curr = core->common.map[map].first;
76 while (curr != NULL) {
77 sim_core_mapping *tbd = curr;
78 curr = curr->next;
79 if (tbd->free_buffer != NULL) {
80 SIM_ASSERT(tbd->buffer != NULL);
81 zfree(tbd->free_buffer);
82 }
83 zfree(tbd);
84 }
85 core->common.map[map].first = NULL;
86 }
87 }
88 #endif
89
90
91 #if EXTERN_SIM_CORE_P
92 static SIM_RC
93 sim_core_init (SIM_DESC sd)
94 {
95 /* Nothing to do */
96 return SIM_RC_OK;
97 }
98 #endif
99
100
101
102 #ifndef SIM_CORE_SIGNAL
103 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
104 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
105 #endif
106
107 #if EXTERN_SIM_CORE_P
108 void
109 sim_core_signal (SIM_DESC sd,
110 sim_cpu *cpu,
111 sim_cia cia,
112 unsigned map,
113 int nr_bytes,
114 address_word addr,
115 transfer_type transfer,
116 sim_core_signals sig)
117 {
118 const char *copy = (transfer == read_transfer ? "read" : "write");
119 address_word ip = CIA_ADDR (cia);
120 switch (sig)
121 {
122 case sim_core_unmapped_signal:
123 sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
124 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
125 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
126 break;
127 case sim_core_unaligned_signal:
128 sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
129 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
130 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
131 break;
132 default:
133 sim_engine_abort (sd, cpu, cia,
134 "sim_core_signal - internal error - bad switch");
135 }
136 }
137 #endif
138
139
140 #if EXTERN_SIM_CORE_P
141 static sim_core_mapping *
142 new_sim_core_mapping (SIM_DESC sd,
143 int level,
144 int space,
145 address_word addr,
146 address_word nr_bytes,
147 unsigned modulo,
148 #if WITH_HW
149 struct hw *device,
150 #else
151 device *device,
152 #endif
153 void *buffer,
154 void *free_buffer)
155 {
156 sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
157 /* common */
158 new_mapping->level = level;
159 new_mapping->space = space;
160 new_mapping->base = addr;
161 new_mapping->nr_bytes = nr_bytes;
162 new_mapping->bound = addr + (nr_bytes - 1);
163 if (modulo == 0)
164 new_mapping->mask = (unsigned) 0 - 1;
165 else
166 new_mapping->mask = modulo - 1;
167 new_mapping->buffer = buffer;
168 new_mapping->free_buffer = free_buffer;
169 new_mapping->device = device;
170 return new_mapping;
171 }
172 #endif
173
174
175 #if EXTERN_SIM_CORE_P
176 static void
177 sim_core_map_attach (SIM_DESC sd,
178 sim_core_map *access_map,
179 int level,
180 int space,
181 address_word addr,
182 address_word nr_bytes,
183 unsigned modulo,
184 #if WITH_HW
185 struct hw *client, /*callback/default*/
186 #else
187 device *client, /*callback/default*/
188 #endif
189 void *buffer, /*raw_memory*/
190 void *free_buffer) /*raw_memory*/
191 {
192 /* find the insertion point for this additional mapping and then
193 insert */
194 sim_core_mapping *next_mapping;
195 sim_core_mapping **last_mapping;
196
197 SIM_ASSERT ((client == NULL) != (buffer == NULL));
198 SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
199
200 /* actually do occasionally get a zero size map */
201 if (nr_bytes == 0)
202 {
203 #if (WITH_DEVICES)
204 device_error(client, "called on sim_core_map_attach with size zero");
205 #endif
206 #if (WITH_HW)
207 sim_hw_abort (sd, client, "called on sim_core_map_attach with size zero");
208 #endif
209 sim_io_error (sd, "called on sim_core_map_attach with size zero");
210 }
211
212 /* find the insertion point (between last/next) */
213 next_mapping = access_map->first;
214 last_mapping = &access_map->first;
215 while(next_mapping != NULL
216 && (next_mapping->level < level
217 || (next_mapping->level == level
218 && next_mapping->bound < addr)))
219 {
220 /* provided levels are the same */
221 /* assert: next_mapping->base > all bases before next_mapping */
222 /* assert: next_mapping->bound >= all bounds before next_mapping */
223 last_mapping = &next_mapping->next;
224 next_mapping = next_mapping->next;
225 }
226
227 /* check insertion point correct */
228 SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
229 if (next_mapping != NULL && next_mapping->level == level
230 && next_mapping->base < (addr + (nr_bytes - 1)))
231 {
232 #if (WITH_DEVICES)
233 device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
234 space,
235 (long) addr,
236 (long) nr_bytes,
237 (long) (addr + (nr_bytes - 1)),
238 next_mapping->space,
239 (long) next_mapping->base,
240 (long) next_mapping->bound,
241 (long) next_mapping->nr_bytes);
242 #endif
243 #if WITH_HW
244 sim_hw_abort (sd, client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
245 space,
246 (long) addr,
247 (long) nr_bytes,
248 (long) (addr + (nr_bytes - 1)),
249 next_mapping->space,
250 (long) next_mapping->base,
251 (long) next_mapping->bound,
252 (long) next_mapping->nr_bytes);
253 #endif
254 sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
255 space,
256 (long) addr,
257 (long) nr_bytes,
258 (long) (addr + (nr_bytes - 1)),
259 next_mapping->space,
260 (long) next_mapping->base,
261 (long) next_mapping->bound,
262 (long) next_mapping->nr_bytes);
263 }
264
265 /* create/insert the new mapping */
266 *last_mapping = new_sim_core_mapping(sd,
267 level,
268 space, addr, nr_bytes, modulo,
269 client, buffer, free_buffer);
270 (*last_mapping)->next = next_mapping;
271 }
272 #endif
273
274
275 /* Attach memory or a memory mapped device to the simulator.
276 See sim-core.h for a full description. */
277
278 #if EXTERN_SIM_CORE_P
279 void
280 sim_core_attach (SIM_DESC sd,
281 sim_cpu *cpu,
282 int level,
283 unsigned mapmask,
284 int space,
285 address_word addr,
286 address_word nr_bytes,
287 unsigned modulo,
288 #if WITH_HW
289 struct hw *client,
290 #else
291 device *client,
292 #endif
293 void *optional_buffer)
294 {
295 sim_core *memory = STATE_CORE(sd);
296 unsigned map;
297 void *buffer;
298 void *free_buffer;
299
300 /* check for for attempt to use unimplemented per-processor core map */
301 if (cpu != NULL)
302 sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
303
304 /* verify modulo memory */
305 if (!WITH_MODULO_MEMORY && modulo != 0)
306 {
307 #if (WITH_DEVICES)
308 device_error (client, "sim_core_attach - internal error - modulo memory disabled");
309 #endif
310 #if (WITH_HW)
311 sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo memory disabled");
312 #endif
313 sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
314 }
315 if (client != NULL && modulo != 0)
316 {
317 #if (WITH_DEVICES)
318 device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict");
319 #endif
320 #if (WITH_HW)
321 sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo and callback memory conflict");
322 #endif
323 sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
324 }
325 if (modulo != 0)
326 {
327 unsigned mask = modulo - 1;
328 /* any zero bits */
329 while (mask >= sizeof (unsigned64)) /* minimum modulo */
330 {
331 if ((mask & 1) == 0)
332 mask = 0;
333 else
334 mask >>= 1;
335 }
336 if (mask != sizeof (unsigned64) - 1)
337 {
338 #if (WITH_DEVICES)
339 device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
340 #endif
341 #if (WITH_HW)
342 sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
343 #endif
344 sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
345 }
346 }
347
348 /* verify consistency between device and buffer */
349 if (client != NULL && optional_buffer != NULL)
350 {
351 #if (WITH_DEVICES)
352 device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
353 #endif
354 #if (WITH_HW)
355 sim_hw_abort (sd, client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
356 #endif
357 sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
358 }
359 if (client == NULL)
360 {
361 if (optional_buffer == NULL)
362 {
363 int padding = (addr % sizeof (unsigned64));
364 unsigned long bytes = (modulo == 0 ? nr_bytes : modulo) + padding;
365 free_buffer = zalloc (bytes);
366 buffer = (char*) free_buffer + padding;
367 }
368 else
369 {
370 buffer = optional_buffer;
371 free_buffer = NULL;
372 }
373 }
374 else
375 {
376 /* a device */
377 buffer = NULL;
378 free_buffer = NULL;
379 }
380
381 /* attach the region to all applicable access maps */
382 for (map = 0;
383 map < nr_maps;
384 map++)
385 {
386 if (mapmask & (1 << map))
387 {
388 sim_core_map_attach (sd, &memory->common.map[map],
389 level, space, addr, nr_bytes, modulo,
390 client, buffer, free_buffer);
391 free_buffer = NULL;
392 }
393 }
394
395 /* Just copy this map to each of the processor specific data structures.
396 FIXME - later this will be replaced by true processor specific
397 maps. */
398 {
399 int i;
400 for (i = 0; i < MAX_NR_PROCESSORS; i++)
401 {
402 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
403 }
404 }
405 }
406 #endif
407
408
409 /* Remove any memory reference related to this address */
410 #if EXTERN_SIM_CORE_P
411 static void
412 sim_core_map_detach (SIM_DESC sd,
413 sim_core_map *access_map,
414 int level,
415 int space,
416 address_word addr)
417 {
418 sim_core_mapping **entry;
419 for (entry = &access_map->first;
420 (*entry) != NULL;
421 entry = &(*entry)->next)
422 {
423 if ((*entry)->base == addr
424 && (*entry)->level == level
425 && (*entry)->space == space)
426 {
427 sim_core_mapping *dead = (*entry);
428 (*entry) = dead->next;
429 if (dead->free_buffer != NULL)
430 zfree (dead->free_buffer);
431 zfree (dead);
432 return;
433 }
434 }
435 }
436 #endif
437
438 #if EXTERN_SIM_CORE_P
439 void
440 sim_core_detach (SIM_DESC sd,
441 sim_cpu *cpu,
442 int level,
443 int address_space,
444 address_word addr)
445 {
446 sim_core *memory = STATE_CORE (sd);
447 unsigned map;
448 for (map = 0; map < nr_maps; map++)
449 {
450 sim_core_map_detach (sd, &memory->common.map[map],
451 level, address_space, addr);
452 }
453 /* Just copy this update to each of the processor specific data
454 structures. FIXME - later this will be replaced by true
455 processor specific maps. */
456 {
457 int i;
458 for (i = 0; i < MAX_NR_PROCESSORS; i++)
459 {
460 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
461 }
462 }
463 }
464 #endif
465
466
467 STATIC_INLINE_SIM_CORE\
468 (sim_core_mapping *)
469 sim_core_find_mapping(sim_core_common *core,
470 unsigned map,
471 address_word addr,
472 unsigned nr_bytes,
473 transfer_type transfer,
474 int abort, /*either 0 or 1 - hint to inline/-O */
475 sim_cpu *cpu, /* abort => cpu != NULL */
476 sim_cia cia)
477 {
478 sim_core_mapping *mapping = core->map[map].first;
479 ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
480 ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
481 ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
482 while (mapping != NULL)
483 {
484 if (addr >= mapping->base
485 && (addr + (nr_bytes - 1)) <= mapping->bound)
486 return mapping;
487 mapping = mapping->next;
488 }
489 if (abort)
490 {
491 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
492 sim_core_unmapped_signal);
493 }
494 return NULL;
495 }
496
497
498 STATIC_INLINE_SIM_CORE\
499 (void *)
500 sim_core_translate (sim_core_mapping *mapping,
501 address_word addr)
502 {
503 if (WITH_MODULO_MEMORY)
504 return (void *)((unsigned8 *) mapping->buffer
505 + ((addr - mapping->base) & mapping->mask));
506 else
507 return (void *)((unsigned8 *) mapping->buffer
508 + addr - mapping->base);
509 }
510
511
512 #if EXTERN_SIM_CORE_P
513 unsigned
514 sim_core_read_buffer (SIM_DESC sd,
515 sim_cpu *cpu,
516 unsigned map,
517 void *buffer,
518 address_word addr,
519 unsigned len)
520 {
521 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
522 unsigned count = 0;
523 while (count < len)
524 {
525 unsigned_word raddr = addr + count;
526 sim_core_mapping *mapping =
527 sim_core_find_mapping (core, map,
528 raddr, /*nr-bytes*/1,
529 read_transfer,
530 0 /*dont-abort*/, NULL, NULL_CIA);
531 if (mapping == NULL)
532 break;
533 #if (WITH_DEVICES)
534 if (mapping->device != NULL)
535 {
536 int nr_bytes = len - count;
537 if (raddr + nr_bytes - 1> mapping->bound)
538 nr_bytes = mapping->bound - raddr + 1;
539 if (device_io_read_buffer (mapping->device,
540 (unsigned_1*)buffer + count,
541 mapping->space,
542 raddr,
543 nr_bytes,
544 cpu,
545 CIA_GET (cpu)) != nr_bytes)
546 break;
547 count += nr_bytes;
548 continue;
549 }
550 #endif
551 #if (WITH_HW)
552 if (mapping->device != NULL)
553 {
554 int nr_bytes = len - count;
555 if (raddr + nr_bytes - 1> mapping->bound)
556 nr_bytes = mapping->bound - raddr + 1;
557 if (sim_hw_io_read_buffer (sd, mapping->device,
558 (unsigned_1*)buffer + count,
559 mapping->space,
560 raddr,
561 nr_bytes) != nr_bytes)
562 break;
563 count += nr_bytes;
564 continue;
565 }
566 #endif
567 ((unsigned_1*)buffer)[count] =
568 *(unsigned_1*)sim_core_translate(mapping, raddr);
569 count += 1;
570 }
571 return count;
572 }
573 #endif
574
575
576 #if EXTERN_SIM_CORE_P
577 unsigned
578 sim_core_write_buffer (SIM_DESC sd,
579 sim_cpu *cpu,
580 unsigned map,
581 const void *buffer,
582 address_word addr,
583 unsigned len)
584 {
585 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
586 unsigned count = 0;
587 while (count < len)
588 {
589 unsigned_word raddr = addr + count;
590 sim_core_mapping *mapping =
591 sim_core_find_mapping (core, map,
592 raddr, /*nr-bytes*/1,
593 write_transfer,
594 0 /*dont-abort*/, NULL, NULL_CIA);
595 if (mapping == NULL)
596 break;
597 #if (WITH_DEVICES)
598 if (WITH_CALLBACK_MEMORY
599 && mapping->device != NULL)
600 {
601 int nr_bytes = len - count;
602 if (raddr + nr_bytes - 1 > mapping->bound)
603 nr_bytes = mapping->bound - raddr + 1;
604 if (device_io_write_buffer (mapping->device,
605 (unsigned_1*)buffer + count,
606 mapping->space,
607 raddr,
608 nr_bytes,
609 cpu,
610 CIA_GET(cpu)) != nr_bytes)
611 break;
612 count += nr_bytes;
613 continue;
614 }
615 #endif
616 #if (WITH_HW)
617 if (WITH_CALLBACK_MEMORY
618 && mapping->device != NULL)
619 {
620 int nr_bytes = len - count;
621 if (raddr + nr_bytes - 1 > mapping->bound)
622 nr_bytes = mapping->bound - raddr + 1;
623 if (sim_hw_io_write_buffer (sd, mapping->device,
624 (unsigned_1*)buffer + count,
625 mapping->space,
626 raddr,
627 nr_bytes) != nr_bytes)
628 break;
629 count += nr_bytes;
630 continue;
631 }
632 #endif
633 *(unsigned_1*)sim_core_translate(mapping, raddr) =
634 ((unsigned_1*)buffer)[count];
635 count += 1;
636 }
637 return count;
638 }
639 #endif
640
641
642 #if EXTERN_SIM_CORE_P
643 void
644 sim_core_set_xor (SIM_DESC sd,
645 sim_cpu *cpu,
646 int is_xor)
647 {
648 /* set up the XOR map if required. */
649 if (WITH_XOR_ENDIAN) {
650 {
651 sim_core *core = STATE_CORE (sd);
652 sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
653 if (cpu_core != NULL)
654 {
655 int i = 1;
656 unsigned mask;
657 if (is_xor)
658 mask = WITH_XOR_ENDIAN - 1;
659 else
660 mask = 0;
661 while (i - 1 < WITH_XOR_ENDIAN)
662 {
663 cpu_core->xor[i-1] = mask;
664 mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
665 i = (i << 1);
666 }
667 }
668 else
669 {
670 if (is_xor)
671 core->byte_xor = WITH_XOR_ENDIAN - 1;
672 else
673 core->byte_xor = 0;
674 }
675 }
676 }
677 else {
678 if (is_xor)
679 sim_engine_abort (sd, NULL, NULL_CIA,
680 "Attempted to enable xor-endian mode when permenantly disabled.");
681 }
682 }
683 #endif
684
685
686 #if EXTERN_SIM_CORE_P
687 static void
688 reverse_n (unsigned_1 *dest,
689 const unsigned_1 *src,
690 int nr_bytes)
691 {
692 int i;
693 for (i = 0; i < nr_bytes; i++)
694 {
695 dest [nr_bytes - i - 1] = src [i];
696 }
697 }
698 #endif
699
700
701 #if EXTERN_SIM_CORE_P
702 unsigned
703 sim_core_xor_read_buffer (SIM_DESC sd,
704 sim_cpu *cpu,
705 unsigned map,
706 void *buffer,
707 address_word addr,
708 unsigned nr_bytes)
709 {
710 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
711 if (!WITH_XOR_ENDIAN || !byte_xor)
712 return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
713 else
714 /* only break up transfers when xor-endian is both selected and enabled */
715 {
716 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
717 unsigned nr_transfered = 0;
718 address_word start = addr;
719 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
720 address_word stop;
721 /* initial and intermediate transfers are broken when they cross
722 an XOR endian boundary */
723 while (nr_transfered + nr_this_transfer < nr_bytes)
724 /* initial/intermediate transfers */
725 {
726 /* since xor-endian is enabled stop^xor defines the start
727 address of the transfer */
728 stop = start + nr_this_transfer - 1;
729 SIM_ASSERT (start <= stop);
730 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
731 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
732 != nr_this_transfer)
733 return nr_transfered;
734 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
735 nr_transfered += nr_this_transfer;
736 nr_this_transfer = WITH_XOR_ENDIAN;
737 start = stop + 1;
738 }
739 /* final transfer */
740 nr_this_transfer = nr_bytes - nr_transfered;
741 stop = start + nr_this_transfer - 1;
742 SIM_ASSERT (stop == (addr + nr_bytes - 1));
743 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
744 != nr_this_transfer)
745 return nr_transfered;
746 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
747 return nr_bytes;
748 }
749 }
750 #endif
751
752
753 #if EXTERN_SIM_CORE_P
754 unsigned
755 sim_core_xor_write_buffer (SIM_DESC sd,
756 sim_cpu *cpu,
757 unsigned map,
758 const void *buffer,
759 address_word addr,
760 unsigned nr_bytes)
761 {
762 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
763 if (!WITH_XOR_ENDIAN || !byte_xor)
764 return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
765 else
766 /* only break up transfers when xor-endian is both selected and enabled */
767 {
768 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
769 unsigned nr_transfered = 0;
770 address_word start = addr;
771 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
772 address_word stop;
773 /* initial and intermediate transfers are broken when they cross
774 an XOR endian boundary */
775 while (nr_transfered + nr_this_transfer < nr_bytes)
776 /* initial/intermediate transfers */
777 {
778 /* since xor-endian is enabled stop^xor defines the start
779 address of the transfer */
780 stop = start + nr_this_transfer - 1;
781 SIM_ASSERT (start <= stop);
782 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
783 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
784 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
785 != nr_this_transfer)
786 return nr_transfered;
787 nr_transfered += nr_this_transfer;
788 nr_this_transfer = WITH_XOR_ENDIAN;
789 start = stop + 1;
790 }
791 /* final transfer */
792 nr_this_transfer = nr_bytes - nr_transfered;
793 stop = start + nr_this_transfer - 1;
794 SIM_ASSERT (stop == (addr + nr_bytes - 1));
795 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
796 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
797 != nr_this_transfer)
798 return nr_transfered;
799 return nr_bytes;
800 }
801 }
802 #endif
803
804
805
806 /* define the read/write 1/2/4/8/16/word functions */
807
808 #define N 16
809 #include "sim-n-core.h"
810
811 #define N 8
812 #include "sim-n-core.h"
813
814 #define N 7
815 #define M 8
816 #include "sim-n-core.h"
817
818 #define N 6
819 #define M 8
820 #include "sim-n-core.h"
821
822 #define N 5
823 #define M 8
824 #include "sim-n-core.h"
825
826 #define N 4
827 #include "sim-n-core.h"
828
829 #define N 3
830 #define M 4
831 #include "sim-n-core.h"
832
833 #define N 2
834 #include "sim-n-core.h"
835
836 #define N 1
837 #include "sim-n-core.h"
838
839 #endif