sim/common/sim-core.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef SIM_CORE_H
  23 #define SIM_CORE_H
  24
  25
  26 /* core signals (error conditions)
  27    Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
  28    details.  */
  29
  30 typedef enum {
  31   sim_core_unmapped_signal,
  32   sim_core_unaligned_signal,
  33   nr_sim_core_signals,
  34 } sim_core_signals;
  35
  36 /* Type of SIM_CORE_SIGNAL handler.  */
  37 typedef void (SIM_CORE_SIGNAL_FN)
  38      (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes,
  39       address_word addr, transfer_type transfer, sim_core_signals sig);
  40
  41 extern SIM_CORE_SIGNAL_FN sim_core_signal;
  42
  43
  44 /* basic types */
  45
  46 typedef struct _sim_core_mapping sim_core_mapping;
  47 struct _sim_core_mapping {
  48   /* common */
  49   int level;
  50   int space;
  51   unsigned_word base;
  52   unsigned_word bound;
  53   unsigned_word nr_bytes;
  54   unsigned mask;
  55   /* memory map */
  56   void *free_buffer;
  57   void *buffer;
  58   /* callback map */
  59 #if (WITH_HW)
  60   struct hw *device;
  61 #else
  62   device *device;
  63 #endif
  64   /* tracing */
  65   int trace;
  66   /* growth */
  67   sim_core_mapping *next;
  68 };
  69
  70 typedef struct _sim_core_map sim_core_map;
  71 struct _sim_core_map {
  72   sim_core_mapping *first;
  73 };
  74
  75
  76 typedef struct _sim_core_common {
  77   sim_core_map map[nr_maps];
  78 } sim_core_common;
  79
  80
  81 /* Main core structure */
  82
  83 typedef struct _sim_core sim_core;
  84 struct _sim_core {
  85   sim_core_common common;
  86   address_word byte_xor; /* apply xor universally */
  87 };
  88
  89
  90 /* Per CPU distributed component of the core.  At present this is
  91    mostly a clone of the global core data structure. */
  92
  93 typedef struct _sim_cpu_core {
  94   sim_core_common common;
  95   address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
  96 } sim_cpu_core;
  97
  98
  99 /* Install the "core" module.  */
 100
 101 EXTERN_SIM_CORE\
 102 (SIM_RC) sim_core_install (SIM_DESC sd);
 103
 104
 105
 106 /* Create a memory region within the core.
 107
 108    CPU - when non NULL, specifes the single processor that the memory
 109    space is to be attached to. (INIMPLEMENTED).
 110
 111    LEVEL - specifies the ordering of the memory region.  Lower regions
 112    are searched first.  Within a level, memory regions can not
 113    overlap.
 114
 115    MAPMASK - Bitmask specifying the memory maps that the region is to
 116    be attached to.  Typically the enums sim-basics.h:access_* are used.
 117
 118    ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is
 119    translated into ADDRESS_SPACE:OFFSET before being passed to the
 120    client device.
 121
 122    MODULO - when the simulator has been configured WITH_MODULO support
 123    and is greater than zero, specifies that accesses to the region
 124    [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
 125    .. ADDR+MODULO).  The modulo value must be a power of two.
 126
 127    DEVICE - When non NULL, indicates that this is a callback memory
 128    space and specified device's memory callback handler should be
 129    called.
 130
 131    OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for
 132    data read & written to the region.  Normally a more efficient
 133    internal structure is used.  It is assumed that buffer is allocated
 134    such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
 135    (OPTIONAL_BUFFER % 8) == (ADDR % 8)).  It is defined to be a sub-optimal
 136    hook that allows clients to do nasty things that the interface doesn't
 137    accomodate. */
 138
 139 EXTERN_SIM_CORE\
 140 (void) sim_core_attach
 141 (SIM_DESC sd,
 142  sim_cpu *cpu,
 143  int level,
 144  unsigned mapmask,
 145  int address_space,
 146  address_word addr,
 147  address_word nr_bytes,
 148  unsigned modulo,
 149 #if (WITH_HW)
 150  struct hw *client,
 151 #else
 152  device *client,
 153 #endif
 154  void *optional_buffer);
 155
 156
 157 /* Delete a memory section within the core.
 158
 159  */
 160
 161 EXTERN_SIM_CORE\
 162 (void) sim_core_detach
 163 (SIM_DESC sd,
 164  sim_cpu *cpu,
 165  int level,
 166  int address_space,
 167  address_word addr);
 168
 169
 170 /* Variable sized read/write
 171
 172    Transfer a variable sized block of raw data between the host and
 173    target.  Should any problems occure, the number of bytes
 174    successfully transfered is returned.
 175
 176    No host/target byte endian conversion is performed.  No xor-endian
 177    conversion is performed.
 178
 179    If CPU argument, when non NULL, specifies the processor specific
 180    address map that is to be used in the transfer. */
 181
 182
 183 EXTERN_SIM_CORE\
 184 (unsigned) sim_core_read_buffer
 185 (SIM_DESC sd,
 186  sim_cpu *cpu,
 187  unsigned map,
 188  void *buffer,
 189  address_word addr,
 190  unsigned nr_bytes);
 191
 192 EXTERN_SIM_CORE\
 193 (unsigned) sim_core_write_buffer
 194 (SIM_DESC sd,
 195  sim_cpu *cpu,
 196  unsigned map,
 197  const void *buffer,
 198  address_word addr,
 199  unsigned nr_bytes);
 200
 201
 202
 203 /* Configure the core's XOR endian transfer mode.  Only applicable
 204    when WITH_XOR_ENDIAN is enabled.
 205
 206    Targets suporting XOR endian, shall notify the core of any changes
 207    in state via this call.
 208
 209    The CPU argument, when non NULL, specifes the single processor that
 210    the xor-endian configuration is to be applied to. */
 211
 212 EXTERN_SIM_CORE\
 213 (void) sim_core_set_xor\
 214 (SIM_DESC sd,
 215  sim_cpu *cpu,
 216  int is_xor);
 217
 218
 219 /* XOR version of variable sized read/write.
 220
 221    Transfer a variable sized block of raw data between the host and
 222    target.  Should any problems occure, the number of bytes
 223    successfully transfered is returned.
 224
 225    No host/target byte endian conversion is performed.  If applicable
 226    (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
 227    performed.
 228
 229    If CPU argument, when non NULL, specifies the processor specific
 230    address map that is to be used in the transfer. */
 231
 232 EXTERN_SIM_CORE\
 233 (unsigned) sim_core_xor_read_buffer
 234 (SIM_DESC sd,
 235  sim_cpu *cpu,
 236  unsigned map,
 237  void *buffer,
 238  address_word addr,
 239  unsigned nr_bytes);
 240
 241 EXTERN_SIM_CORE\
 242 (unsigned) sim_core_xor_write_buffer
 243 (SIM_DESC sd,
 244  sim_cpu *cpu,
 245  unsigned map,
 246  const void *buffer,
 247  address_word addr,
 248  unsigned nr_bytes);
 249
 250
 251
 252 /* Fixed sized, processor oriented, read/write.
 253
 254    Transfer a fixed amout of memory between the host and target.  The
 255    data transfered is translated from/to host to/from target byte
 256    order (including xor endian).  Should the transfer fail, the
 257    operation shall abort (no return).
 258
 259    ALIGNED assumes yhat the specified ADDRESS is correctly alligned
 260    for an N byte transfer (no alignment checks are made).  Passing an
 261    incorrectly aligned ADDRESS is erroneous.
 262
 263    UNALIGNED checks/modifies the ADDRESS according to the requirements
 264    of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
 265    taken should the check fail.
 266
 267    MISSALIGNED transfers the data regardless.
 268
 269    Misaligned xor-endian accesses are broken into a sequence of
 270    transfers each <= WITH_XOR_ENDIAN bytes */
 271
 272
 273 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
 274 INLINE_SIM_CORE\
 275 (void) sim_core_write_##ALIGNMENT##_##N \
 276 (sim_cpu *cpu, \
 277  sim_cia cia, \
 278  unsigned map, \
 279  address_word addr, \
 280  unsigned_##M val);
 281
 282 DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
 283 DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
 284 DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
 285 DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
 286 DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
 287
 288 #define sim_core_write_unaligned_1 sim_core_write_aligned_1
 289 DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
 290 DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
 291 DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
 292 DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
 293
 294 DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
 295 DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
 296 DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
 297 DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
 298
 299 #define sim_core_write_1 sim_core_write_aligned_1
 300 #define sim_core_write_2 sim_core_write_aligned_2
 301 #define sim_core_write_4 sim_core_write_aligned_4
 302 #define sim_core_write_8 sim_core_write_aligned_8
 303 #define sim_core_write_16 sim_core_write_aligned_16
 304
 305 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
 306 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
 307 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
 308
 309 #undef DECLARE_SIM_CORE_WRITE_N
 310
 311
 312 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
 313 INLINE_SIM_CORE\
 314 (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
 315 (sim_cpu *cpu, \
 316  sim_cia cia, \
 317  unsigned map, \
 318  address_word addr);
 319
 320 DECLARE_SIM_CORE_READ_N(aligned,1,1)
 321 DECLARE_SIM_CORE_READ_N(aligned,2,2)
 322 DECLARE_SIM_CORE_READ_N(aligned,4,4)
 323 DECLARE_SIM_CORE_READ_N(aligned,8,8)
 324 DECLARE_SIM_CORE_READ_N(aligned,16,16)
 325
 326 #define sim_core_read_unaligned_1 sim_core_read_aligned_1
 327 DECLARE_SIM_CORE_READ_N(unaligned,2,2)
 328 DECLARE_SIM_CORE_READ_N(unaligned,4,4)
 329 DECLARE_SIM_CORE_READ_N(unaligned,8,8)
 330 DECLARE_SIM_CORE_READ_N(unaligned,16,16)
 331
 332 DECLARE_SIM_CORE_READ_N(misaligned,3,4)
 333 DECLARE_SIM_CORE_READ_N(misaligned,5,8)
 334 DECLARE_SIM_CORE_READ_N(misaligned,6,8)
 335 DECLARE_SIM_CORE_READ_N(misaligned,7,8)
 336
 337
 338 #define sim_core_read_1 sim_core_read_aligned_1
 339 #define sim_core_read_2 sim_core_read_aligned_2
 340 #define sim_core_read_4 sim_core_read_aligned_4
 341 #define sim_core_read_8 sim_core_read_aligned_8
 342 #define sim_core_read_16 sim_core_read_aligned_16
 343
 344 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
 345 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
 346 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
 347
 348 #undef DECLARE_SIM_CORE_READ_N
 349
 350
 351 #endif