sim/common/sim-core.h

   1 /* The common simulator framework for GDB, the GNU Debugger.
   2
   3    Copyright 2002-2013 Free Software Foundation, Inc.
   4
   5    Contributed by Andrew Cagney and Red Hat.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22
  23 #ifndef SIM_CORE_H
  24 #define SIM_CORE_H
  25
  26
  27 /* core signals (error conditions)
  28    Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
  29    details.  */
  30
  31 typedef enum {
  32   sim_core_unmapped_signal,
  33   sim_core_unaligned_signal,
  34   nr_sim_core_signals,
  35 } sim_core_signals;
  36
  37 /* Type of SIM_CORE_SIGNAL handler.  */
  38 typedef void (SIM_CORE_SIGNAL_FN)
  39      (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes,
  40       address_word addr, transfer_type transfer, sim_core_signals sig);
  41
  42 extern SIM_CORE_SIGNAL_FN sim_core_signal;
  43
  44
  45 /* basic types */
  46
  47 typedef struct _sim_core_mapping sim_core_mapping;
  48 struct _sim_core_mapping {
  49   /* common */
  50   int level;
  51   int space;
  52   unsigned_word base;
  53   unsigned_word bound;
  54   unsigned_word nr_bytes;
  55   unsigned mask;
  56   /* memory map */
  57   void *free_buffer;
  58   void *buffer;
  59   /* callback map */
  60 #if (WITH_HW)
  61   struct hw *device;
  62 #else
  63   device *device;
  64 #endif
  65   /* tracing */
  66   int trace;
  67   /* growth */
  68   sim_core_mapping *next;
  69 };
  70
  71 typedef struct _sim_core_map sim_core_map;
  72 struct _sim_core_map {
  73   sim_core_mapping *first;
  74 };
  75
  76
  77 typedef struct _sim_core_common {
  78   sim_core_map map[nr_maps];
  79 } sim_core_common;
  80
  81
  82 /* Main core structure */
  83
  84 typedef struct _sim_core sim_core;
  85 struct _sim_core {
  86   sim_core_common common;
  87   address_word byte_xor; /* apply xor universally */
  88 };
  89
  90
  91 /* Per CPU distributed component of the core.  At present this is
  92    mostly a clone of the global core data structure. */
  93
  94 typedef struct _sim_cpu_core {
  95   sim_core_common common;
  96   address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
  97 } sim_cpu_core;
  98
  99
 100 /* Install the "core" module.  */
 101
 102 extern SIM_RC sim_core_install (SIM_DESC sd);
 103
 104
 105
 106 /* Create a memory region within the core.
 107
 108    CPU - when non NULL, specifes the single processor that the memory
 109    space is to be attached to. (INIMPLEMENTED).
 110
 111    LEVEL - specifies the ordering of the memory region.  Lower regions
 112    are searched first.  Within a level, memory regions can not
 113    overlap.
 114
 115    MAPMASK - Bitmask specifying the memory maps that the region is to
 116    be attached to.  Typically the enums sim-basics.h:access_* are used.
 117
 118    ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is
 119    translated into ADDRESS_SPACE:OFFSET before being passed to the
 120    client device.
 121
 122    MODULO - when the simulator has been configured WITH_MODULO support
 123    and is greater than zero, specifies that accesses to the region
 124    [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
 125    .. ADDR+MODULO).  The modulo value must be a power of two.
 126
 127    DEVICE - When non NULL, indicates that this is a callback memory
 128    space and specified device's memory callback handler should be
 129    called.
 130
 131    OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for
 132    data read & written to the region.  Normally a more efficient
 133    internal structure is used.  It is assumed that buffer is allocated
 134    such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
 135    (OPTIONAL_BUFFER % 8) == (ADDR % 8)).  It is defined to be a sub-optimal
 136    hook that allows clients to do nasty things that the interface doesn't
 137    accomodate. */
 138
 139 extern void sim_core_attach
 140 (SIM_DESC sd,
 141  sim_cpu *cpu,
 142  int level,
 143  unsigned mapmask,
 144  int address_space,
 145  address_word addr,
 146  address_word nr_bytes,
 147  unsigned modulo,
 148 #if (WITH_HW)
 149  struct hw *client,
 150 #else
 151  device *client,
 152 #endif
 153  void *optional_buffer);
 154
 155
 156 /* Delete a memory section within the core.
 157
 158  */
 159
 160 extern void sim_core_detach
 161 (SIM_DESC sd,
 162  sim_cpu *cpu,
 163  int level,
 164  int address_space,
 165  address_word addr);
 166
 167
 168 /* Variable sized read/write
 169
 170    Transfer a variable sized block of raw data between the host and
 171    target.  Should any problems occur, the number of bytes
 172    successfully transfered is returned.
 173
 174    No host/target byte endian conversion is performed.  No xor-endian
 175    conversion is performed.
 176
 177    If CPU argument, when non NULL, specifies the processor specific
 178    address map that is to be used in the transfer. */
 179
 180
 181 extern unsigned sim_core_read_buffer
 182 (SIM_DESC sd,
 183  sim_cpu *cpu,
 184  unsigned map,
 185  void *buffer,
 186  address_word addr,
 187  unsigned nr_bytes);
 188
 189 extern unsigned sim_core_write_buffer
 190 (SIM_DESC sd,
 191  sim_cpu *cpu,
 192  unsigned map,
 193  const void *buffer,
 194  address_word addr,
 195  unsigned nr_bytes);
 196
 197
 198
 199 /* Configure the core's XOR endian transfer mode.  Only applicable
 200    when WITH_XOR_ENDIAN is enabled.
 201
 202    Targets suporting XOR endian, shall notify the core of any changes
 203    in state via this call.
 204
 205    The CPU argument, when non NULL, specifes the single processor that
 206    the xor-endian configuration is to be applied to. */
 207
 208 extern void sim_core_set_xor
 209 (SIM_DESC sd,
 210  sim_cpu *cpu,
 211  int is_xor);
 212
 213
 214 /* XOR version of variable sized read/write.
 215
 216    Transfer a variable sized block of raw data between the host and
 217    target.  Should any problems occur, the number of bytes
 218    successfully transfered is returned.
 219
 220    No host/target byte endian conversion is performed.  If applicable
 221    (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
 222    performed.
 223
 224    If CPU argument, when non NULL, specifies the processor specific
 225    address map that is to be used in the transfer. */
 226
 227 extern unsigned sim_core_xor_read_buffer
 228 (SIM_DESC sd,
 229  sim_cpu *cpu,
 230  unsigned map,
 231  void *buffer,
 232  address_word addr,
 233  unsigned nr_bytes);
 234
 235 extern unsigned sim_core_xor_write_buffer
 236 (SIM_DESC sd,
 237  sim_cpu *cpu,
 238  unsigned map,
 239  const void *buffer,
 240  address_word addr,
 241  unsigned nr_bytes);
 242
 243
 244 /* Translate an address based on a map.  */
 245
 246 extern void *sim_core_trans_addr
 247 (SIM_DESC sd,
 248  sim_cpu *cpu,
 249  unsigned map,
 250  address_word addr);
 251
 252
 253 /* Fixed sized, processor oriented, read/write.
 254
 255    Transfer a fixed amout of memory between the host and target.  The
 256    data transfered is translated from/to host to/from target byte
 257    order (including xor endian).  Should the transfer fail, the
 258    operation shall abort (no return).
 259
 260    ALIGNED assumes yhat the specified ADDRESS is correctly alligned
 261    for an N byte transfer (no alignment checks are made).  Passing an
 262    incorrectly aligned ADDRESS is erroneous.
 263
 264    UNALIGNED checks/modifies the ADDRESS according to the requirements
 265    of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
 266    taken should the check fail.
 267
 268    MISSALIGNED transfers the data regardless.
 269
 270    Misaligned xor-endian accesses are broken into a sequence of
 271    transfers each <= WITH_XOR_ENDIAN bytes */
 272
 273
 274 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
 275 INLINE_SIM_CORE\
 276 (void) sim_core_write_##ALIGNMENT##_##N \
 277 (sim_cpu *cpu, \
 278  sim_cia cia, \
 279  unsigned map, \
 280  address_word addr, \
 281  unsigned_##M val);
 282
 283 DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
 284 DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
 285 DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
 286 DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
 287 DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
 288
 289 #define sim_core_write_unaligned_1 sim_core_write_aligned_1
 290 DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
 291 DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
 292 DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
 293 DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
 294
 295 DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
 296 DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
 297 DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
 298 DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
 299
 300 #define sim_core_write_1 sim_core_write_aligned_1
 301 #define sim_core_write_2 sim_core_write_aligned_2
 302 #define sim_core_write_4 sim_core_write_aligned_4
 303 #define sim_core_write_8 sim_core_write_aligned_8
 304 #define sim_core_write_16 sim_core_write_aligned_16
 305
 306 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
 307 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
 308 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
 309
 310 #undef DECLARE_SIM_CORE_WRITE_N
 311
 312
 313 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
 314 INLINE_SIM_CORE\
 315 (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
 316 (sim_cpu *cpu, \
 317  sim_cia cia, \
 318  unsigned map, \
 319  address_word addr);
 320
 321 DECLARE_SIM_CORE_READ_N(aligned,1,1)
 322 DECLARE_SIM_CORE_READ_N(aligned,2,2)
 323 DECLARE_SIM_CORE_READ_N(aligned,4,4)
 324 DECLARE_SIM_CORE_READ_N(aligned,8,8)
 325 DECLARE_SIM_CORE_READ_N(aligned,16,16)
 326
 327 #define sim_core_read_unaligned_1 sim_core_read_aligned_1
 328 DECLARE_SIM_CORE_READ_N(unaligned,2,2)
 329 DECLARE_SIM_CORE_READ_N(unaligned,4,4)
 330 DECLARE_SIM_CORE_READ_N(unaligned,8,8)
 331 DECLARE_SIM_CORE_READ_N(unaligned,16,16)
 332
 333 DECLARE_SIM_CORE_READ_N(misaligned,3,4)
 334 DECLARE_SIM_CORE_READ_N(misaligned,5,8)
 335 DECLARE_SIM_CORE_READ_N(misaligned,6,8)
 336 DECLARE_SIM_CORE_READ_N(misaligned,7,8)
 337
 338
 339 #define sim_core_read_1 sim_core_read_aligned_1
 340 #define sim_core_read_2 sim_core_read_aligned_2
 341 #define sim_core_read_4 sim_core_read_aligned_4
 342 #define sim_core_read_8 sim_core_read_aligned_8
 343 #define sim_core_read_16 sim_core_read_aligned_16
 344
 345 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
 346 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
 347 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
 348
 349 #undef DECLARE_SIM_CORE_READ_N
 350
 351
 352 #if (WITH_DEVICES)
 353 /* TODO: create sim/common/device.h */
 354 /* These are defined with each particular cpu.  */
 355 void device_error (device *me, const char *message, ...) __attribute__((format (printf, 2, 3)));
 356 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
 357 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
 358 #endif
 359
 360
 361 #endif