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1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2024 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 /* This must come before any other includes. */
21 #include "defs.h"
22
23 #include <signal.h>
24 #include <errno.h>
25 #include <sys/types.h>
26 #include <sys/stat.h>
27 #include <unistd.h>
28 #include <string.h>
29 #include <time.h>
30 #include <sys/time.h>
31
32 #include "bfd.h"
33
34 #include "sim-main.h"
35 #include "sim-signal.h"
36 #include "simops.h"
37 #include "target-newlib-syscall.h"
38
39 #include "cr16-sim.h"
40
41 #ifdef HAVE_UTIME_H
42 #include <utime.h>
43 #endif
44 #include <sys/wait.h>
45
46 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
47
48 enum op_types {
49 OP_VOID,
50 OP_CONSTANT3,
51 OP_UCONSTANT3,
52 OP_CONSTANT4,
53 OP_CONSTANT4_1,
54 OP_CONSTANT5,
55 OP_CONSTANT6,
56 OP_CONSTANT16,
57 OP_UCONSTANT16,
58 OP_CONSTANT20,
59 OP_UCONSTANT20,
60 OP_CONSTANT32,
61 OP_UCONSTANT32,
62 OP_MEMREF,
63 OP_MEMREF2,
64 OP_MEMREF3,
65
66 OP_DISP5,
67 OP_DISP17,
68 OP_DISP25,
69 OP_DISPE9,
70 //OP_ABS20,
71 OP_ABS20_OUTPUT,
72 //OP_ABS24,
73 OP_ABS24_OUTPUT,
74
75 OP_R_BASE_DISPS16,
76 OP_R_BASE_DISP20,
77 OP_R_BASE_DISPS20,
78 OP_R_BASE_DISPE20,
79
80 OP_RP_BASE_DISPE0,
81 OP_RP_BASE_DISP4,
82 OP_RP_BASE_DISPE4,
83 OP_RP_BASE_DISP14,
84 OP_RP_BASE_DISP16,
85 OP_RP_BASE_DISP20,
86 OP_RP_BASE_DISPS20,
87 OP_RP_BASE_DISPE20,
88
89 OP_R_INDEX7_ABS20,
90 OP_R_INDEX8_ABS20,
91
92 OP_RP_INDEX_DISP0,
93 OP_RP_INDEX_DISP14,
94 OP_RP_INDEX_DISP20,
95 OP_RP_INDEX_DISPS20,
96
97 OP_REG,
98 OP_REGP,
99 OP_PROC_REG,
100 OP_PROC_REGP,
101 OP_COND,
102 OP_RA
103 };
104
105
106 enum {
107 PSR_MASK = (PSR_I_BIT
108 | PSR_P_BIT
109 | PSR_E_BIT
110 | PSR_N_BIT
111 | PSR_Z_BIT
112 | PSR_F_BIT
113 | PSR_U_BIT
114 | PSR_L_BIT
115 | PSR_T_BIT
116 | PSR_C_BIT),
117 /* The following bits in the PSR _can't_ be set by instructions such
118 as mvtc. */
119 PSR_HW_MASK = (PSR_MASK)
120 };
121
122 /* cond Code Condition True State
123 * EQ Equal Z flag is 1
124 * NE Not Equal Z flag is 0
125 * CS Carry Set C flag is 1
126 * CC Carry Clear C flag is 0
127 * HI Higher L flag is 1
128 * LS Lower or Same L flag is 0
129 * GT Greater Than N flag is 1
130 * LE Less Than or Equal To N flag is 0
131 * FS Flag Set F flag is 1
132 * FC Flag Clear F flag is 0
133 * LO Lower Z and L flags are 0
134 * HS Higher or Same Z or L flag is 1
135 * LT Less Than Z and N flags are 0
136 * GE Greater Than or Equal To Z or N flag is 1. */
137
138 static int cond_stat(int cond)
139 {
140 switch (cond)
141 {
142 case 0: return PSR_Z; break;
143 case 1: return !PSR_Z; break;
144 case 2: return PSR_C; break;
145 case 3: return !PSR_C; break;
146 case 4: return PSR_L; break;
147 case 5: return !PSR_L; break;
148 case 6: return PSR_N; break;
149 case 7: return !PSR_N; break;
150 case 8: return PSR_F; break;
151 case 9: return !PSR_F; break;
152 case 10: return !PSR_Z && !PSR_L; break;
153 case 11: return PSR_Z || PSR_L; break;
154 case 12: return !PSR_Z && !PSR_N; break;
155 case 13: return PSR_Z || PSR_N; break;
156 case 14: return 1; break; /*ALWAYS. */
157 default:
158 // case NEVER: return false; break;
159 //case NO_COND_CODE:
160 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
161 return 0; break;
162 }
163 return 0;
164 }
165
166
167 creg_t
168 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
169 {
170 /* A MASK bit is set when the corresponding bit in the CR should
171 be left alone. */
172 /* This assumes that (VAL & MASK) == 0. */
173 switch (cr)
174 {
175 case PSR_CR:
176 if (psw_hw_p)
177 val &= PSR_HW_MASK;
178 #if 0
179 else
180 val &= PSR_MASK;
181 sim_io_printf
182 (sd,
183 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
184 EXCEPTION (SIM_SIGILL);
185 #endif
186 /* keep an up-to-date psw around for tracing. */
187 State.trace.psw = (State.trace.psw & mask) | val;
188 break;
189 default:
190 break;
191 }
192 /* only issue an update if the register is being changed. */
193 if ((State.cregs[cr] & ~mask) != val)
194 SLOT_PEND_MASK (State.cregs[cr], mask, val);
195
196 return val;
197 }
198
199 #ifdef DEBUG
200 static void trace_input_func (SIM_DESC sd,
201 const char *name,
202 enum op_types in1,
203 enum op_types in2,
204 enum op_types in3);
205
206 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
207
208 #ifndef SIZE_INSTRUCTION
209 #define SIZE_INSTRUCTION 8
210 #endif
211
212 #ifndef SIZE_OPERANDS
213 #define SIZE_OPERANDS 18
214 #endif
215
216 #ifndef SIZE_VALUES
217 #define SIZE_VALUES 13
218 #endif
219
220 #ifndef SIZE_LOCATION
221 #define SIZE_LOCATION 20
222 #endif
223
224 #ifndef SIZE_PC
225 #define SIZE_PC 4
226 #endif
227
228 #ifndef SIZE_LINE_NUMBER
229 #define SIZE_LINE_NUMBER 2
230 #endif
231
232 static void
233 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
234 {
235 char *comma;
236 enum op_types in[3];
237 int i;
238 char buf[1024];
239 char *p;
240 long tmp;
241 char *type;
242 const char *filename;
243 const char *functionname;
244 unsigned int linenumber;
245 bfd_vma byte_pc;
246
247 if ((cr16_debug & DEBUG_TRACE) == 0)
248 return;
249
250 switch (State.ins_type)
251 {
252 default:
253 case INS_UNKNOWN: type = " ?"; break;
254 }
255
256 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
257 sim_io_printf (sd,
258 "0x%.*x %s: %-*s ",
259 SIZE_PC, (unsigned)PC,
260 type,
261 SIZE_INSTRUCTION, name);
262
263 else
264 {
265 buf[0] = '\0';
266 byte_pc = PC;
267 if (STATE_TEXT_SECTION (sd)
268 && byte_pc >= STATE_TEXT_START (sd)
269 && byte_pc < STATE_TEXT_END (sd))
270 {
271 filename = (const char *)0;
272 functionname = (const char *)0;
273 linenumber = 0;
274 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
275 STATE_TEXT_SECTION (sd),
276 (struct bfd_symbol **)0,
277 byte_pc - STATE_TEXT_START (sd),
278 &filename, &functionname, &linenumber))
279 {
280 p = buf;
281 if (linenumber)
282 {
283 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
284 p += strlen (p);
285 }
286 else
287 {
288 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
289 p += SIZE_LINE_NUMBER+2;
290 }
291
292 if (functionname)
293 {
294 sprintf (p, "%s ", functionname);
295 p += strlen (p);
296 }
297 else if (filename)
298 {
299 char *q = strrchr (filename, '/');
300 sprintf (p, "%s ", (q) ? q+1 : filename);
301 p += strlen (p);
302 }
303
304 if (*p == ' ')
305 *p = '\0';
306 }
307 }
308
309 sim_io_printf (sd,
310 "0x%.*x %s: %-*.*s %-*s ",
311 SIZE_PC, (unsigned)PC,
312 type,
313 SIZE_LOCATION, SIZE_LOCATION, buf,
314 SIZE_INSTRUCTION, name);
315 }
316
317 in[0] = in1;
318 in[1] = in2;
319 in[2] = in3;
320 comma = "";
321 p = buf;
322 for (i = 0; i < 3; i++)
323 {
324 switch (in[i])
325 {
326 case OP_VOID:
327 break;
328
329 case OP_REG:
330 case OP_REGP:
331 sprintf (p, "%sr%d", comma, OP[i]);
332 p += strlen (p);
333 comma = ",";
334 break;
335
336 case OP_PROC_REG:
337 sprintf (p, "%scr%d", comma, OP[i]);
338 p += strlen (p);
339 comma = ",";
340 break;
341
342 case OP_CONSTANT16:
343 sprintf (p, "%s%d", comma, OP[i]);
344 p += strlen (p);
345 comma = ",";
346 break;
347
348 case OP_CONSTANT4:
349 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
350 p += strlen (p);
351 comma = ",";
352 break;
353
354 case OP_CONSTANT3:
355 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
356 p += strlen (p);
357 comma = ",";
358 break;
359
360 case OP_MEMREF:
361 sprintf (p, "%s@r%d", comma, OP[i]);
362 p += strlen (p);
363 comma = ",";
364 break;
365
366 case OP_MEMREF2:
367 sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]);
368 p += strlen (p);
369 comma = ",";
370 break;
371
372 case OP_MEMREF3:
373 sprintf (p, "%s@%d", comma, OP[i]);
374 p += strlen (p);
375 comma = ",";
376 break;
377 }
378 }
379
380 if ((cr16_debug & DEBUG_VALUES) == 0)
381 {
382 *p++ = '\n';
383 *p = '\0';
384 sim_io_printf (sd, "%s", buf);
385 }
386 else
387 {
388 *p = '\0';
389 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
390
391 p = buf;
392 for (i = 0; i < 3; i++)
393 {
394 buf[0] = '\0';
395 switch (in[i])
396 {
397 case OP_VOID:
398 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
399 break;
400
401 case OP_REG:
402 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
403 (uint16_t) GPR (OP[i]));
404 break;
405
406 case OP_REGP:
407 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1)));
408 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
409 break;
410
411 case OP_PROC_REG:
412 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16_t) CREG (OP[i]));
414 break;
415
416 case OP_CONSTANT16:
417 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16_t)OP[i]);
419 break;
420
421 case OP_CONSTANT4:
422 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
423 (uint16_t)SEXT4(OP[i]));
424 break;
425
426 case OP_CONSTANT3:
427 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
428 (uint16_t)SEXT3(OP[i]));
429 break;
430
431 case OP_MEMREF2:
432 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
433 (uint16_t)OP[i]);
434 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
435 (uint16_t)GPR (OP[i + 1]));
436 i++;
437 break;
438 }
439 }
440 }
441
442 sim_io_flush_stdout (sd);
443 }
444
445 static void
446 do_trace_output_flush (SIM_DESC sd)
447 {
448 sim_io_flush_stdout (sd);
449 }
450
451 static void
452 do_trace_output_finish (SIM_DESC sd)
453 {
454 sim_io_printf (sd,
455 " F0=%d F1=%d C=%d\n",
456 (State.trace.psw & PSR_F_BIT) != 0,
457 (State.trace.psw & PSR_F_BIT) != 0,
458 (State.trace.psw & PSR_C_BIT) != 0);
459 sim_io_flush_stdout (sd);
460 }
461
462 #if 0
463 static void
464 trace_output_40 (SIM_DESC sd, uint64_t val)
465 {
466 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
467 {
468 sim_io_printf (sd,
469 " :: %*s0x%.2x%.8lx",
470 SIZE_VALUES - 12,
471 "",
472 ((int)(val >> 32) & 0xff),
473 ((unsigned long) val) & 0xffffffff);
474 do_trace_output_finish ();
475 }
476 }
477 #endif
478
479 static void
480 trace_output_32 (SIM_DESC sd, uint32_t val)
481 {
482 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
483 {
484 sim_io_printf (sd,
485 " :: %*s0x%.8x",
486 SIZE_VALUES - 10,
487 "",
488 (int) val);
489 do_trace_output_finish (sd);
490 }
491 }
492
493 static void
494 trace_output_16 (SIM_DESC sd, uint16_t val)
495 {
496 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
497 {
498 sim_io_printf (sd,
499 " :: %*s0x%.4x",
500 SIZE_VALUES - 6,
501 "",
502 (int) val);
503 do_trace_output_finish (sd);
504 }
505 }
506
507 static void
508 trace_output_void (SIM_DESC sd)
509 {
510 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
511 {
512 sim_io_printf (sd, "\n");
513 do_trace_output_flush (sd);
514 }
515 }
516
517 static void
518 trace_output_flag (SIM_DESC sd)
519 {
520 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
521 {
522 sim_io_printf (sd,
523 " :: %*s",
524 SIZE_VALUES,
525 "");
526 do_trace_output_finish (sd);
527 }
528 }
529
530
531
532
533 #else
534 #define trace_input(NAME, IN1, IN2, IN3)
535 #define trace_output(RESULT)
536 #endif
537
538 /* addub. */
539 void
540 OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
541 {
542 uint8_t tmp;
543 uint8_t a = OP[0] & 0xff;
544 uint16_t b = (GPR (OP[1])) & 0xff;
545 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
546 tmp = (a + b) & 0xff;
547 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
548 trace_output_16 (sd, tmp);
549 }
550
551 /* addub. */
552 void
553 OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
554 {
555 uint16_t tmp;
556 uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
557 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
558 tmp = (a + b) & 0xff;
559 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
560 trace_output_16 (sd, tmp);
561 }
562
563 /* addub. */
564 void
565 OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
566 {
567 uint8_t a = (GPR (OP[0])) & 0xff;
568 uint8_t b = (GPR (OP[1])) & 0xff;
569 uint16_t tmp = (a + b) & 0xff;
570 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
571 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
572 trace_output_16 (sd, tmp);
573 }
574
575 /* adduw. */
576 void
577 OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
578 {
579 uint16_t a = OP[0];
580 uint16_t b = GPR (OP[1]);
581 uint16_t tmp = (a + b);
582 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
583 SET_GPR (OP[1], tmp);
584 trace_output_16 (sd, tmp);
585 }
586
587 /* adduw. */
588 void
589 OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
590 {
591 uint16_t a = OP[0];
592 uint16_t b = GPR (OP[1]);
593 uint16_t tmp = (a + b);
594 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
595 SET_GPR (OP[1], tmp);
596 trace_output_16 (sd, tmp);
597 }
598
599 /* adduw. */
600 void
601 OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
602 {
603 uint16_t a = GPR (OP[0]);
604 uint16_t b = GPR (OP[1]);
605 uint16_t tmp = (a + b);
606 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
607 SET_GPR (OP[1], tmp);
608 trace_output_16 (sd, tmp);
609 }
610
611 /* addb. */
612 void
613 OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
614 {
615 uint8_t a = OP[0];
616 uint8_t b = (GPR (OP[1]) & 0xff);
617 uint16_t tmp = (a + b) & 0xff;
618 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
619 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
620 SET_PSR_C (tmp > 0xFF);
621 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
622 trace_output_16 (sd, tmp);
623 }
624
625 /* addb. */
626 void
627 OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
628 {
629 uint8_t a = (OP[0]) & 0xff;
630 uint8_t b = (GPR (OP[1]) & 0xff);
631 uint16_t tmp = (a + b) & 0xff;
632 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
633 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
634 SET_PSR_C (tmp > 0xFF);
635 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
636 trace_output_16 (sd, tmp);
637 }
638
639 /* addb. */
640 void
641 OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
642 {
643 uint8_t a = (GPR (OP[0]) & 0xff);
644 uint8_t b = (GPR (OP[1]) & 0xff);
645 uint16_t tmp = (a + b) & 0xff;
646 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
647 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
648 SET_PSR_C (tmp > 0xFF);
649 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
650 trace_output_16 (sd, tmp);
651 }
652
653 /* addw. */
654 void
655 OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
656 {
657 int16_t a = OP[0];
658 uint16_t tmp, b = GPR (OP[1]);
659 tmp = (a + b);
660 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
661 SET_GPR (OP[1], tmp);
662 SET_PSR_C (tmp > 0xFFFF);
663 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
664 trace_output_16 (sd, tmp);
665 }
666
667 /* addw. */
668 void
669 OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
670 {
671 int16_t a = OP[0];
672 uint16_t tmp, b = GPR (OP[1]);
673 tmp = (a + b);
674 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
675 SET_GPR (OP[1], tmp);
676 SET_PSR_C (tmp > 0xFFFF);
677 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
678 trace_output_16 (sd, tmp);
679 }
680
681 /* addw. */
682 void
683 OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
684 {
685 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
686 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
687 tmp = (a + b);
688 SET_GPR (OP[1], tmp);
689 SET_PSR_C (tmp > 0xFFFF);
690 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
691 trace_output_16 (sd, tmp);
692 }
693
694 /* addcb. */
695 void
696 OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
697 {
698 uint8_t tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
699 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
700 tmp = (a + b + PSR_C) & 0xff;
701 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
702 SET_PSR_C (tmp > 0xFF);
703 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
704 trace_output_16 (sd, tmp);
705 }
706
707 /* addcb. */
708 void
709 OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
710 {
711 int8_t a = OP[0] & 0xff;
712 uint8_t b = (GPR (OP[1])) & 0xff;
713 uint8_t tmp = (a + b + PSR_C) & 0xff;
714 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
715 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
716 SET_PSR_C (tmp > 0xFF);
717 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
718 trace_output_16 (sd, tmp);
719 }
720
721 /* addcb. */
722 void
723 OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
724 {
725 uint8_t a = (GPR (OP[0])) & 0xff;
726 uint8_t b = (GPR (OP[1])) & 0xff;
727 uint8_t tmp = (a + b + PSR_C) & 0xff;
728 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
729 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
730 SET_PSR_C (tmp > 0xFF);
731 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
732 trace_output_16 (sd, tmp);
733 }
734
735 /* addcw. */
736 void
737 OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
738 {
739 uint16_t a = OP[0];
740 uint16_t b = GPR (OP[1]);
741 uint16_t tmp = (a + b + PSR_C);
742 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
743 SET_GPR (OP[1], tmp);
744 SET_PSR_C (tmp > 0xFFFF);
745 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
746 trace_output_16 (sd, tmp);
747 }
748
749 /* addcw. */
750 void
751 OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
752 {
753 int16_t a = OP[0];
754 uint16_t b = GPR (OP[1]);
755 uint16_t tmp = (a + b + PSR_C);
756 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
757 SET_GPR (OP[1], tmp);
758 SET_PSR_C (tmp > 0xFFFF);
759 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
760 trace_output_16 (sd, tmp);
761 }
762
763 /* addcw. */
764 void
765 OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
766 {
767 uint16_t a = GPR (OP[1]);
768 uint16_t b = GPR (OP[1]);
769 uint16_t tmp = (a + b + PSR_C);
770 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
771 SET_GPR (OP[1], tmp);
772 SET_PSR_C (tmp > 0xFFFF);
773 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
774 trace_output_16 (sd, tmp);
775 }
776
777 /* addd. */
778 void
779 OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
780 {
781 int16_t a = (OP[0]);
782 uint32_t b = GPR32 (OP[1]);
783 uint32_t tmp = (a + b);
784 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
785 SET_GPR32 (OP[1], tmp);
786 SET_PSR_C (tmp > 0xFFFFFFFF);
787 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
788 trace_output_32 (sd, tmp);
789 }
790
791 /* addd. */
792 void
793 OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
794 {
795 int32_t a = (SEXT16(OP[0]));
796 uint32_t b = GPR32 (OP[1]);
797 uint32_t tmp = (a + b);
798 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
799 SET_GPR32 (OP[1], tmp);
800 SET_PSR_C (tmp > 0xFFFFFFFF);
801 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
802 trace_output_32 (sd, tmp);
803 }
804
805 /* addd. */
806 void
807 OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
808 {
809 uint32_t a = GPR32 (OP[0]);
810 uint32_t b = GPR32 (OP[1]);
811 uint32_t tmp = (a + b);
812 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
813 SET_GPR32 (OP[1], tmp);
814 trace_output_32 (sd, tmp);
815 SET_PSR_C (tmp > 0xFFFFFFFF);
816 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
817 }
818
819 /* addd. */
820 void
821 OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
822 {
823 uint32_t a = OP[0];
824 uint32_t b = GPR32 (OP[1]);
825 uint32_t tmp;
826 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
827 tmp = (a + b);
828 SET_GPR32 (OP[1], tmp);
829 SET_PSR_C (tmp > 0xFFFFFFFF);
830 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
831 trace_output_32 (sd, tmp);
832 }
833
834 /* addd. */
835 void
836 OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
837 {
838 int32_t a = OP[0];
839 uint32_t b = GPR32 (OP[1]);
840 uint32_t tmp;
841 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
842 tmp = (a + b);
843 SET_GPR32 (OP[1], tmp);
844 SET_PSR_C (tmp > 0xFFFFFFFF);
845 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
846 trace_output_32 (sd, tmp);
847 }
848
849 /* andb. */
850 void
851 OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
852 {
853 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
854 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
855 tmp = a & b;
856 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
857 trace_output_16 (sd, tmp);
858 }
859
860 /* andb. */
861 void
862 OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
863 {
864 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
865 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
866 tmp = a & b;
867 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
868 trace_output_16 (sd, tmp);
869 }
870
871 /* andb. */
872 void
873 OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
874 {
875 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
876 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
877 tmp = a & b;
878 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
879 trace_output_16 (sd, tmp);
880 }
881
882 /* andw. */
883 void
884 OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
885 {
886 uint16_t tmp, a = OP[0], b = GPR (OP[1]);
887 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
888 tmp = a & b;
889 SET_GPR (OP[1], tmp);
890 trace_output_16 (sd, tmp);
891 }
892
893 /* andw. */
894 void
895 OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
896 {
897 uint16_t tmp, a = OP[0], b = GPR (OP[1]);
898 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
899 tmp = a & b;
900 SET_GPR (OP[1], tmp);
901 trace_output_16 (sd, tmp);
902 }
903
904 /* andw. */
905 void
906 OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
907 {
908 uint16_t tmp, a = GPR (OP[0]), b = GPR (OP[1]);
909 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
910 tmp = a & b;
911 SET_GPR (OP[1], tmp);
912 trace_output_16 (sd, tmp);
913 }
914
915 /* andd. */
916 void
917 OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
918 {
919 uint32_t tmp, a = OP[0], b = GPR32 (OP[1]);
920 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
921 tmp = a & b;
922 SET_GPR32 (OP[1], tmp);
923 trace_output_32 (sd, tmp);
924 }
925
926 /* andd. */
927 void
928 OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
929 {
930 uint32_t tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
931 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
932 tmp = a & b;
933 SET_GPR32 (OP[1], tmp);
934 trace_output_32 (sd, tmp);
935 }
936
937 /* ord. */
938 void
939 OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
940 {
941 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
942 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
943 tmp = a | b;
944 SET_GPR32 (OP[1], tmp);
945 trace_output_32 (sd, tmp);
946 }
947
948 /* ord. */
949 void
950 OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
951 {
952 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
953 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
954 tmp = a | b;
955 SET_GPR32 (OP[1], tmp);
956 trace_output_32 (sd, tmp);
957 }
958
959 /* xord. */
960 void
961 OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
962 {
963 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]);
964 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
965 tmp = a ^ b;
966 SET_GPR32 (OP[1], tmp);
967 trace_output_32 (sd, tmp);
968 }
969
970 /* xord. */
971 void
972 OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
973 {
974 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
975 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
976 tmp = a ^ b;
977 SET_GPR32 (OP[1], tmp);
978 trace_output_32 (sd, tmp);
979 }
980
981
982 /* b. */
983 void
984 OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
985 {
986 uint32_t tmp = 0, cond = cond_stat (OP[0]);
987 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
988 if (cond)
989 {
990 if (sign_flag)
991 tmp = (PC - (OP[1]));
992 else
993 tmp = (PC + (OP[1]));
994 /* If the resulting PC value is less than 0x00_0000 or greater
995 than 0xFF_FFFF, this instruction causes an IAD trap.*/
996
997 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
998 {
999 trace_output_void (sd);
1000 EXCEPTION (SIM_SIGBUS);
1001 }
1002 else
1003 JMP (tmp);
1004 }
1005 sign_flag = 0; /* Reset sign_flag. */
1006 trace_output_32 (sd, tmp);
1007 }
1008
1009 /* b. */
1010 void
1011 OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
1012 {
1013 uint32_t tmp = 0, cond = cond_stat (OP[0]);
1014 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1015 if (cond)
1016 {
1017 if (sign_flag)
1018 tmp = (PC - OP[1]);
1019 else
1020 tmp = (PC + OP[1]);
1021 /* If the resulting PC value is less than 0x00_0000 or greater
1022 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1023
1024 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1025 {
1026 trace_output_void (sd);
1027 EXCEPTION (SIM_SIGBUS);
1028 }
1029 else
1030 JMP (tmp);
1031 }
1032 sign_flag = 0; /* Reset sign_flag. */
1033 trace_output_32 (sd, tmp);
1034 }
1035
1036 /* b. */
1037 void
1038 OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
1039 {
1040 uint32_t tmp = 0, cond = cond_stat (OP[0]);
1041 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1042 if (cond)
1043 {
1044 if (sign_flag)
1045 tmp = (PC - (OP[1]));
1046 else
1047 tmp = (PC + (OP[1]));
1048 /* If the resulting PC value is less than 0x00_0000 or greater
1049 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1050
1051 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1052 {
1053 trace_output_void (sd);
1054 EXCEPTION (SIM_SIGBUS);
1055 }
1056 else
1057 JMP (tmp);
1058 }
1059 sign_flag = 0; /* Reset sign_flag. */
1060 trace_output_32 (sd, tmp);
1061 }
1062
1063 /* bal. */
1064 void
1065 OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
1066 {
1067 uint32_t tmp;
1068 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1069 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1070 SET_GPR32 (14, tmp);
1071 if (sign_flag)
1072 tmp = (PC - (OP[1]));
1073 else
1074 tmp = (PC + (OP[1]));
1075
1076 /* If the resulting PC value is less than 0x00_0000 or greater
1077 than 0xFF_FFFF, this instruction causes an IAD trap. */
1078
1079 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1080 {
1081 trace_output_void (sd);
1082 EXCEPTION (SIM_SIGBUS);
1083 }
1084 else
1085 JMP (tmp);
1086 sign_flag = 0; /* Reset sign_flag. */
1087 trace_output_32 (sd, tmp);
1088 }
1089
1090
1091 /* bal. */
1092 void
1093 OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
1094 {
1095 uint32_t tmp;
1096 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1097 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1098 SET_GPR32 (OP[0], tmp);
1099 if (sign_flag)
1100 tmp = ((PC) - (OP[1]));
1101 else
1102 tmp = ((PC) + (OP[1]));
1103 /* If the resulting PC value is less than 0x00_0000 or greater
1104 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1105
1106 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1107 {
1108 trace_output_void (sd);
1109 EXCEPTION (SIM_SIGBUS);
1110 }
1111 else
1112 JMP (tmp);
1113 sign_flag = 0; /* Reset sign_flag. */
1114 trace_output_32 (sd, tmp);
1115 }
1116
1117 /* jal. */
1118 void
1119 OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
1120 {
1121 uint32_t tmp;
1122 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1123 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1124 tmp = GPR32 (OP[1]);
1125 tmp = SEXT24(tmp << 1);
1126 /* If the resulting PC value is less than 0x00_0000 or greater
1127 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1128
1129 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1130 {
1131 trace_output_void (sd);
1132 EXCEPTION (SIM_SIGBUS);
1133 }
1134 else
1135 JMP (tmp);
1136
1137 trace_output_32 (sd, tmp);
1138 }
1139
1140
1141 /* jal. */
1142 void
1143 OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
1144 {
1145 uint32_t tmp;
1146 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1147 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1148 tmp = GPR32 (OP[0]);
1149 tmp = SEXT24(tmp << 1);
1150 /* If the resulting PC value is less than 0x00_0000 or greater
1151 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1152
1153 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1154 {
1155 trace_output_void (sd);
1156 EXCEPTION (SIM_SIGBUS);
1157 }
1158 else
1159 JMP (tmp);
1160
1161 trace_output_32 (sd, tmp);
1162 }
1163
1164
1165 /* beq0b. */
1166 void
1167 OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
1168 {
1169 uint32_t addr;
1170 uint8_t a = (GPR (OP[0]) & 0xFF);
1171 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1172 addr = OP[1];
1173 if (a == 0)
1174 {
1175 if (sign_flag)
1176 addr = (PC - OP[1]);
1177 else
1178 addr = (PC + OP[1]);
1179
1180 JMP (addr);
1181 }
1182 sign_flag = 0; /* Reset sign_flag. */
1183 trace_output_void (sd);
1184 }
1185
1186 /* bne0b. */
1187 void
1188 OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
1189 {
1190 uint32_t addr;
1191 uint8_t a = (GPR (OP[0]) & 0xFF);
1192 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1193 addr = OP[1];
1194 if (a != 0)
1195 {
1196 if (sign_flag)
1197 addr = (PC - OP[1]);
1198 else
1199 addr = (PC + OP[1]);
1200
1201 JMP (addr);
1202 }
1203 sign_flag = 0; /* Reset sign_flag. */
1204 trace_output_void (sd);
1205 }
1206
1207 /* beq0w. */
1208 void
1209 OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
1210 {
1211 uint32_t addr;
1212 uint16_t a = GPR (OP[0]);
1213 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1214 addr = OP[1];
1215 if (a == 0)
1216 {
1217 if (sign_flag)
1218 addr = (PC - OP[1]);
1219 else
1220 addr = (PC + OP[1]);
1221
1222 JMP (addr);
1223 }
1224 sign_flag = 0; /* Reset sign_flag. */
1225 trace_output_void (sd);
1226 }
1227
1228 /* bne0w. */
1229 void
1230 OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
1231 {
1232 uint32_t addr;
1233 uint16_t a = GPR (OP[0]);
1234 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1235 addr = OP[1];
1236 if (a != 0)
1237 {
1238 if (sign_flag)
1239 addr = (PC - OP[1]);
1240 else
1241 addr = (PC + OP[1]);
1242
1243 JMP (addr);
1244 }
1245 sign_flag = 0; /* Reset sign_flag. */
1246 trace_output_void (sd);
1247 }
1248
1249
1250 /* jeq. */
1251 void
1252 OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
1253 {
1254 uint32_t tmp = 0;
1255 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1256 if ((PSR_Z) == 1)
1257 {
1258 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1259 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1260 }
1261 trace_output_32 (sd, tmp);
1262 }
1263
1264 /* jne. */
1265 void
1266 OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
1267 {
1268 uint32_t tmp = 0;
1269 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1270 if ((PSR_Z) == 0)
1271 {
1272 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1273 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1274 }
1275 trace_output_32 (sd, tmp);
1276 }
1277
1278 /* jcs. */
1279 void
1280 OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
1281 {
1282 uint32_t tmp = 0;
1283 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1284 if ((PSR_C) == 1)
1285 {
1286 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1287 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1288 }
1289 trace_output_32 (sd, tmp);
1290 }
1291
1292 /* jcc. */
1293 void
1294 OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
1295 {
1296 uint32_t tmp = 0;
1297 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1298 if ((PSR_C) == 0)
1299 {
1300 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1301 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1302 }
1303 trace_output_32 (sd, tmp);
1304 }
1305
1306 /* jhi. */
1307 void
1308 OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
1309 {
1310 uint32_t tmp = 0;
1311 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1312 if ((PSR_L) == 1)
1313 {
1314 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1315 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1316 }
1317 trace_output_32 (sd, tmp);
1318 }
1319
1320 /* jls. */
1321 void
1322 OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
1323 {
1324 uint32_t tmp = 0;
1325 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1326 if ((PSR_L) == 0)
1327 {
1328 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1329 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1330 }
1331 trace_output_32 (sd, tmp);
1332 }
1333
1334 /* jgt. */
1335 void
1336 OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
1337 {
1338 uint32_t tmp = 0;
1339 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1340 if ((PSR_N) == 1)
1341 {
1342 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1343 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1344 }
1345 trace_output_32 (sd, tmp);
1346 }
1347
1348 /* jle. */
1349 void
1350 OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
1351 {
1352 uint32_t tmp = 0;
1353 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1354 if ((PSR_N) == 0)
1355 {
1356 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1357 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1358 }
1359 trace_output_32 (sd, tmp);
1360 }
1361
1362
1363 /* jfs. */
1364 void
1365 OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
1366 {
1367 uint32_t tmp = 0;
1368 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1369 if ((PSR_F) == 1)
1370 {
1371 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1372 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1373 }
1374 trace_output_32 (sd, tmp);
1375 }
1376
1377 /* jfc. */
1378 void
1379 OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
1380 {
1381 uint32_t tmp = 0;
1382 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1383 if ((PSR_F) == 0)
1384 {
1385 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1386 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1387 }
1388 trace_output_32 (sd, tmp);
1389 }
1390
1391 /* jlo. */
1392 void
1393 OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
1394 {
1395 uint32_t tmp = 0;
1396 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1397 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1398 {
1399 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1400 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1401 }
1402 trace_output_32 (sd, tmp);
1403 }
1404
1405 /* jhs. */
1406 void
1407 OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
1408 {
1409 uint32_t tmp = 0;
1410 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1411 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1412 {
1413 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1414 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1415 }
1416 trace_output_32 (sd, tmp);
1417 }
1418
1419 /* jlt. */
1420 void
1421 OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
1422 {
1423 uint32_t tmp = 0;
1424 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1425 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1426 {
1427 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1428 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1429 }
1430 trace_output_32 (sd, tmp);
1431 }
1432
1433 /* jge. */
1434 void
1435 OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
1436 {
1437 uint32_t tmp = 0;
1438 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1439 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1440 {
1441 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1442 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1443 }
1444 trace_output_32 (sd, tmp);
1445 }
1446
1447 /* jump. */
1448 void
1449 OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
1450 {
1451 uint32_t tmp;
1452 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1453 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1454 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1455 trace_output_32 (sd, tmp);
1456 }
1457
1458 /* jusr. */
1459 void
1460 OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
1461 {
1462 uint32_t tmp;
1463 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1464 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1465 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1466 SET_PSR_U(1);
1467 trace_output_32 (sd, tmp);
1468 }
1469
1470 /* seq. */
1471 void
1472 OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
1473 {
1474 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1475 if ((PSR_Z) == 1)
1476 SET_GPR (OP[0], 1);
1477 else
1478 SET_GPR (OP[0], 0);
1479 trace_output_void (sd);
1480 }
1481 /* sne. */
1482 void
1483 OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
1484 {
1485 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1486 if ((PSR_Z) == 0)
1487 SET_GPR (OP[0], 1);
1488 else
1489 SET_GPR (OP[0], 0);
1490 trace_output_void (sd);
1491 }
1492
1493 /* scs. */
1494 void
1495 OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
1496 {
1497 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1498 if ((PSR_C) == 1)
1499 SET_GPR (OP[0], 1);
1500 else
1501 SET_GPR (OP[0], 0);
1502 trace_output_void (sd);
1503 }
1504
1505 /* scc. */
1506 void
1507 OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
1508 {
1509 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1510 if ((PSR_C) == 0)
1511 SET_GPR (OP[0], 1);
1512 else
1513 SET_GPR (OP[0], 0);
1514 trace_output_void (sd);
1515 }
1516
1517 /* shi. */
1518 void
1519 OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
1520 {
1521 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1522 if ((PSR_L) == 1)
1523 SET_GPR (OP[0], 1);
1524 else
1525 SET_GPR (OP[0], 0);
1526 trace_output_void (sd);
1527 }
1528
1529 /* sls. */
1530 void
1531 OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
1532 {
1533 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1534 if ((PSR_L) == 0)
1535 SET_GPR (OP[0], 1);
1536 else
1537 SET_GPR (OP[0], 0);
1538 trace_output_void (sd);
1539 }
1540
1541 /* sgt. */
1542 void
1543 OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
1544 {
1545 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1546 if ((PSR_N) == 1)
1547 SET_GPR (OP[0], 1);
1548 else
1549 SET_GPR (OP[0], 0);
1550 trace_output_void (sd);
1551 }
1552
1553 /* sle. */
1554 void
1555 OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
1556 {
1557 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1558 if ((PSR_N) == 0)
1559 SET_GPR (OP[0], 1);
1560 else
1561 SET_GPR (OP[0], 0);
1562 trace_output_void (sd);
1563 }
1564
1565 /* sfs. */
1566 void
1567 OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
1568 {
1569 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1570 if ((PSR_F) == 1)
1571 SET_GPR (OP[0], 1);
1572 else
1573 SET_GPR (OP[0], 0);
1574 trace_output_void (sd);
1575 }
1576
1577 /* sfc. */
1578 void
1579 OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
1580 {
1581 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1582 if ((PSR_F) == 0)
1583 SET_GPR (OP[0], 1);
1584 else
1585 SET_GPR (OP[0], 0);
1586 trace_output_void (sd);
1587 }
1588
1589
1590 /* slo. */
1591 void
1592 OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
1593 {
1594 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1595 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1596 SET_GPR (OP[0], 1);
1597 else
1598 SET_GPR (OP[0], 0);
1599 trace_output_void (sd);
1600 }
1601
1602 /* shs. */
1603 void
1604 OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
1605 {
1606 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1607 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1608 SET_GPR (OP[0], 1);
1609 else
1610 SET_GPR (OP[0], 0);
1611 trace_output_void (sd);
1612 }
1613
1614 /* slt. */
1615 void
1616 OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
1617 {
1618 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1619 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1620 SET_GPR (OP[0], 1);
1621 else
1622 SET_GPR (OP[0], 0);
1623 trace_output_void (sd);
1624 }
1625
1626 /* sge. */
1627 void
1628 OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
1629 {
1630 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1631 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1632 SET_GPR (OP[0], 1);
1633 else
1634 SET_GPR (OP[0], 0);
1635 trace_output_void (sd);
1636 }
1637
1638 /* cbitb. */
1639 void
1640 OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
1641 {
1642 uint8_t a = OP[0] & 0xff;
1643 uint32_t addr = OP[1], tmp;
1644 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1645 tmp = RB (addr);
1646 SET_PSR_F (tmp & (1 << a));
1647 tmp = tmp & ~(1 << a);
1648 SB (addr, tmp);
1649 trace_output_32 (sd, tmp);
1650 }
1651
1652 /* cbitb. */
1653 void
1654 OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
1655 {
1656 uint8_t a = OP[0] & 0xff;
1657 uint32_t addr = OP[1], tmp;
1658 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1659 tmp = RB (addr);
1660 SET_PSR_F (tmp & (1 << a));
1661 tmp = tmp & ~(1 << a);
1662 SB (addr, tmp);
1663 trace_output_32 (sd, tmp);
1664 }
1665
1666 /* cbitb. */
1667 void
1668 OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
1669 {
1670 uint8_t a = (OP[0]) & 0xff;
1671 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1672 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1673 tmp = RB (addr);
1674 SET_PSR_F (tmp & (1 << a));
1675 tmp = tmp & ~(1 << a);
1676 SB (addr, tmp);
1677 trace_output_32 (sd, addr);
1678 }
1679
1680 /* cbitb. */
1681 void
1682 OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
1683 {
1684 uint8_t a = (OP[0]) & 0xff;
1685 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1686 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1687 tmp = RB (addr);
1688 SET_PSR_F (tmp & (1 << a));
1689 tmp = tmp & ~(1 << a);
1690 SB (addr, tmp);
1691 trace_output_32 (sd, addr);
1692 }
1693
1694 /* cbitb. */
1695 void
1696 OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
1697 {
1698 uint8_t a = (OP[0]) & 0xff;
1699 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1700 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1701 tmp = RB (addr);
1702 SET_PSR_F (tmp & (1 << a));
1703 tmp = tmp & ~(1 << a);
1704 SB (addr, tmp);
1705 trace_output_32 (sd, addr);
1706 }
1707
1708 /* cbitb. */
1709 void
1710 OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
1711 {
1712 uint8_t a = (OP[0]) & 0xff;
1713 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1714 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1715 tmp = RB (addr);
1716 SET_PSR_F (tmp & (1 << a));
1717 tmp = tmp & ~(1 << a);
1718 SB (addr, tmp);
1719 trace_output_32 (sd, addr);
1720 }
1721
1722 /* cbitb. */
1723 void
1724 OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
1725 {
1726 uint8_t a = (OP[0]) & 0xff;
1727 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1728 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1729 tmp = RB (addr);
1730 SET_PSR_F (tmp & (1 << a));
1731 tmp = tmp & ~(1 << a);
1732 SB (addr, tmp);
1733 trace_output_32 (sd, addr);
1734
1735 }
1736
1737 /* cbitb. */
1738 void
1739 OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
1740 {
1741 uint8_t a = (OP[0]) & 0xff;
1742 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1743 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1744 tmp = RB (addr);
1745 SET_PSR_F (tmp & (1 << a));
1746 tmp = tmp & ~(1 << a);
1747 SB (addr, tmp);
1748 trace_output_32 (sd, addr);
1749 }
1750
1751 /* cbitb. */
1752 void
1753 OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
1754 {
1755 uint8_t a = (OP[0]) & 0xff;
1756 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1757 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1758 tmp = RB (addr);
1759 SET_PSR_F (tmp & (1 << a));
1760 tmp = tmp & ~(1 << a);
1761 SB (addr, tmp);
1762 trace_output_32 (sd, addr);
1763 }
1764
1765
1766 /* cbitw. */
1767 void
1768 OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
1769 {
1770 uint16_t a = OP[0];
1771 uint32_t addr = OP[1], tmp;
1772 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1773 tmp = RW (addr);
1774 SET_PSR_F (tmp & (1 << a));
1775 tmp = tmp & ~(1 << a);
1776 SW (addr, tmp);
1777 trace_output_32 (sd, tmp);
1778 }
1779
1780 /* cbitw. */
1781 void
1782 OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
1783 {
1784 uint16_t a = OP[0];
1785 uint32_t addr = OP[1], tmp;
1786 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1787 tmp = RW (addr);
1788 SET_PSR_F (tmp & (1 << a));
1789 tmp = tmp & ~(1 << a);
1790 SW (addr, tmp);
1791 trace_output_32 (sd, tmp);
1792 }
1793
1794 /* cbitw. */
1795 void
1796 OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
1797 {
1798 uint32_t addr;
1799 uint16_t a = (OP[0]), tmp;
1800 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1801
1802 if (OP[1] == 0)
1803 addr = (GPR32 (12)) + OP[2];
1804 else
1805 addr = (GPR32 (13)) + OP[2];
1806
1807 tmp = RW (addr);
1808 SET_PSR_F (tmp & (1 << a));
1809 tmp = tmp & ~(1 << a);
1810 SW (addr, tmp);
1811 trace_output_32 (sd, addr);
1812
1813 }
1814
1815 /* cbitw. */
1816 void
1817 OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
1818 {
1819 uint16_t a = (OP[0]);
1820 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1821 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1822 tmp = RW (addr);
1823 SET_PSR_F (tmp & (1 << a));
1824 tmp = tmp & ~(1 << a);
1825 SW (addr, tmp);
1826 trace_output_32 (sd, addr);
1827 }
1828
1829 /* cbitw. */
1830 void
1831 OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
1832 {
1833 uint16_t a = (OP[0]);
1834 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1835 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1836 tmp = RW (addr);
1837 SET_PSR_F (tmp & (1 << a));
1838 tmp = tmp & ~(1 << a);
1839 SW (addr, tmp);
1840 trace_output_32 (sd, addr);
1841 }
1842
1843
1844 /* cbitw. */
1845 void
1846 OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
1847 {
1848 uint16_t a = (OP[0]);
1849 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1850 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1851 tmp = RW (addr);
1852 SET_PSR_F (tmp & (1 << a));
1853 tmp = tmp & ~(1 << a);
1854 SW (addr, tmp);
1855 trace_output_32 (sd, addr);
1856 }
1857
1858 /* cbitw. */
1859 void
1860 OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
1861 {
1862 uint16_t a = (OP[0]);
1863 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1864 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1865 tmp = RW (addr);
1866 SET_PSR_F (tmp & (1 << a));
1867 tmp = tmp & ~(1 << a);
1868 SW (addr, tmp);
1869 trace_output_32 (sd, addr);
1870 }
1871
1872
1873 /* cbitw. */
1874 void
1875 OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
1876 {
1877 uint16_t a = (OP[0]);
1878 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1879 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1880 tmp = RW (addr);
1881 SET_PSR_F (tmp & (1 << a));
1882 tmp = tmp & ~(1 << a);
1883 SW (addr, tmp);
1884 trace_output_32 (sd, addr);
1885 }
1886
1887 /* cbitw. */
1888 void
1889 OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
1890 {
1891 uint16_t a = (OP[0]);
1892 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1893 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1894 tmp = RW (addr);
1895 SET_PSR_F (tmp & (1 << a));
1896 tmp = tmp & ~(1 << a);
1897 SW (addr, tmp);
1898 trace_output_32 (sd, addr);
1899 }
1900
1901 /* sbitb. */
1902 void
1903 OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
1904 {
1905 uint8_t a = OP[0] & 0xff;
1906 uint32_t addr = OP[1], tmp;
1907 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1908 tmp = RB (addr);
1909 SET_PSR_F (tmp & (1 << a));
1910 tmp = tmp | (1 << a);
1911 SB (addr, tmp);
1912 trace_output_32 (sd, tmp);
1913 }
1914
1915 /* sbitb. */
1916 void
1917 OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
1918 {
1919 uint8_t a = OP[0] & 0xff;
1920 uint32_t addr = OP[1], tmp;
1921 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1922 tmp = RB (addr);
1923 SET_PSR_F (tmp & (1 << a));
1924 tmp = tmp | (1 << a);
1925 SB (addr, tmp);
1926 trace_output_32 (sd, tmp);
1927 }
1928
1929 /* sbitb. */
1930 void
1931 OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
1932 {
1933 uint8_t a = OP[0] & 0xff;
1934 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1935 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1936 tmp = RB (addr);
1937 SET_PSR_F (tmp & (1 << a));
1938 tmp = tmp | (1 << a);
1939 SB (addr, tmp);
1940 trace_output_32 (sd, tmp);
1941 }
1942
1943 /* sbitb. */
1944 void
1945 OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
1946 {
1947 uint8_t a = OP[0] & 0xff;
1948 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1949 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1950 tmp = RB (addr);
1951 SET_PSR_F (tmp & (1 << a));
1952 tmp = tmp | (1 << a);
1953 SB (addr, tmp);
1954 trace_output_32 (sd, tmp);
1955 }
1956
1957 /* sbitb. */
1958 void
1959 OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
1960 {
1961 uint8_t a = OP[0] & 0xff;
1962 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
1963 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1964 tmp = RB (addr);
1965 SET_PSR_F (tmp & (1 << a));
1966 tmp = tmp | (1 << a);
1967 SB (addr, tmp);
1968 trace_output_32 (sd, tmp);
1969 }
1970
1971
1972 /* sbitb. */
1973 void
1974 OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
1975 {
1976 uint8_t a = OP[0] & 0xff;
1977 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1978 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1979 tmp = RB (addr);
1980 SET_PSR_F (tmp & (1 << a));
1981 tmp = tmp | (1 << a);
1982 SB (addr, tmp);
1983 trace_output_32 (sd, tmp);
1984 }
1985
1986 /* sbitb. */
1987 void
1988 OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
1989 {
1990 uint8_t a = OP[0] & 0xff;
1991 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
1992 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1993 tmp = RB (addr);
1994 SET_PSR_F (tmp & (1 << a));
1995 tmp = tmp | (1 << a);
1996 SB (addr, tmp);
1997 trace_output_32 (sd, tmp);
1998 }
1999
2000
2001 /* sbitb. */
2002 void
2003 OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
2004 {
2005 uint8_t a = OP[0] & 0xff;
2006 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2007 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2008 tmp = RB (addr);
2009 SET_PSR_F (tmp & (1 << a));
2010 tmp = tmp | (1 << a);
2011 SB (addr, tmp);
2012 trace_output_32 (sd, tmp);
2013 }
2014
2015
2016 /* sbitb. */
2017 void
2018 OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
2019 {
2020 uint8_t a = OP[0] & 0xff;
2021 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2022 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2023 tmp = RB (addr);
2024 SET_PSR_F (tmp & (1 << a));
2025 tmp = tmp | (1 << a);
2026 SB (addr, tmp);
2027 trace_output_32 (sd, tmp);
2028 }
2029
2030
2031 /* sbitw. */
2032 void
2033 OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
2034 {
2035 uint16_t a = OP[0];
2036 uint32_t addr = OP[1], tmp;
2037 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2038 tmp = RW (addr);
2039 SET_PSR_F (tmp & (1 << a));
2040 tmp = tmp | (1 << a);
2041 SW (addr, tmp);
2042 trace_output_32 (sd, tmp);
2043 }
2044
2045 /* sbitw. */
2046 void
2047 OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
2048 {
2049 uint16_t a = OP[0];
2050 uint32_t addr = OP[1], tmp;
2051 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2052 tmp = RW (addr);
2053 SET_PSR_F (tmp & (1 << a));
2054 tmp = tmp | (1 << a);
2055 SW (addr, tmp);
2056 trace_output_32 (sd, tmp);
2057 }
2058
2059 /* sbitw. */
2060 void
2061 OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
2062 {
2063 uint32_t addr;
2064 uint16_t a = (OP[0]), tmp;
2065 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2066
2067 if (OP[1] == 0)
2068 addr = (GPR32 (12)) + OP[2];
2069 else
2070 addr = (GPR32 (13)) + OP[2];
2071
2072 tmp = RW (addr);
2073 SET_PSR_F (tmp & (1 << a));
2074 tmp = tmp | (1 << a);
2075 SW (addr, tmp);
2076 trace_output_32 (sd, addr);
2077 }
2078
2079 /* sbitw. */
2080 void
2081 OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
2082 {
2083 uint16_t a = (OP[0]);
2084 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2085 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2086 tmp = RW (addr);
2087 SET_PSR_F (tmp & (1 << a));
2088 tmp = tmp | (1 << a);
2089 SW (addr, tmp);
2090 trace_output_32 (sd, addr);
2091 }
2092
2093 /* sbitw. */
2094 void
2095 OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
2096 {
2097 uint16_t a = (OP[0]);
2098 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2099 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2100 tmp = RW (addr);
2101 SET_PSR_F (tmp & (1 << a));
2102 tmp = tmp | (1 << a);
2103 SW (addr, tmp);
2104 trace_output_32 (sd, addr);
2105 }
2106
2107 /* sbitw. */
2108 void
2109 OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
2110 {
2111 uint16_t a = (OP[0]);
2112 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2113 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2114 tmp = RW (addr);
2115 SET_PSR_F (tmp & (1 << a));
2116 tmp = tmp | (1 << a);
2117 SW (addr, tmp);
2118 trace_output_32 (sd, addr);
2119 }
2120
2121 /* sbitw. */
2122 void
2123 OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
2124 {
2125 uint16_t a = (OP[0]);
2126 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2127 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2128 tmp = RW (addr);
2129 SET_PSR_F (tmp & (1 << a));
2130 tmp = tmp | (1 << a);
2131 SW (addr, tmp);
2132 trace_output_32 (sd, addr);
2133 }
2134
2135 /* sbitw. */
2136 void
2137 OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
2138 {
2139 uint16_t a = (OP[0]);
2140 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2141 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2142 tmp = RW (addr);
2143 SET_PSR_F (tmp & (1 << a));
2144 tmp = tmp | (1 << a);
2145 SW (addr, tmp);
2146 trace_output_32 (sd, addr);
2147 }
2148
2149 /* sbitw. */
2150 void
2151 OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
2152 {
2153 uint16_t a = (OP[0]);
2154 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2155 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2156 tmp = RW (addr);
2157 SET_PSR_F (tmp & (1 << a));
2158 tmp = tmp | (1 << a);
2159 SW (addr, tmp);
2160 trace_output_32 (sd, addr);
2161 }
2162
2163
2164 /* tbitb. */
2165 void
2166 OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
2167 {
2168 uint8_t a = OP[0] & 0xff;
2169 uint32_t addr = OP[1], tmp;
2170 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2171 tmp = RB (addr);
2172 SET_PSR_F (tmp & (1 << a));
2173 trace_output_32 (sd, tmp);
2174 }
2175
2176 /* tbitb. */
2177 void
2178 OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
2179 {
2180 uint8_t a = OP[0] & 0xff;
2181 uint32_t addr = OP[1], tmp;
2182 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2183 tmp = RB (addr);
2184 SET_PSR_F (tmp & (1 << a));
2185 trace_output_32 (sd, tmp);
2186 }
2187
2188 /* tbitb. */
2189 void
2190 OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
2191 {
2192 uint8_t a = (OP[0]) & 0xff;
2193 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2194 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2195 tmp = RB (addr);
2196 SET_PSR_F (tmp & (1 << a));
2197 trace_output_32 (sd, addr);
2198 }
2199
2200 /* tbitb. */
2201 void
2202 OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
2203 {
2204 uint8_t a = (OP[0]) & 0xff;
2205 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2206 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2207 tmp = RB (addr);
2208 SET_PSR_F (tmp & (1 << a));
2209 trace_output_32 (sd, addr);
2210 }
2211
2212 /* tbitb. */
2213 void
2214 OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
2215 {
2216 uint8_t a = (OP[0]) & 0xff;
2217 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2218 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2219 tmp = RB (addr);
2220 SET_PSR_F (tmp & (1 << a));
2221 trace_output_32 (sd, addr);
2222 }
2223
2224 /* tbitb. */
2225 void
2226 OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
2227 {
2228 uint8_t a = (OP[0]) & 0xff;
2229 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2230 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2231 tmp = RB (addr);
2232 SET_PSR_F (tmp & (1 << a));
2233 trace_output_32 (sd, addr);
2234 }
2235
2236 /* tbitb. */
2237 void
2238 OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
2239 {
2240 uint8_t a = (OP[0]) & 0xff;
2241 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2242 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2243 tmp = RB (addr);
2244 SET_PSR_F (tmp & (1 << a));
2245 trace_output_32 (sd, addr);
2246 }
2247
2248 /* tbitb. */
2249 void
2250 OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
2251 {
2252 uint8_t a = (OP[0]) & 0xff;
2253 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2254 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2255 tmp = RB (addr);
2256 SET_PSR_F (tmp & (1 << a));
2257 trace_output_32 (sd, addr);
2258 }
2259
2260 /* tbitb. */
2261 void
2262 OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
2263 {
2264 uint8_t a = (OP[0]) & 0xff;
2265 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2266 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2267 tmp = RB (addr);
2268 SET_PSR_F (tmp & (1 << a));
2269 trace_output_32 (sd, addr);
2270 }
2271
2272
2273 /* tbitw. */
2274 void
2275 OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
2276 {
2277 uint16_t a = OP[0];
2278 uint32_t addr = OP[1], tmp;
2279 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2280 tmp = RW (addr);
2281 SET_PSR_F (tmp & (1 << a));
2282 trace_output_32 (sd, tmp);
2283 }
2284
2285 /* tbitw. */
2286 void
2287 OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
2288 {
2289 uint16_t a = OP[0];
2290 uint32_t addr = OP[1], tmp;
2291 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2292 tmp = RW (addr);
2293 SET_PSR_F (tmp & (1 << a));
2294 trace_output_32 (sd, tmp);
2295 }
2296
2297
2298 /* tbitw. */
2299 void
2300 OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
2301 {
2302 uint32_t addr;
2303 uint16_t a = (OP[0]), tmp;
2304 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2305
2306 if (OP[1] == 0)
2307 addr = (GPR32 (12)) + OP[2];
2308 else
2309 addr = (GPR32 (13)) + OP[2];
2310
2311 tmp = RW (addr);
2312 SET_PSR_F (tmp & (1 << a));
2313 trace_output_32 (sd, addr);
2314 }
2315
2316 /* tbitw. */
2317 void
2318 OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
2319 {
2320 uint16_t a = (OP[0]);
2321 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2322 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2323 tmp = RW (addr);
2324 SET_PSR_F (tmp & (1 << a));
2325 trace_output_32 (sd, addr);
2326 }
2327
2328 /* tbitw. */
2329 void
2330 OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
2331 {
2332 uint16_t a = (OP[0]);
2333 uint32_t addr = (GPR (OP[2])) + OP[1], tmp;
2334 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2335 tmp = RW (addr);
2336 SET_PSR_F (tmp & (1 << a));
2337 trace_output_32 (sd, addr);
2338 }
2339
2340 /* tbitw. */
2341 void
2342 OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
2343 {
2344 uint16_t a = (OP[0]);
2345 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2346 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2347 tmp = RW (addr);
2348 SET_PSR_F (tmp & (1 << a));
2349 trace_output_32 (sd, addr);
2350 }
2351
2352 /* tbitw. */
2353 void
2354 OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
2355 {
2356 uint16_t a = (OP[0]);
2357 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2358 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2359 tmp = RW (addr);
2360 SET_PSR_F (tmp & (1 << a));
2361 trace_output_32 (sd, addr);
2362 }
2363
2364 /* tbitw. */
2365 void
2366 OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
2367 {
2368 uint16_t a = (OP[0]);
2369 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2370 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2371 tmp = RW (addr);
2372 SET_PSR_F (tmp & (1 << a));
2373 trace_output_32 (sd, addr);
2374 }
2375
2376
2377 /* tbitw. */
2378 void
2379 OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
2380 {
2381 uint16_t a = (OP[0]);
2382 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp;
2383 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2384 tmp = RW (addr);
2385 SET_PSR_F (tmp & (1 << a));
2386 trace_output_32 (sd, addr);
2387 }
2388
2389
2390 /* tbit. */
2391 void
2392 OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
2393 {
2394 uint16_t a = OP[0];
2395 uint16_t b = (GPR (OP[1]));
2396 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2397 SET_PSR_F (b & (1 << a));
2398 trace_output_16 (sd, b);
2399 }
2400
2401 /* tbit. */
2402 void
2403 OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
2404 {
2405 uint16_t a = GPR (OP[0]);
2406 uint16_t b = (GPR (OP[1]));
2407 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2408 SET_PSR_F (b & (1 << a));
2409 trace_output_16 (sd, b);
2410 }
2411
2412
2413 /* cmpb. */
2414 void
2415 OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
2416 {
2417 uint8_t a = (OP[0]) & 0xFF;
2418 uint8_t b = (GPR (OP[1])) & 0xFF;
2419 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2420 SET_PSR_Z (a == b);
2421 SET_PSR_N ((int8_t)a > (int8_t)b);
2422 SET_PSR_L (a > b);
2423 trace_output_flag (sd);
2424 }
2425
2426 /* cmpb. */
2427 void
2428 OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
2429 {
2430 uint8_t a = (OP[0]) & 0xFF;
2431 uint8_t b = (GPR (OP[1])) & 0xFF;
2432 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2433 SET_PSR_Z (a == b);
2434 SET_PSR_N ((int8_t)a > (int8_t)b);
2435 SET_PSR_L (a > b);
2436 trace_output_flag (sd);
2437 }
2438
2439 /* cmpb. */
2440 void
2441 OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
2442 {
2443 uint8_t a = (GPR (OP[0])) & 0xFF;
2444 uint8_t b = (GPR (OP[1])) & 0xFF;
2445 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2446 SET_PSR_Z (a == b);
2447 SET_PSR_N ((int8_t)a > (int8_t)b);
2448 SET_PSR_L (a > b);
2449 trace_output_flag (sd);
2450 }
2451
2452 /* cmpw. */
2453 void
2454 OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
2455 {
2456 uint16_t a = (OP[0]);
2457 uint16_t b = GPR (OP[1]);
2458 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2459 SET_PSR_Z (a == b);
2460 SET_PSR_N ((int16_t)a > (int16_t)b);
2461 SET_PSR_L (a > b);
2462 trace_output_flag (sd);
2463 }
2464
2465 /* cmpw. */
2466 void
2467 OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
2468 {
2469 uint16_t a = (OP[0]);
2470 uint16_t b = GPR (OP[1]);
2471 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2472 SET_PSR_Z (a == b);
2473 SET_PSR_N ((int16_t)a > (int16_t)b);
2474 SET_PSR_L (a > b);
2475 trace_output_flag (sd);
2476 }
2477
2478 /* cmpw. */
2479 void
2480 OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
2481 {
2482 uint16_t a = GPR (OP[0]) ;
2483 uint16_t b = GPR (OP[1]) ;
2484 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2485 SET_PSR_Z (a == b);
2486 SET_PSR_N ((int16_t)a > (int16_t)b);
2487 SET_PSR_L (a > b);
2488 trace_output_flag (sd);
2489 }
2490
2491 /* cmpd. */
2492 void
2493 OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
2494 {
2495 uint32_t a = (OP[0]);
2496 uint32_t b = GPR32 (OP[1]);
2497 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2498 SET_PSR_Z (a == b);
2499 SET_PSR_N ((int32_t)a > (int32_t)b);
2500 SET_PSR_L (a > b);
2501 trace_output_flag (sd);
2502 }
2503
2504 /* cmpd. */
2505 void
2506 OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
2507 {
2508 uint32_t a = (SEXT16(OP[0]));
2509 uint32_t b = GPR32 (OP[1]);
2510 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2511 SET_PSR_Z (a == b);
2512 SET_PSR_N ((int32_t)a > (int32_t)b);
2513 SET_PSR_L (a > b);
2514 trace_output_flag (sd);
2515 }
2516
2517 /* cmpd. */
2518 void
2519 OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
2520 {
2521 uint32_t a = GPR32 (OP[0]) ;
2522 uint32_t b = GPR32 (OP[1]) ;
2523 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2524 SET_PSR_Z (a == b);
2525 SET_PSR_N ((int32_t)a > (int32_t)b);
2526 SET_PSR_L (a > b);
2527 trace_output_flag (sd);
2528 }
2529
2530 /* cmpd. */
2531 void
2532 OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
2533 {
2534 uint32_t a = (OP[0]);
2535 uint32_t b = GPR32 (OP[1]);
2536 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2537 SET_PSR_Z (a == b);
2538 SET_PSR_N ((int32_t)a > (int32_t)b);
2539 SET_PSR_L (a > b);
2540 trace_output_flag (sd);
2541 }
2542
2543
2544 /* movb. */
2545 void
2546 OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
2547 {
2548 uint8_t tmp = OP[0] & 0xFF;
2549 uint16_t a = (GPR (OP[1])) & 0xFF00;
2550 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2551 SET_GPR (OP[1], (a | tmp));
2552 trace_output_16 (sd, tmp);
2553 }
2554
2555 /* movb. */
2556 void
2557 OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
2558 {
2559 uint8_t tmp = OP[0] & 0xFF;
2560 uint16_t a = (GPR (OP[1])) & 0xFF00;
2561 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2562 SET_GPR (OP[1], (a | tmp));
2563 trace_output_16 (sd, tmp);
2564 }
2565
2566 /* movb. */
2567 void
2568 OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
2569 {
2570 uint8_t tmp = (GPR (OP[0])) & 0xFF;
2571 uint16_t a = (GPR (OP[1])) & 0xFF00;
2572 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2573 SET_GPR (OP[1], (a | tmp));
2574 trace_output_16 (sd, tmp);
2575 }
2576
2577 /* movw. */
2578 void
2579 OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
2580 {
2581 uint16_t tmp = OP[0];
2582 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2583 SET_GPR (OP[1], (tmp & 0xffff));
2584 trace_output_16 (sd, tmp);
2585 }
2586
2587 /* movw. */
2588 void
2589 OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
2590 {
2591 int16_t tmp = OP[0];
2592 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2593 SET_GPR (OP[1], (tmp & 0xffff));
2594 trace_output_16 (sd, tmp);
2595 }
2596
2597 /* movw. */
2598 void
2599 OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
2600 {
2601 uint16_t tmp = GPR (OP[0]);
2602 uint32_t a = GPR32 (OP[1]);
2603 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2604 a = (a & 0xffff0000) | tmp;
2605 SET_GPR32 (OP[1], a);
2606 trace_output_16 (sd, tmp);
2607 }
2608
2609 /* movxb. */
2610 void
2611 OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
2612 {
2613 uint8_t tmp = (GPR (OP[0])) & 0xFF;
2614 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2615 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2616 trace_output_16 (sd, tmp);
2617 }
2618
2619 /* movzb. */
2620 void
2621 OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
2622 {
2623 uint8_t tmp = (GPR (OP[0])) & 0xFF;
2624 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2625 SET_GPR (OP[1], tmp);
2626 trace_output_16 (sd, tmp);
2627 }
2628
2629 /* movxw. */
2630 void
2631 OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
2632 {
2633 uint16_t tmp = GPR (OP[0]);
2634 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2635 SET_GPR32 (OP[1], SEXT16(tmp));
2636 trace_output_16 (sd, tmp);
2637 }
2638
2639 /* movzw. */
2640 void
2641 OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
2642 {
2643 uint16_t tmp = GPR (OP[0]);
2644 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2645 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2646 trace_output_16 (sd, tmp);
2647 }
2648
2649 /* movd. */
2650 void
2651 OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
2652 {
2653 int32_t tmp = OP[0];
2654 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2655 SET_GPR32 (OP[1], tmp);
2656 trace_output_32 (sd, tmp);
2657 }
2658
2659 /* movd. */
2660 void
2661 OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
2662 {
2663 int32_t tmp = SEXT16(OP[0]);
2664 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2665 SET_GPR32 (OP[1], tmp);
2666 trace_output_32 (sd, tmp);
2667 }
2668
2669 /* movd. */
2670 void
2671 OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
2672 {
2673 uint32_t tmp = GPR32 (OP[0]);
2674 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2675 SET_GPR32 (OP[1], tmp);
2676 trace_output_32 (sd, tmp);
2677 }
2678
2679 /* movd. */
2680 void
2681 OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
2682 {
2683 uint32_t tmp = OP[0];
2684 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2685 SET_GPR32 (OP[1], tmp);
2686 trace_output_32 (sd, tmp);
2687 }
2688
2689 /* movd. */
2690 void
2691 OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
2692 {
2693 int32_t tmp = OP[0];
2694 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2695 SET_GPR32 (OP[1], tmp);
2696 trace_output_32 (sd, tmp);
2697 }
2698
2699 /* loadm. */
2700 void
2701 OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
2702 {
2703 uint32_t addr = GPR (0);
2704 uint16_t count = OP[0], reg = 2, tmp;
2705 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2706 if ((addr & 1))
2707 {
2708 trace_output_void (sd);
2709 EXCEPTION (SIM_SIGBUS);
2710 }
2711
2712 while (count)
2713 {
2714 tmp = RW (addr);
2715 SET_GPR (reg, tmp);
2716 addr +=2;
2717 --count;
2718 reg++;
2719 if (reg == 6) reg = 8;
2720 };
2721
2722 SET_GPR (0, addr);
2723 trace_output_void (sd);
2724 }
2725
2726
2727 /* loadmp. */
2728 void
2729 OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
2730 {
2731 uint32_t addr = GPR32 (0);
2732 uint16_t count = OP[0], reg = 2, tmp;
2733 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2734 if ((addr & 1))
2735 {
2736 trace_output_void (sd);
2737 EXCEPTION (SIM_SIGBUS);
2738 }
2739
2740 while (count)
2741 {
2742 tmp = RW (addr);
2743 SET_GPR (reg, tmp);
2744 addr +=2;
2745 --count;
2746 reg++;
2747 if (reg == 6) reg = 8;
2748 };
2749
2750 SET_GPR32 (0, addr);
2751 trace_output_void (sd);
2752 }
2753
2754
2755 /* loadb. */
2756 void
2757 OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
2758 {
2759 /* loadb ABS20, REG
2760 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2761 * REG = [ADDR]
2762 * NOTE: remap is
2763 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2764 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2765 * by the core to 16M-64k to 16M. */
2766
2767 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
2768 uint32_t addr = OP[0];
2769 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2770 if (addr > 0xEFFFF) addr |= 0xF00000;
2771 tmp = (RB (addr));
2772 SET_GPR (OP[1], (a | tmp));
2773 trace_output_16 (sd, tmp);
2774 }
2775
2776 /* loadb. */
2777 void
2778 OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
2779 {
2780 /* loadb ABS24, REG
2781 * ADDR = abs24
2782 * REGR = [ADDR]. */
2783
2784 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00;
2785 uint32_t addr = OP[0];
2786 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2787 tmp = (RB (addr));
2788 SET_GPR (OP[1], (a | tmp));
2789 trace_output_16 (sd, tmp);
2790 }
2791
2792 /* loadb. */
2793 void
2794 OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
2795 {
2796 /* loadb [Rindex]ABS20 REG
2797 * ADDR = Rindex + zext24(disp20)
2798 * REGR = [ADDR]. */
2799
2800 uint32_t addr;
2801 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
2802 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2803
2804 if (OP[0] == 0)
2805 addr = (GPR32 (12)) + OP[1];
2806 else
2807 addr = (GPR32 (13)) + OP[1];
2808
2809 tmp = (RB (addr));
2810 SET_GPR (OP[2], (a | tmp));
2811 trace_output_16 (sd, tmp);
2812 }
2813
2814
2815 /* loadb. */
2816 void
2817 OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
2818 {
2819 /* loadb DIPS4(REGP) REG
2820 * ADDR = RPBASE + zext24(DISP4)
2821 * REG = [ADDR]. */
2822 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00;
2823 uint32_t addr = (GPR32 (OP[1])) + OP[0];
2824 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2825 tmp = (RB (addr));
2826 SET_GPR (OP[2], (a | tmp));
2827 trace_output_16 (sd, tmp);
2828 }
2829
2830 /* loadb. */
2831 void
2832 OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
2833 {
2834 /* loadb [Rindex]disp0(RPbasex) REG
2835 * ADDR = Rpbasex + Rindex
2836 * REGR = [ADDR] */
2837
2838 uint32_t addr;
2839 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
2840 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2841
2842 addr = (GPR32 (OP[2])) + OP[1];
2843
2844 if (OP[0] == 0)
2845 addr = (GPR32 (12)) + addr;
2846 else
2847 addr = (GPR32 (13)) + addr;
2848
2849 tmp = (RB (addr));
2850 SET_GPR (OP[3], (a | tmp));
2851 trace_output_16 (sd, tmp);
2852 }
2853
2854 /* loadb. */
2855 void
2856 OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
2857 {
2858 /* loadb [Rindex]disp14(RPbasex) REG
2859 * ADDR = Rpbasex + Rindex + zext24(disp14)
2860 * REGR = [ADDR] */
2861
2862 uint32_t addr;
2863 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
2864
2865 addr = (GPR32 (OP[2])) + OP[1];
2866
2867 if (OP[0] == 0)
2868 addr = (GPR32 (12)) + addr;
2869 else
2870 addr = (GPR32 (13)) + addr;
2871
2872 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2873 tmp = (RB (addr));
2874 SET_GPR (OP[3], (a | tmp));
2875 trace_output_16 (sd, tmp);
2876 }
2877
2878
2879 /* loadb. */
2880 void
2881 OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
2882 {
2883 /* loadb DISPE20(REG) REG
2884 * zext24(Rbase) + zext24(dispe20)
2885 * REG = [ADDR] */
2886
2887 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2888 uint32_t addr = OP[0] + (GPR (OP[1]));
2889 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2890 tmp = (RB (addr));
2891 SET_GPR (OP[2], (a | tmp));
2892 trace_output_16 (sd, tmp);
2893 }
2894
2895 /* loadb. */
2896 void
2897 OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
2898 {
2899 /* loadb DISP20(REG) REG
2900 * ADDR = zext24(Rbase) + zext24(disp20)
2901 * REG = [ADDR] */
2902
2903 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2904 uint32_t addr = OP[0] + (GPR (OP[1]));
2905 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2906 tmp = (RB (addr));
2907 SET_GPR (OP[2], (a | tmp));
2908 trace_output_16 (sd, tmp);
2909 }
2910
2911 /* loadb. */
2912 void
2913 OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
2914 {
2915 /* loadb disp16(REGP) REG
2916 * ADDR = RPbase + zext24(disp16)
2917 * REGR = [ADDR] */
2918
2919 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2920 uint32_t addr = (GPR32 (OP[1])) + OP[0];
2921 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2922 tmp = (RB (addr));
2923 SET_GPR (OP[2], (a | tmp));
2924 trace_output_16 (sd, tmp);
2925 }
2926
2927 /* loadb. */
2928 void
2929 OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
2930 {
2931 /* loadb disp20(REGP) REG
2932 * ADDR = RPbase + zext24(disp20)
2933 * REGR = [ADDR] */
2934 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2935 uint32_t addr = (GPR32 (OP[1])) + OP[0];
2936 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2937 tmp = (RB (addr));
2938 SET_GPR (OP[2], (a | tmp));
2939 trace_output_16 (sd, tmp);
2940 }
2941
2942
2943 /* loadb. */
2944 void
2945 OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
2946 {
2947 /* loadb -disp20(REGP) REG
2948 * ADDR = RPbase + zext24(-disp20)
2949 * REGR = [ADDR] */
2950 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00;
2951 uint32_t addr = (GPR32 (OP[1])) + OP[1];
2952 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2953 tmp = (RB (addr));
2954 SET_GPR (OP[2], (a | tmp));
2955 trace_output_16 (sd, tmp);
2956 }
2957
2958 /* loadb. */
2959 void
2960 OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
2961 {
2962 /* loadb [Rindex]disp20(RPbasexb) REG
2963 * ADDR = RPbasex + Rindex + zext24(disp20)
2964 * REGR = [ADDR] */
2965
2966 uint32_t addr;
2967 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00;
2968 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2969
2970 addr = (GPR32 (OP[2])) + OP[1];
2971
2972 if (OP[0] == 0)
2973 addr = (GPR32 (12)) + addr;
2974 else
2975 addr = (GPR32 (13)) + addr;
2976
2977 tmp = (RB (addr));
2978 SET_GPR (OP[3], (a | tmp));
2979 trace_output_16 (sd, tmp);
2980 }
2981
2982
2983 /* loadw. */
2984 void
2985 OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
2986 {
2987 /* loadw ABS20, REG
2988 * ADDR = zext24(abs20) | remap
2989 * REGR = [ADDR]
2990 * NOTE: remap is
2991 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2992 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2993 * by the core to 16M-64k to 16M. */
2994
2995 uint16_t tmp;
2996 uint32_t addr = OP[0];
2997 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
2998 if (addr > 0xEFFFF) addr |= 0xF00000;
2999 tmp = (RW (addr));
3000 SET_GPR (OP[1], tmp);
3001 trace_output_16 (sd, tmp);
3002 }
3003
3004
3005 /* loadw. */
3006 void
3007 OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
3008 {
3009 /* loadw ABS24, REG
3010 * ADDR = abs24
3011 * REGR = [ADDR] */
3012 uint16_t tmp;
3013 uint32_t addr = OP[0];
3014 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3015 tmp = (RW (addr));
3016 SET_GPR (OP[1], tmp);
3017 trace_output_16 (sd, tmp);
3018 }
3019
3020 /* loadw. */
3021 void
3022 OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
3023 {
3024 /* loadw [Rindex]ABS20 REG
3025 * ADDR = Rindex + zext24(disp20)
3026 * REGR = [ADDR] */
3027
3028 uint32_t addr;
3029 uint16_t tmp;
3030 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3031
3032 if (OP[0] == 0)
3033 addr = (GPR32 (12)) + OP[1];
3034 else
3035 addr = (GPR32 (13)) + OP[1];
3036
3037 tmp = (RW (addr));
3038 SET_GPR (OP[2], tmp);
3039 trace_output_16 (sd, tmp);
3040 }
3041
3042
3043 /* loadw. */
3044 void
3045 OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
3046 {
3047 /* loadw DIPS4(REGP) REGP
3048 * ADDR = RPBASE + zext24(DISP4)
3049 * REGP = [ADDR]. */
3050 uint16_t tmp;
3051 uint32_t addr, a;
3052 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3053 addr = (GPR32 (OP[1])) + OP[0];
3054 tmp = (RW (addr));
3055 if (OP[2] > 11)
3056 {
3057 a = (GPR32 (OP[2])) & 0xffff0000;
3058 SET_GPR32 (OP[2], (a | tmp));
3059 }
3060 else
3061 SET_GPR (OP[2], tmp);
3062
3063 trace_output_16 (sd, tmp);
3064 }
3065
3066
3067 /* loadw. */
3068 void
3069 OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
3070 {
3071 /* loadw [Rindex]disp0(RPbasex) REG
3072 * ADDR = Rpbasex + Rindex
3073 * REGR = [ADDR] */
3074
3075 uint32_t addr;
3076 uint16_t tmp;
3077 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3078
3079 addr = (GPR32 (OP[2])) + OP[1];
3080
3081 if (OP[0] == 0)
3082 addr = (GPR32 (12)) + addr;
3083 else
3084 addr = (GPR32 (13)) + addr;
3085
3086 tmp = RW (addr);
3087 SET_GPR (OP[3], tmp);
3088 trace_output_16 (sd, tmp);
3089 }
3090
3091
3092 /* loadw. */
3093 void
3094 OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
3095 {
3096 /* loadw [Rindex]disp14(RPbasex) REG
3097 * ADDR = Rpbasex + Rindex + zext24(disp14)
3098 * REGR = [ADDR] */
3099
3100 uint32_t addr;
3101 uint16_t tmp;
3102 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3103 addr = (GPR32 (OP[2])) + OP[1];
3104
3105 if (OP[0] == 0)
3106 addr = (GPR32 (12)) + addr;
3107 else
3108 addr = (GPR32 (13)) + addr;
3109
3110 tmp = (RW (addr));
3111 SET_GPR (OP[3], tmp);
3112 trace_output_16 (sd, tmp);
3113 }
3114
3115 /* loadw. */
3116 void
3117 OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
3118 {
3119 /* loadw dispe20(REG) REGP
3120 * REGP = [DISPE20+[REG]] */
3121
3122 uint16_t tmp;
3123 uint32_t addr, a;
3124 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3125 addr = OP[0] + (GPR (OP[1]));
3126 tmp = (RW (addr));
3127 if (OP[2] > 11)
3128 {
3129 a = (GPR32 (OP[2])) & 0xffff0000;
3130 SET_GPR32 (OP[2], (a | tmp));
3131 }
3132 else
3133 SET_GPR (OP[2], tmp);
3134
3135 trace_output_16 (sd, tmp);
3136 }
3137
3138
3139 /* loadw. */
3140 void
3141 OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
3142 {
3143 /* loadw DISP20(REG) REGP
3144 * ADDR = zext24(Rbase) + zext24(disp20)
3145 * REGP = [ADDR] */
3146
3147 uint16_t tmp;
3148 uint32_t addr, a;
3149 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3150 addr = OP[0] + (GPR (OP[1]));
3151 tmp = (RW (addr));
3152 if (OP[2] > 11)
3153 {
3154 a = (GPR32 (OP[2])) & 0xffff0000;
3155 SET_GPR32 (OP[2], (a | tmp));
3156 }
3157 else
3158 SET_GPR (OP[2], tmp);
3159
3160 trace_output_16 (sd, tmp);
3161 }
3162
3163 /* loadw. */
3164 void
3165 OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
3166 {
3167 /* loadw disp16(REGP) REGP
3168 * ADDR = RPbase + zext24(disp16)
3169 * REGP = [ADDR] */
3170 uint16_t tmp;
3171 uint32_t addr, a;
3172 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3173 addr = (GPR32 (OP[1])) + OP[0];
3174 tmp = (RW (addr));
3175 if (OP[2] > 11)
3176 {
3177 a = (GPR32 (OP[2])) & 0xffff0000;
3178 SET_GPR32 (OP[2], (a | tmp));
3179 }
3180 else
3181 SET_GPR (OP[2], tmp);
3182
3183 trace_output_16 (sd, tmp);
3184 }
3185
3186 /* loadw. */
3187 void
3188 OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
3189 {
3190 /* loadw disp20(REGP) REGP
3191 * ADDR = RPbase + zext24(disp20)
3192 * REGP = [ADDR] */
3193 uint16_t tmp;
3194 uint32_t addr, a;
3195 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3196 addr = (GPR32 (OP[1])) + OP[0];
3197 tmp = (RW (addr));
3198 if (OP[2] > 11)
3199 {
3200 a = (GPR32 (OP[2])) & 0xffff0000;
3201 SET_GPR32 (OP[2], (a | tmp));
3202 }
3203 else
3204 SET_GPR (OP[2], tmp);
3205
3206 trace_output_16 (sd, tmp);
3207 }
3208
3209 /* loadw. */
3210 void
3211 OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
3212 {
3213 /* loadw -disp20(REGP) REG
3214 * ADDR = RPbase + zext24(-disp20)
3215 * REGR = [ADDR] */
3216
3217 uint16_t tmp;
3218 uint32_t addr, a;
3219 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3220 addr = (GPR32 (OP[1])) + OP[0];
3221 tmp = (RB (addr));
3222 if (OP[2] > 11)
3223 {
3224 a = (GPR32 (OP[2])) & 0xffff0000;
3225 SET_GPR32 (OP[2], (a | tmp));
3226 }
3227 else
3228 SET_GPR (OP[2], tmp);
3229
3230 trace_output_16 (sd, tmp);
3231 }
3232
3233
3234 /* loadw. */
3235 void
3236 OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
3237 {
3238 /* loadw [Rindex]disp20(RPbasexb) REG
3239 * ADDR = RPbasex + Rindex + zext24(disp20)
3240 * REGR = [ADDR] */
3241
3242 uint32_t addr;
3243 uint16_t tmp;
3244 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3245
3246 if (OP[0] == 0)
3247 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3248 else
3249 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3250
3251 tmp = (RW (addr));
3252 SET_GPR (OP[3], tmp);
3253 trace_output_16 (sd, tmp);
3254 }
3255
3256
3257 /* loadd. */
3258 void
3259 OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
3260 {
3261 /* loadd ABS20, REGP
3262 * ADDR = zext24(abs20) | remap
3263 * REGP = [ADDR]
3264 * NOTE: remap is
3265 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3266 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3267 * by the core to 16M-64k to 16M. */
3268
3269 uint32_t addr, tmp;
3270 addr = OP[0];
3271 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3272 if (addr > 0xEFFFF) addr |= 0xF00000;
3273 tmp = RLW (addr);
3274 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3275 SET_GPR32 (OP[1], tmp);
3276 trace_output_32 (sd, tmp);
3277 }
3278
3279 /* loadd. */
3280 void
3281 OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
3282 {
3283 /* loadd ABS24, REGP
3284 * ADDR = abs24
3285 * REGP = [ADDR] */
3286
3287 uint32_t addr = OP[0];
3288 uint32_t tmp;
3289 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3290 tmp = RLW (addr);
3291 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3292 SET_GPR32 (OP[1],tmp);
3293 trace_output_32 (sd, tmp);
3294 }
3295
3296
3297 /* loadd. */
3298 void
3299 OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
3300 {
3301 /* loadd [Rindex]ABS20 REGP
3302 * ADDR = Rindex + zext24(disp20)
3303 * REGP = [ADDR] */
3304
3305 uint32_t addr, tmp;
3306 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3307
3308 if (OP[0] == 0)
3309 addr = (GPR32 (12)) + OP[1];
3310 else
3311 addr = (GPR32 (13)) + OP[1];
3312
3313 tmp = RLW (addr);
3314 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3315 SET_GPR32 (OP[2], tmp);
3316 trace_output_32 (sd, tmp);
3317 }
3318
3319
3320 /* loadd. */
3321 void
3322 OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
3323 {
3324 /* loadd dips4(regp) REGP
3325 * ADDR = Rpbase + zext24(disp4)
3326 * REGP = [ADDR] */
3327
3328 uint32_t tmp, addr = (GPR32 (OP[1])) + OP[0];
3329 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3330 tmp = RLW (addr);
3331 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3332 SET_GPR32 (OP[2], tmp);
3333 trace_output_32 (sd, tmp);
3334 }
3335
3336
3337 /* loadd. */
3338 void
3339 OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
3340 {
3341 /* loadd [Rindex]disp0(RPbasex) REGP
3342 * ADDR = Rpbasex + Rindex
3343 * REGP = [ADDR] */
3344
3345 uint32_t addr, tmp;
3346 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3347
3348 if (OP[0] == 0)
3349 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3350 else
3351 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3352
3353 tmp = RLW (addr);
3354 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3355 SET_GPR32 (OP[3], tmp);
3356 trace_output_32 (sd, tmp);
3357 }
3358
3359
3360 /* loadd. */
3361 void
3362 OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
3363 {
3364 /* loadd [Rindex]disp14(RPbasex) REGP
3365 * ADDR = Rpbasex + Rindex + zext24(disp14)
3366 * REGR = [ADDR] */
3367
3368 uint32_t addr, tmp;
3369 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3370
3371 if (OP[0] == 0)
3372 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3373 else
3374 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3375
3376 tmp = RLW (addr);
3377 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3378 SET_GPR (OP[3],tmp);
3379 trace_output_32 (sd, tmp);
3380 }
3381
3382
3383 /* loadd. */
3384 void
3385 OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
3386 {
3387 /* loadd dispe20(REG) REG
3388 * zext24(Rbase) + zext24(dispe20)
3389 * REG = [ADDR] */
3390
3391 uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
3392 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3393 tmp = RLW (addr);
3394 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3395 SET_GPR32 (OP[2], tmp);
3396 trace_output_32 (sd, tmp);
3397 }
3398
3399
3400 /* loadd. */
3401 void
3402 OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
3403 {
3404 /* loadd DISP20(REG) REG
3405 * ADDR = zext24(Rbase) + zext24(disp20)
3406 * REG = [ADDR] */
3407
3408 uint32_t tmp, addr = OP[0] + (GPR (OP[1]));
3409 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3410 tmp = RLW (addr);
3411 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3412 SET_GPR32 (OP[2], tmp);
3413 trace_output_32 (sd, tmp);
3414 }
3415
3416 /* loadd. */
3417 void
3418 OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
3419 {
3420 /* loadd disp16(REGP) REGP
3421 * ADDR = RPbase + zext24(disp16)
3422 * REGR = [ADDR] */
3423 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
3424 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3425 tmp = RLW (addr);
3426 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3427 SET_GPR32 (OP[2], tmp);
3428 trace_output_32 (sd, tmp);
3429 }
3430
3431
3432 /* loadd. */
3433 void
3434 OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
3435 {
3436 /* loadd disp20(REGP) REGP
3437 * ADDR = RPbase + zext24(disp20)
3438 * REGP = [ADDR] */
3439 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
3440 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3441 tmp = RLW (addr);
3442 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3443 SET_GPR32 (OP[2], tmp);
3444 trace_output_32 (sd, tmp);
3445 }
3446
3447 /* loadd. */
3448 void
3449 OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
3450 {
3451 /* loadd -disp20(REGP) REGP
3452 * ADDR = RPbase + zext24(-disp20)
3453 * REGP = [ADDR] */
3454
3455 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1]));
3456 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3457 tmp = RLW (addr);
3458 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3459 SET_GPR32 (OP[2], tmp);
3460 trace_output_32 (sd, tmp);
3461 }
3462
3463 /* loadd. */
3464 void
3465 OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
3466 {
3467 /* loadd [Rindex]disp20(RPbasexb) REGP
3468 * ADDR = RPbasex + Rindex + zext24(disp20)
3469 * REGP = [ADDR] */
3470
3471 uint32_t addr, tmp;
3472 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3473
3474 if (OP[0] == 0)
3475 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3476 else
3477 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3478
3479 tmp = RLW (addr);
3480 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3481 SET_GPR32 (OP[3], tmp);
3482 trace_output_32 (sd, tmp);
3483 }
3484
3485
3486 /* storb. */
3487 void
3488 OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
3489 {
3490 /* storb REG, ABS20
3491 * ADDR = zext24(abs20) | remap
3492 * [ADDR] = REGR
3493 * NOTE: remap is
3494 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3495 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3496 * by the core to 16M-64k to 16M. */
3497
3498 uint8_t a = ((GPR (OP[0])) & 0xff);
3499 uint32_t addr = OP[1];
3500 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3501 SB (addr, a);
3502 trace_output_32 (sd, addr);
3503 }
3504
3505 /* storb. */
3506 void
3507 OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
3508 {
3509 /* storb REG, ABS24
3510 * ADDR = abs24
3511 * [ADDR] = REGR. */
3512
3513 uint8_t a = ((GPR (OP[0])) & 0xff);
3514 uint32_t addr = OP[1];
3515 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3516 SB (addr, a);
3517 trace_output_32 (sd, addr);
3518 }
3519
3520 /* storb. */
3521 void
3522 OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
3523 {
3524 /* storb REG, [Rindex]ABS20
3525 * ADDR = Rindex + zext24(disp20)
3526 * [ADDR] = REGR */
3527
3528 uint32_t addr;
3529 uint8_t a = ((GPR (OP[0])) & 0xff);
3530 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3531
3532 if (OP[1] == 0)
3533 addr = (GPR32 (12)) + OP[2];
3534 else
3535 addr = (GPR32 (13)) + OP[2];
3536
3537 SB (addr, a);
3538 trace_output_32 (sd, addr);
3539 }
3540
3541 /* storb. */
3542 void
3543 OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
3544 {
3545 /* storb REG, DIPS4(REGP)
3546 * ADDR = RPBASE + zext24(DISP4)
3547 * [ADDR] = REG. */
3548
3549 uint16_t a = ((GPR (OP[0])) & 0xff);
3550 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3551 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3552 SB (addr, a);
3553 trace_output_32 (sd, addr);
3554 }
3555
3556 /* storb. */
3557 void
3558 OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
3559 {
3560 /* storb [Rindex]disp0(RPbasex) REG
3561 * ADDR = Rpbasex + Rindex
3562 * [ADDR] = REGR */
3563
3564 uint32_t addr;
3565 uint8_t a = ((GPR (OP[0])) & 0xff);
3566 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3567
3568 if (OP[1] == 0)
3569 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3570 else
3571 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3572
3573 SB (addr, a);
3574 trace_output_32 (sd, addr);
3575 }
3576
3577 /* storb. */
3578 void
3579 OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
3580 {
3581 /* storb REG, [Rindex]disp14(RPbasex)
3582 * ADDR = Rpbasex + Rindex + zext24(disp14)
3583 * [ADDR] = REGR */
3584
3585 uint8_t a = ((GPR (OP[0])) & 0xff);
3586 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3587 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3588 SB (addr, a);
3589 trace_output_32 (sd, addr);
3590 }
3591
3592 /* storb. */
3593 void
3594 OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
3595 {
3596 /* storb REG, DISPE20(REG)
3597 * zext24(Rbase) + zext24(dispe20)
3598 * [ADDR] = REG */
3599
3600 uint8_t a = ((GPR (OP[0])) & 0xff);
3601 uint32_t addr = OP[1] + (GPR (OP[2]));
3602 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3603 SB (addr, a);
3604 trace_output_32 (sd, addr);
3605 }
3606
3607 /* storb. */
3608 void
3609 OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
3610 {
3611 /* storb REG, DISP20(REG)
3612 * ADDR = zext24(Rbase) + zext24(disp20)
3613 * [ADDR] = REG */
3614
3615 uint8_t a = (GPR (OP[0]) & 0xff);
3616 uint32_t addr = OP[1] + (GPR (OP[2]));
3617 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3618 SB (addr, a);
3619 trace_output_32 (sd, addr);
3620 }
3621
3622 /* storb. */
3623 void
3624 OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
3625 {
3626 /* storb REG, disp16(REGP)
3627 * ADDR = RPbase + zext24(disp16)
3628 * [ADDR] = REGP */
3629
3630 uint8_t a = ((GPR (OP[0])) & 0xff);
3631 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3632 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3633 SB (addr, a);
3634 trace_output_32 (sd, addr);
3635 }
3636
3637 /* storb. */
3638 void
3639 OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
3640 {
3641 /* storb REG, disp20(REGP)
3642 * ADDR = RPbase + zext24(disp20)
3643 * [ADDR] = REGP */
3644
3645 uint8_t a = ((GPR (OP[0])) & 0xff);
3646 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3647 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3648 SB (addr, a);
3649 trace_output_32 (sd, addr);
3650 }
3651
3652 /* storb. */
3653 void
3654 OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
3655 {
3656 /* storb REG, -disp20(REGP)
3657 * ADDR = RPbase + zext24(-disp20)
3658 * [ADDR] = REGP */
3659
3660 uint8_t a = (GPR (OP[0]) & 0xff);
3661 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3662 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3663 SB (addr, a);
3664 trace_output_32 (sd, addr);
3665 }
3666
3667 /* storb. */
3668 void
3669 OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
3670 {
3671 /* storb REG, [Rindex]disp20(RPbase)
3672 * ADDR = RPbasex + Rindex + zext24(disp20)
3673 * [ADDR] = REGP */
3674
3675 uint8_t a = (GPR (OP[0])) & 0xff;
3676 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3677 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3678 SB (addr, a);
3679 trace_output_32 (sd, addr);
3680 }
3681
3682 /* STR_IMM instructions. */
3683 /* storb . */
3684 void
3685 OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
3686 {
3687 uint8_t a = (OP[0]) & 0xff;
3688 uint32_t addr = OP[1];
3689 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3690 SB (addr, a);
3691 trace_output_32 (sd, addr);
3692 }
3693
3694 /* storb. */
3695 void
3696 OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
3697 {
3698 uint8_t a = (OP[0]) & 0xff;
3699 uint32_t addr = OP[1];
3700 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3701 SB (addr, a);
3702 trace_output_32 (sd, addr);
3703 }
3704
3705 /* storb. */
3706 void
3707 OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
3708 {
3709 uint32_t addr;
3710 uint8_t a = (OP[0]) & 0xff;
3711 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3712
3713 if (OP[1] == 0)
3714 addr = (GPR32 (12)) + OP[2];
3715 else
3716 addr = (GPR32 (13)) + OP[2];
3717
3718 SB (addr, a);
3719 trace_output_32 (sd, addr);
3720 }
3721
3722 /* storb. */
3723 void
3724 OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
3725 {
3726 uint8_t a = (OP[0]) & 0xff;
3727 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3728 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3729 SB (addr, a);
3730 trace_output_32 (sd, addr);
3731 }
3732
3733 /* storb. */
3734 void
3735 OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
3736 {
3737 uint8_t a = (OP[0]) & 0xff;
3738 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3739 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3740 SB (addr, a);
3741 trace_output_32 (sd, addr);
3742 }
3743
3744 /* storb. */
3745 void
3746 OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
3747 {
3748 uint8_t a = (OP[0]) & 0xff;
3749 uint32_t addr = (GPR (OP[2])) + OP[1];
3750 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3751 SB (addr, a);
3752 trace_output_32 (sd, addr);
3753 }
3754
3755 /* storb. */
3756 void
3757 OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
3758 {
3759 uint8_t a = (OP[0]) & 0xff;
3760 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3761 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3762 SB (addr, a);
3763 trace_output_32 (sd, addr);
3764 }
3765
3766 /* storb. */
3767 void
3768 OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
3769 {
3770 uint8_t a = (OP[0]) & 0xff;
3771 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3772 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3773 SB (addr, a);
3774 trace_output_32 (sd, addr);
3775 }
3776
3777 /* storb. */
3778 void
3779 OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
3780 {
3781 uint8_t a = (OP[0]) & 0xff;
3782 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3783 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3784 SB (addr, a);
3785 trace_output_32 (sd, addr);
3786 }
3787 /* endif for STR_IMM. */
3788
3789 /* storw . */
3790 void
3791 OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
3792 {
3793 uint16_t a = GPR (OP[0]);
3794 uint32_t addr = OP[1];
3795 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3796 SW (addr, a);
3797 trace_output_32 (sd, addr);
3798 }
3799
3800 /* storw. */
3801 void
3802 OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
3803 {
3804 uint16_t a = GPR (OP[0]);
3805 uint32_t addr = OP[1];
3806 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3807 SW (addr, a);
3808 trace_output_32 (sd, addr);
3809 }
3810
3811 /* storw. */
3812 void
3813 OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
3814 {
3815 uint32_t addr;
3816 uint16_t a = GPR (OP[0]);
3817 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3818
3819 if (OP[1] == 0)
3820 addr = (GPR32 (12)) + OP[2];
3821 else
3822 addr = (GPR32 (13)) + OP[2];
3823
3824 SW (addr, a);
3825 trace_output_32 (sd, addr);
3826 }
3827
3828
3829 /* storw. */
3830 void
3831 OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
3832 {
3833 uint16_t a = (GPR (OP[0]));
3834 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3835 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3836 SW (addr, a);
3837 trace_output_32 (sd, addr);
3838 }
3839
3840 /* storw. */
3841 void
3842 OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
3843 {
3844 uint16_t a = GPR (OP[0]);
3845 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3846 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3847 SW (addr, a);
3848 trace_output_32 (sd, addr);
3849 }
3850
3851 /* storw. */
3852 void
3853 OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
3854 {
3855 uint16_t a = GPR (OP[0]);
3856 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3857 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3858 SW (addr, a);
3859 trace_output_32 (sd, addr);
3860 }
3861
3862 /* storw. */
3863 void
3864 OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
3865 {
3866 uint16_t a = (GPR (OP[0]));
3867 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3868 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3869 SW (addr, a);
3870 trace_output_32 (sd, addr);
3871 }
3872
3873 /* storw. */
3874 void
3875 OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
3876 {
3877 uint16_t a = (GPR (OP[0]));
3878 uint32_t addr = (GPR (OP[2])) + OP[1];
3879 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3880 SW (addr, a);
3881 trace_output_32 (sd, addr);
3882 }
3883
3884 /* storw. */
3885 void
3886 OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
3887 {
3888 uint16_t a = (GPR (OP[0]));
3889 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3890 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3891 SW (addr, a);
3892 trace_output_32 (sd, addr);
3893 }
3894
3895 /* storw. */
3896 void
3897 OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
3898 {
3899 uint16_t a = (GPR (OP[0]));
3900 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3901 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3902 SW (addr, a);
3903 trace_output_32 (sd, addr);
3904 }
3905
3906 /* storw. */
3907 void
3908 OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
3909 {
3910 uint16_t a = (GPR (OP[0]));
3911 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3912 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3913 SW (addr, a);
3914 trace_output_32 (sd, addr);
3915 }
3916
3917 /* storw. */
3918 void
3919 OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
3920 {
3921 uint16_t a = (GPR (OP[0]));
3922 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3923 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3924 SW (addr, a);
3925 trace_output_32 (sd, addr);
3926 }
3927
3928 /* STORE-w IMM instruction *****/
3929 /* storw . */
3930 void
3931 OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
3932 {
3933 uint16_t a = OP[0];
3934 uint32_t addr = OP[1];
3935 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3936 SW (addr, a);
3937 trace_output_32 (sd, addr);
3938 }
3939
3940 /* storw. */
3941 void
3942 OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
3943 {
3944 uint16_t a = OP[0];
3945 uint32_t addr = OP[1];
3946 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3947 SW (addr, a);
3948 trace_output_32 (sd, addr);
3949 }
3950
3951 /* storw. */
3952 void
3953 OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
3954 {
3955 uint32_t addr;
3956 uint16_t a = OP[0];
3957 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3958
3959 if (OP[1] == 0)
3960 addr = (GPR32 (12)) + OP[2];
3961 else
3962 addr = (GPR32 (13)) + OP[2];
3963
3964 SW (addr, a);
3965 trace_output_32 (sd, addr);
3966 }
3967
3968 /* storw. */
3969 void
3970 OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
3971 {
3972 uint16_t a = OP[0];
3973 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3974 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3975 SW (addr, a);
3976 trace_output_32 (sd, addr);
3977 }
3978
3979 /* storw. */
3980 void
3981 OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
3982 {
3983 uint16_t a = OP[0];
3984 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3985 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3986 SW (addr, a);
3987 trace_output_32 (sd, addr);
3988 }
3989
3990 /* storw. */
3991 void
3992 OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
3993 {
3994 uint16_t a = OP[0];
3995 uint32_t addr = (GPR32 (OP[2])) + OP[1];
3996 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3997 SW (addr, a);
3998 trace_output_32 (sd, addr);
3999 }
4000
4001 /* storw. */
4002 void
4003 OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
4004 {
4005 uint16_t a = OP[0];
4006 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4007 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4008 SW (addr, a);
4009 trace_output_32 (sd, addr);
4010 }
4011
4012
4013 /* storw. */
4014 void
4015 OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
4016 {
4017 uint16_t a = OP[0];
4018 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4019 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4020 SW (addr, a);
4021 trace_output_32 (sd, addr);
4022 }
4023
4024 /* storw. */
4025 void
4026 OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
4027 {
4028 uint16_t a = OP[0];
4029 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4030 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4031 SW (addr, a);
4032 trace_output_32 (sd, addr);
4033 }
4034
4035
4036 /* stord. */
4037 void
4038 OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
4039 {
4040 uint32_t a = GPR32 (OP[0]);
4041 uint32_t addr = OP[1];
4042 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4043 SLW (addr, a);
4044 trace_output_32 (sd, addr);
4045 }
4046
4047 /* stord. */
4048 void
4049 OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
4050 {
4051 uint32_t a = GPR32 (OP[0]);
4052 uint32_t addr = OP[1];
4053 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4054 SLW (addr, a);
4055 trace_output_32 (sd, addr);
4056 }
4057
4058 /* stord. */
4059 void
4060 OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
4061 {
4062 uint32_t addr, a = GPR32 (OP[0]);
4063 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4064
4065 if (OP[1] == 0)
4066 addr = (GPR32 (12)) + OP[2];
4067 else
4068 addr = (GPR32 (13)) + OP[2];
4069
4070 SLW (addr, a);
4071 trace_output_32 (sd, addr);
4072 }
4073
4074 /* stord. */
4075 void
4076 OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
4077 {
4078 uint32_t a = GPR32 (OP[0]);
4079 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4080 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4081 SLW (addr, a);
4082 trace_output_32 (sd, addr);
4083 }
4084
4085 /* stord. */
4086 void
4087 OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
4088 {
4089 uint32_t a = GPR32 (OP[0]);
4090 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4091 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4092 SLW (addr, a);
4093 trace_output_32 (sd, addr);
4094 }
4095
4096 /* stord. */
4097 void
4098 OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
4099 {
4100 uint32_t a = GPR32 (OP[0]);
4101 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4102 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4103 SLW (addr, a);
4104 trace_output_32 (sd, addr);
4105 }
4106
4107 /* stord. */
4108 void
4109 OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
4110 {
4111 uint32_t a = GPR32 (OP[0]);
4112 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4113 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4114 SLW (addr, a);
4115 trace_output_32 (sd, addr);
4116 }
4117
4118 /* stord. */
4119 void
4120 OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
4121 {
4122 uint32_t a = GPR32 (OP[0]);
4123 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4124 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4125 SLW (addr, a);
4126 trace_output_32 (sd, addr);
4127 }
4128
4129 /* stord. */
4130 void
4131 OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
4132 {
4133 uint32_t a = GPR32 (OP[0]);
4134 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4135 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4136 SLW (addr, a);
4137 trace_output_32 (sd, addr);
4138 }
4139
4140 /* stord. */
4141 void
4142 OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
4143 {
4144 uint32_t a = GPR32 (OP[0]);
4145 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4146 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4147 SLW (addr, a);
4148 trace_output_32 (sd, addr);
4149 }
4150
4151 /* stord. */
4152 void
4153 OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
4154 {
4155 uint32_t a = GPR32 (OP[0]);
4156 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4157 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4158 SLW (addr, a);
4159 trace_output_32 (sd, addr);
4160 }
4161
4162 /* stord. */
4163 void
4164 OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
4165 {
4166 uint32_t a = GPR32 (OP[0]);
4167 uint32_t addr = (GPR32 (OP[2])) + OP[1];
4168 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4169 SLW (addr, a);
4170 trace_output_32 (sd, addr);
4171 }
4172
4173 /* macqu. */
4174 void
4175 OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
4176 {
4177 int32_t tmp;
4178 int16_t src1, src2;
4179 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4180 src1 = GPR (OP[0]);
4181 src2 = GPR (OP[1]);
4182 tmp = src1 * src2;
4183 /*REVISIT FOR SATURATION and Q FORMAT. */
4184 SET_GPR32 (OP[2], tmp);
4185 trace_output_32 (sd, tmp);
4186 }
4187
4188 /* macuw. */
4189 void
4190 OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
4191 {
4192 uint32_t tmp;
4193 uint16_t src1, src2;
4194 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4195 src1 = GPR (OP[0]);
4196 src2 = GPR (OP[1]);
4197 tmp = src1 * src2;
4198 /*REVISIT FOR SATURATION. */
4199 SET_GPR32 (OP[2], tmp);
4200 trace_output_32 (sd, tmp);
4201 }
4202
4203 /* macsw. */
4204 void
4205 OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
4206 {
4207 int32_t tmp;
4208 int16_t src1, src2;
4209 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4210 src1 = GPR (OP[0]);
4211 src2 = GPR (OP[1]);
4212 tmp = src1 * src2;
4213 /*REVISIT FOR SATURATION. */
4214 SET_GPR32 (OP[2], tmp);
4215 trace_output_32 (sd, tmp);
4216 }
4217
4218
4219 /* mulb. */
4220 void
4221 OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
4222 {
4223 int16_t tmp;
4224 int8_t a = (OP[0]) & 0xff;
4225 int8_t b = (GPR (OP[1])) & 0xff;
4226 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4227 tmp = (a * b) & 0xff;
4228 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4229 trace_output_16 (sd, tmp);
4230 }
4231
4232 /* mulb. */
4233 void
4234 OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
4235 {
4236 int16_t tmp;
4237 int8_t a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4238 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4239 tmp = (a * b) & 0xff;
4240 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4241 trace_output_16 (sd, tmp);
4242 }
4243
4244
4245 /* mulb. */
4246 void
4247 OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
4248 {
4249 int16_t tmp;
4250 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4251 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4252 tmp = (a * b) & 0xff;
4253 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4254 trace_output_16 (sd, tmp);
4255 }
4256
4257
4258 /* mulw. */
4259 void
4260 OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
4261 {
4262 int32_t tmp;
4263 uint16_t a = OP[0];
4264 int16_t b = (GPR (OP[1]));
4265 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4266 tmp = (a * b) & 0xffff;
4267 SET_GPR (OP[1], tmp);
4268 trace_output_32 (sd, tmp);
4269 }
4270
4271 /* mulw. */
4272 void
4273 OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
4274 {
4275 int32_t tmp;
4276 int16_t a = OP[0], b = (GPR (OP[1]));
4277 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4278 tmp = (a * b) & 0xffff;
4279 SET_GPR (OP[1], tmp);
4280 trace_output_32 (sd, tmp);
4281 }
4282
4283
4284 /* mulw. */
4285 void
4286 OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
4287 {
4288 int32_t tmp;
4289 int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
4290 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4291 tmp = (a * b) & 0xffff;
4292 SET_GPR (OP[1], tmp);
4293 trace_output_32 (sd, tmp);
4294 }
4295
4296
4297 /* mulsb. */
4298 void
4299 OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
4300 {
4301 int16_t tmp;
4302 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4303 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4304 tmp = a * b;
4305 SET_GPR (OP[1], tmp);
4306 trace_output_32 (sd, tmp);
4307 }
4308
4309 /* mulsw. */
4310 void
4311 OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
4312 {
4313 int32_t tmp;
4314 int16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
4315 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4316 tmp = a * b;
4317 SET_GPR32 (OP[1], tmp);
4318 trace_output_32 (sd, tmp);
4319 }
4320
4321 /* muluw. */
4322 void
4323 OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
4324 {
4325 uint32_t tmp;
4326 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
4327 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4328 tmp = a * b;
4329 SET_GPR32 (OP[1], tmp);
4330 trace_output_32 (sd, tmp);
4331 }
4332
4333
4334 /* nop. */
4335 void
4336 OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
4337 {
4338 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4339
4340 #if 0
4341 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4342 switch (State.ins_type)
4343 {
4344 default:
4345 ins_type_counters[ (int)INS_UNKNOWN ]++;
4346 break;
4347
4348 }
4349 EXCEPTION (SIM_SIGTRAP);
4350 #endif
4351 trace_output_void (sd);
4352 }
4353
4354
4355 /* orb. */
4356 void
4357 OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
4358 {
4359 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4360 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4361 tmp = a | b;
4362 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4363 trace_output_16 (sd, tmp);
4364 }
4365
4366 /* orb. */
4367 void
4368 OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
4369 {
4370 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4371 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4372 tmp = a | b;
4373 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4374 trace_output_16 (sd, tmp);
4375 }
4376
4377 /* orb. */
4378 void
4379 OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
4380 {
4381 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4382 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4383 tmp = a | b;
4384 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4385 trace_output_16 (sd, tmp);
4386 }
4387
4388 /* orw. */
4389 void
4390 OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
4391 {
4392 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
4393 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4394 tmp = a | b;
4395 SET_GPR (OP[1], tmp);
4396 trace_output_16 (sd, tmp);
4397 }
4398
4399
4400 /* orw. */
4401 void
4402 OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
4403 {
4404 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
4405 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4406 tmp = a | b;
4407 SET_GPR (OP[1], tmp);
4408 trace_output_16 (sd, tmp);
4409 }
4410
4411 /* orw. */
4412 void
4413 OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
4414 {
4415 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4416 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4417 tmp = a | b;
4418 SET_GPR (OP[1], tmp);
4419 trace_output_16 (sd, tmp);
4420 }
4421
4422
4423 /* lshb. */
4424 void
4425 OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
4426 {
4427 uint16_t a = OP[0];
4428 uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
4429 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4430 /* A positive count specifies a shift to the left;
4431 * A negative count specifies a shift to the right. */
4432 if (sign_flag)
4433 tmp = b >> a;
4434 else
4435 tmp = b << a;
4436
4437 sign_flag = 0; /* Reset sign_flag. */
4438
4439 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4440 trace_output_16 (sd, tmp);
4441 }
4442
4443 /* lshb. */
4444 void
4445 OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
4446 {
4447 uint16_t a = (GPR (OP[0])) & 0xff;
4448 uint16_t tmp, b = (GPR (OP[1])) & 0xFF;
4449 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4450 if (a & ((long)1 << 3))
4451 {
4452 sign_flag = 1;
4453 a = ~(a) + 1;
4454 }
4455 a = (unsigned int) (a & 0x7);
4456
4457 /* A positive count specifies a shift to the left;
4458 * A negative count specifies a shift to the right. */
4459 if (sign_flag)
4460 tmp = b >> a;
4461 else
4462 tmp = b << a;
4463
4464 sign_flag = 0; /* Reset sign_flag. */
4465 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4466 trace_output_16 (sd, tmp);
4467 }
4468
4469 /* lshw. */
4470 void
4471 OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
4472 {
4473 uint16_t tmp, b = GPR (OP[1]);
4474 int16_t a = GPR (OP[0]);
4475 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4476 if (a & ((long)1 << 4))
4477 {
4478 sign_flag = 1;
4479 a = ~(a) + 1;
4480 }
4481 a = (unsigned int) (a & 0xf);
4482
4483 /* A positive count specifies a shift to the left;
4484 * A negative count specifies a shift to the right. */
4485 if (sign_flag)
4486 tmp = b >> a;
4487 else
4488 tmp = b << a;
4489
4490 sign_flag = 0; /* Reset sign_flag. */
4491 SET_GPR (OP[1], (tmp & 0xffff));
4492 trace_output_16 (sd, tmp);
4493 }
4494
4495 /* lshw. */
4496 void
4497 OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
4498 {
4499 uint16_t tmp, b = GPR (OP[1]);
4500 uint16_t a = OP[0];
4501 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4502 /* A positive count specifies a shift to the left;
4503 * A negative count specifies a shift to the right. */
4504 if (sign_flag)
4505 tmp = b >> a;
4506 else
4507 tmp = b << a;
4508
4509 sign_flag = 0; /* Reset sign_flag. */
4510 SET_GPR (OP[1], (tmp & 0xffff));
4511 trace_output_16 (sd, tmp);
4512 }
4513
4514 /* lshd. */
4515 void
4516 OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
4517 {
4518 uint32_t tmp, b = GPR32 (OP[1]);
4519 uint16_t a = OP[0];
4520 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4521 /* A positive count specifies a shift to the left;
4522 * A negative count specifies a shift to the right. */
4523 if (sign_flag)
4524 tmp = b >> a;
4525 else
4526 tmp = b << a;
4527
4528 sign_flag = 0; /* Reset sign flag. */
4529
4530 SET_GPR32 (OP[1], tmp);
4531 trace_output_32 (sd, tmp);
4532 }
4533
4534 /* lshd. */
4535 void
4536 OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
4537 {
4538 uint32_t tmp, b = GPR32 (OP[1]);
4539 uint16_t a = GPR (OP[0]);
4540 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4541 if (a & ((long)1 << 5))
4542 {
4543 sign_flag = 1;
4544 a = ~(a) + 1;
4545 }
4546 a = (unsigned int) (a & 0x1f);
4547 /* A positive count specifies a shift to the left;
4548 * A negative count specifies a shift to the right. */
4549 if (sign_flag)
4550 tmp = b >> a;
4551 else
4552 tmp = b << a;
4553
4554 sign_flag = 0; /* Reset sign flag. */
4555
4556 SET_GPR32 (OP[1], tmp);
4557 trace_output_32 (sd, tmp);
4558 }
4559
4560 /* ashub. */
4561 void
4562 OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
4563 {
4564 uint16_t a = OP[0];
4565 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
4566 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4567 /* A positive count specifies a shift to the left;
4568 * A negative count specifies a shift to the right. */
4569 if (sign_flag)
4570 tmp = b >> a;
4571 else
4572 tmp = b << a;
4573
4574 sign_flag = 0; /* Reset sign flag. */
4575
4576 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4577 trace_output_16 (sd, tmp);
4578 }
4579
4580 /* ashub. */
4581 void
4582 OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
4583 {
4584 uint16_t a = OP[0];
4585 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
4586 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4587 /* A positive count specifies a shift to the left;
4588 * A negative count specifies a shift to the right. */
4589 if (sign_flag)
4590 tmp = b >> a;
4591 else
4592 tmp = b << a;
4593
4594 sign_flag = 0; /* Reset sign flag. */
4595
4596 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4597 trace_output_16 (sd, tmp);
4598 }
4599
4600
4601 /* ashub. */
4602 void
4603 OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
4604 {
4605 int16_t a = (GPR (OP[0]));
4606 int8_t tmp, b = (GPR (OP[1])) & 0xFF;
4607 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4608
4609 if (a & ((long)1 << 3))
4610 {
4611 sign_flag = 1;
4612 a = ~(a) + 1;
4613 }
4614 a = (unsigned int) (a & 0x7);
4615
4616 /* A positive count specifies a shift to the left;
4617 * A negative count specifies a shift to the right. */
4618 if (sign_flag)
4619 tmp = b >> a;
4620 else
4621 tmp = b << a;
4622
4623 sign_flag = 0; /* Reset sign flag. */
4624
4625 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4626 trace_output_16 (sd, tmp);
4627 }
4628
4629
4630 /* ashuw. */
4631 void
4632 OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
4633 {
4634 int16_t tmp, b = GPR (OP[1]);
4635 uint16_t a = OP[0];
4636 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4637 /* A positive count specifies a shift to the left;
4638 * A negative count specifies a shift to the right. */
4639 if (sign_flag)
4640 tmp = b >> a;
4641 else
4642 tmp = b << a;
4643
4644 sign_flag = 0; /* Reset sign flag. */
4645
4646 SET_GPR (OP[1], (tmp & 0xffff));
4647 trace_output_16 (sd, tmp);
4648 }
4649
4650 /* ashuw. */
4651 void
4652 OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
4653 {
4654 int16_t tmp, b = GPR (OP[1]);
4655 uint16_t a = OP[0];
4656 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4657 /* A positive count specifies a shift to the left;
4658 * A negative count specifies a shift to the right. */
4659 if (sign_flag)
4660 tmp = b >> a;
4661 else
4662 tmp = b << a;
4663
4664 sign_flag = 0; /* Reset sign flag. */
4665 SET_GPR (OP[1], (tmp & 0xffff));
4666 trace_output_16 (sd, tmp);
4667 }
4668
4669 /* ashuw. */
4670 void
4671 OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
4672 {
4673 int16_t tmp;
4674 int16_t a = GPR (OP[0]), b = GPR (OP[1]);
4675 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4676
4677 if (a & ((long)1 << 4))
4678 {
4679 sign_flag = 1;
4680 a = ~(a) + 1;
4681 }
4682 a = (unsigned int) (a & 0xf);
4683 /* A positive count specifies a shift to the left;
4684 * A negative count specifies a shift to the right. */
4685
4686 if (sign_flag)
4687 tmp = b >> a;
4688 else
4689 tmp = b << a;
4690
4691 sign_flag = 0; /* Reset sign flag. */
4692 SET_GPR (OP[1], (tmp & 0xffff));
4693 trace_output_16 (sd, tmp);
4694 }
4695
4696 /* ashud. */
4697 void
4698 OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
4699 {
4700 int32_t tmp,b = GPR32 (OP[1]);
4701 uint32_t a = OP[0];
4702 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4703 /* A positive count specifies a shift to the left;
4704 * A negative count specifies a shift to the right. */
4705 if (sign_flag)
4706 tmp = b >> a;
4707 else
4708 tmp = b << a;
4709
4710 sign_flag = 0; /* Reset sign flag. */
4711 SET_GPR32 (OP[1], tmp);
4712 trace_output_32 (sd, tmp);
4713 }
4714
4715 /* ashud. */
4716 void
4717 OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
4718 {
4719 int32_t tmp;
4720 int32_t a = OP[0], b = GPR32 (OP[1]);
4721 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4722 /* A positive count specifies a shift to the left;
4723 * A negative count specifies a shift to the right. */
4724 if (sign_flag)
4725 tmp = b >> a;
4726 else
4727 tmp = b << a;
4728
4729 sign_flag = 0; /* Reset sign flag. */
4730 SET_GPR32 (OP[1], tmp);
4731 trace_output_32 (sd, tmp);
4732 }
4733
4734 /* ashud. */
4735 void
4736 OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
4737 {
4738 int32_t tmp;
4739 int32_t a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4740 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4741
4742 if (a & ((long)1 << 5))
4743 {
4744 sign_flag = 1;
4745 a = ~(a) + 1;
4746 }
4747 a = (unsigned int) (a & 0x1f);
4748 /* A positive count specifies a shift to the left;
4749 * A negative count specifies a shift to the right. */
4750 if (sign_flag)
4751 tmp = b >> a;
4752 else
4753 tmp = b << a;
4754
4755 sign_flag = 0; /* Reset sign flag. */
4756 SET_GPR32 (OP[1], tmp);
4757 trace_output_32 (sd, tmp);
4758 }
4759
4760
4761 /* storm. */
4762 void
4763 OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
4764 {
4765 uint32_t addr = GPR (1);
4766 uint16_t count = OP[0], reg = 2;
4767 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4768 if ((addr & 1))
4769 {
4770 trace_output_void (sd);
4771 EXCEPTION (SIM_SIGBUS);
4772 }
4773
4774 while (count)
4775 {
4776 SW (addr, (GPR (reg)));
4777 addr +=2;
4778 --count;
4779 reg++;
4780 if (reg == 6) reg = 8;
4781 };
4782
4783 SET_GPR (1, addr);
4784
4785 trace_output_void (sd);
4786 }
4787
4788
4789 /* stormp. */
4790 void
4791 OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
4792 {
4793 uint32_t addr = GPR32 (6);
4794 uint16_t count = OP[0], reg = 2;
4795 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4796 if ((addr & 1))
4797 {
4798 trace_output_void (sd);
4799 EXCEPTION (SIM_SIGBUS);
4800 }
4801
4802 while (count)
4803 {
4804 SW (addr, (GPR (reg)));
4805 addr +=2;
4806 --count;
4807 reg++;
4808 if (reg == 6) reg = 8;
4809 };
4810
4811 SET_GPR32 (6, addr);
4812 trace_output_void (sd);
4813 }
4814
4815 /* subb. */
4816 void
4817 OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
4818 {
4819 uint8_t a = OP[0];
4820 uint8_t b = (GPR (OP[1])) & 0xff;
4821 uint16_t tmp = (~a + 1 + b) & 0xff;
4822 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4823 /* see ../common/sim-alu.h for a more extensive discussion on how to
4824 compute the carry/overflow bits. */
4825 SET_PSR_C (tmp > 0xff);
4826 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4827 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4828 trace_output_16 (sd, tmp);
4829 }
4830
4831 /* subb. */
4832 void
4833 OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
4834 {
4835 uint8_t a = OP[0] & 0xFF;
4836 uint8_t b = (GPR (OP[1])) & 0xFF;
4837 uint16_t tmp = (~a + 1 + b) & 0xFF;
4838 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4839 /* see ../common/sim-alu.h for a more extensive discussion on how to
4840 compute the carry/overflow bits. */
4841 SET_PSR_C (tmp > 0xff);
4842 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4843 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4844 trace_output_16 (sd, tmp);
4845 }
4846
4847 /* subb. */
4848 void
4849 OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
4850 {
4851 uint8_t a = (GPR (OP[0])) & 0xFF;
4852 uint8_t b = (GPR (OP[1])) & 0xFF;
4853 uint16_t tmp = (~a + 1 + b) & 0xff;
4854 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4855 /* see ../common/sim-alu.h for a more extensive discussion on how to
4856 compute the carry/overflow bits. */
4857 SET_PSR_C (tmp > 0xff);
4858 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4859 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4860 trace_output_16 (sd, tmp);
4861 }
4862
4863 /* subw. */
4864 void
4865 OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
4866 {
4867 uint16_t a = OP[0];
4868 uint16_t b = GPR (OP[1]);
4869 uint16_t tmp = (~a + 1 + b);
4870 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4871 /* see ../common/sim-alu.h for a more extensive discussion on how to
4872 compute the carry/overflow bits. */
4873 SET_PSR_C (tmp > 0xffff);
4874 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4875 SET_GPR (OP[1], tmp);
4876 trace_output_16 (sd, tmp);
4877 }
4878
4879 /* subw. */
4880 void
4881 OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
4882 {
4883 uint16_t a = OP[0];
4884 uint16_t b = GPR (OP[1]);
4885 uint32_t tmp = (~a + 1 + b);
4886 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4887 /* see ../common/sim-alu.h for a more extensive discussion on how to
4888 compute the carry/overflow bits. */
4889 SET_PSR_C (tmp > 0xffff);
4890 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4891 SET_GPR (OP[1], tmp & 0xffff);
4892 trace_output_16 (sd, tmp);
4893 }
4894
4895 /* subw. */
4896 void
4897 OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
4898 {
4899 uint16_t a = GPR (OP[0]);
4900 uint16_t b = GPR (OP[1]);
4901 uint32_t tmp = (~a + 1 + b);
4902 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4903 /* see ../common/sim-alu.h for a more extensive discussion on how to
4904 compute the carry/overflow bits. */
4905 SET_PSR_C (tmp > 0xffff);
4906 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4907 SET_GPR (OP[1], tmp & 0xffff);
4908 trace_output_16 (sd, tmp);
4909 }
4910
4911 /* subcb. */
4912 void
4913 OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
4914 {
4915 uint8_t a = OP[0];
4916 uint8_t b = (GPR (OP[1])) & 0xff;
4917 //uint16_t tmp1 = a + 1;
4918 uint16_t tmp1 = a + (PSR_C);
4919 uint16_t tmp = (~tmp1 + 1 + b);
4920 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4921 /* see ../common/sim-alu.h for a more extensive discussion on how to
4922 compute the carry/overflow bits. */
4923 SET_PSR_C (tmp > 0xff);
4924 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4925 SET_GPR (OP[1], tmp);
4926 trace_output_16 (sd, tmp);
4927 }
4928
4929 /* subcb. */
4930 void
4931 OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
4932 {
4933 uint16_t a = OP[0];
4934 uint16_t b = (GPR (OP[1])) & 0xff;
4935 //uint16_t tmp1 = a + 1;
4936 uint16_t tmp1 = a + (PSR_C);
4937 uint16_t tmp = (~tmp1 + 1 + b);
4938 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4939 /* see ../common/sim-alu.h for a more extensive discussion on how to
4940 compute the carry/overflow bits. */
4941 SET_PSR_C (tmp > 0xff);
4942 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4943 SET_GPR (OP[1], tmp);
4944 trace_output_16 (sd, tmp);
4945 }
4946
4947 /* subcb. */
4948 void
4949 OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
4950 {
4951 uint16_t a = (GPR (OP[0])) & 0xff;
4952 uint16_t b = (GPR (OP[1])) & 0xff;
4953 uint16_t tmp1 = a + (PSR_C);
4954 uint16_t tmp = (~tmp1 + 1 + b);
4955 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4956 /* see ../common/sim-alu.h for a more extensive discussion on how to
4957 compute the carry/overflow bits. */
4958 SET_PSR_C (tmp > 0xff);
4959 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4960 SET_GPR (OP[1], tmp);
4961 trace_output_16 (sd, tmp);
4962 }
4963
4964 /* subcw. */
4965 void
4966 OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
4967 {
4968 uint16_t a = OP[0], b = (GPR (OP[1]));
4969 uint16_t tmp1 = a + (PSR_C);
4970 uint16_t tmp = (~tmp1 + 1 + b);
4971 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4972 /* see ../common/sim-alu.h for a more extensive discussion on how to
4973 compute the carry/overflow bits. */
4974 SET_PSR_C (tmp > 0xffff);
4975 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4976 SET_GPR (OP[1], tmp);
4977 trace_output_16 (sd, tmp);
4978 }
4979
4980 /* subcw. */
4981 void
4982 OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
4983 {
4984 int16_t a = OP[0];
4985 uint16_t b = GPR (OP[1]);
4986 uint16_t tmp1 = a + (PSR_C);
4987 uint16_t tmp = (~tmp1 + 1 + b);
4988 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
4989 /* see ../common/sim-alu.h for a more extensive discussion on how to
4990 compute the carry/overflow bits. */
4991 SET_PSR_C (tmp > 0xffff);
4992 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4993 SET_GPR (OP[1], tmp);
4994 trace_output_16 (sd, tmp);
4995 }
4996
4997 /* subcw. */
4998 void
4999 OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
5000 {
5001 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1]));
5002 uint16_t tmp1 = a + (PSR_C);
5003 uint16_t tmp = (~tmp1 + 1 + b);
5004 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5005 /* see ../common/sim-alu.h for a more extensive discussion on how to
5006 compute the carry/overflow bits. */
5007 SET_PSR_C (tmp > 0xffff);
5008 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5009 SET_GPR (OP[1], tmp);
5010 trace_output_16 (sd, tmp);
5011 }
5012
5013 /* subd. */
5014 void
5015 OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
5016 {
5017 int32_t a = OP[0];
5018 uint32_t b = GPR32 (OP[1]);
5019 uint32_t tmp = (~a + 1 + b);
5020 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5021 /* see ../common/sim-alu.h for a more extensive discussion on how to
5022 compute the carry/overflow bits. */
5023 SET_PSR_C (tmp > 0xffffffff);
5024 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5025 ((b & 0x80000000) != (tmp & 0x80000000)));
5026 SET_GPR32 (OP[1], tmp);
5027 trace_output_32 (sd, tmp);
5028 }
5029
5030 /* subd. */
5031 void
5032 OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
5033 {
5034 uint32_t a = GPR32 (OP[0]);
5035 uint32_t b = GPR32 (OP[1]);
5036 uint32_t tmp = (~a + 1 + b);
5037 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5038 /* see ../common/sim-alu.h for a more extensive discussion on how to
5039 compute the carry/overflow bits. */
5040 SET_PSR_C (tmp > 0xffffffff);
5041 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5042 ((b & 0x80000000) != (tmp & 0x80000000)));
5043 SET_GPR32 (OP[1], tmp);
5044 trace_output_32 (sd, tmp);
5045 }
5046
5047 /* excp. */
5048 void
5049 OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
5050 {
5051 host_callback *cb = STATE_CALLBACK (sd);
5052 uint32_t tmp;
5053 uint16_t a;
5054 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5055 switch (OP[0])
5056 {
5057 default:
5058 #if (DEBUG & DEBUG_TRAP) == 0
5059 {
5060 #if 0
5061 uint16_t vec = OP[0] + TRAP_VECTOR_START;
5062 SET_BPC (PC + 1);
5063 SET_BPSR (PSR);
5064 SET_PSR (PSR & PSR_SM_BIT);
5065 JMP (vec);
5066 break;
5067 #endif
5068 }
5069 #else /* if debugging use trap to print registers */
5070 {
5071 int i;
5072 static int first_time = 1;
5073
5074 if (first_time)
5075 {
5076 first_time = 0;
5077 sim_io_printf (sd, "Trap # PC ");
5078 for (i = 0; i < 16; i++)
5079 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
5080 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
5081 }
5082
5083 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5084
5085 for (i = 0; i < 16; i++)
5086 sim_io_printf (sd, " %.4x", (int) GPR (i));
5087
5088 for (i = 0; i < 2; i++)
5089 sim_io_printf (sd, " %.2x%.8lx",
5090 ((int)(ACC (i) >> 32) & 0xff),
5091 ((unsigned long) ACC (i)) & 0xffffffff);
5092
5093 sim_io_printf (sd, " %d %d %d\n",
5094 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5095 sim_io_flush_stdout (sd);
5096 break;
5097 }
5098 #endif
5099 case 8: /* new system call trap */
5100 /* Trap 8 is used for simulating low-level I/O */
5101 {
5102 uint32_t result = 0;
5103 errno = 0;
5104
5105 /* Registers passed to trap 0. */
5106
5107 #define FUNC GPR (0) /* function number. */
5108 #define PARM1 GPR (2) /* optional parm 1. */
5109 #define PARM2 GPR (3) /* optional parm 2. */
5110 #define PARM3 GPR (4) /* optional parm 3. */
5111 #define PARM4 GPR (5) /* optional parm 4. */
5112
5113 /* Registers set by trap 0 */
5114
5115 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5116 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5117 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5118
5119 /* Turn a pointer in a register into a pointer into real memory. */
5120
5121 #define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
5122
5123 switch (FUNC)
5124 {
5125 #if !defined(__GO32__) && !defined(_WIN32)
5126 case TARGET_NEWLIB_CR16_SYS_fork:
5127 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5128 RETVAL (fork ());
5129 trace_output_16 (sd, result);
5130 break;
5131
5132 #define getpid() 47
5133 case TARGET_NEWLIB_CR16_SYS_getpid:
5134 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5135 RETVAL (getpid ());
5136 trace_output_16 (sd, result);
5137 break;
5138
5139 case TARGET_NEWLIB_CR16_SYS_kill:
5140 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5141 if (PARM1 == getpid ())
5142 {
5143 trace_output_void (sd);
5144 EXCEPTION (PARM2);
5145 }
5146 else
5147 {
5148 int os_sig = -1;
5149 switch (PARM2)
5150 {
5151 #ifdef SIGHUP
5152 case 1: os_sig = SIGHUP; break;
5153 #endif
5154 #ifdef SIGINT
5155 case 2: os_sig = SIGINT; break;
5156 #endif
5157 #ifdef SIGQUIT
5158 case 3: os_sig = SIGQUIT; break;
5159 #endif
5160 #ifdef SIGILL
5161 case 4: os_sig = SIGILL; break;
5162 #endif
5163 #ifdef SIGTRAP
5164 case 5: os_sig = SIGTRAP; break;
5165 #endif
5166 #ifdef SIGABRT
5167 case 6: os_sig = SIGABRT; break;
5168 #elif defined(SIGIOT)
5169 case 6: os_sig = SIGIOT; break;
5170 #endif
5171 #ifdef SIGEMT
5172 case 7: os_sig = SIGEMT; break;
5173 #endif
5174 #ifdef SIGFPE
5175 case 8: os_sig = SIGFPE; break;
5176 #endif
5177 #ifdef SIGKILL
5178 case 9: os_sig = SIGKILL; break;
5179 #endif
5180 #ifdef SIGBUS
5181 case 10: os_sig = SIGBUS; break;
5182 #endif
5183 #ifdef SIGSEGV
5184 case 11: os_sig = SIGSEGV; break;
5185 #endif
5186 #ifdef SIGSYS
5187 case 12: os_sig = SIGSYS; break;
5188 #endif
5189 #ifdef SIGPIPE
5190 case 13: os_sig = SIGPIPE; break;
5191 #endif
5192 #ifdef SIGALRM
5193 case 14: os_sig = SIGALRM; break;
5194 #endif
5195 #ifdef SIGTERM
5196 case 15: os_sig = SIGTERM; break;
5197 #endif
5198 #ifdef SIGURG
5199 case 16: os_sig = SIGURG; break;
5200 #endif
5201 #ifdef SIGSTOP
5202 case 17: os_sig = SIGSTOP; break;
5203 #endif
5204 #ifdef SIGTSTP
5205 case 18: os_sig = SIGTSTP; break;
5206 #endif
5207 #ifdef SIGCONT
5208 case 19: os_sig = SIGCONT; break;
5209 #endif
5210 #ifdef SIGCHLD
5211 case 20: os_sig = SIGCHLD; break;
5212 #elif defined(SIGCLD)
5213 case 20: os_sig = SIGCLD; break;
5214 #endif
5215 #ifdef SIGTTIN
5216 case 21: os_sig = SIGTTIN; break;
5217 #endif
5218 #ifdef SIGTTOU
5219 case 22: os_sig = SIGTTOU; break;
5220 #endif
5221 #ifdef SIGIO
5222 case 23: os_sig = SIGIO; break;
5223 #elif defined (SIGPOLL)
5224 case 23: os_sig = SIGPOLL; break;
5225 #endif
5226 #ifdef SIGXCPU
5227 case 24: os_sig = SIGXCPU; break;
5228 #endif
5229 #ifdef SIGXFSZ
5230 case 25: os_sig = SIGXFSZ; break;
5231 #endif
5232 #ifdef SIGVTALRM
5233 case 26: os_sig = SIGVTALRM; break;
5234 #endif
5235 #ifdef SIGPROF
5236 case 27: os_sig = SIGPROF; break;
5237 #endif
5238 #ifdef SIGWINCH
5239 case 28: os_sig = SIGWINCH; break;
5240 #endif
5241 #ifdef SIGLOST
5242 case 29: os_sig = SIGLOST; break;
5243 #endif
5244 #ifdef SIGUSR1
5245 case 30: os_sig = SIGUSR1; break;
5246 #endif
5247 #ifdef SIGUSR2
5248 case 31: os_sig = SIGUSR2; break;
5249 #endif
5250 }
5251
5252 if (os_sig == -1)
5253 {
5254 trace_output_void (sd);
5255 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
5256 sim_io_flush_stdout (sd);
5257 EXCEPTION (SIM_SIGILL);
5258 }
5259 else
5260 {
5261 RETVAL (kill (PARM1, PARM2));
5262 trace_output_16 (sd, result);
5263 }
5264 }
5265 break;
5266
5267 case TARGET_NEWLIB_CR16_SYS_execve:
5268 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5269 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5270 (char **)MEMPTR (PARM4)));
5271 trace_output_16 (sd, result);
5272 break;
5273
5274 case TARGET_NEWLIB_CR16_SYS_execv:
5275 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5276 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5277 trace_output_16 (sd, result);
5278 break;
5279
5280 case TARGET_NEWLIB_CR16_SYS_pipe:
5281 {
5282 reg_t buf;
5283 int host_fd[2];
5284
5285 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5286 buf = PARM1;
5287 RETVAL (pipe (host_fd));
5288 SW (buf, host_fd[0]);
5289 buf += sizeof(uint16_t);
5290 SW (buf, host_fd[1]);
5291 trace_output_16 (sd, result);
5292 }
5293 break;
5294
5295 case TARGET_NEWLIB_CR16_SYS_wait:
5296 {
5297 int status;
5298 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5299 RETVAL (wait (&status));
5300 if (PARM1)
5301 SW (PARM1, status);
5302 trace_output_16 (sd, result);
5303 }
5304 break;
5305 #else
5306 case TARGET_NEWLIB_CR16_SYS_getpid:
5307 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5308 RETVAL (1);
5309 trace_output_16 (sd, result);
5310 break;
5311
5312 case TARGET_NEWLIB_CR16_SYS_kill:
5313 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5314 trace_output_void (sd);
5315 EXCEPTION (PARM2);
5316 break;
5317 #endif
5318
5319 case TARGET_NEWLIB_CR16_SYS_read:
5320 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5321 RETVAL (cb->read (cb, PARM1,
5322 MEMPTR (((unsigned long)PARM3 << 16)
5323 | ((unsigned long)PARM2)), PARM4));
5324 trace_output_16 (sd, result);
5325 break;
5326
5327 case TARGET_NEWLIB_CR16_SYS_write:
5328 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5329 RETVAL ((int)cb->write (cb, PARM1,
5330 MEMPTR (((unsigned long)PARM3 << 16)
5331 | PARM2), PARM4));
5332 trace_output_16 (sd, result);
5333 break;
5334
5335 case TARGET_NEWLIB_CR16_SYS_lseek:
5336 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5337 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2),
5338 PARM4));
5339 trace_output_32 (sd, result);
5340 break;
5341
5342 case TARGET_NEWLIB_CR16_SYS_close:
5343 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5344 RETVAL (cb->close (cb, PARM1));
5345 trace_output_16 (sd, result);
5346 break;
5347
5348 case TARGET_NEWLIB_CR16_SYS_open:
5349 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5350 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16)
5351 | PARM1), PARM3));
5352 trace_output_32 (sd, result);
5353 break;
5354
5355 case TARGET_NEWLIB_CR16_SYS_rename:
5356 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5357 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1),
5358 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3)));
5359 trace_output_16 (sd, result);
5360 break;
5361
5362 case 0x408: /* REVISIT: Added a dummy getenv call. */
5363 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5364 RETVAL32 (0);
5365 trace_output_32 (sd, result);
5366 break;
5367
5368 case TARGET_NEWLIB_CR16_SYS_exit:
5369 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5370 trace_output_void (sd);
5371 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5372 break;
5373
5374 case TARGET_NEWLIB_CR16_SYS_unlink:
5375 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5376 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1)));
5377 trace_output_16 (sd, result);
5378 break;
5379
5380 case TARGET_NEWLIB_CR16_SYS_stat:
5381 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5382 /* stat system call. */
5383 {
5384 struct stat host_stat;
5385 reg_t buf;
5386
5387 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5388
5389 buf = PARM2;
5390
5391 /* The hard-coded offsets and sizes were determined by using
5392 * the CR16 compiler on a test program that used struct stat.
5393 */
5394 SW (buf, host_stat.st_dev);
5395 SW (buf+2, host_stat.st_ino);
5396 SW (buf+4, host_stat.st_mode);
5397 SW (buf+6, host_stat.st_nlink);
5398 SW (buf+8, host_stat.st_uid);
5399 SW (buf+10, host_stat.st_gid);
5400 SW (buf+12, host_stat.st_rdev);
5401 SLW (buf+16, host_stat.st_size);
5402 SLW (buf+20, host_stat.st_atime);
5403 SLW (buf+28, host_stat.st_mtime);
5404 SLW (buf+36, host_stat.st_ctime);
5405 }
5406 trace_output_16 (sd, result);
5407 break;
5408
5409 case TARGET_NEWLIB_CR16_SYS_chown:
5410 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5411 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5412 trace_output_16 (sd, result);
5413 break;
5414
5415 case TARGET_NEWLIB_CR16_SYS_chmod:
5416 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5417 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5418 trace_output_16 (sd, result);
5419 break;
5420
5421 case TARGET_NEWLIB_CR16_SYS_utime:
5422 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5423 /* Cast the second argument to void *, to avoid type mismatch
5424 if a prototype is present. */
5425 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5426 trace_output_16 (sd, result);
5427 break;
5428
5429 case TARGET_NEWLIB_CR16_SYS_time:
5430 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5431 RETVAL32 (time (NULL));
5432 trace_output_32 (sd, result);
5433 break;
5434
5435 default:
5436 a = OP[0];
5437 switch (a)
5438 {
5439 case TRAP_BREAKPOINT:
5440 tmp = (PC);
5441 JMP(tmp);
5442 trace_output_void (sd);
5443 EXCEPTION (SIM_SIGTRAP);
5444 break;
5445 case SIGTRAP: /* supervisor call ? */
5446 trace_output_void (sd);
5447 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5448 break;
5449 default:
5450 cb->error (cb, "Unknown syscall %d", FUNC);
5451 break;
5452 }
5453 }
5454 if ((uint16_t) result == (uint16_t) -1)
5455 RETERR (cb->get_errno (cb));
5456 else
5457 RETERR (0);
5458 break;
5459 }
5460 }
5461 }
5462
5463
5464 /* push. */
5465 void
5466 OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
5467 {
5468 uint16_t a = OP[0] + 1, b = OP[1], i = 0;
5469 uint32_t tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5470 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5471
5472 for (; i < a; ++i)
5473 {
5474 if ((b+i) <= 11)
5475 {
5476 SW (sp_addr, (GPR (b+i)));
5477 sp_addr +=2;
5478 }
5479 else
5480 {
5481 if (is_regp == 0)
5482 tmp = (GPR32 (b+i));
5483 else
5484 tmp = (GPR32 (b+i-1));
5485
5486 if ((a-i) > 1)
5487 {
5488 SLW (sp_addr, tmp);
5489 sp_addr +=4;
5490 }
5491 else
5492 {
5493 SW (sp_addr, tmp);
5494 sp_addr +=2;
5495 }
5496 ++i;
5497 is_regp = 1;
5498 }
5499 }
5500
5501 sp_addr +=4;
5502
5503 /* Store RA address. */
5504 tmp = (GPR32 (14));
5505 SLW(sp_addr,tmp);
5506
5507 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5508 SET_GPR32 (15, sp_addr); /* Update SP address. */
5509
5510 trace_output_void (sd);
5511 }
5512
5513 /* push. */
5514 void
5515 OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
5516 {
5517 uint32_t sp_addr, tmp, is_regp = 0;
5518 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5519 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5520
5521 if (c == 1)
5522 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5523 else
5524 sp_addr = (GPR32 (15)) - (a * 2);
5525
5526 for (; i < a; ++i)
5527 {
5528 if ((b+i) <= 11)
5529 {
5530 SW (sp_addr, (GPR (b+i)));
5531 sp_addr +=2;
5532 }
5533 else
5534 {
5535 if (is_regp == 0)
5536 tmp = (GPR32 (b+i));
5537 else
5538 tmp = (GPR32 (b+i-1));
5539
5540 if ((a-i) > 1)
5541 {
5542 SLW (sp_addr, tmp);
5543 sp_addr +=4;
5544 }
5545 else
5546 {
5547 SW (sp_addr, tmp);
5548 sp_addr +=2;
5549 }
5550 ++i;
5551 is_regp = 1;
5552 }
5553 }
5554
5555 if (c == 1)
5556 {
5557 /* Store RA address. */
5558 tmp = (GPR32 (14));
5559 SLW(sp_addr,tmp);
5560 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5561 }
5562 else
5563 sp_addr = (GPR32 (15)) - (a * 2);
5564
5565 SET_GPR32 (15, sp_addr); /* Update SP address. */
5566
5567 trace_output_void (sd);
5568 }
5569
5570
5571 /* push. */
5572 void
5573 OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
5574 {
5575 uint32_t sp_addr = (GPR32 (15)), tmp;
5576 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5577 tmp = (GPR32 (14));
5578 SLW(sp_addr-4,tmp); /* Store RA address. */
5579 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5580 trace_output_void (sd);
5581 }
5582
5583
5584 /* pop. */
5585 void
5586 OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
5587 {
5588 uint16_t a = OP[0] + 1, b = OP[1], i = 0;
5589 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5590 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5591
5592 for (; i < a; ++i)
5593 {
5594 if ((b+i) <= 11)
5595 {
5596 SET_GPR ((b+i), RW(sp_addr));
5597 sp_addr +=2;
5598 }
5599 else
5600 {
5601 if ((a-i) > 1)
5602 {
5603 tmp = RLW(sp_addr);
5604 sp_addr +=4;
5605 }
5606 else
5607 {
5608 tmp = RW(sp_addr);
5609 sp_addr +=2;
5610
5611 if (is_regp == 0)
5612 tmp = (tmp << 16) | (GPR32 (b+i));
5613 else
5614 tmp = (tmp << 16) | (GPR32 (b+i-1));
5615 }
5616
5617 if (is_regp == 0)
5618 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5619 | ((tmp >> 16) & 0xffff)));
5620 else
5621 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5622 | ((tmp >> 16) & 0xffff)));
5623
5624 ++i;
5625 is_regp = 1;
5626 }
5627 }
5628
5629 tmp = RLW(sp_addr); /* store RA also. */
5630 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5631
5632 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5633
5634 trace_output_void (sd);
5635 }
5636
5637 /* pop. */
5638 void
5639 OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
5640 {
5641 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5642 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5643 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5644
5645 for (; i < a; ++i)
5646 {
5647 if ((b+i) <= 11)
5648 {
5649 SET_GPR ((b+i), RW(sp_addr));
5650 sp_addr +=2;
5651 }
5652 else
5653 {
5654 if ((a-i) > 1)
5655 {
5656 tmp = RLW(sp_addr);
5657 sp_addr +=4;
5658 }
5659 else
5660 {
5661 tmp = RW(sp_addr);
5662 sp_addr +=2;
5663
5664 if (is_regp == 0)
5665 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5666 else
5667 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5668 }
5669
5670 if (is_regp == 0)
5671 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5672 else
5673 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5674 ++i;
5675 is_regp = 1;
5676 }
5677 }
5678
5679 if (c == 1)
5680 {
5681 tmp = RLW(sp_addr); /* Store RA Reg. */
5682 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5683 sp_addr +=4;
5684 }
5685
5686 SET_GPR32 (15, sp_addr); /* Update SP address. */
5687
5688 trace_output_void (sd);
5689 }
5690
5691 /* pop. */
5692 void
5693 OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
5694 {
5695 uint32_t sp_addr = GPR32 (15);
5696 uint32_t tmp;
5697 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5698
5699 tmp = RLW(sp_addr);
5700 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5701 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5702
5703 trace_output_void (sd);
5704 }
5705
5706 /* popret. */
5707 void
5708 OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
5709 {
5710 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5711 OP_5_9 (sd, cpu);
5712 JMP(((GPR32(14)) << 1) & 0xffffff);
5713
5714 trace_output_void (sd);
5715 }
5716
5717 /* popret. */
5718 void
5719 OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
5720 {
5721 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5722 OP_2_8 (sd, cpu);
5723 JMP(((GPR32(14)) << 1) & 0xffffff);
5724
5725 trace_output_void (sd);
5726 }
5727
5728 /* popret. */
5729 void
5730 OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
5731 {
5732 uint32_t tmp;
5733 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5734 OP_21E_10 (sd, cpu);
5735 tmp = (((GPR32(14)) << 1) & 0xffffff);
5736 /* If the resulting PC value is less than 0x00_0000 or greater
5737 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5738
5739 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5740 {
5741 trace_output_void (sd);
5742 EXCEPTION (SIM_SIGBUS);
5743 }
5744 else
5745 JMP (tmp);
5746
5747 trace_output_32 (sd, tmp);
5748 }
5749
5750
5751 /* cinv[i]. */
5752 void
5753 OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
5754 {
5755 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5756 SET_PSR_I (1);
5757 trace_output_void (sd);
5758 }
5759
5760 /* cinv[i,u]. */
5761 void
5762 OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
5763 {
5764 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5765 SET_PSR_I (1);
5766 trace_output_void (sd);
5767 }
5768
5769 /* cinv[d]. */
5770 void
5771 OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
5772 {
5773 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5774 SET_PSR_I (1);
5775 trace_output_void (sd);
5776 }
5777
5778 /* cinv[d,u]. */
5779 void
5780 OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
5781 {
5782 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5783 SET_PSR_I (1);
5784 trace_output_void (sd);
5785 }
5786
5787 /* cinv[d,i]. */
5788 void
5789 OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
5790 {
5791 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5792 SET_PSR_I (1);
5793 trace_output_void (sd);
5794 }
5795
5796 /* cinv[d,i,u]. */
5797 void
5798 OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
5799 {
5800 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5801 SET_PSR_I (1);
5802 trace_output_void (sd);
5803 }
5804
5805 /* retx. */
5806 void
5807 OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
5808 {
5809 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5810 SET_PSR_I (1);
5811 trace_output_void (sd);
5812 }
5813
5814 /* di. */
5815 void
5816 OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
5817 {
5818 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5819 SET_PSR_I (1);
5820 trace_output_void (sd);
5821 }
5822
5823 /* ei. */
5824 void
5825 OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
5826 {
5827 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5828 SET_PSR_I (1);
5829 trace_output_void (sd);
5830 }
5831
5832 /* wait. */
5833 void
5834 OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
5835 {
5836 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5837 trace_output_void (sd);
5838 EXCEPTION (SIM_SIGTRAP);
5839 }
5840
5841 /* ewait. */
5842 void
5843 OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
5844 {
5845 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5846 SET_PSR_I (1);
5847 trace_output_void (sd);
5848 }
5849
5850 /* xorb. */
5851 void
5852 OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
5853 {
5854 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5855 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5856 tmp = a ^ b;
5857 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5858 trace_output_16 (sd, tmp);
5859 }
5860
5861 /* xorb. */
5862 void
5863 OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
5864 {
5865 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5866 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5867 tmp = a ^ b;
5868 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5869 trace_output_16 (sd, tmp);
5870 }
5871
5872 /* xorb. */
5873 void
5874 OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
5875 {
5876 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5877 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5878 tmp = a ^ b;
5879 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5880 trace_output_16 (sd, tmp);
5881 }
5882
5883 /* xorw. */
5884 void
5885 OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
5886 {
5887 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
5888 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5889 tmp = a ^ b;
5890 SET_GPR (OP[1], tmp);
5891 trace_output_16 (sd, tmp);
5892 }
5893
5894 /* xorw. */
5895 void
5896 OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
5897 {
5898 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1]));
5899 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5900 tmp = a ^ b;
5901 SET_GPR (OP[1], tmp);
5902 trace_output_16 (sd, tmp);
5903 }
5904
5905 /* xorw. */
5906 void
5907 OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
5908 {
5909 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5910 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5911 tmp = a ^ b;
5912 SET_GPR (OP[1], tmp);
5913 trace_output_16 (sd, tmp);
5914 }
5915
5916 /*REVISIT FOR LPR/SPR . */
5917
5918 /* lpr. */
5919 void
5920 OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
5921 {
5922 uint16_t a = GPR (OP[0]);
5923 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5924 SET_CREG (OP[1], a);
5925 trace_output_16 (sd, a);
5926 }
5927
5928 /* lprd. */
5929 void
5930 OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
5931 {
5932 uint32_t a = GPR32 (OP[0]);
5933 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5934 SET_CREG (OP[1], a);
5935 trace_output_flag (sd);
5936 }
5937
5938 /* spr. */
5939 void
5940 OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
5941 {
5942 uint16_t a = CREG (OP[0]);
5943 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5944 SET_GPR (OP[1], a);
5945 trace_output_16 (sd, a);
5946 }
5947
5948 /* sprd. */
5949 void
5950 OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
5951 {
5952 uint32_t a = CREG (OP[0]);
5953 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5954 SET_GPR32 (OP[1], a);
5955 trace_output_32 (sd, a);
5956 }
5957
5958 /* null. */
5959 void
5960 OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
5961 {
5962 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
5963 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
5964 }
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