sim/cris/cpuv10.h

   1 /* CPU family header for crisv10f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 3 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #ifndef CPU_CRISV10F_H
  25 #define CPU_CRISV10F_H
  26
  27 /* Maximum number of instructions that are fetched at a time.
  28    This is for LIW type instructions sets (e.g. m32r).  */
  29 #define MAX_LIW_INSNS 1
  30
  31 /* Maximum number of instructions that can be executed in parallel.  */
  32 #define MAX_PARALLEL_INSNS 1
  33
  34 /* CPU state information.  */
  35 typedef struct {
  36   /* Hardware elements.  */
  37   struct {
  38   /* program counter */
  39   USI h_pc;
  40 #define GET_H_PC() CPU (h_pc)
  41 #define SET_H_PC(x) \
  42 do { \
  43 CPU (h_pc) = ANDSI ((x), (~ (1)));\
  44 ;} while (0)
  45   /* General purpose registers */
  46   SI h_gr_real_pc[16];
  47 #define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1]
  48 #define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x))
  49   /* Special registers for v10 */
  50   SI h_sr_v10[16];
  51 #define GET_H_SR_V10(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (10) : (ORIF (((index) == (((UINT) 5))), ((index) == (((UINT) 13))))) ? (ORSI (ANDSI (CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), 0)))))))))) : (CPU (h_sr_v10[index]))
  52 #define SET_H_SR_V10(index, x) \
  53 do { \
  54 if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
  55 ((void) 0); /*nop*/\
  56 }\
  57  else if (ORIF ((((index)) == (((UINT) 5))), (((index)) == (((UINT) 13))))) {\
  58 {\
  59 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
  60 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
  61 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
  62 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
  63 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
  64 SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
  65 SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
  66 CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
  67 CPU (h_sr_v10[((UINT) 5)]) = (x);\
  68 CPU (h_sr_v10[((UINT) 13)]) = (x);\
  69 }\
  70 }\
  71  else {\
  72 CPU (h_sr_v10[(index)]) = (x);\
  73 }\
  74 ;} while (0)
  75   /* carry bit */
  76   BI h_cbit;
  77 #define GET_H_CBIT() CPU (h_cbit)
  78 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
  79   /* overflow bit */
  80   BI h_vbit;
  81 #define GET_H_VBIT() CPU (h_vbit)
  82 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
  83   /* zero bit */
  84   BI h_zbit;
  85 #define GET_H_ZBIT() CPU (h_zbit)
  86 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
  87   /* sign bit */
  88   BI h_nbit;
  89 #define GET_H_NBIT() CPU (h_nbit)
  90 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
  91   /* extended-arithmetic bit */
  92   BI h_xbit;
  93 #define GET_H_XBIT() CPU (h_xbit)
  94 #define SET_H_XBIT(x) (CPU (h_xbit) = (x))
  95   /* interrupt-enable bit */
  96   BI h_ibit_pre_v32;
  97 #define GET_H_IBIT_PRE_V32() CPU (h_ibit_pre_v32)
  98 #define SET_H_IBIT_PRE_V32(x) (CPU (h_ibit_pre_v32) = (x))
  99   /* sequence-broken bit */
 100   BI h_pbit;
 101 #define GET_H_PBIT() CPU (h_pbit)
 102 #define SET_H_PBIT(x) (CPU (h_pbit) = (x))
 103   /* user mode bit */
 104   BI h_ubit_pre_v32;
 105 #define GET_H_UBIT_PRE_V32() CPU (h_ubit_pre_v32)
 106 #define SET_H_UBIT_PRE_V32(x) (CPU (h_ubit_pre_v32) = (x))
 107   /* instruction-is-prefixed bit */
 108   BI h_insn_prefixed_p_pre_v32;
 109 #define GET_H_INSN_PREFIXED_P_PRE_V32() CPU (h_insn_prefixed_p_pre_v32)
 110 #define SET_H_INSN_PREFIXED_P_PRE_V32(x) (CPU (h_insn_prefixed_p_pre_v32) = (x))
 111   /* Prefix-address register */
 112   SI h_prefixreg_pre_v32;
 113 #define GET_H_PREFIXREG_PRE_V32() CPU (h_prefixreg_pre_v32)
 114 #define SET_H_PREFIXREG_PRE_V32(x) (CPU (h_prefixreg_pre_v32) = (x))
 115   } hardware;
 116 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 117 } CRISV10F_CPU_DATA;
 118
 119 /* Virtual regs.  */
 120
 121 #define GET_H_V32_NON_V32() 0
 122 #define SET_H_V32_NON_V32(x) \
 123 do { \
 124 cgen_rtx_error (current_cpu, "Can't set h-v32");\
 125 ;} while (0)
 126 #define GET_H_GR(index) GET_H_GR_PC (index)
 127 #define SET_H_GR(index, x) \
 128 do { \
 129 SET_H_GR_PC ((index), (x));\
 130 ;} while (0)
 131 #define GET_H_GR_PC(index) ((((index) == (15))) ? ((cgen_rtx_error (current_cpu, "General register read of PC is not implemented."), 0)) : (CPU (h_gr_real_pc[index])))
 132 #define SET_H_GR_PC(index, x) \
 133 do { \
 134 {\
 135 if ((((index)) == (15))) {\
 136 cgen_rtx_error (current_cpu, "General register write to PC is not implemented.");\
 137 }\
 138 CPU (h_gr_real_pc[(index)]) = (x);\
 139 }\
 140 ;} while (0)
 141 #define GET_H_RAW_GR_PC(index) CPU (h_gr_real_pc[index])
 142 #define SET_H_RAW_GR_PC(index, x) \
 143 do { \
 144 CPU (h_gr_real_pc[(index)]) = (x);\
 145 ;} while (0)
 146 #define GET_H_SR(index) GET_H_SR_V10 (index)
 147 #define SET_H_SR(index, x) \
 148 do { \
 149 SET_H_SR_V10 ((index), (x));\
 150 ;} while (0)
 151 #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_PRE_V32 ()
 152 #define SET_H_CBIT_MOVE(x) \
 153 do { \
 154 SET_H_CBIT_MOVE_PRE_V32 ((x));\
 155 ;} while (0)
 156 #define GET_H_CBIT_MOVE_PRE_V32() CPU (h_cbit)
 157 #define SET_H_CBIT_MOVE_PRE_V32(x) \
 158 do { \
 159 CPU (h_cbit) = (x);\
 160 ;} while (0)
 161 #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_PRE_V32 ()
 162 #define SET_H_VBIT_MOVE(x) \
 163 do { \
 164 SET_H_VBIT_MOVE_PRE_V32 ((x));\
 165 ;} while (0)
 166 #define GET_H_VBIT_MOVE_PRE_V32() CPU (h_vbit)
 167 #define SET_H_VBIT_MOVE_PRE_V32(x) \
 168 do { \
 169 CPU (h_vbit) = (x);\
 170 ;} while (0)
 171 #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_PRE_V32 ()
 172 #define SET_H_ZBIT_MOVE(x) \
 173 do { \
 174 SET_H_ZBIT_MOVE_PRE_V32 ((x));\
 175 ;} while (0)
 176 #define GET_H_ZBIT_MOVE_PRE_V32() CPU (h_zbit)
 177 #define SET_H_ZBIT_MOVE_PRE_V32(x) \
 178 do { \
 179 CPU (h_zbit) = (x);\
 180 ;} while (0)
 181 #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_PRE_V32 ()
 182 #define SET_H_NBIT_MOVE(x) \
 183 do { \
 184 SET_H_NBIT_MOVE_PRE_V32 ((x));\
 185 ;} while (0)
 186 #define GET_H_NBIT_MOVE_PRE_V32() CPU (h_nbit)
 187 #define SET_H_NBIT_MOVE_PRE_V32(x) \
 188 do { \
 189 CPU (h_nbit) = (x);\
 190 ;} while (0)
 191 #define GET_H_IBIT() CPU (h_ibit_pre_v32)
 192 #define SET_H_IBIT(x) \
 193 do { \
 194 CPU (h_ibit_pre_v32) = (x);\
 195 ;} while (0)
 196 #define GET_H_UBIT() CPU (h_ubit_pre_v32)
 197 #define SET_H_UBIT(x) \
 198 do { \
 199 CPU (h_ubit_pre_v32) = (x);\
 200 ;} while (0)
 201 #define GET_H_INSN_PREFIXED_P() CPU (h_insn_prefixed_p_pre_v32)
 202 #define SET_H_INSN_PREFIXED_P(x) \
 203 do { \
 204 CPU (h_insn_prefixed_p_pre_v32) = (x);\
 205 ;} while (0)
 206
 207 /* Cover fns for register access.  */
 208 BI crisv10f_h_v32_non_v32_get (SIM_CPU *);
 209 void crisv10f_h_v32_non_v32_set (SIM_CPU *, BI);
 210 USI crisv10f_h_pc_get (SIM_CPU *);
 211 void crisv10f_h_pc_set (SIM_CPU *, USI);
 212 SI crisv10f_h_gr_get (SIM_CPU *, UINT);
 213 void crisv10f_h_gr_set (SIM_CPU *, UINT, SI);
 214 SI crisv10f_h_gr_pc_get (SIM_CPU *, UINT);
 215 void crisv10f_h_gr_pc_set (SIM_CPU *, UINT, SI);
 216 SI crisv10f_h_gr_real_pc_get (SIM_CPU *, UINT);
 217 void crisv10f_h_gr_real_pc_set (SIM_CPU *, UINT, SI);
 218 SI crisv10f_h_raw_gr_pc_get (SIM_CPU *, UINT);
 219 void crisv10f_h_raw_gr_pc_set (SIM_CPU *, UINT, SI);
 220 SI crisv10f_h_sr_get (SIM_CPU *, UINT);
 221 void crisv10f_h_sr_set (SIM_CPU *, UINT, SI);
 222 SI crisv10f_h_sr_v10_get (SIM_CPU *, UINT);
 223 void crisv10f_h_sr_v10_set (SIM_CPU *, UINT, SI);
 224 BI crisv10f_h_cbit_get (SIM_CPU *);
 225 void crisv10f_h_cbit_set (SIM_CPU *, BI);
 226 BI crisv10f_h_cbit_move_get (SIM_CPU *);
 227 void crisv10f_h_cbit_move_set (SIM_CPU *, BI);
 228 BI crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *);
 229 void crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *, BI);
 230 BI crisv10f_h_vbit_get (SIM_CPU *);
 231 void crisv10f_h_vbit_set (SIM_CPU *, BI);
 232 BI crisv10f_h_vbit_move_get (SIM_CPU *);
 233 void crisv10f_h_vbit_move_set (SIM_CPU *, BI);
 234 BI crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *);
 235 void crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *, BI);
 236 BI crisv10f_h_zbit_get (SIM_CPU *);
 237 void crisv10f_h_zbit_set (SIM_CPU *, BI);
 238 BI crisv10f_h_zbit_move_get (SIM_CPU *);
 239 void crisv10f_h_zbit_move_set (SIM_CPU *, BI);
 240 BI crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *);
 241 void crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *, BI);
 242 BI crisv10f_h_nbit_get (SIM_CPU *);
 243 void crisv10f_h_nbit_set (SIM_CPU *, BI);
 244 BI crisv10f_h_nbit_move_get (SIM_CPU *);
 245 void crisv10f_h_nbit_move_set (SIM_CPU *, BI);
 246 BI crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *);
 247 void crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *, BI);
 248 BI crisv10f_h_xbit_get (SIM_CPU *);
 249 void crisv10f_h_xbit_set (SIM_CPU *, BI);
 250 BI crisv10f_h_ibit_get (SIM_CPU *);
 251 void crisv10f_h_ibit_set (SIM_CPU *, BI);
 252 BI crisv10f_h_ibit_pre_v32_get (SIM_CPU *);
 253 void crisv10f_h_ibit_pre_v32_set (SIM_CPU *, BI);
 254 BI crisv10f_h_pbit_get (SIM_CPU *);
 255 void crisv10f_h_pbit_set (SIM_CPU *, BI);
 256 BI crisv10f_h_ubit_get (SIM_CPU *);
 257 void crisv10f_h_ubit_set (SIM_CPU *, BI);
 258 BI crisv10f_h_ubit_pre_v32_get (SIM_CPU *);
 259 void crisv10f_h_ubit_pre_v32_set (SIM_CPU *, BI);
 260 BI crisv10f_h_insn_prefixed_p_get (SIM_CPU *);
 261 void crisv10f_h_insn_prefixed_p_set (SIM_CPU *, BI);
 262 BI crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *);
 263 void crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *, BI);
 264 SI crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *);
 265 void crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *, SI);
 266
 267 /* These must be hand-written.  */
 268 extern CPUREG_FETCH_FN crisv10f_fetch_register;
 269 extern CPUREG_STORE_FN crisv10f_store_register;
 270
 271 typedef struct {
 272   int empty;
 273 } MODEL_CRISV10_DATA;
 274
 275 /* Instruction argument buffer.  */
 276
 277 union sem_fields {
 278   struct { /* no operands */
 279     int empty;
 280   } fmt_empty;
 281   struct { /*  */
 282     UINT f_u4;
 283   } sfmt_break;
 284   struct { /*  */
 285     UINT f_dstsrc;
 286   } sfmt_setf;
 287   struct { /*  */
 288     IADDR i_o_word_pcrel;
 289     UINT f_operand2;
 290   } sfmt_bcc_w;
 291   struct { /*  */
 292     IADDR i_o_pcrel;
 293     UINT f_operand2;
 294   } sfmt_bcc_b;
 295   struct { /*  */
 296     UINT f_memmode;
 297     unsigned char in_h_gr_SI_14;
 298     unsigned char out_h_gr_SI_14;
 299   } sfmt_move_m_spplus_p8;
 300   struct { /*  */
 301     INT f_s8;
 302     UINT f_operand2;
 303     unsigned char in_Rd;
 304   } sfmt_addoq;
 305   struct { /*  */
 306     INT f_indir_pc__dword;
 307     UINT f_operand2;
 308     unsigned char out_Pd;
 309   } sfmt_move_c_sprv10_p9;
 310   struct { /*  */
 311     INT f_indir_pc__word;
 312     UINT f_operand2;
 313     unsigned char out_Pd;
 314   } sfmt_move_c_sprv10_p5;
 315   struct { /*  */
 316     INT f_s6;
 317     UINT f_operand2;
 318     unsigned char out_Rd;
 319   } sfmt_moveq;
 320   struct { /*  */
 321     INT f_indir_pc__dword;
 322     UINT f_operand2;
 323     unsigned char in_Rd;
 324     unsigned char out_Rd;
 325   } sfmt_bound_cd;
 326   struct { /*  */
 327     INT f_indir_pc__word;
 328     UINT f_operand2;
 329     unsigned char in_Rd;
 330     unsigned char out_Rd;
 331   } sfmt_bound_cw;
 332   struct { /*  */
 333     INT f_indir_pc__byte;
 334     UINT f_operand2;
 335     unsigned char in_Rd;
 336     unsigned char out_Rd;
 337   } sfmt_bound_cb;
 338   struct { /*  */
 339     UINT f_operand2;
 340     UINT f_u5;
 341     unsigned char in_Rd;
 342     unsigned char out_Rd;
 343   } sfmt_asrq;
 344   struct { /*  */
 345     INT f_s6;
 346     UINT f_operand2;
 347     unsigned char in_Rd;
 348     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 349   } sfmt_andq;
 350   struct { /*  */
 351     INT f_indir_pc__dword;
 352     UINT f_operand2;
 353     unsigned char in_Rd;
 354     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 355   } sfmt_addcdr;
 356   struct { /*  */
 357     INT f_indir_pc__word;
 358     UINT f_operand2;
 359     unsigned char in_Rd;
 360     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 361   } sfmt_addcwr;
 362   struct { /*  */
 363     INT f_indir_pc__byte;
 364     UINT f_operand2;
 365     unsigned char in_Rd;
 366     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 367   } sfmt_addcbr;
 368   struct { /*  */
 369     UINT f_operand1;
 370     UINT f_operand2;
 371     unsigned char in_Ps;
 372     unsigned char out_h_gr_SI_index_of__DFLT_Rs;
 373   } sfmt_move_spr_rv10;
 374   struct { /*  */
 375     UINT f_operand2;
 376     UINT f_u6;
 377     unsigned char in_Rd;
 378     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 379   } sfmt_addq;
 380   struct { /*  */
 381     UINT f_operand1;
 382     UINT f_operand2;
 383     unsigned char in_Rd;
 384     unsigned char in_Rs;
 385     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 386   } sfmt_add_b_r;
 387   struct { /*  */
 388     UINT f_operand1;
 389     UINT f_operand2;
 390     unsigned char in_Rd;
 391     unsigned char in_Rs;
 392     unsigned char out_Rd;
 393     unsigned char out_h_sr_SI_7;
 394   } sfmt_muls_b;
 395   struct { /*  */
 396     UINT f_memmode;
 397     UINT f_operand1;
 398     UINT f_operand2;
 399     unsigned char in_Ps;
 400     unsigned char in_Rs;
 401     unsigned char out_Rs;
 402   } sfmt_move_spr_mv10;
 403   struct { /*  */
 404     UINT f_memmode;
 405     UINT f_operand1;
 406     UINT f_operand2;
 407     unsigned char in_Rs;
 408     unsigned char out_Pd;
 409     unsigned char out_Rs;
 410   } sfmt_move_m_sprv10;
 411   struct { /*  */
 412     UINT f_memmode;
 413     UINT f_operand1;
 414     UINT f_operand2;
 415     unsigned char in_Rd;
 416     unsigned char in_Rs;
 417     unsigned char out_Rd;
 418     unsigned char out_Rs;
 419   } sfmt_bound_m_b_m;
 420   struct { /*  */
 421     UINT f_memmode;
 422     UINT f_operand1;
 423     UINT f_operand2;
 424     unsigned char in_Rd;
 425     unsigned char in_Rs;
 426     unsigned char out_Rs;
 427     unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
 428   } sfmt_add_m_b_m;
 429   struct { /*  */
 430     UINT f_memmode;
 431     UINT f_operand1;
 432     UINT f_operand2;
 433     unsigned char in_Rd;
 434     unsigned char in_Rs;
 435     unsigned char out_Rs;
 436     unsigned char out_h_gr_SI_0;
 437     unsigned char out_h_gr_SI_1;
 438     unsigned char out_h_gr_SI_10;
 439     unsigned char out_h_gr_SI_11;
 440     unsigned char out_h_gr_SI_12;
 441     unsigned char out_h_gr_SI_13;
 442     unsigned char out_h_gr_SI_14;
 443     unsigned char out_h_gr_SI_2;
 444     unsigned char out_h_gr_SI_3;
 445     unsigned char out_h_gr_SI_4;
 446     unsigned char out_h_gr_SI_5;
 447     unsigned char out_h_gr_SI_6;
 448     unsigned char out_h_gr_SI_7;
 449     unsigned char out_h_gr_SI_8;
 450     unsigned char out_h_gr_SI_9;
 451   } sfmt_movem_m_r;
 452   struct { /*  */
 453     UINT f_memmode;
 454     UINT f_operand1;
 455     UINT f_operand2;
 456     unsigned char in_Rd;
 457     unsigned char in_Rs;
 458     unsigned char in_h_gr_SI_0;
 459     unsigned char in_h_gr_SI_1;
 460     unsigned char in_h_gr_SI_10;
 461     unsigned char in_h_gr_SI_11;
 462     unsigned char in_h_gr_SI_12;
 463     unsigned char in_h_gr_SI_13;
 464     unsigned char in_h_gr_SI_14;
 465     unsigned char in_h_gr_SI_15;
 466     unsigned char in_h_gr_SI_2;
 467     unsigned char in_h_gr_SI_3;
 468     unsigned char in_h_gr_SI_4;
 469     unsigned char in_h_gr_SI_5;
 470     unsigned char in_h_gr_SI_6;
 471     unsigned char in_h_gr_SI_7;
 472     unsigned char in_h_gr_SI_8;
 473     unsigned char in_h_gr_SI_9;
 474     unsigned char out_Rs;
 475   } sfmt_movem_r_m;
 476 #if WITH_SCACHE_PBB
 477   /* Writeback handler.  */
 478   struct {
 479     /* Pointer to argbuf entry for insn whose results need writing back.  */
 480     const struct argbuf *abuf;
 481   } write;
 482   /* x-before handler */
 483   struct {
 484     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 485     int first_p;
 486   } before;
 487   /* x-after handler */
 488   struct {
 489     int empty;
 490   } after;
 491   /* This entry is used to terminate each pbb.  */
 492   struct {
 493     /* Number of insns in pbb.  */
 494     int insn_count;
 495     /* Next pbb to execute.  */
 496     SCACHE *next;
 497     SCACHE *branch_target;
 498   } chain;
 499 #endif
 500 };
 501
 502 /* The ARGBUF struct.  */
 503 struct argbuf {
 504   /* These are the baseclass definitions.  */
 505   IADDR addr;
 506   const IDESC *idesc;
 507   char trace_p;
 508   char profile_p;
 509   /* ??? Temporary hack for skip insns.  */
 510   char skip_count;
 511   char unused;
 512   /* cpu specific data follows */
 513   union sem semantic;
 514   int written;
 515   union sem_fields fields;
 516 };
 517
 518 /* A cached insn.
 519
 520    ??? SCACHE used to contain more than just argbuf.  We could delete the
 521    type entirely and always just use ARGBUF, but for future concerns and as
 522    a level of abstraction it is left in.  */
 523
 524 struct scache {
 525   struct argbuf argbuf;
 526 };
 527
 528 /* Macros to simplify extraction, reading and semantic code.
 529    These define and assign the local vars that contain the insn's fields.  */
 530
 531 #define EXTRACT_IFMT_EMPTY_VARS \
 532   unsigned int length;
 533 #define EXTRACT_IFMT_EMPTY_CODE \
 534   length = 0; \
 535
 536 #define EXTRACT_IFMT_NOP_VARS \
 537   UINT f_operand2; \
 538   UINT f_mode; \
 539   UINT f_opcode; \
 540   UINT f_size; \
 541   UINT f_operand1; \
 542   unsigned int length;
 543 #define EXTRACT_IFMT_NOP_CODE \
 544   length = 2; \
 545   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 546   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 547   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 548   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 549   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 550
 551 #define EXTRACT_IFMT_MOVE_B_R_VARS \
 552   UINT f_operand2; \
 553   UINT f_mode; \
 554   UINT f_opcode; \
 555   UINT f_size; \
 556   UINT f_operand1; \
 557   unsigned int length;
 558 #define EXTRACT_IFMT_MOVE_B_R_CODE \
 559   length = 2; \
 560   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 561   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 562   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 563   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 564   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 565
 566 #define EXTRACT_IFMT_MOVEPCR_VARS \
 567   UINT f_operand2; \
 568   UINT f_mode; \
 569   UINT f_opcode; \
 570   UINT f_size; \
 571   UINT f_operand1; \
 572   unsigned int length;
 573 #define EXTRACT_IFMT_MOVEPCR_CODE \
 574   length = 2; \
 575   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 576   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 577   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 578   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 579   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 580
 581 #define EXTRACT_IFMT_MOVEQ_VARS \
 582   UINT f_operand2; \
 583   UINT f_mode; \
 584   UINT f_opcode; \
 585   INT f_s6; \
 586   unsigned int length;
 587 #define EXTRACT_IFMT_MOVEQ_CODE \
 588   length = 2; \
 589   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 590   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 591   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 592   f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
 593
 594 #define EXTRACT_IFMT_MOVECBR_VARS \
 595   UINT f_operand2; \
 596   INT f_indir_pc__byte; \
 597   UINT f_mode; \
 598   UINT f_opcode; \
 599   UINT f_size; \
 600   UINT f_operand1; \
 601   /* Contents of trailing part of insn.  */ \
 602   UINT word_1; \
 603   unsigned int length;
 604 #define EXTRACT_IFMT_MOVECBR_CODE \
 605   length = 4; \
 606   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 607   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 608   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 609   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 610   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 611   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 612   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 613
 614 #define EXTRACT_IFMT_MOVECWR_VARS \
 615   UINT f_operand2; \
 616   INT f_indir_pc__word; \
 617   UINT f_mode; \
 618   UINT f_opcode; \
 619   UINT f_size; \
 620   UINT f_operand1; \
 621   /* Contents of trailing part of insn.  */ \
 622   UINT word_1; \
 623   unsigned int length;
 624 #define EXTRACT_IFMT_MOVECWR_CODE \
 625   length = 4; \
 626   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 627   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 628   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 629   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 630   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 631   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 632   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 633
 634 #define EXTRACT_IFMT_MOVECDR_VARS \
 635   INT f_indir_pc__dword; \
 636   UINT f_operand2; \
 637   UINT f_mode; \
 638   UINT f_opcode; \
 639   UINT f_size; \
 640   UINT f_operand1; \
 641   /* Contents of trailing part of insn.  */ \
 642   UINT word_1; \
 643   unsigned int length;
 644 #define EXTRACT_IFMT_MOVECDR_CODE \
 645   length = 6; \
 646   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 647   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 648   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 649   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 650   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 651   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 652   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 653
 654 #define EXTRACT_IFMT_MOVUCBR_VARS \
 655   UINT f_operand2; \
 656   INT f_indir_pc__byte; \
 657   UINT f_mode; \
 658   UINT f_opcode; \
 659   UINT f_size; \
 660   UINT f_operand1; \
 661   /* Contents of trailing part of insn.  */ \
 662   UINT word_1; \
 663   unsigned int length;
 664 #define EXTRACT_IFMT_MOVUCBR_CODE \
 665   length = 4; \
 666   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 667   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 668   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 669   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 670   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 671   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 672   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 673
 674 #define EXTRACT_IFMT_MOVUCWR_VARS \
 675   UINT f_operand2; \
 676   INT f_indir_pc__word; \
 677   UINT f_mode; \
 678   UINT f_opcode; \
 679   UINT f_size; \
 680   UINT f_operand1; \
 681   /* Contents of trailing part of insn.  */ \
 682   UINT word_1; \
 683   unsigned int length;
 684 #define EXTRACT_IFMT_MOVUCWR_CODE \
 685   length = 4; \
 686   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 687   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 688   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 689   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 690   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 691   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 692   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 693
 694 #define EXTRACT_IFMT_ADDQ_VARS \
 695   UINT f_operand2; \
 696   UINT f_mode; \
 697   UINT f_opcode; \
 698   UINT f_u6; \
 699   unsigned int length;
 700 #define EXTRACT_IFMT_ADDQ_CODE \
 701   length = 2; \
 702   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 703   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 704   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 705   f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
 706
 707 #define EXTRACT_IFMT_CMP_M_B_M_VARS \
 708   UINT f_operand2; \
 709   UINT f_membit; \
 710   UINT f_memmode; \
 711   UINT f_opcode; \
 712   UINT f_size; \
 713   UINT f_operand1; \
 714   unsigned int length;
 715 #define EXTRACT_IFMT_CMP_M_B_M_CODE \
 716   length = 2; \
 717   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 718   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 719   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 720   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 721   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 722   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 723
 724 #define EXTRACT_IFMT_MOVE_R_SPRV10_VARS \
 725   UINT f_operand2; \
 726   UINT f_mode; \
 727   UINT f_opcode; \
 728   UINT f_size; \
 729   UINT f_operand1; \
 730   unsigned int length;
 731 #define EXTRACT_IFMT_MOVE_R_SPRV10_CODE \
 732   length = 2; \
 733   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 734   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 735   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 736   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 737   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 738
 739 #define EXTRACT_IFMT_MOVE_SPR_RV10_VARS \
 740   UINT f_operand2; \
 741   UINT f_mode; \
 742   UINT f_opcode; \
 743   UINT f_size; \
 744   UINT f_operand1; \
 745   unsigned int length;
 746 #define EXTRACT_IFMT_MOVE_SPR_RV10_CODE \
 747   length = 2; \
 748   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 749   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 750   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 751   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 752   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 753
 754 #define EXTRACT_IFMT_RET_TYPE_VARS \
 755   UINT f_operand2; \
 756   UINT f_mode; \
 757   UINT f_opcode; \
 758   UINT f_size; \
 759   UINT f_operand1; \
 760   unsigned int length;
 761 #define EXTRACT_IFMT_RET_TYPE_CODE \
 762   length = 2; \
 763   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 764   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 765   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 766   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 767   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 768
 769 #define EXTRACT_IFMT_MOVE_M_SPRV10_VARS \
 770   UINT f_operand2; \
 771   UINT f_membit; \
 772   UINT f_memmode; \
 773   UINT f_opcode; \
 774   UINT f_size; \
 775   UINT f_operand1; \
 776   unsigned int length;
 777 #define EXTRACT_IFMT_MOVE_M_SPRV10_CODE \
 778   length = 2; \
 779   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 780   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 781   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 782   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 783   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 784   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 785
 786 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_VARS \
 787   UINT f_operand2; \
 788   INT f_indir_pc__word; \
 789   UINT f_mode; \
 790   UINT f_opcode; \
 791   UINT f_size; \
 792   UINT f_operand1; \
 793   /* Contents of trailing part of insn.  */ \
 794   UINT word_1; \
 795   unsigned int length;
 796 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_CODE \
 797   length = 4; \
 798   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 799   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 800   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 801   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 802   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 803   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 804   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 805
 806 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_VARS \
 807   INT f_indir_pc__dword; \
 808   UINT f_operand2; \
 809   UINT f_mode; \
 810   UINT f_opcode; \
 811   UINT f_size; \
 812   UINT f_operand1; \
 813   /* Contents of trailing part of insn.  */ \
 814   UINT word_1; \
 815   unsigned int length;
 816 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_CODE \
 817   length = 6; \
 818   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 819   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 820   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 821   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 822   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 823   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 824   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 825
 826 #define EXTRACT_IFMT_MOVE_SPR_MV10_VARS \
 827   UINT f_operand2; \
 828   UINT f_membit; \
 829   UINT f_memmode; \
 830   UINT f_opcode; \
 831   UINT f_size; \
 832   UINT f_operand1; \
 833   unsigned int length;
 834 #define EXTRACT_IFMT_MOVE_SPR_MV10_CODE \
 835   length = 2; \
 836   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 837   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 838   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 839   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 840   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 841   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 842
 843 #define EXTRACT_IFMT_SBFS_VARS \
 844   UINT f_operand2; \
 845   UINT f_membit; \
 846   UINT f_memmode; \
 847   UINT f_opcode; \
 848   UINT f_size; \
 849   UINT f_operand1; \
 850   unsigned int length;
 851 #define EXTRACT_IFMT_SBFS_CODE \
 852   length = 2; \
 853   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 854   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 855   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 856   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 857   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 858   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 859
 860 #define EXTRACT_IFMT_SWAP_VARS \
 861   UINT f_operand2; \
 862   UINT f_mode; \
 863   UINT f_opcode; \
 864   UINT f_size; \
 865   UINT f_operand1; \
 866   unsigned int length;
 867 #define EXTRACT_IFMT_SWAP_CODE \
 868   length = 2; \
 869   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 870   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 871   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 872   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 873   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 874
 875 #define EXTRACT_IFMT_ASRQ_VARS \
 876   UINT f_operand2; \
 877   UINT f_mode; \
 878   UINT f_opcode; \
 879   UINT f_b5; \
 880   UINT f_u5; \
 881   unsigned int length;
 882 #define EXTRACT_IFMT_ASRQ_CODE \
 883   length = 2; \
 884   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 885   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 886   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 887   f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
 888   f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
 889
 890 #define EXTRACT_IFMT_SETF_VARS \
 891   UINT f_mode; \
 892   UINT f_opcode; \
 893   UINT f_size; \
 894   UINT f_operand2; \
 895   UINT f_operand1; \
 896   UINT f_dstsrc; \
 897   unsigned int length;
 898 #define EXTRACT_IFMT_SETF_CODE \
 899   length = 2; \
 900   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 901   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 902   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 903   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 904   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 905   f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
 906
 907 #define EXTRACT_IFMT_BCC_B_VARS \
 908   UINT f_operand2; \
 909   UINT f_mode; \
 910   UINT f_opcode_hi; \
 911   INT f_disp9_hi; \
 912   UINT f_disp9_lo; \
 913   INT f_disp9; \
 914   unsigned int length;
 915 #define EXTRACT_IFMT_BCC_B_CODE \
 916   length = 2; \
 917   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 918   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 919   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
 920   f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
 921   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 922 {\
 923   SI tmp_abslo;\
 924   SI tmp_absval;\
 925   tmp_abslo = ((f_disp9_lo) << (1));\
 926   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
 927   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
 928 }\
 929
 930 #define EXTRACT_IFMT_BA_B_VARS \
 931   UINT f_operand2; \
 932   UINT f_mode; \
 933   UINT f_opcode_hi; \
 934   INT f_disp9_hi; \
 935   UINT f_disp9_lo; \
 936   INT f_disp9; \
 937   unsigned int length;
 938 #define EXTRACT_IFMT_BA_B_CODE \
 939   length = 2; \
 940   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 941   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 942   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
 943   f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
 944   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 945 {\
 946   SI tmp_abslo;\
 947   SI tmp_absval;\
 948   tmp_abslo = ((f_disp9_lo) << (1));\
 949   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
 950   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
 951 }\
 952
 953 #define EXTRACT_IFMT_BCC_W_VARS \
 954   UINT f_operand2; \
 955   SI f_indir_pc__word_pcrel; \
 956   UINT f_mode; \
 957   UINT f_opcode; \
 958   UINT f_size; \
 959   UINT f_operand1; \
 960   /* Contents of trailing part of insn.  */ \
 961   UINT word_1; \
 962   unsigned int length;
 963 #define EXTRACT_IFMT_BCC_W_CODE \
 964   length = 4; \
 965   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 966   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 967   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
 968   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 969   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 970   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 971   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 972
 973 #define EXTRACT_IFMT_BA_W_VARS \
 974   UINT f_operand2; \
 975   SI f_indir_pc__word_pcrel; \
 976   UINT f_mode; \
 977   UINT f_opcode; \
 978   UINT f_size; \
 979   UINT f_operand1; \
 980   /* Contents of trailing part of insn.  */ \
 981   UINT word_1; \
 982   unsigned int length;
 983 #define EXTRACT_IFMT_BA_W_CODE \
 984   length = 4; \
 985   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 986   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 987   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
 988   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 989   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 990   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 991   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 992
 993 #define EXTRACT_IFMT_JUMP_C_VARS \
 994   INT f_indir_pc__dword; \
 995   UINT f_operand2; \
 996   UINT f_mode; \
 997   UINT f_opcode; \
 998   UINT f_size; \
 999   UINT f_operand1; \
1000   /* Contents of trailing part of insn.  */ \
1001   UINT word_1; \
1002   unsigned int length;
1003 #define EXTRACT_IFMT_JUMP_C_CODE \
1004   length = 6; \
1005   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1006   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
1007   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1008   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1009   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1010   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1011   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1012
1013 #define EXTRACT_IFMT_BREAK_VARS \
1014   UINT f_operand2; \
1015   UINT f_mode; \
1016   UINT f_opcode; \
1017   UINT f_size; \
1018   UINT f_u4; \
1019   unsigned int length;
1020 #define EXTRACT_IFMT_BREAK_CODE \
1021   length = 2; \
1022   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1023   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1024   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1025   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1026   f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1027
1028 #define EXTRACT_IFMT_SCC_VARS \
1029   UINT f_operand2; \
1030   UINT f_mode; \
1031   UINT f_opcode; \
1032   UINT f_size; \
1033   UINT f_operand1; \
1034   unsigned int length;
1035 #define EXTRACT_IFMT_SCC_CODE \
1036   length = 2; \
1037   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1038   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1039   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1040   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1041   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1042
1043 #define EXTRACT_IFMT_ADDOQ_VARS \
1044   UINT f_operand2; \
1045   UINT f_mode; \
1046   UINT f_opcode_hi; \
1047   INT f_s8; \
1048   unsigned int length;
1049 #define EXTRACT_IFMT_ADDOQ_CODE \
1050   length = 2; \
1051   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1052   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1053   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1054   f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1055
1056 #define EXTRACT_IFMT_BDAPQPC_VARS \
1057   UINT f_operand2; \
1058   UINT f_mode; \
1059   UINT f_opcode_hi; \
1060   INT f_s8; \
1061   unsigned int length;
1062 #define EXTRACT_IFMT_BDAPQPC_CODE \
1063   length = 2; \
1064   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1065   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1066   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1067   f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1068
1069 /* Collection of various things for the trace handler to use.  */
1070
1071 typedef struct trace_record {
1072   IADDR pc;
1073   /* FIXME:wip */
1074 } TRACE_RECORD;
1075
1076 #endif /* CPU_CRISV10F_H */