sim/cris/cpuv10.h

   1 /* CPU family header for crisv10f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2010 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef CPU_CRISV10F_H
  26 #define CPU_CRISV10F_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 1
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* The size of an "int" needed to hold an instruction word.
  36    This is usually 32 bits, but some architectures needs 64 bits.  */
  37 typedef CGEN_INSN_INT CGEN_INSN_WORD;
  38
  39 #include "cgen-engine.h"
  40
  41 /* CPU state information.  */
  42 typedef struct {
  43   /* Hardware elements.  */
  44   struct {
  45   /* program counter */
  46   USI h_pc;
  47 #define GET_H_PC() CPU (h_pc)
  48 #define SET_H_PC(x) \
  49 do { \
  50 CPU (h_pc) = ANDSI ((x), (~ (1)));\
  51 ;} while (0)
  52   /* General purpose registers */
  53   SI h_gr_real_pc[16];
  54 #define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1]
  55 #define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x))
  56   /* Special registers for v10 */
  57   SI h_sr_v10[16];
  58 #define GET_H_SR_V10(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (10) : (ORIF (((index) == (((UINT) 5))), ((index) == (((UINT) 13))))) ? (ORSI (ANDSI (CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), 0)))))))))) : (CPU (h_sr_v10[index]))
  59 #define SET_H_SR_V10(index, x) \
  60 do { \
  61 if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
  62 ((void) 0); /*nop*/\
  63 }\
  64  else if (ORIF ((((index)) == (((UINT) 5))), (((index)) == (((UINT) 13))))) {\
  65 {\
  66 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
  67 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
  68 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
  69 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
  70 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
  71 SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
  72 SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
  73 CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
  74 CPU (h_sr_v10[((UINT) 5)]) = (x);\
  75 CPU (h_sr_v10[((UINT) 13)]) = (x);\
  76 }\
  77 }\
  78  else {\
  79 CPU (h_sr_v10[(index)]) = (x);\
  80 }\
  81 ;} while (0)
  82   /* carry bit */
  83   BI h_cbit;
  84 #define GET_H_CBIT() CPU (h_cbit)
  85 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
  86   /* overflow bit */
  87   BI h_vbit;
  88 #define GET_H_VBIT() CPU (h_vbit)
  89 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
  90   /* zero bit */
  91   BI h_zbit;
  92 #define GET_H_ZBIT() CPU (h_zbit)
  93 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
  94   /* sign bit */
  95   BI h_nbit;
  96 #define GET_H_NBIT() CPU (h_nbit)
  97 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
  98   /* extended-arithmetic bit */
  99   BI h_xbit;
 100 #define GET_H_XBIT() CPU (h_xbit)
 101 #define SET_H_XBIT(x) (CPU (h_xbit) = (x))
 102   /* interrupt-enable bit */
 103   BI h_ibit_pre_v32;
 104 #define GET_H_IBIT_PRE_V32() CPU (h_ibit_pre_v32)
 105 #define SET_H_IBIT_PRE_V32(x) (CPU (h_ibit_pre_v32) = (x))
 106   /* sequence-broken bit */
 107   BI h_pbit;
 108 #define GET_H_PBIT() CPU (h_pbit)
 109 #define SET_H_PBIT(x) (CPU (h_pbit) = (x))
 110   /* user mode bit */
 111   BI h_ubit_pre_v32;
 112 #define GET_H_UBIT_PRE_V32() CPU (h_ubit_pre_v32)
 113 #define SET_H_UBIT_PRE_V32(x) (CPU (h_ubit_pre_v32) = (x))
 114   /* instruction-is-prefixed bit */
 115   BI h_insn_prefixed_p_pre_v32;
 116 #define GET_H_INSN_PREFIXED_P_PRE_V32() CPU (h_insn_prefixed_p_pre_v32)
 117 #define SET_H_INSN_PREFIXED_P_PRE_V32(x) (CPU (h_insn_prefixed_p_pre_v32) = (x))
 118   /* Prefix-address register */
 119   SI h_prefixreg_pre_v32;
 120 #define GET_H_PREFIXREG_PRE_V32() CPU (h_prefixreg_pre_v32)
 121 #define SET_H_PREFIXREG_PRE_V32(x) (CPU (h_prefixreg_pre_v32) = (x))
 122   } hardware;
 123 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 124 } CRISV10F_CPU_DATA;
 125
 126 /* Virtual regs.  */
 127
 128 #define GET_H_V32_NON_V32() 0
 129 #define SET_H_V32_NON_V32(x) \
 130 do { \
 131 cgen_rtx_error (current_cpu, "Can't set h-v32");\
 132 ;} while (0)
 133 #define GET_H_GR(index) GET_H_GR_PC (index)
 134 #define SET_H_GR(index, x) \
 135 do { \
 136 SET_H_GR_PC ((index), (x));\
 137 ;} while (0)
 138 #define GET_H_GR_PC(index) ((((index) == (15))) ? ((cgen_rtx_error (current_cpu, "General register read of PC is not implemented."), 0)) : (CPU (h_gr_real_pc[index])))
 139 #define SET_H_GR_PC(index, x) \
 140 do { \
 141 {\
 142 if ((((index)) == (15))) {\
 143 cgen_rtx_error (current_cpu, "General register write to PC is not implemented.");\
 144 }\
 145 CPU (h_gr_real_pc[(index)]) = (x);\
 146 }\
 147 ;} while (0)
 148 #define GET_H_RAW_GR_PC(index) CPU (h_gr_real_pc[index])
 149 #define SET_H_RAW_GR_PC(index, x) \
 150 do { \
 151 CPU (h_gr_real_pc[(index)]) = (x);\
 152 ;} while (0)
 153 #define GET_H_SR(index) GET_H_SR_V10 (index)
 154 #define SET_H_SR(index, x) \
 155 do { \
 156 SET_H_SR_V10 ((index), (x));\
 157 ;} while (0)
 158 #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_PRE_V32 ()
 159 #define SET_H_CBIT_MOVE(x) \
 160 do { \
 161 SET_H_CBIT_MOVE_PRE_V32 ((x));\
 162 ;} while (0)
 163 #define GET_H_CBIT_MOVE_PRE_V32() CPU (h_cbit)
 164 #define SET_H_CBIT_MOVE_PRE_V32(x) \
 165 do { \
 166 CPU (h_cbit) = (x);\
 167 ;} while (0)
 168 #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_PRE_V32 ()
 169 #define SET_H_VBIT_MOVE(x) \
 170 do { \
 171 SET_H_VBIT_MOVE_PRE_V32 ((x));\
 172 ;} while (0)
 173 #define GET_H_VBIT_MOVE_PRE_V32() CPU (h_vbit)
 174 #define SET_H_VBIT_MOVE_PRE_V32(x) \
 175 do { \
 176 CPU (h_vbit) = (x);\
 177 ;} while (0)
 178 #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_PRE_V32 ()
 179 #define SET_H_ZBIT_MOVE(x) \
 180 do { \
 181 SET_H_ZBIT_MOVE_PRE_V32 ((x));\
 182 ;} while (0)
 183 #define GET_H_ZBIT_MOVE_PRE_V32() CPU (h_zbit)
 184 #define SET_H_ZBIT_MOVE_PRE_V32(x) \
 185 do { \
 186 CPU (h_zbit) = (x);\
 187 ;} while (0)
 188 #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_PRE_V32 ()
 189 #define SET_H_NBIT_MOVE(x) \
 190 do { \
 191 SET_H_NBIT_MOVE_PRE_V32 ((x));\
 192 ;} while (0)
 193 #define GET_H_NBIT_MOVE_PRE_V32() CPU (h_nbit)
 194 #define SET_H_NBIT_MOVE_PRE_V32(x) \
 195 do { \
 196 CPU (h_nbit) = (x);\
 197 ;} while (0)
 198 #define GET_H_IBIT() CPU (h_ibit_pre_v32)
 199 #define SET_H_IBIT(x) \
 200 do { \
 201 CPU (h_ibit_pre_v32) = (x);\
 202 ;} while (0)
 203 #define GET_H_UBIT() CPU (h_ubit_pre_v32)
 204 #define SET_H_UBIT(x) \
 205 do { \
 206 CPU (h_ubit_pre_v32) = (x);\
 207 ;} while (0)
 208 #define GET_H_INSN_PREFIXED_P() CPU (h_insn_prefixed_p_pre_v32)
 209 #define SET_H_INSN_PREFIXED_P(x) \
 210 do { \
 211 CPU (h_insn_prefixed_p_pre_v32) = (x);\
 212 ;} while (0)
 213
 214 /* Cover fns for register access.  */
 215 BI crisv10f_h_v32_non_v32_get (SIM_CPU *);
 216 void crisv10f_h_v32_non_v32_set (SIM_CPU *, BI);
 217 USI crisv10f_h_pc_get (SIM_CPU *);
 218 void crisv10f_h_pc_set (SIM_CPU *, USI);
 219 SI crisv10f_h_gr_get (SIM_CPU *, UINT);
 220 void crisv10f_h_gr_set (SIM_CPU *, UINT, SI);
 221 SI crisv10f_h_gr_pc_get (SIM_CPU *, UINT);
 222 void crisv10f_h_gr_pc_set (SIM_CPU *, UINT, SI);
 223 SI crisv10f_h_gr_real_pc_get (SIM_CPU *, UINT);
 224 void crisv10f_h_gr_real_pc_set (SIM_CPU *, UINT, SI);
 225 SI crisv10f_h_raw_gr_pc_get (SIM_CPU *, UINT);
 226 void crisv10f_h_raw_gr_pc_set (SIM_CPU *, UINT, SI);
 227 SI crisv10f_h_sr_get (SIM_CPU *, UINT);
 228 void crisv10f_h_sr_set (SIM_CPU *, UINT, SI);
 229 SI crisv10f_h_sr_v10_get (SIM_CPU *, UINT);
 230 void crisv10f_h_sr_v10_set (SIM_CPU *, UINT, SI);
 231 BI crisv10f_h_cbit_get (SIM_CPU *);
 232 void crisv10f_h_cbit_set (SIM_CPU *, BI);
 233 BI crisv10f_h_cbit_move_get (SIM_CPU *);
 234 void crisv10f_h_cbit_move_set (SIM_CPU *, BI);
 235 BI crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *);
 236 void crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *, BI);
 237 BI crisv10f_h_vbit_get (SIM_CPU *);
 238 void crisv10f_h_vbit_set (SIM_CPU *, BI);
 239 BI crisv10f_h_vbit_move_get (SIM_CPU *);
 240 void crisv10f_h_vbit_move_set (SIM_CPU *, BI);
 241 BI crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *);
 242 void crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *, BI);
 243 BI crisv10f_h_zbit_get (SIM_CPU *);
 244 void crisv10f_h_zbit_set (SIM_CPU *, BI);
 245 BI crisv10f_h_zbit_move_get (SIM_CPU *);
 246 void crisv10f_h_zbit_move_set (SIM_CPU *, BI);
 247 BI crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *);
 248 void crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *, BI);
 249 BI crisv10f_h_nbit_get (SIM_CPU *);
 250 void crisv10f_h_nbit_set (SIM_CPU *, BI);
 251 BI crisv10f_h_nbit_move_get (SIM_CPU *);
 252 void crisv10f_h_nbit_move_set (SIM_CPU *, BI);
 253 BI crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *);
 254 void crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *, BI);
 255 BI crisv10f_h_xbit_get (SIM_CPU *);
 256 void crisv10f_h_xbit_set (SIM_CPU *, BI);
 257 BI crisv10f_h_ibit_get (SIM_CPU *);
 258 void crisv10f_h_ibit_set (SIM_CPU *, BI);
 259 BI crisv10f_h_ibit_pre_v32_get (SIM_CPU *);
 260 void crisv10f_h_ibit_pre_v32_set (SIM_CPU *, BI);
 261 BI crisv10f_h_pbit_get (SIM_CPU *);
 262 void crisv10f_h_pbit_set (SIM_CPU *, BI);
 263 BI crisv10f_h_ubit_get (SIM_CPU *);
 264 void crisv10f_h_ubit_set (SIM_CPU *, BI);
 265 BI crisv10f_h_ubit_pre_v32_get (SIM_CPU *);
 266 void crisv10f_h_ubit_pre_v32_set (SIM_CPU *, BI);
 267 BI crisv10f_h_insn_prefixed_p_get (SIM_CPU *);
 268 void crisv10f_h_insn_prefixed_p_set (SIM_CPU *, BI);
 269 BI crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *);
 270 void crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *, BI);
 271 SI crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *);
 272 void crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *, SI);
 273
 274 /* These must be hand-written.  */
 275 extern CPUREG_FETCH_FN crisv10f_fetch_register;
 276 extern CPUREG_STORE_FN crisv10f_store_register;
 277
 278 typedef struct {
 279   int empty;
 280 } MODEL_CRISV10_DATA;
 281
 282 /* Instruction argument buffer.  */
 283
 284 union sem_fields {
 285   struct { /* no operands */
 286     int empty;
 287   } sfmt_empty;
 288   struct { /*  */
 289     UINT f_u4;
 290   } sfmt_break;
 291   struct { /*  */
 292     UINT f_dstsrc;
 293   } sfmt_setf;
 294   struct { /*  */
 295     IADDR i_o_word_pcrel;
 296     UINT f_operand2;
 297   } sfmt_bcc_w;
 298   struct { /*  */
 299     IADDR i_o_pcrel;
 300     UINT f_operand2;
 301   } sfmt_bcc_b;
 302   struct { /*  */
 303     UINT f_memmode;
 304     unsigned char in_h_gr_SI_14;
 305     unsigned char out_h_gr_SI_14;
 306   } sfmt_move_m_spplus_p8;
 307   struct { /*  */
 308     INT f_s8;
 309     UINT f_operand2;
 310     unsigned char in_Rd;
 311   } sfmt_addoq;
 312   struct { /*  */
 313     INT f_indir_pc__dword;
 314     UINT f_operand2;
 315     unsigned char out_Pd;
 316   } sfmt_move_c_sprv10_p9;
 317   struct { /*  */
 318     INT f_indir_pc__word;
 319     UINT f_operand2;
 320     unsigned char out_Pd;
 321   } sfmt_move_c_sprv10_p5;
 322   struct { /*  */
 323     INT f_s6;
 324     UINT f_operand2;
 325     unsigned char out_Rd;
 326   } sfmt_moveq;
 327   struct { /*  */
 328     INT f_indir_pc__dword;
 329     UINT f_operand2;
 330     unsigned char in_Rd;
 331     unsigned char out_Rd;
 332   } sfmt_bound_cd;
 333   struct { /*  */
 334     INT f_indir_pc__word;
 335     UINT f_operand2;
 336     unsigned char in_Rd;
 337     unsigned char out_Rd;
 338   } sfmt_bound_cw;
 339   struct { /*  */
 340     INT f_indir_pc__byte;
 341     UINT f_operand2;
 342     unsigned char in_Rd;
 343     unsigned char out_Rd;
 344   } sfmt_bound_cb;
 345   struct { /*  */
 346     UINT f_operand2;
 347     UINT f_u5;
 348     unsigned char in_Rd;
 349     unsigned char out_Rd;
 350   } sfmt_asrq;
 351   struct { /*  */
 352     INT f_s6;
 353     UINT f_operand2;
 354     unsigned char in_Rd;
 355     unsigned char out_h_gr_SI_index_of__INT_Rd;
 356   } sfmt_andq;
 357   struct { /*  */
 358     INT f_indir_pc__dword;
 359     UINT f_operand2;
 360     unsigned char in_Rd;
 361     unsigned char out_h_gr_SI_index_of__INT_Rd;
 362   } sfmt_addcdr;
 363   struct { /*  */
 364     INT f_indir_pc__word;
 365     UINT f_operand2;
 366     unsigned char in_Rd;
 367     unsigned char out_h_gr_SI_index_of__INT_Rd;
 368   } sfmt_addcwr;
 369   struct { /*  */
 370     INT f_indir_pc__byte;
 371     UINT f_operand2;
 372     unsigned char in_Rd;
 373     unsigned char out_h_gr_SI_index_of__INT_Rd;
 374   } sfmt_addcbr;
 375   struct { /*  */
 376     UINT f_operand1;
 377     UINT f_operand2;
 378     unsigned char in_Ps;
 379     unsigned char out_h_gr_SI_index_of__INT_Rs;
 380   } sfmt_move_spr_rv10;
 381   struct { /*  */
 382     UINT f_operand2;
 383     UINT f_u6;
 384     unsigned char in_Rd;
 385     unsigned char out_h_gr_SI_index_of__INT_Rd;
 386   } sfmt_addq;
 387   struct { /*  */
 388     UINT f_operand1;
 389     UINT f_operand2;
 390     unsigned char in_Rd;
 391     unsigned char in_Rs;
 392     unsigned char out_h_gr_SI_index_of__INT_Rd;
 393   } sfmt_add_b_r;
 394   struct { /*  */
 395     UINT f_operand1;
 396     UINT f_operand2;
 397     unsigned char in_Rd;
 398     unsigned char in_Rs;
 399     unsigned char out_Rd;
 400     unsigned char out_h_sr_SI_7;
 401   } sfmt_muls_b;
 402   struct { /*  */
 403     UINT f_memmode;
 404     UINT f_operand1;
 405     UINT f_operand2;
 406     unsigned char in_Ps;
 407     unsigned char in_Rs;
 408     unsigned char out_Rs;
 409   } sfmt_move_spr_mv10;
 410   struct { /*  */
 411     UINT f_memmode;
 412     UINT f_operand1;
 413     UINT f_operand2;
 414     unsigned char in_Rs;
 415     unsigned char out_Pd;
 416     unsigned char out_Rs;
 417   } sfmt_move_m_sprv10;
 418   struct { /*  */
 419     UINT f_memmode;
 420     UINT f_operand1;
 421     UINT f_operand2;
 422     unsigned char in_Rd;
 423     unsigned char in_Rs;
 424     unsigned char out_Rd;
 425     unsigned char out_Rs;
 426   } sfmt_bound_m_b_m;
 427   struct { /*  */
 428     UINT f_memmode;
 429     UINT f_operand1;
 430     UINT f_operand2;
 431     unsigned char in_Rd;
 432     unsigned char in_Rs;
 433     unsigned char out_Rs;
 434     unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__UINT_inc_index_of__INT_Rs_index_of__INT_Rd;
 435   } sfmt_add_m_b_m;
 436   struct { /*  */
 437     UINT f_memmode;
 438     UINT f_operand1;
 439     UINT f_operand2;
 440     unsigned char in_Rd;
 441     unsigned char in_Rs;
 442     unsigned char out_Rs;
 443     unsigned char out_h_gr_SI_0;
 444     unsigned char out_h_gr_SI_1;
 445     unsigned char out_h_gr_SI_10;
 446     unsigned char out_h_gr_SI_11;
 447     unsigned char out_h_gr_SI_12;
 448     unsigned char out_h_gr_SI_13;
 449     unsigned char out_h_gr_SI_14;
 450     unsigned char out_h_gr_SI_2;
 451     unsigned char out_h_gr_SI_3;
 452     unsigned char out_h_gr_SI_4;
 453     unsigned char out_h_gr_SI_5;
 454     unsigned char out_h_gr_SI_6;
 455     unsigned char out_h_gr_SI_7;
 456     unsigned char out_h_gr_SI_8;
 457     unsigned char out_h_gr_SI_9;
 458   } sfmt_movem_m_r;
 459   struct { /*  */
 460     UINT f_memmode;
 461     UINT f_operand1;
 462     UINT f_operand2;
 463     unsigned char in_Rd;
 464     unsigned char in_Rs;
 465     unsigned char in_h_gr_SI_0;
 466     unsigned char in_h_gr_SI_1;
 467     unsigned char in_h_gr_SI_10;
 468     unsigned char in_h_gr_SI_11;
 469     unsigned char in_h_gr_SI_12;
 470     unsigned char in_h_gr_SI_13;
 471     unsigned char in_h_gr_SI_14;
 472     unsigned char in_h_gr_SI_15;
 473     unsigned char in_h_gr_SI_2;
 474     unsigned char in_h_gr_SI_3;
 475     unsigned char in_h_gr_SI_4;
 476     unsigned char in_h_gr_SI_5;
 477     unsigned char in_h_gr_SI_6;
 478     unsigned char in_h_gr_SI_7;
 479     unsigned char in_h_gr_SI_8;
 480     unsigned char in_h_gr_SI_9;
 481     unsigned char out_Rs;
 482   } sfmt_movem_r_m;
 483 #if WITH_SCACHE_PBB
 484   /* Writeback handler.  */
 485   struct {
 486     /* Pointer to argbuf entry for insn whose results need writing back.  */
 487     const struct argbuf *abuf;
 488   } write;
 489   /* x-before handler */
 490   struct {
 491     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 492     int first_p;
 493   } before;
 494   /* x-after handler */
 495   struct {
 496     int empty;
 497   } after;
 498   /* This entry is used to terminate each pbb.  */
 499   struct {
 500     /* Number of insns in pbb.  */
 501     int insn_count;
 502     /* Next pbb to execute.  */
 503     SCACHE *next;
 504     SCACHE *branch_target;
 505   } chain;
 506 #endif
 507 };
 508
 509 /* The ARGBUF struct.  */
 510 struct argbuf {
 511   /* These are the baseclass definitions.  */
 512   IADDR addr;
 513   const IDESC *idesc;
 514   char trace_p;
 515   char profile_p;
 516   /* ??? Temporary hack for skip insns.  */
 517   char skip_count;
 518   char unused;
 519   /* cpu specific data follows */
 520   union sem semantic;
 521   int written;
 522   union sem_fields fields;
 523 };
 524
 525 /* A cached insn.
 526
 527    ??? SCACHE used to contain more than just argbuf.  We could delete the
 528    type entirely and always just use ARGBUF, but for future concerns and as
 529    a level of abstraction it is left in.  */
 530
 531 struct scache {
 532   struct argbuf argbuf;
 533 };
 534
 535 /* Macros to simplify extraction, reading and semantic code.
 536    These define and assign the local vars that contain the insn's fields.  */
 537
 538 #define EXTRACT_IFMT_EMPTY_VARS \
 539   unsigned int length;
 540 #define EXTRACT_IFMT_EMPTY_CODE \
 541   length = 0; \
 542
 543 #define EXTRACT_IFMT_NOP_VARS \
 544   UINT f_operand2; \
 545   UINT f_mode; \
 546   UINT f_opcode; \
 547   UINT f_size; \
 548   UINT f_operand1; \
 549   unsigned int length;
 550 #define EXTRACT_IFMT_NOP_CODE \
 551   length = 2; \
 552   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 553   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 554   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 555   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 556   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 557
 558 #define EXTRACT_IFMT_MOVE_B_R_VARS \
 559   UINT f_operand2; \
 560   UINT f_mode; \
 561   UINT f_opcode; \
 562   UINT f_size; \
 563   UINT f_operand1; \
 564   unsigned int length;
 565 #define EXTRACT_IFMT_MOVE_B_R_CODE \
 566   length = 2; \
 567   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 568   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 569   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 570   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 571   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 572
 573 #define EXTRACT_IFMT_MOVEPCR_VARS \
 574   UINT f_operand2; \
 575   UINT f_mode; \
 576   UINT f_opcode; \
 577   UINT f_size; \
 578   UINT f_operand1; \
 579   unsigned int length;
 580 #define EXTRACT_IFMT_MOVEPCR_CODE \
 581   length = 2; \
 582   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 583   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 584   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 585   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 586   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 587
 588 #define EXTRACT_IFMT_MOVEQ_VARS \
 589   UINT f_operand2; \
 590   UINT f_mode; \
 591   UINT f_opcode; \
 592   INT f_s6; \
 593   unsigned int length;
 594 #define EXTRACT_IFMT_MOVEQ_CODE \
 595   length = 2; \
 596   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 597   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 598   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 599   f_s6 = EXTRACT_LSB0_SINT (insn, 16, 5, 6); \
 600
 601 #define EXTRACT_IFMT_MOVECBR_VARS \
 602   UINT f_operand2; \
 603   INT f_indir_pc__byte; \
 604   UINT f_mode; \
 605   UINT f_opcode; \
 606   UINT f_size; \
 607   UINT f_operand1; \
 608   /* Contents of trailing part of insn.  */ \
 609   UINT word_1; \
 610   unsigned int length;
 611 #define EXTRACT_IFMT_MOVECBR_CODE \
 612   length = 4; \
 613   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 614   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 615   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 616   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 617   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 618   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 619   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 620
 621 #define EXTRACT_IFMT_MOVECWR_VARS \
 622   UINT f_operand2; \
 623   INT f_indir_pc__word; \
 624   UINT f_mode; \
 625   UINT f_opcode; \
 626   UINT f_size; \
 627   UINT f_operand1; \
 628   /* Contents of trailing part of insn.  */ \
 629   UINT word_1; \
 630   unsigned int length;
 631 #define EXTRACT_IFMT_MOVECWR_CODE \
 632   length = 4; \
 633   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 634   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 635   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 636   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 637   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 638   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 639   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 640
 641 #define EXTRACT_IFMT_MOVECDR_VARS \
 642   INT f_indir_pc__dword; \
 643   UINT f_operand2; \
 644   UINT f_mode; \
 645   UINT f_opcode; \
 646   UINT f_size; \
 647   UINT f_operand1; \
 648   /* Contents of trailing part of insn.  */ \
 649   UINT word_1; \
 650   unsigned int length;
 651 #define EXTRACT_IFMT_MOVECDR_CODE \
 652   length = 6; \
 653   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 654   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 655   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 656   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 657   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 658   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 659   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 660
 661 #define EXTRACT_IFMT_MOVUCBR_VARS \
 662   UINT f_operand2; \
 663   INT f_indir_pc__byte; \
 664   UINT f_mode; \
 665   UINT f_opcode; \
 666   UINT f_size; \
 667   UINT f_operand1; \
 668   /* Contents of trailing part of insn.  */ \
 669   UINT word_1; \
 670   unsigned int length;
 671 #define EXTRACT_IFMT_MOVUCBR_CODE \
 672   length = 4; \
 673   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 674   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 675   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 676   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 677   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 678   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 679   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 680
 681 #define EXTRACT_IFMT_MOVUCWR_VARS \
 682   UINT f_operand2; \
 683   INT f_indir_pc__word; \
 684   UINT f_mode; \
 685   UINT f_opcode; \
 686   UINT f_size; \
 687   UINT f_operand1; \
 688   /* Contents of trailing part of insn.  */ \
 689   UINT word_1; \
 690   unsigned int length;
 691 #define EXTRACT_IFMT_MOVUCWR_CODE \
 692   length = 4; \
 693   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 694   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 695   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 696   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 697   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 698   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 699   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 700
 701 #define EXTRACT_IFMT_ADDQ_VARS \
 702   UINT f_operand2; \
 703   UINT f_mode; \
 704   UINT f_opcode; \
 705   UINT f_u6; \
 706   unsigned int length;
 707 #define EXTRACT_IFMT_ADDQ_CODE \
 708   length = 2; \
 709   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 710   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 711   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 712   f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
 713
 714 #define EXTRACT_IFMT_CMP_M_B_M_VARS \
 715   UINT f_operand2; \
 716   UINT f_membit; \
 717   UINT f_memmode; \
 718   UINT f_opcode; \
 719   UINT f_size; \
 720   UINT f_operand1; \
 721   unsigned int length;
 722 #define EXTRACT_IFMT_CMP_M_B_M_CODE \
 723   length = 2; \
 724   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 725   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 726   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 727   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 728   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 729   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 730
 731 #define EXTRACT_IFMT_MOVE_R_SPRV10_VARS \
 732   UINT f_operand2; \
 733   UINT f_mode; \
 734   UINT f_opcode; \
 735   UINT f_size; \
 736   UINT f_operand1; \
 737   unsigned int length;
 738 #define EXTRACT_IFMT_MOVE_R_SPRV10_CODE \
 739   length = 2; \
 740   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 741   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 742   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 743   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 744   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 745
 746 #define EXTRACT_IFMT_MOVE_SPR_RV10_VARS \
 747   UINT f_operand2; \
 748   UINT f_mode; \
 749   UINT f_opcode; \
 750   UINT f_size; \
 751   UINT f_operand1; \
 752   unsigned int length;
 753 #define EXTRACT_IFMT_MOVE_SPR_RV10_CODE \
 754   length = 2; \
 755   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 756   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 757   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 758   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 759   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 760
 761 #define EXTRACT_IFMT_RET_TYPE_VARS \
 762   UINT f_operand2; \
 763   UINT f_mode; \
 764   UINT f_opcode; \
 765   UINT f_size; \
 766   UINT f_operand1; \
 767   unsigned int length;
 768 #define EXTRACT_IFMT_RET_TYPE_CODE \
 769   length = 2; \
 770   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 771   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 772   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 773   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 774   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 775
 776 #define EXTRACT_IFMT_MOVE_M_SPRV10_VARS \
 777   UINT f_operand2; \
 778   UINT f_membit; \
 779   UINT f_memmode; \
 780   UINT f_opcode; \
 781   UINT f_size; \
 782   UINT f_operand1; \
 783   unsigned int length;
 784 #define EXTRACT_IFMT_MOVE_M_SPRV10_CODE \
 785   length = 2; \
 786   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 787   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 788   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 789   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 790   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 791   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 792
 793 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_VARS \
 794   UINT f_operand2; \
 795   INT f_indir_pc__word; \
 796   UINT f_mode; \
 797   UINT f_opcode; \
 798   UINT f_size; \
 799   UINT f_operand1; \
 800   /* Contents of trailing part of insn.  */ \
 801   UINT word_1; \
 802   unsigned int length;
 803 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_CODE \
 804   length = 4; \
 805   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 806   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 807   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 808   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 809   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 810   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 811   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 812
 813 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_VARS \
 814   INT f_indir_pc__dword; \
 815   UINT f_operand2; \
 816   UINT f_mode; \
 817   UINT f_opcode; \
 818   UINT f_size; \
 819   UINT f_operand1; \
 820   /* Contents of trailing part of insn.  */ \
 821   UINT word_1; \
 822   unsigned int length;
 823 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_CODE \
 824   length = 6; \
 825   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 826   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 827   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 828   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 829   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 830   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 831   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 832
 833 #define EXTRACT_IFMT_MOVE_SPR_MV10_VARS \
 834   UINT f_operand2; \
 835   UINT f_membit; \
 836   UINT f_memmode; \
 837   UINT f_opcode; \
 838   UINT f_size; \
 839   UINT f_operand1; \
 840   unsigned int length;
 841 #define EXTRACT_IFMT_MOVE_SPR_MV10_CODE \
 842   length = 2; \
 843   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 844   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 845   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 846   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 847   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 848   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 849
 850 #define EXTRACT_IFMT_SBFS_VARS \
 851   UINT f_operand2; \
 852   UINT f_membit; \
 853   UINT f_memmode; \
 854   UINT f_opcode; \
 855   UINT f_size; \
 856   UINT f_operand1; \
 857   unsigned int length;
 858 #define EXTRACT_IFMT_SBFS_CODE \
 859   length = 2; \
 860   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 861   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 862   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 863   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 864   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 865   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 866
 867 #define EXTRACT_IFMT_SWAP_VARS \
 868   UINT f_operand2; \
 869   UINT f_mode; \
 870   UINT f_opcode; \
 871   UINT f_size; \
 872   UINT f_operand1; \
 873   unsigned int length;
 874 #define EXTRACT_IFMT_SWAP_CODE \
 875   length = 2; \
 876   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 877   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 878   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 879   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 880   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 881
 882 #define EXTRACT_IFMT_ASRQ_VARS \
 883   UINT f_operand2; \
 884   UINT f_mode; \
 885   UINT f_opcode; \
 886   UINT f_b5; \
 887   UINT f_u5; \
 888   unsigned int length;
 889 #define EXTRACT_IFMT_ASRQ_CODE \
 890   length = 2; \
 891   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 892   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 893   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 894   f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
 895   f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
 896
 897 #define EXTRACT_IFMT_SETF_VARS \
 898   UINT f_mode; \
 899   UINT f_opcode; \
 900   UINT f_size; \
 901   UINT f_operand2; \
 902   UINT f_operand1; \
 903   UINT f_dstsrc; \
 904   unsigned int length;
 905 #define EXTRACT_IFMT_SETF_CODE \
 906   length = 2; \
 907   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 908   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 909   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 910   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 911   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 912   f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
 913
 914 #define EXTRACT_IFMT_BCC_B_VARS \
 915   UINT f_operand2; \
 916   UINT f_mode; \
 917   UINT f_opcode_hi; \
 918   INT f_disp9_hi; \
 919   UINT f_disp9_lo; \
 920   INT f_disp9; \
 921   unsigned int length;
 922 #define EXTRACT_IFMT_BCC_B_CODE \
 923   length = 2; \
 924   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 925   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 926   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
 927   f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \
 928   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 929 {\
 930   SI tmp_abslo;\
 931   SI tmp_absval;\
 932   tmp_abslo = ((f_disp9_lo) << (1));\
 933   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
 934   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
 935 }\
 936
 937 #define EXTRACT_IFMT_BA_B_VARS \
 938   UINT f_operand2; \
 939   UINT f_mode; \
 940   UINT f_opcode_hi; \
 941   INT f_disp9_hi; \
 942   UINT f_disp9_lo; \
 943   INT f_disp9; \
 944   unsigned int length;
 945 #define EXTRACT_IFMT_BA_B_CODE \
 946   length = 2; \
 947   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 948   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 949   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
 950   f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \
 951   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 952 {\
 953   SI tmp_abslo;\
 954   SI tmp_absval;\
 955   tmp_abslo = ((f_disp9_lo) << (1));\
 956   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
 957   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
 958 }\
 959
 960 #define EXTRACT_IFMT_BCC_W_VARS \
 961   UINT f_operand2; \
 962   SI f_indir_pc__word_pcrel; \
 963   UINT f_mode; \
 964   UINT f_opcode; \
 965   UINT f_size; \
 966   UINT f_operand1; \
 967   /* Contents of trailing part of insn.  */ \
 968   UINT word_1; \
 969   unsigned int length;
 970 #define EXTRACT_IFMT_BCC_W_CODE \
 971   length = 4; \
 972   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 973   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 974   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
 975   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 976   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 977   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 978   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 979
 980 #define EXTRACT_IFMT_BA_W_VARS \
 981   UINT f_operand2; \
 982   SI f_indir_pc__word_pcrel; \
 983   UINT f_mode; \
 984   UINT f_opcode; \
 985   UINT f_size; \
 986   UINT f_operand1; \
 987   /* Contents of trailing part of insn.  */ \
 988   UINT word_1; \
 989   unsigned int length;
 990 #define EXTRACT_IFMT_BA_W_CODE \
 991   length = 4; \
 992   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 993   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 994   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
 995   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 996   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 997   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 998   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 999
1000 #define EXTRACT_IFMT_JUMP_C_VARS \
1001   INT f_indir_pc__dword; \
1002   UINT f_operand2; \
1003   UINT f_mode; \
1004   UINT f_opcode; \
1005   UINT f_size; \
1006   UINT f_operand1; \
1007   /* Contents of trailing part of insn.  */ \
1008   UINT word_1; \
1009   unsigned int length;
1010 #define EXTRACT_IFMT_JUMP_C_CODE \
1011   length = 6; \
1012   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1013   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
1014   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1015   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1016   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1017   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1018   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1019
1020 #define EXTRACT_IFMT_BREAK_VARS \
1021   UINT f_operand2; \
1022   UINT f_mode; \
1023   UINT f_opcode; \
1024   UINT f_size; \
1025   UINT f_u4; \
1026   unsigned int length;
1027 #define EXTRACT_IFMT_BREAK_CODE \
1028   length = 2; \
1029   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1030   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1031   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1032   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1033   f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1034
1035 #define EXTRACT_IFMT_SCC_VARS \
1036   UINT f_operand2; \
1037   UINT f_mode; \
1038   UINT f_opcode; \
1039   UINT f_size; \
1040   UINT f_operand1; \
1041   unsigned int length;
1042 #define EXTRACT_IFMT_SCC_CODE \
1043   length = 2; \
1044   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1045   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1046   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1047   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1048   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1049
1050 #define EXTRACT_IFMT_ADDOQ_VARS \
1051   UINT f_operand2; \
1052   UINT f_mode; \
1053   UINT f_opcode_hi; \
1054   INT f_s8; \
1055   unsigned int length;
1056 #define EXTRACT_IFMT_ADDOQ_CODE \
1057   length = 2; \
1058   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1059   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1060   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1061   f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \
1062
1063 #define EXTRACT_IFMT_BDAPQPC_VARS \
1064   UINT f_operand2; \
1065   UINT f_mode; \
1066   UINT f_opcode_hi; \
1067   INT f_s8; \
1068   unsigned int length;
1069 #define EXTRACT_IFMT_BDAPQPC_CODE \
1070   length = 2; \
1071   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1072   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1073   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1074   f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \
1075
1076 /* Collection of various things for the trace handler to use.  */
1077
1078 typedef struct trace_record {
1079   IADDR pc;
1080   /* FIXME:wip */
1081 } TRACE_RECORD;
1082
1083 #endif /* CPU_CRISV10F_H */