sim/cris/semcrisv10f-switch.c

   1 /* Simulator instruction semantics for crisv10f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2015 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #ifdef DEFINE_LABELS
  25
  26   /* The labels have the case they have because the enum of insn types
  27      is all uppercase and in the non-stdc case the insn symbol is built
  28      into the enum name.  */
  29
  30   static struct {
  31     int index;
  32     void *label;
  33   } labels[] = {
  34     { CRISV10F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  35     { CRISV10F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  36     { CRISV10F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  37     { CRISV10F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  38     { CRISV10F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  39     { CRISV10F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  40     { CRISV10F_INSN_NOP, && case_sem_INSN_NOP },
  41     { CRISV10F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  42     { CRISV10F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  43     { CRISV10F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  44     { CRISV10F_INSN_MOVEPCR, && case_sem_INSN_MOVEPCR },
  45     { CRISV10F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  46     { CRISV10F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  47     { CRISV10F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  48     { CRISV10F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  49     { CRISV10F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  50     { CRISV10F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  51     { CRISV10F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  52     { CRISV10F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  53     { CRISV10F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  54     { CRISV10F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  55     { CRISV10F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  56     { CRISV10F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  57     { CRISV10F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  58     { CRISV10F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  59     { CRISV10F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  60     { CRISV10F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  61     { CRISV10F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  62     { CRISV10F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  63     { CRISV10F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  64     { CRISV10F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  65     { CRISV10F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  66     { CRISV10F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  67     { CRISV10F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  68     { CRISV10F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  69     { CRISV10F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  70     { CRISV10F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  71     { CRISV10F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  72     { CRISV10F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  73     { CRISV10F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  74     { CRISV10F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  75     { CRISV10F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  76     { CRISV10F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  77     { CRISV10F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  78     { CRISV10F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  79     { CRISV10F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  80     { CRISV10F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  81     { CRISV10F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  82     { CRISV10F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  83     { CRISV10F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  84     { CRISV10F_INSN_MOVE_R_SPRV10, && case_sem_INSN_MOVE_R_SPRV10 },
  85     { CRISV10F_INSN_MOVE_SPR_RV10, && case_sem_INSN_MOVE_SPR_RV10 },
  86     { CRISV10F_INSN_RET_TYPE, && case_sem_INSN_RET_TYPE },
  87     { CRISV10F_INSN_MOVE_M_SPRV10, && case_sem_INSN_MOVE_M_SPRV10 },
  88     { CRISV10F_INSN_MOVE_C_SPRV10_P5, && case_sem_INSN_MOVE_C_SPRV10_P5 },
  89     { CRISV10F_INSN_MOVE_C_SPRV10_P9, && case_sem_INSN_MOVE_C_SPRV10_P9 },
  90     { CRISV10F_INSN_MOVE_C_SPRV10_P10, && case_sem_INSN_MOVE_C_SPRV10_P10 },
  91     { CRISV10F_INSN_MOVE_C_SPRV10_P11, && case_sem_INSN_MOVE_C_SPRV10_P11 },
  92     { CRISV10F_INSN_MOVE_C_SPRV10_P12, && case_sem_INSN_MOVE_C_SPRV10_P12 },
  93     { CRISV10F_INSN_MOVE_C_SPRV10_P13, && case_sem_INSN_MOVE_C_SPRV10_P13 },
  94     { CRISV10F_INSN_MOVE_C_SPRV10_P7, && case_sem_INSN_MOVE_C_SPRV10_P7 },
  95     { CRISV10F_INSN_MOVE_C_SPRV10_P14, && case_sem_INSN_MOVE_C_SPRV10_P14 },
  96     { CRISV10F_INSN_MOVE_C_SPRV10_P15, && case_sem_INSN_MOVE_C_SPRV10_P15 },
  97     { CRISV10F_INSN_MOVE_SPR_MV10, && case_sem_INSN_MOVE_SPR_MV10 },
  98     { CRISV10F_INSN_SBFS, && case_sem_INSN_SBFS },
  99     { CRISV10F_INSN_MOVEM_R_M, && case_sem_INSN_MOVEM_R_M },
 100     { CRISV10F_INSN_MOVEM_M_R, && case_sem_INSN_MOVEM_M_R },
 101     { CRISV10F_INSN_MOVEM_M_PC, && case_sem_INSN_MOVEM_M_PC },
 102     { CRISV10F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 103     { CRISV10F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 104     { CRISV10F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 105     { CRISV10F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 106     { CRISV10F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 107     { CRISV10F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 108     { CRISV10F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 109     { CRISV10F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 110     { CRISV10F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 111     { CRISV10F_INSN_ADDCPC, && case_sem_INSN_ADDCPC },
 112     { CRISV10F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 113     { CRISV10F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 114     { CRISV10F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 115     { CRISV10F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 116     { CRISV10F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 117     { CRISV10F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 118     { CRISV10F_INSN_ADDSPCPC, && case_sem_INSN_ADDSPCPC },
 119     { CRISV10F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 120     { CRISV10F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 121     { CRISV10F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 122     { CRISV10F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 123     { CRISV10F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 124     { CRISV10F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 125     { CRISV10F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 126     { CRISV10F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 127     { CRISV10F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 128     { CRISV10F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 129     { CRISV10F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 130     { CRISV10F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 131     { CRISV10F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 132     { CRISV10F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 133     { CRISV10F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 134     { CRISV10F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 135     { CRISV10F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 136     { CRISV10F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 137     { CRISV10F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 138     { CRISV10F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 139     { CRISV10F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 140     { CRISV10F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 141     { CRISV10F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 142     { CRISV10F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 143     { CRISV10F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 144     { CRISV10F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 145     { CRISV10F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 146     { CRISV10F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 147     { CRISV10F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 148     { CRISV10F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 149     { CRISV10F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 150     { CRISV10F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 151     { CRISV10F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 152     { CRISV10F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 153     { CRISV10F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 154     { CRISV10F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 155     { CRISV10F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 156     { CRISV10F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 157     { CRISV10F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 158     { CRISV10F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 159     { CRISV10F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 160     { CRISV10F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 161     { CRISV10F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 162     { CRISV10F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 163     { CRISV10F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 164     { CRISV10F_INSN_MSTEP, && case_sem_INSN_MSTEP },
 165     { CRISV10F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 166     { CRISV10F_INSN_ABS, && case_sem_INSN_ABS },
 167     { CRISV10F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 168     { CRISV10F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 169     { CRISV10F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 170     { CRISV10F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 171     { CRISV10F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 172     { CRISV10F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 173     { CRISV10F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 174     { CRISV10F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 175     { CRISV10F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 176     { CRISV10F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 177     { CRISV10F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 178     { CRISV10F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 179     { CRISV10F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 180     { CRISV10F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 181     { CRISV10F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 182     { CRISV10F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 183     { CRISV10F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 184     { CRISV10F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 185     { CRISV10F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 186     { CRISV10F_INSN_ORQ, && case_sem_INSN_ORQ },
 187     { CRISV10F_INSN_XOR, && case_sem_INSN_XOR },
 188     { CRISV10F_INSN_SWAP, && case_sem_INSN_SWAP },
 189     { CRISV10F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 190     { CRISV10F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 191     { CRISV10F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 192     { CRISV10F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 193     { CRISV10F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 194     { CRISV10F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 195     { CRISV10F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 196     { CRISV10F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 197     { CRISV10F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 198     { CRISV10F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 199     { CRISV10F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 200     { CRISV10F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 201     { CRISV10F_INSN_BTST, && case_sem_INSN_BTST },
 202     { CRISV10F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 203     { CRISV10F_INSN_SETF, && case_sem_INSN_SETF },
 204     { CRISV10F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 205     { CRISV10F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 206     { CRISV10F_INSN_BA_B, && case_sem_INSN_BA_B },
 207     { CRISV10F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 208     { CRISV10F_INSN_BA_W, && case_sem_INSN_BA_W },
 209     { CRISV10F_INSN_JUMP_R, && case_sem_INSN_JUMP_R },
 210     { CRISV10F_INSN_JUMP_M, && case_sem_INSN_JUMP_M },
 211     { CRISV10F_INSN_JUMP_C, && case_sem_INSN_JUMP_C },
 212     { CRISV10F_INSN_BREAK, && case_sem_INSN_BREAK },
 213     { CRISV10F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 214     { CRISV10F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 215     { CRISV10F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 216     { CRISV10F_INSN_BOUND_M_B_M, && case_sem_INSN_BOUND_M_B_M },
 217     { CRISV10F_INSN_BOUND_M_W_M, && case_sem_INSN_BOUND_M_W_M },
 218     { CRISV10F_INSN_BOUND_M_D_M, && case_sem_INSN_BOUND_M_D_M },
 219     { CRISV10F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 220     { CRISV10F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 221     { CRISV10F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 222     { CRISV10F_INSN_SCC, && case_sem_INSN_SCC },
 223     { CRISV10F_INSN_LZ, && case_sem_INSN_LZ },
 224     { CRISV10F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 225     { CRISV10F_INSN_BDAPQPC, && case_sem_INSN_BDAPQPC },
 226     { CRISV10F_INSN_BDAP_32_PC, && case_sem_INSN_BDAP_32_PC },
 227     { CRISV10F_INSN_MOVE_M_PCPLUS_P0, && case_sem_INSN_MOVE_M_PCPLUS_P0 },
 228     { CRISV10F_INSN_MOVE_M_SPPLUS_P8, && case_sem_INSN_MOVE_M_SPPLUS_P8 },
 229     { CRISV10F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 230     { CRISV10F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 231     { CRISV10F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 232     { CRISV10F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 233     { CRISV10F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 234     { CRISV10F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 235     { CRISV10F_INSN_DIP_M, && case_sem_INSN_DIP_M },
 236     { CRISV10F_INSN_DIP_C, && case_sem_INSN_DIP_C },
 237     { CRISV10F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 238     { CRISV10F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 239     { CRISV10F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 240     { CRISV10F_INSN_BIAP_PC_B_R, && case_sem_INSN_BIAP_PC_B_R },
 241     { CRISV10F_INSN_BIAP_PC_W_R, && case_sem_INSN_BIAP_PC_W_R },
 242     { CRISV10F_INSN_BIAP_PC_D_R, && case_sem_INSN_BIAP_PC_D_R },
 243     { 0, 0 }
 244   };
 245   int i;
 246
 247   for (i = 0; labels[i].label != 0; ++i)
 248     {
 249 #if FAST_P
 250       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 251 #else
 252       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 253 #endif
 254     }
 255
 256 #undef DEFINE_LABELS
 257 #endif /* DEFINE_LABELS */
 258
 259 #ifdef DEFINE_SWITCH
 260
 261 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 262    off frills like tracing and profiling.  */
 263 /* FIXME: A better way would be to have TRACE_RESULT check for something
 264    that can cause it to be optimized out.  Another way would be to emit
 265    special handlers into the instruction "stream".  */
 266
 267 #if FAST_P
 268 #undef TRACE_RESULT
 269 #define TRACE_RESULT(cpu, abuf, name, type, val)
 270 #endif
 271
 272 #undef GET_ATTR
 273 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 274
 275 {
 276
 277 #if WITH_SCACHE_PBB
 278
 279 /* Branch to next handler without going around main loop.  */
 280 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 281 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 282
 283 #else /* ! WITH_SCACHE_PBB */
 284
 285 #define NEXT(vpc) BREAK (sem)
 286 #ifdef __GNUC__
 287 #if FAST_P
 288   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 289 #else
 290   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 291 #endif
 292 #else
 293   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 294 #endif
 295
 296 #endif /* ! WITH_SCACHE_PBB */
 297
 298     {
 299
 300   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 301 {
 302   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 303   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 304 #define FLD(f) abuf->fields.sfmt_empty.f
 305   int UNUSED written = 0;
 306   IADDR UNUSED pc = abuf->addr;
 307   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 308
 309   {
 310     /* Update the recorded pc in the cpu state struct.
 311        Only necessary for WITH_SCACHE case, but to avoid the
 312        conditional compilation ....  */
 313     SET_H_PC (pc);
 314     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 315        using the default-insn-bitsize spec.  When executing insns in parallel
 316        we may want to queue the fault and continue execution.  */
 317     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 318     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 319   }
 320
 321 #undef FLD
 322 }
 323   NEXT (vpc);
 324
 325   CASE (sem, INSN_X_AFTER) : /* --after-- */
 326 {
 327   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 328   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 329 #define FLD(f) abuf->fields.sfmt_empty.f
 330   int UNUSED written = 0;
 331   IADDR UNUSED pc = abuf->addr;
 332   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 333
 334   {
 335 #if WITH_SCACHE_PBB_CRISV10F
 336     crisv10f_pbb_after (current_cpu, sem_arg);
 337 #endif
 338   }
 339
 340 #undef FLD
 341 }
 342   NEXT (vpc);
 343
 344   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 345 {
 346   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 347   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 348 #define FLD(f) abuf->fields.sfmt_empty.f
 349   int UNUSED written = 0;
 350   IADDR UNUSED pc = abuf->addr;
 351   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 352
 353   {
 354 #if WITH_SCACHE_PBB_CRISV10F
 355     crisv10f_pbb_before (current_cpu, sem_arg);
 356 #endif
 357   }
 358
 359 #undef FLD
 360 }
 361   NEXT (vpc);
 362
 363   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 364 {
 365   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 366   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 367 #define FLD(f) abuf->fields.sfmt_empty.f
 368   int UNUSED written = 0;
 369   IADDR UNUSED pc = abuf->addr;
 370   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 371
 372   {
 373 #if WITH_SCACHE_PBB_CRISV10F
 374 #ifdef DEFINE_SWITCH
 375     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 376                                pbb_br_type, pbb_br_npc);
 377     BREAK (sem);
 378 #else
 379     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 380     vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
 381                                CPU_PBB_BR_TYPE (current_cpu),
 382                                CPU_PBB_BR_NPC (current_cpu));
 383 #endif
 384 #endif
 385   }
 386
 387 #undef FLD
 388 }
 389   NEXT (vpc);
 390
 391   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 392 {
 393   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 394   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 395 #define FLD(f) abuf->fields.sfmt_empty.f
 396   int UNUSED written = 0;
 397   IADDR UNUSED pc = abuf->addr;
 398   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 399
 400   {
 401 #if WITH_SCACHE_PBB_CRISV10F
 402     vpc = crisv10f_pbb_chain (current_cpu, sem_arg);
 403 #ifdef DEFINE_SWITCH
 404     BREAK (sem);
 405 #endif
 406 #endif
 407   }
 408
 409 #undef FLD
 410 }
 411   NEXT (vpc);
 412
 413   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 414 {
 415   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 416   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 417 #define FLD(f) abuf->fields.sfmt_empty.f
 418   int UNUSED written = 0;
 419   IADDR UNUSED pc = abuf->addr;
 420   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 421
 422   {
 423 #if WITH_SCACHE_PBB_CRISV10F
 424 #if defined DEFINE_SWITCH || defined FAST_P
 425     /* In the switch case FAST_P is a constant, allowing several optimizations
 426        in any called inline functions.  */
 427     vpc = crisv10f_pbb_begin (current_cpu, FAST_P);
 428 #else
 429 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 430     vpc = crisv10f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 431 #else
 432     vpc = crisv10f_pbb_begin (current_cpu, 0);
 433 #endif
 434 #endif
 435 #endif
 436   }
 437
 438 #undef FLD
 439 }
 440   NEXT (vpc);
 441
 442   CASE (sem, INSN_NOP) : /* nop */
 443 {
 444   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 445   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 446 #define FLD(f) abuf->fields.sfmt_empty.f
 447   int UNUSED written = 0;
 448   IADDR UNUSED pc = abuf->addr;
 449   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 450
 451 {
 452   {
 453     BI opval = 0;
 454     CPU (h_xbit) = opval;
 455     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 456   }
 457   {
 458     BI opval = 0;
 459     SET_H_INSN_PREFIXED_P (opval);
 460     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 461   }
 462 }
 463
 464 #undef FLD
 465 }
 466   NEXT (vpc);
 467
 468   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 469 {
 470   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 471   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 472 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 473   int UNUSED written = 0;
 474   IADDR UNUSED pc = abuf->addr;
 475   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 476
 477 {
 478   QI tmp_newval;
 479   tmp_newval = GET_H_GR (FLD (f_operand1));
 480 {
 481   SI tmp_oldregval;
 482   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 483   {
 484     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 485     SET_H_GR (FLD (f_operand2), opval);
 486     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 487   }
 488 }
 489 {
 490   {
 491     BI opval = LTQI (tmp_newval, 0);
 492     CPU (h_nbit) = opval;
 493     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 494   }
 495   {
 496     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 497     CPU (h_zbit) = opval;
 498     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 499   }
 500 SET_H_CBIT_MOVE (0);
 501 SET_H_VBIT_MOVE (0);
 502 {
 503   {
 504     BI opval = 0;
 505     CPU (h_xbit) = opval;
 506     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 507   }
 508   {
 509     BI opval = 0;
 510     SET_H_INSN_PREFIXED_P (opval);
 511     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 512   }
 513 }
 514 }
 515 }
 516
 517 #undef FLD
 518 }
 519   NEXT (vpc);
 520
 521   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 522 {
 523   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 524   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 525 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 526   int UNUSED written = 0;
 527   IADDR UNUSED pc = abuf->addr;
 528   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 529
 530 {
 531   HI tmp_newval;
 532   tmp_newval = GET_H_GR (FLD (f_operand1));
 533 {
 534   SI tmp_oldregval;
 535   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 536   {
 537     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 538     SET_H_GR (FLD (f_operand2), opval);
 539     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 540   }
 541 }
 542 {
 543   {
 544     BI opval = LTHI (tmp_newval, 0);
 545     CPU (h_nbit) = opval;
 546     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 547   }
 548   {
 549     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 550     CPU (h_zbit) = opval;
 551     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 552   }
 553 SET_H_CBIT_MOVE (0);
 554 SET_H_VBIT_MOVE (0);
 555 {
 556   {
 557     BI opval = 0;
 558     CPU (h_xbit) = opval;
 559     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 560   }
 561   {
 562     BI opval = 0;
 563     SET_H_INSN_PREFIXED_P (opval);
 564     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 565   }
 566 }
 567 }
 568 }
 569
 570 #undef FLD
 571 }
 572   NEXT (vpc);
 573
 574   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 575 {
 576   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 577   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 578 #define FLD(f) abuf->fields.sfmt_add_b_r.f
 579   int UNUSED written = 0;
 580   IADDR UNUSED pc = abuf->addr;
 581   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 582
 583 {
 584   SI tmp_newval;
 585   tmp_newval = GET_H_GR (FLD (f_operand1));
 586   {
 587     SI opval = tmp_newval;
 588     SET_H_GR (FLD (f_operand2), opval);
 589     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 590   }
 591 {
 592   {
 593     BI opval = LTSI (tmp_newval, 0);
 594     CPU (h_nbit) = opval;
 595     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 596   }
 597   {
 598     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 599     CPU (h_zbit) = opval;
 600     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 601   }
 602 SET_H_CBIT_MOVE (0);
 603 SET_H_VBIT_MOVE (0);
 604 {
 605   {
 606     BI opval = 0;
 607     CPU (h_xbit) = opval;
 608     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 609   }
 610   {
 611     BI opval = 0;
 612     SET_H_INSN_PREFIXED_P (opval);
 613     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 614   }
 615 }
 616 }
 617 }
 618
 619 #undef FLD
 620 }
 621   NEXT (vpc);
 622
 623   CASE (sem, INSN_MOVEPCR) : /* move.d PC,${Rd} */
 624 {
 625   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 626   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 627 #define FLD(f) abuf->fields.sfmt_moveq.f
 628   int UNUSED written = 0;
 629   IADDR UNUSED pc = abuf->addr;
 630   SEM_BRANCH_INIT
 631   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 632
 633 {
 634   SI tmp_pcval;
 635   tmp_pcval = ADDSI (pc, 2);
 636   {
 637     SI opval = tmp_pcval;
 638     SET_H_GR (FLD (f_operand2), opval);
 639     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 640   }
 641 {
 642   {
 643     BI opval = LTSI (tmp_pcval, 0);
 644     CPU (h_nbit) = opval;
 645     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 646   }
 647   {
 648     BI opval = ANDIF (EQSI (tmp_pcval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 649     CPU (h_zbit) = opval;
 650     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 651   }
 652 SET_H_CBIT_MOVE (0);
 653 SET_H_VBIT_MOVE (0);
 654 {
 655   {
 656     BI opval = 0;
 657     CPU (h_xbit) = opval;
 658     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 659   }
 660   {
 661     BI opval = 0;
 662     SET_H_INSN_PREFIXED_P (opval);
 663     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 664   }
 665 }
 666 }
 667 }
 668
 669   SEM_BRANCH_FINI (vpc);
 670 #undef FLD
 671 }
 672   NEXT (vpc);
 673
 674   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 675 {
 676   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 677   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 678 #define FLD(f) abuf->fields.sfmt_moveq.f
 679   int UNUSED written = 0;
 680   IADDR UNUSED pc = abuf->addr;
 681   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 682
 683 {
 684   SI tmp_newval;
 685   tmp_newval = FLD (f_s6);
 686   {
 687     SI opval = tmp_newval;
 688     SET_H_GR (FLD (f_operand2), opval);
 689     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 690   }
 691 {
 692 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 693 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 694 SET_H_CBIT_MOVE (0);
 695 SET_H_VBIT_MOVE (0);
 696 {
 697   {
 698     BI opval = 0;
 699     CPU (h_xbit) = opval;
 700     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 701   }
 702   {
 703     BI opval = 0;
 704     SET_H_INSN_PREFIXED_P (opval);
 705     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 706   }
 707 }
 708 }
 709 }
 710
 711 #undef FLD
 712 }
 713   NEXT (vpc);
 714
 715   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 716 {
 717   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 718   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 719 #define FLD(f) abuf->fields.sfmt_muls_b.f
 720   int UNUSED written = 0;
 721   IADDR UNUSED pc = abuf->addr;
 722   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 723
 724 {
 725   QI tmp_tmpops;
 726   SI tmp_newval;
 727   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 728   tmp_newval = EXTQISI (tmp_tmpops);
 729   {
 730     SI opval = tmp_newval;
 731     SET_H_GR (FLD (f_operand2), opval);
 732     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 733   }
 734 {
 735   {
 736     BI opval = LTSI (tmp_newval, 0);
 737     CPU (h_nbit) = opval;
 738     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 739   }
 740   {
 741     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 742     CPU (h_zbit) = opval;
 743     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 744   }
 745 SET_H_CBIT_MOVE (0);
 746 SET_H_VBIT_MOVE (0);
 747 {
 748   {
 749     BI opval = 0;
 750     CPU (h_xbit) = opval;
 751     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 752   }
 753   {
 754     BI opval = 0;
 755     SET_H_INSN_PREFIXED_P (opval);
 756     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 757   }
 758 }
 759 }
 760 }
 761
 762 #undef FLD
 763 }
 764   NEXT (vpc);
 765
 766   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 767 {
 768   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 769   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 770 #define FLD(f) abuf->fields.sfmt_muls_b.f
 771   int UNUSED written = 0;
 772   IADDR UNUSED pc = abuf->addr;
 773   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 774
 775 {
 776   HI tmp_tmpops;
 777   SI tmp_newval;
 778   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 779   tmp_newval = EXTHISI (tmp_tmpops);
 780   {
 781     SI opval = tmp_newval;
 782     SET_H_GR (FLD (f_operand2), opval);
 783     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 784   }
 785 {
 786   {
 787     BI opval = LTSI (tmp_newval, 0);
 788     CPU (h_nbit) = opval;
 789     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 790   }
 791   {
 792     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 793     CPU (h_zbit) = opval;
 794     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 795   }
 796 SET_H_CBIT_MOVE (0);
 797 SET_H_VBIT_MOVE (0);
 798 {
 799   {
 800     BI opval = 0;
 801     CPU (h_xbit) = opval;
 802     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 803   }
 804   {
 805     BI opval = 0;
 806     SET_H_INSN_PREFIXED_P (opval);
 807     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 808   }
 809 }
 810 }
 811 }
 812
 813 #undef FLD
 814 }
 815   NEXT (vpc);
 816
 817   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 818 {
 819   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 820   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 821 #define FLD(f) abuf->fields.sfmt_muls_b.f
 822   int UNUSED written = 0;
 823   IADDR UNUSED pc = abuf->addr;
 824   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 825
 826 {
 827   QI tmp_tmpops;
 828   SI tmp_newval;
 829   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 830   tmp_newval = ZEXTQISI (tmp_tmpops);
 831   {
 832     SI opval = tmp_newval;
 833     SET_H_GR (FLD (f_operand2), opval);
 834     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 835   }
 836 {
 837   {
 838     BI opval = LTSI (tmp_newval, 0);
 839     CPU (h_nbit) = opval;
 840     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 841   }
 842   {
 843     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 844     CPU (h_zbit) = opval;
 845     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 846   }
 847 SET_H_CBIT_MOVE (0);
 848 SET_H_VBIT_MOVE (0);
 849 {
 850   {
 851     BI opval = 0;
 852     CPU (h_xbit) = opval;
 853     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 854   }
 855   {
 856     BI opval = 0;
 857     SET_H_INSN_PREFIXED_P (opval);
 858     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 859   }
 860 }
 861 }
 862 }
 863
 864 #undef FLD
 865 }
 866   NEXT (vpc);
 867
 868   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 869 {
 870   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 871   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 872 #define FLD(f) abuf->fields.sfmt_muls_b.f
 873   int UNUSED written = 0;
 874   IADDR UNUSED pc = abuf->addr;
 875   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 876
 877 {
 878   HI tmp_tmpops;
 879   SI tmp_newval;
 880   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 881   tmp_newval = ZEXTHISI (tmp_tmpops);
 882   {
 883     SI opval = tmp_newval;
 884     SET_H_GR (FLD (f_operand2), opval);
 885     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 886   }
 887 {
 888   {
 889     BI opval = LTSI (tmp_newval, 0);
 890     CPU (h_nbit) = opval;
 891     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 892   }
 893   {
 894     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 895     CPU (h_zbit) = opval;
 896     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 897   }
 898 SET_H_CBIT_MOVE (0);
 899 SET_H_VBIT_MOVE (0);
 900 {
 901   {
 902     BI opval = 0;
 903     CPU (h_xbit) = opval;
 904     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 905   }
 906   {
 907     BI opval = 0;
 908     SET_H_INSN_PREFIXED_P (opval);
 909     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 910   }
 911 }
 912 }
 913 }
 914
 915 #undef FLD
 916 }
 917   NEXT (vpc);
 918
 919   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 920 {
 921   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 922   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 923 #define FLD(f) abuf->fields.sfmt_addcbr.f
 924   int UNUSED written = 0;
 925   IADDR UNUSED pc = abuf->addr;
 926   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 927
 928 {
 929   QI tmp_newval;
 930   tmp_newval = FLD (f_indir_pc__byte);
 931 {
 932   SI tmp_oldregval;
 933   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 934   {
 935     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 936     SET_H_GR (FLD (f_operand2), opval);
 937     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 938   }
 939 }
 940 {
 941   {
 942     BI opval = LTQI (tmp_newval, 0);
 943     CPU (h_nbit) = opval;
 944     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 945   }
 946   {
 947     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 948     CPU (h_zbit) = opval;
 949     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 950   }
 951 SET_H_CBIT_MOVE (0);
 952 SET_H_VBIT_MOVE (0);
 953 {
 954   {
 955     BI opval = 0;
 956     CPU (h_xbit) = opval;
 957     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 958   }
 959   {
 960     BI opval = 0;
 961     SET_H_INSN_PREFIXED_P (opval);
 962     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 963   }
 964 }
 965 }
 966 }
 967
 968 #undef FLD
 969 }
 970   NEXT (vpc);
 971
 972   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 973 {
 974   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 975   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 976 #define FLD(f) abuf->fields.sfmt_addcwr.f
 977   int UNUSED written = 0;
 978   IADDR UNUSED pc = abuf->addr;
 979   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 980
 981 {
 982   HI tmp_newval;
 983   tmp_newval = FLD (f_indir_pc__word);
 984 {
 985   SI tmp_oldregval;
 986   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
 987   {
 988     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 989     SET_H_GR (FLD (f_operand2), opval);
 990     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 991   }
 992 }
 993 {
 994   {
 995     BI opval = LTHI (tmp_newval, 0);
 996     CPU (h_nbit) = opval;
 997     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 998   }
 999   {
1000     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1001     CPU (h_zbit) = opval;
1002     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1003   }
1004 SET_H_CBIT_MOVE (0);
1005 SET_H_VBIT_MOVE (0);
1006 {
1007   {
1008     BI opval = 0;
1009     CPU (h_xbit) = opval;
1010     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1011   }
1012   {
1013     BI opval = 0;
1014     SET_H_INSN_PREFIXED_P (opval);
1015     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1016   }
1017 }
1018 }
1019 }
1020
1021 #undef FLD
1022 }
1023   NEXT (vpc);
1024
1025   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
1026 {
1027   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1028   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1029 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1030   int UNUSED written = 0;
1031   IADDR UNUSED pc = abuf->addr;
1032   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1033
1034 {
1035   SI tmp_newval;
1036   tmp_newval = FLD (f_indir_pc__dword);
1037   {
1038     SI opval = tmp_newval;
1039     SET_H_GR (FLD (f_operand2), opval);
1040     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1041   }
1042 {
1043   {
1044     BI opval = LTSI (tmp_newval, 0);
1045     CPU (h_nbit) = opval;
1046     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1047   }
1048   {
1049     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1050     CPU (h_zbit) = opval;
1051     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1052   }
1053 SET_H_CBIT_MOVE (0);
1054 SET_H_VBIT_MOVE (0);
1055 {
1056   {
1057     BI opval = 0;
1058     CPU (h_xbit) = opval;
1059     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1060   }
1061   {
1062     BI opval = 0;
1063     SET_H_INSN_PREFIXED_P (opval);
1064     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1065   }
1066 }
1067 }
1068 }
1069
1070 #undef FLD
1071 }
1072   NEXT (vpc);
1073
1074   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
1075 {
1076   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1077   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1078 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1079   int UNUSED written = 0;
1080   IADDR UNUSED pc = abuf->addr;
1081   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1082
1083 {
1084   SI tmp_newval;
1085   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1086   {
1087     SI opval = tmp_newval;
1088     SET_H_GR (FLD (f_operand2), opval);
1089     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1090   }
1091 {
1092   {
1093     BI opval = LTSI (tmp_newval, 0);
1094     CPU (h_nbit) = opval;
1095     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1096   }
1097   {
1098     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1099     CPU (h_zbit) = opval;
1100     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1101   }
1102 SET_H_CBIT_MOVE (0);
1103 SET_H_VBIT_MOVE (0);
1104 {
1105   {
1106     BI opval = 0;
1107     CPU (h_xbit) = opval;
1108     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1109   }
1110   {
1111     BI opval = 0;
1112     SET_H_INSN_PREFIXED_P (opval);
1113     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1114   }
1115 }
1116 }
1117 }
1118
1119 #undef FLD
1120 }
1121   NEXT (vpc);
1122
1123   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1124 {
1125   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1126   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1127 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1128   int UNUSED written = 0;
1129   IADDR UNUSED pc = abuf->addr;
1130   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1131
1132 {
1133   SI tmp_newval;
1134   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1135   {
1136     SI opval = tmp_newval;
1137     SET_H_GR (FLD (f_operand2), opval);
1138     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1139   }
1140 {
1141   {
1142     BI opval = LTSI (tmp_newval, 0);
1143     CPU (h_nbit) = opval;
1144     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1145   }
1146   {
1147     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1148     CPU (h_zbit) = opval;
1149     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1150   }
1151 SET_H_CBIT_MOVE (0);
1152 SET_H_VBIT_MOVE (0);
1153 {
1154   {
1155     BI opval = 0;
1156     CPU (h_xbit) = opval;
1157     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1158   }
1159   {
1160     BI opval = 0;
1161     SET_H_INSN_PREFIXED_P (opval);
1162     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1163   }
1164 }
1165 }
1166 }
1167
1168 #undef FLD
1169 }
1170   NEXT (vpc);
1171
1172   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1173 {
1174   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1175   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1176 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1177   int UNUSED written = 0;
1178   IADDR UNUSED pc = abuf->addr;
1179   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1180
1181 {
1182   SI tmp_newval;
1183   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1184   {
1185     SI opval = tmp_newval;
1186     SET_H_GR (FLD (f_operand2), opval);
1187     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1188   }
1189 {
1190   {
1191     BI opval = LTSI (tmp_newval, 0);
1192     CPU (h_nbit) = opval;
1193     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1194   }
1195   {
1196     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1197     CPU (h_zbit) = opval;
1198     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1199   }
1200 SET_H_CBIT_MOVE (0);
1201 SET_H_VBIT_MOVE (0);
1202 {
1203   {
1204     BI opval = 0;
1205     CPU (h_xbit) = opval;
1206     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1207   }
1208   {
1209     BI opval = 0;
1210     SET_H_INSN_PREFIXED_P (opval);
1211     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1212   }
1213 }
1214 }
1215 }
1216
1217 #undef FLD
1218 }
1219   NEXT (vpc);
1220
1221   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1222 {
1223   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1224   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1225 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1226   int UNUSED written = 0;
1227   IADDR UNUSED pc = abuf->addr;
1228   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1229
1230 {
1231   SI tmp_newval;
1232   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1233   {
1234     SI opval = tmp_newval;
1235     SET_H_GR (FLD (f_operand2), opval);
1236     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1237   }
1238 {
1239   {
1240     BI opval = LTSI (tmp_newval, 0);
1241     CPU (h_nbit) = opval;
1242     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1243   }
1244   {
1245     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1246     CPU (h_zbit) = opval;
1247     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1248   }
1249 SET_H_CBIT_MOVE (0);
1250 SET_H_VBIT_MOVE (0);
1251 {
1252   {
1253     BI opval = 0;
1254     CPU (h_xbit) = opval;
1255     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1256   }
1257   {
1258     BI opval = 0;
1259     SET_H_INSN_PREFIXED_P (opval);
1260     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1261   }
1262 }
1263 }
1264 }
1265
1266 #undef FLD
1267 }
1268   NEXT (vpc);
1269
1270   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1271 {
1272   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1273   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1274 #define FLD(f) abuf->fields.sfmt_addq.f
1275   int UNUSED written = 0;
1276   IADDR UNUSED pc = abuf->addr;
1277   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1278
1279 {
1280   SI tmp_tmpopd;
1281   SI tmp_tmpops;
1282   BI tmp_carry;
1283   SI tmp_newval;
1284   tmp_tmpops = FLD (f_u6);
1285   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1286   tmp_carry = CPU (h_cbit);
1287   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1288   {
1289     SI opval = tmp_newval;
1290     SET_H_GR (FLD (f_operand2), opval);
1291     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1292   }
1293 {
1294   {
1295     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1296     CPU (h_cbit) = opval;
1297     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1298   }
1299   {
1300     BI opval = LTSI (tmp_newval, 0);
1301     CPU (h_nbit) = opval;
1302     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1303   }
1304   {
1305     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1306     CPU (h_zbit) = opval;
1307     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1308   }
1309   {
1310     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1311     CPU (h_vbit) = opval;
1312     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1313   }
1314 {
1315   {
1316     BI opval = 0;
1317     CPU (h_xbit) = opval;
1318     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1319   }
1320   {
1321     BI opval = 0;
1322     SET_H_INSN_PREFIXED_P (opval);
1323     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1324   }
1325 }
1326 }
1327 }
1328
1329 #undef FLD
1330 }
1331   NEXT (vpc);
1332
1333   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1334 {
1335   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1336   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1337 #define FLD(f) abuf->fields.sfmt_addq.f
1338   int UNUSED written = 0;
1339   IADDR UNUSED pc = abuf->addr;
1340   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1341
1342 {
1343   SI tmp_tmpopd;
1344   SI tmp_tmpops;
1345   BI tmp_carry;
1346   SI tmp_newval;
1347   tmp_tmpops = FLD (f_u6);
1348   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1349   tmp_carry = CPU (h_cbit);
1350   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1351   {
1352     SI opval = tmp_newval;
1353     SET_H_GR (FLD (f_operand2), opval);
1354     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1355   }
1356 {
1357   {
1358     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1359     CPU (h_cbit) = opval;
1360     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1361   }
1362   {
1363     BI opval = LTSI (tmp_newval, 0);
1364     CPU (h_nbit) = opval;
1365     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1366   }
1367   {
1368     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1369     CPU (h_zbit) = opval;
1370     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1371   }
1372   {
1373     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1374     CPU (h_vbit) = opval;
1375     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1376   }
1377 {
1378   {
1379     BI opval = 0;
1380     CPU (h_xbit) = opval;
1381     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1382   }
1383   {
1384     BI opval = 0;
1385     SET_H_INSN_PREFIXED_P (opval);
1386     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1387   }
1388 }
1389 }
1390 }
1391
1392 #undef FLD
1393 }
1394   NEXT (vpc);
1395
1396   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1397 {
1398   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1399   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1400 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1401   int UNUSED written = 0;
1402   IADDR UNUSED pc = abuf->addr;
1403   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1404
1405 {
1406   QI tmp_tmpopd;
1407   QI tmp_tmpops;
1408   BI tmp_carry;
1409   QI tmp_newval;
1410   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1411   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1412   tmp_carry = CPU (h_cbit);
1413   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1414 ((void) 0); /*nop*/
1415 {
1416   {
1417     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1418     CPU (h_cbit) = opval;
1419     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1420   }
1421   {
1422     BI opval = LTQI (tmp_newval, 0);
1423     CPU (h_nbit) = opval;
1424     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1425   }
1426   {
1427     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1428     CPU (h_zbit) = opval;
1429     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1430   }
1431   {
1432     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1433     CPU (h_vbit) = opval;
1434     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1435   }
1436 {
1437   {
1438     BI opval = 0;
1439     CPU (h_xbit) = opval;
1440     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1441   }
1442   {
1443     BI opval = 0;
1444     SET_H_INSN_PREFIXED_P (opval);
1445     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1446   }
1447 }
1448 }
1449 }
1450
1451 #undef FLD
1452 }
1453   NEXT (vpc);
1454
1455   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1456 {
1457   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1458   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1459 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1460   int UNUSED written = 0;
1461   IADDR UNUSED pc = abuf->addr;
1462   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1463
1464 {
1465   HI tmp_tmpopd;
1466   HI tmp_tmpops;
1467   BI tmp_carry;
1468   HI tmp_newval;
1469   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1470   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1471   tmp_carry = CPU (h_cbit);
1472   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1473 ((void) 0); /*nop*/
1474 {
1475   {
1476     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1477     CPU (h_cbit) = opval;
1478     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1479   }
1480   {
1481     BI opval = LTHI (tmp_newval, 0);
1482     CPU (h_nbit) = opval;
1483     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1484   }
1485   {
1486     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1487     CPU (h_zbit) = opval;
1488     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1489   }
1490   {
1491     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1492     CPU (h_vbit) = opval;
1493     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1494   }
1495 {
1496   {
1497     BI opval = 0;
1498     CPU (h_xbit) = opval;
1499     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1500   }
1501   {
1502     BI opval = 0;
1503     SET_H_INSN_PREFIXED_P (opval);
1504     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1505   }
1506 }
1507 }
1508 }
1509
1510 #undef FLD
1511 }
1512   NEXT (vpc);
1513
1514   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1515 {
1516   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1517   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1518 #define FLD(f) abuf->fields.sfmt_add_b_r.f
1519   int UNUSED written = 0;
1520   IADDR UNUSED pc = abuf->addr;
1521   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1522
1523 {
1524   SI tmp_tmpopd;
1525   SI tmp_tmpops;
1526   BI tmp_carry;
1527   SI tmp_newval;
1528   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1529   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1530   tmp_carry = CPU (h_cbit);
1531   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1532 ((void) 0); /*nop*/
1533 {
1534   {
1535     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1536     CPU (h_cbit) = opval;
1537     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1538   }
1539   {
1540     BI opval = LTSI (tmp_newval, 0);
1541     CPU (h_nbit) = opval;
1542     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1543   }
1544   {
1545     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1546     CPU (h_zbit) = opval;
1547     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1548   }
1549   {
1550     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1551     CPU (h_vbit) = opval;
1552     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1553   }
1554 {
1555   {
1556     BI opval = 0;
1557     CPU (h_xbit) = opval;
1558     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1559   }
1560   {
1561     BI opval = 0;
1562     SET_H_INSN_PREFIXED_P (opval);
1563     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1564   }
1565 }
1566 }
1567 }
1568
1569 #undef FLD
1570 }
1571   NEXT (vpc);
1572
1573   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1574 {
1575   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1576   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1577 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1578   int UNUSED written = 0;
1579   IADDR UNUSED pc = abuf->addr;
1580   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1581
1582 {
1583   QI tmp_tmpopd;
1584   QI tmp_tmpops;
1585   BI tmp_carry;
1586   QI tmp_newval;
1587   tmp_tmpops = ({   SI tmp_addr;
1588   QI tmp_tmp_mem;
1589   BI tmp_postinc;
1590   tmp_postinc = FLD (f_memmode);
1591 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1592 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1593 ; if (NEBI (tmp_postinc, 0)) {
1594 {
1595 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1596   tmp_addr = ADDSI (tmp_addr, 1);
1597 }
1598   {
1599     SI opval = tmp_addr;
1600     SET_H_GR (FLD (f_operand1), opval);
1601     written |= (1 << 9);
1602     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1603   }
1604 }
1605 }
1606 ; tmp_tmp_mem; });
1607   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1608   tmp_carry = CPU (h_cbit);
1609   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1610 ((void) 0); /*nop*/
1611 {
1612   {
1613     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1614     CPU (h_cbit) = opval;
1615     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1616   }
1617   {
1618     BI opval = LTQI (tmp_newval, 0);
1619     CPU (h_nbit) = opval;
1620     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1621   }
1622   {
1623     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1624     CPU (h_zbit) = opval;
1625     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1626   }
1627   {
1628     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1629     CPU (h_vbit) = opval;
1630     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1631   }
1632 {
1633   {
1634     BI opval = 0;
1635     CPU (h_xbit) = opval;
1636     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1637   }
1638   {
1639     BI opval = 0;
1640     SET_H_INSN_PREFIXED_P (opval);
1641     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1642   }
1643 }
1644 }
1645 }
1646
1647   abuf->written = written;
1648 #undef FLD
1649 }
1650   NEXT (vpc);
1651
1652   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1653 {
1654   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1655   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1656 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1657   int UNUSED written = 0;
1658   IADDR UNUSED pc = abuf->addr;
1659   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1660
1661 {
1662   HI tmp_tmpopd;
1663   HI tmp_tmpops;
1664   BI tmp_carry;
1665   HI tmp_newval;
1666   tmp_tmpops = ({   SI tmp_addr;
1667   HI tmp_tmp_mem;
1668   BI tmp_postinc;
1669   tmp_postinc = FLD (f_memmode);
1670 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1671 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1672 ; if (NEBI (tmp_postinc, 0)) {
1673 {
1674 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1675   tmp_addr = ADDSI (tmp_addr, 2);
1676 }
1677   {
1678     SI opval = tmp_addr;
1679     SET_H_GR (FLD (f_operand1), opval);
1680     written |= (1 << 9);
1681     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1682   }
1683 }
1684 }
1685 ; tmp_tmp_mem; });
1686   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1687   tmp_carry = CPU (h_cbit);
1688   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1689 ((void) 0); /*nop*/
1690 {
1691   {
1692     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1693     CPU (h_cbit) = opval;
1694     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1695   }
1696   {
1697     BI opval = LTHI (tmp_newval, 0);
1698     CPU (h_nbit) = opval;
1699     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1700   }
1701   {
1702     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1703     CPU (h_zbit) = opval;
1704     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1705   }
1706   {
1707     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1708     CPU (h_vbit) = opval;
1709     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1710   }
1711 {
1712   {
1713     BI opval = 0;
1714     CPU (h_xbit) = opval;
1715     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1716   }
1717   {
1718     BI opval = 0;
1719     SET_H_INSN_PREFIXED_P (opval);
1720     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1721   }
1722 }
1723 }
1724 }
1725
1726   abuf->written = written;
1727 #undef FLD
1728 }
1729   NEXT (vpc);
1730
1731   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1732 {
1733   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1734   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1735 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
1736   int UNUSED written = 0;
1737   IADDR UNUSED pc = abuf->addr;
1738   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1739
1740 {
1741   SI tmp_tmpopd;
1742   SI tmp_tmpops;
1743   BI tmp_carry;
1744   SI tmp_newval;
1745   tmp_tmpops = ({   SI tmp_addr;
1746   SI tmp_tmp_mem;
1747   BI tmp_postinc;
1748   tmp_postinc = FLD (f_memmode);
1749 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
1750 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1751 ; if (NEBI (tmp_postinc, 0)) {
1752 {
1753 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1754   tmp_addr = ADDSI (tmp_addr, 4);
1755 }
1756   {
1757     SI opval = tmp_addr;
1758     SET_H_GR (FLD (f_operand1), opval);
1759     written |= (1 << 9);
1760     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1761   }
1762 }
1763 }
1764 ; tmp_tmp_mem; });
1765   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1766   tmp_carry = CPU (h_cbit);
1767   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1768 ((void) 0); /*nop*/
1769 {
1770   {
1771     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1772     CPU (h_cbit) = opval;
1773     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1774   }
1775   {
1776     BI opval = LTSI (tmp_newval, 0);
1777     CPU (h_nbit) = opval;
1778     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1779   }
1780   {
1781     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1782     CPU (h_zbit) = opval;
1783     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1784   }
1785   {
1786     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1787     CPU (h_vbit) = opval;
1788     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1789   }
1790 {
1791   {
1792     BI opval = 0;
1793     CPU (h_xbit) = opval;
1794     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1795   }
1796   {
1797     BI opval = 0;
1798     SET_H_INSN_PREFIXED_P (opval);
1799     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1800   }
1801 }
1802 }
1803 }
1804
1805   abuf->written = written;
1806 #undef FLD
1807 }
1808   NEXT (vpc);
1809
1810   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1811 {
1812   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1813   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1814 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1815   int UNUSED written = 0;
1816   IADDR UNUSED pc = abuf->addr;
1817   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1818
1819 {
1820   QI tmp_tmpopd;
1821   QI tmp_tmpops;
1822   BI tmp_carry;
1823   QI tmp_newval;
1824   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1825   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1826   tmp_carry = CPU (h_cbit);
1827   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1828 ((void) 0); /*nop*/
1829 {
1830   {
1831     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1832     CPU (h_cbit) = opval;
1833     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1834   }
1835   {
1836     BI opval = LTQI (tmp_newval, 0);
1837     CPU (h_nbit) = opval;
1838     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1839   }
1840   {
1841     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1842     CPU (h_zbit) = opval;
1843     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1844   }
1845   {
1846     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1847     CPU (h_vbit) = opval;
1848     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1849   }
1850 {
1851   {
1852     BI opval = 0;
1853     CPU (h_xbit) = opval;
1854     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1855   }
1856   {
1857     BI opval = 0;
1858     SET_H_INSN_PREFIXED_P (opval);
1859     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1860   }
1861 }
1862 }
1863 }
1864
1865 #undef FLD
1866 }
1867   NEXT (vpc);
1868
1869   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1870 {
1871   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1872   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1873 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1874   int UNUSED written = 0;
1875   IADDR UNUSED pc = abuf->addr;
1876   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1877
1878 {
1879   HI tmp_tmpopd;
1880   HI tmp_tmpops;
1881   BI tmp_carry;
1882   HI tmp_newval;
1883   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1884   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1885   tmp_carry = CPU (h_cbit);
1886   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1887 ((void) 0); /*nop*/
1888 {
1889   {
1890     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1891     CPU (h_cbit) = opval;
1892     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1893   }
1894   {
1895     BI opval = LTHI (tmp_newval, 0);
1896     CPU (h_nbit) = opval;
1897     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1898   }
1899   {
1900     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1901     CPU (h_zbit) = opval;
1902     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1903   }
1904   {
1905     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1906     CPU (h_vbit) = opval;
1907     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1908   }
1909 {
1910   {
1911     BI opval = 0;
1912     CPU (h_xbit) = opval;
1913     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1914   }
1915   {
1916     BI opval = 0;
1917     SET_H_INSN_PREFIXED_P (opval);
1918     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1919   }
1920 }
1921 }
1922 }
1923
1924 #undef FLD
1925 }
1926   NEXT (vpc);
1927
1928   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1929 {
1930   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1931   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1932 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1933   int UNUSED written = 0;
1934   IADDR UNUSED pc = abuf->addr;
1935   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1936
1937 {
1938   SI tmp_tmpopd;
1939   SI tmp_tmpops;
1940   BI tmp_carry;
1941   SI tmp_newval;
1942   tmp_tmpops = FLD (f_indir_pc__dword);
1943   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1944   tmp_carry = CPU (h_cbit);
1945   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1946 ((void) 0); /*nop*/
1947 {
1948   {
1949     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1950     CPU (h_cbit) = opval;
1951     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1952   }
1953   {
1954     BI opval = LTSI (tmp_newval, 0);
1955     CPU (h_nbit) = opval;
1956     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1957   }
1958   {
1959     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1960     CPU (h_zbit) = opval;
1961     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1962   }
1963   {
1964     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1965     CPU (h_vbit) = opval;
1966     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1967   }
1968 {
1969   {
1970     BI opval = 0;
1971     CPU (h_xbit) = opval;
1972     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1973   }
1974   {
1975     BI opval = 0;
1976     SET_H_INSN_PREFIXED_P (opval);
1977     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1978   }
1979 }
1980 }
1981 }
1982
1983 #undef FLD
1984 }
1985   NEXT (vpc);
1986
1987   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1988 {
1989   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1990   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1991 #define FLD(f) abuf->fields.sfmt_andq.f
1992   int UNUSED written = 0;
1993   IADDR UNUSED pc = abuf->addr;
1994   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1995
1996 {
1997   SI tmp_tmpopd;
1998   SI tmp_tmpops;
1999   BI tmp_carry;
2000   SI tmp_newval;
2001   tmp_tmpops = FLD (f_s6);
2002   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2003   tmp_carry = CPU (h_cbit);
2004   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2005 ((void) 0); /*nop*/
2006 {
2007   {
2008     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2009     CPU (h_cbit) = opval;
2010     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2011   }
2012   {
2013     BI opval = LTSI (tmp_newval, 0);
2014     CPU (h_nbit) = opval;
2015     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2016   }
2017   {
2018     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2019     CPU (h_zbit) = opval;
2020     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2021   }
2022   {
2023     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2024     CPU (h_vbit) = opval;
2025     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2026   }
2027 {
2028   {
2029     BI opval = 0;
2030     CPU (h_xbit) = opval;
2031     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2032   }
2033   {
2034     BI opval = 0;
2035     SET_H_INSN_PREFIXED_P (opval);
2036     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2037   }
2038 }
2039 }
2040 }
2041
2042 #undef FLD
2043 }
2044   NEXT (vpc);
2045
2046   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
2047 {
2048   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2049   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2050 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2051   int UNUSED written = 0;
2052   IADDR UNUSED pc = abuf->addr;
2053   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2054
2055 {
2056   SI tmp_tmpopd;
2057   SI tmp_tmpops;
2058   BI tmp_carry;
2059   SI tmp_newval;
2060   tmp_tmpops = EXTQISI (({   SI tmp_addr;
2061   QI tmp_tmp_mem;
2062   BI tmp_postinc;
2063   tmp_postinc = FLD (f_memmode);
2064 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2065 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2066 ; if (NEBI (tmp_postinc, 0)) {
2067 {
2068 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2069   tmp_addr = ADDSI (tmp_addr, 1);
2070 }
2071   {
2072     SI opval = tmp_addr;
2073     SET_H_GR (FLD (f_operand1), opval);
2074     written |= (1 << 9);
2075     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2076   }
2077 }
2078 }
2079 ; tmp_tmp_mem; }));
2080   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2081   tmp_carry = CPU (h_cbit);
2082   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2083 ((void) 0); /*nop*/
2084 {
2085   {
2086     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2087     CPU (h_cbit) = opval;
2088     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2089   }
2090   {
2091     BI opval = LTSI (tmp_newval, 0);
2092     CPU (h_nbit) = opval;
2093     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2094   }
2095   {
2096     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2097     CPU (h_zbit) = opval;
2098     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2099   }
2100   {
2101     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2102     CPU (h_vbit) = opval;
2103     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2104   }
2105 {
2106   {
2107     BI opval = 0;
2108     CPU (h_xbit) = opval;
2109     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2110   }
2111   {
2112     BI opval = 0;
2113     SET_H_INSN_PREFIXED_P (opval);
2114     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2115   }
2116 }
2117 }
2118 }
2119
2120   abuf->written = written;
2121 #undef FLD
2122 }
2123   NEXT (vpc);
2124
2125   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2126 {
2127   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2128   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2129 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2130   int UNUSED written = 0;
2131   IADDR UNUSED pc = abuf->addr;
2132   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2133
2134 {
2135   SI tmp_tmpopd;
2136   SI tmp_tmpops;
2137   BI tmp_carry;
2138   SI tmp_newval;
2139   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2140   HI tmp_tmp_mem;
2141   BI tmp_postinc;
2142   tmp_postinc = FLD (f_memmode);
2143 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2144 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2145 ; if (NEBI (tmp_postinc, 0)) {
2146 {
2147 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2148   tmp_addr = ADDSI (tmp_addr, 2);
2149 }
2150   {
2151     SI opval = tmp_addr;
2152     SET_H_GR (FLD (f_operand1), opval);
2153     written |= (1 << 9);
2154     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2155   }
2156 }
2157 }
2158 ; tmp_tmp_mem; }));
2159   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2160   tmp_carry = CPU (h_cbit);
2161   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2162 ((void) 0); /*nop*/
2163 {
2164   {
2165     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2166     CPU (h_cbit) = opval;
2167     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2168   }
2169   {
2170     BI opval = LTSI (tmp_newval, 0);
2171     CPU (h_nbit) = opval;
2172     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2173   }
2174   {
2175     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2176     CPU (h_zbit) = opval;
2177     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2178   }
2179   {
2180     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2181     CPU (h_vbit) = opval;
2182     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2183   }
2184 {
2185   {
2186     BI opval = 0;
2187     CPU (h_xbit) = opval;
2188     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2189   }
2190   {
2191     BI opval = 0;
2192     SET_H_INSN_PREFIXED_P (opval);
2193     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2194   }
2195 }
2196 }
2197 }
2198
2199   abuf->written = written;
2200 #undef FLD
2201 }
2202   NEXT (vpc);
2203
2204   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2205 {
2206   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2207   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2208 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2209   int UNUSED written = 0;
2210   IADDR UNUSED pc = abuf->addr;
2211   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2212
2213 {
2214   SI tmp_tmpopd;
2215   SI tmp_tmpops;
2216   BI tmp_carry;
2217   SI tmp_newval;
2218   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2219   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2220   tmp_carry = CPU (h_cbit);
2221   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2222 ((void) 0); /*nop*/
2223 {
2224   {
2225     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2226     CPU (h_cbit) = opval;
2227     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2228   }
2229   {
2230     BI opval = LTSI (tmp_newval, 0);
2231     CPU (h_nbit) = opval;
2232     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2233   }
2234   {
2235     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2236     CPU (h_zbit) = opval;
2237     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2238   }
2239   {
2240     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2241     CPU (h_vbit) = opval;
2242     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2243   }
2244 {
2245   {
2246     BI opval = 0;
2247     CPU (h_xbit) = opval;
2248     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2249   }
2250   {
2251     BI opval = 0;
2252     SET_H_INSN_PREFIXED_P (opval);
2253     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2254   }
2255 }
2256 }
2257 }
2258
2259 #undef FLD
2260 }
2261   NEXT (vpc);
2262
2263   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2264 {
2265   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2266   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2267 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2268   int UNUSED written = 0;
2269   IADDR UNUSED pc = abuf->addr;
2270   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2271
2272 {
2273   SI tmp_tmpopd;
2274   SI tmp_tmpops;
2275   BI tmp_carry;
2276   SI tmp_newval;
2277   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2278   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2279   tmp_carry = CPU (h_cbit);
2280   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2281 ((void) 0); /*nop*/
2282 {
2283   {
2284     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2285     CPU (h_cbit) = opval;
2286     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2287   }
2288   {
2289     BI opval = LTSI (tmp_newval, 0);
2290     CPU (h_nbit) = opval;
2291     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2292   }
2293   {
2294     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2295     CPU (h_zbit) = opval;
2296     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2297   }
2298   {
2299     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2300     CPU (h_vbit) = opval;
2301     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2302   }
2303 {
2304   {
2305     BI opval = 0;
2306     CPU (h_xbit) = opval;
2307     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2308   }
2309   {
2310     BI opval = 0;
2311     SET_H_INSN_PREFIXED_P (opval);
2312     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2313   }
2314 }
2315 }
2316 }
2317
2318 #undef FLD
2319 }
2320   NEXT (vpc);
2321
2322   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2323 {
2324   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2325   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2326 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2327   int UNUSED written = 0;
2328   IADDR UNUSED pc = abuf->addr;
2329   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2330
2331 {
2332   SI tmp_tmpopd;
2333   SI tmp_tmpops;
2334   BI tmp_carry;
2335   SI tmp_newval;
2336   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2337   QI tmp_tmp_mem;
2338   BI tmp_postinc;
2339   tmp_postinc = FLD (f_memmode);
2340 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2341 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2342 ; if (NEBI (tmp_postinc, 0)) {
2343 {
2344 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2345   tmp_addr = ADDSI (tmp_addr, 1);
2346 }
2347   {
2348     SI opval = tmp_addr;
2349     SET_H_GR (FLD (f_operand1), opval);
2350     written |= (1 << 9);
2351     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2352   }
2353 }
2354 }
2355 ; tmp_tmp_mem; }));
2356   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2357   tmp_carry = CPU (h_cbit);
2358   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2359 ((void) 0); /*nop*/
2360 {
2361   {
2362     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2363     CPU (h_cbit) = opval;
2364     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2365   }
2366   {
2367     BI opval = LTSI (tmp_newval, 0);
2368     CPU (h_nbit) = opval;
2369     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2370   }
2371   {
2372     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2373     CPU (h_zbit) = opval;
2374     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2375   }
2376   {
2377     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2378     CPU (h_vbit) = opval;
2379     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2380   }
2381 {
2382   {
2383     BI opval = 0;
2384     CPU (h_xbit) = opval;
2385     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2386   }
2387   {
2388     BI opval = 0;
2389     SET_H_INSN_PREFIXED_P (opval);
2390     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2391   }
2392 }
2393 }
2394 }
2395
2396   abuf->written = written;
2397 #undef FLD
2398 }
2399   NEXT (vpc);
2400
2401   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2402 {
2403   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2404   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2405 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2406   int UNUSED written = 0;
2407   IADDR UNUSED pc = abuf->addr;
2408   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2409
2410 {
2411   SI tmp_tmpopd;
2412   SI tmp_tmpops;
2413   BI tmp_carry;
2414   SI tmp_newval;
2415   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2416   HI tmp_tmp_mem;
2417   BI tmp_postinc;
2418   tmp_postinc = FLD (f_memmode);
2419 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2420 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2421 ; if (NEBI (tmp_postinc, 0)) {
2422 {
2423 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2424   tmp_addr = ADDSI (tmp_addr, 2);
2425 }
2426   {
2427     SI opval = tmp_addr;
2428     SET_H_GR (FLD (f_operand1), opval);
2429     written |= (1 << 9);
2430     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2431   }
2432 }
2433 }
2434 ; tmp_tmp_mem; }));
2435   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2436   tmp_carry = CPU (h_cbit);
2437   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2438 ((void) 0); /*nop*/
2439 {
2440   {
2441     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2442     CPU (h_cbit) = opval;
2443     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2444   }
2445   {
2446     BI opval = LTSI (tmp_newval, 0);
2447     CPU (h_nbit) = opval;
2448     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2449   }
2450   {
2451     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2452     CPU (h_zbit) = opval;
2453     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2454   }
2455   {
2456     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2457     CPU (h_vbit) = opval;
2458     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2459   }
2460 {
2461   {
2462     BI opval = 0;
2463     CPU (h_xbit) = opval;
2464     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2465   }
2466   {
2467     BI opval = 0;
2468     SET_H_INSN_PREFIXED_P (opval);
2469     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2470   }
2471 }
2472 }
2473 }
2474
2475   abuf->written = written;
2476 #undef FLD
2477 }
2478   NEXT (vpc);
2479
2480   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2481 {
2482   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2483   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2484 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2485   int UNUSED written = 0;
2486   IADDR UNUSED pc = abuf->addr;
2487   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2488
2489 {
2490   SI tmp_tmpopd;
2491   SI tmp_tmpops;
2492   BI tmp_carry;
2493   SI tmp_newval;
2494   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2495   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2496   tmp_carry = CPU (h_cbit);
2497   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2498 ((void) 0); /*nop*/
2499 {
2500   {
2501     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2502     CPU (h_cbit) = opval;
2503     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2504   }
2505   {
2506     BI opval = LTSI (tmp_newval, 0);
2507     CPU (h_nbit) = opval;
2508     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2509   }
2510   {
2511     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2512     CPU (h_zbit) = opval;
2513     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2514   }
2515   {
2516     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2517     CPU (h_vbit) = opval;
2518     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2519   }
2520 {
2521   {
2522     BI opval = 0;
2523     CPU (h_xbit) = opval;
2524     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2525   }
2526   {
2527     BI opval = 0;
2528     SET_H_INSN_PREFIXED_P (opval);
2529     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2530   }
2531 }
2532 }
2533 }
2534
2535 #undef FLD
2536 }
2537   NEXT (vpc);
2538
2539   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2540 {
2541   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2542   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2543 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2544   int UNUSED written = 0;
2545   IADDR UNUSED pc = abuf->addr;
2546   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2547
2548 {
2549   SI tmp_tmpopd;
2550   SI tmp_tmpops;
2551   BI tmp_carry;
2552   SI tmp_newval;
2553   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2554   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2555   tmp_carry = CPU (h_cbit);
2556   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2557 ((void) 0); /*nop*/
2558 {
2559   {
2560     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2561     CPU (h_cbit) = opval;
2562     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2563   }
2564   {
2565     BI opval = LTSI (tmp_newval, 0);
2566     CPU (h_nbit) = opval;
2567     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2568   }
2569   {
2570     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2571     CPU (h_zbit) = opval;
2572     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2573   }
2574   {
2575     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2576     CPU (h_vbit) = opval;
2577     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2578   }
2579 {
2580   {
2581     BI opval = 0;
2582     CPU (h_xbit) = opval;
2583     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2584   }
2585   {
2586     BI opval = 0;
2587     SET_H_INSN_PREFIXED_P (opval);
2588     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2589   }
2590 }
2591 }
2592 }
2593
2594 #undef FLD
2595 }
2596   NEXT (vpc);
2597
2598   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2599 {
2600   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2601   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2602 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2603   int UNUSED written = 0;
2604   IADDR UNUSED pc = abuf->addr;
2605   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2606
2607 {
2608   SI tmp_tmp;
2609   tmp_tmp = ({   SI tmp_addr;
2610   QI tmp_tmp_mem;
2611   BI tmp_postinc;
2612   tmp_postinc = FLD (f_memmode);
2613 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2614 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2615 ; if (NEBI (tmp_postinc, 0)) {
2616 {
2617 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2618   tmp_addr = ADDSI (tmp_addr, 1);
2619 }
2620   {
2621     SI opval = tmp_addr;
2622     SET_H_GR (FLD (f_operand1), opval);
2623     written |= (1 << 10);
2624     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2625   }
2626 }
2627 }
2628 ; tmp_tmp_mem; });
2629 {
2630   SI tmp_oldregval;
2631   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2632   {
2633     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2634     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2635     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2636   }
2637 }
2638 {
2639   {
2640     BI opval = LTQI (tmp_tmp, 0);
2641     CPU (h_nbit) = opval;
2642     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2643   }
2644   {
2645     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2646     CPU (h_zbit) = opval;
2647     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2648   }
2649 SET_H_CBIT_MOVE (0);
2650 SET_H_VBIT_MOVE (0);
2651 {
2652   {
2653     BI opval = 0;
2654     CPU (h_xbit) = opval;
2655     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2656   }
2657   {
2658     BI opval = 0;
2659     SET_H_INSN_PREFIXED_P (opval);
2660     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2661   }
2662 }
2663 }
2664 }
2665
2666   abuf->written = written;
2667 #undef FLD
2668 }
2669   NEXT (vpc);
2670
2671   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2672 {
2673   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2674   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2675 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2676   int UNUSED written = 0;
2677   IADDR UNUSED pc = abuf->addr;
2678   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2679
2680 {
2681   SI tmp_tmp;
2682   tmp_tmp = ({   SI tmp_addr;
2683   HI tmp_tmp_mem;
2684   BI tmp_postinc;
2685   tmp_postinc = FLD (f_memmode);
2686 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2687 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2688 ; if (NEBI (tmp_postinc, 0)) {
2689 {
2690 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2691   tmp_addr = ADDSI (tmp_addr, 2);
2692 }
2693   {
2694     SI opval = tmp_addr;
2695     SET_H_GR (FLD (f_operand1), opval);
2696     written |= (1 << 10);
2697     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2698   }
2699 }
2700 }
2701 ; tmp_tmp_mem; });
2702 {
2703   SI tmp_oldregval;
2704   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2705   {
2706     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2707     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2708     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2709   }
2710 }
2711 {
2712   {
2713     BI opval = LTHI (tmp_tmp, 0);
2714     CPU (h_nbit) = opval;
2715     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2716   }
2717   {
2718     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2719     CPU (h_zbit) = opval;
2720     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2721   }
2722 SET_H_CBIT_MOVE (0);
2723 SET_H_VBIT_MOVE (0);
2724 {
2725   {
2726     BI opval = 0;
2727     CPU (h_xbit) = opval;
2728     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2729   }
2730   {
2731     BI opval = 0;
2732     SET_H_INSN_PREFIXED_P (opval);
2733     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2734   }
2735 }
2736 }
2737 }
2738
2739   abuf->written = written;
2740 #undef FLD
2741 }
2742   NEXT (vpc);
2743
2744   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2745 {
2746   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2747   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2748 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2749   int UNUSED written = 0;
2750   IADDR UNUSED pc = abuf->addr;
2751   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2752
2753 {
2754   SI tmp_tmp;
2755   tmp_tmp = ({   SI tmp_addr;
2756   SI tmp_tmp_mem;
2757   BI tmp_postinc;
2758   tmp_postinc = FLD (f_memmode);
2759 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2760 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2761 ; if (NEBI (tmp_postinc, 0)) {
2762 {
2763 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2764   tmp_addr = ADDSI (tmp_addr, 4);
2765 }
2766   {
2767     SI opval = tmp_addr;
2768     SET_H_GR (FLD (f_operand1), opval);
2769     written |= (1 << 9);
2770     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2771   }
2772 }
2773 }
2774 ; tmp_tmp_mem; });
2775   {
2776     SI opval = tmp_tmp;
2777     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2778     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2779   }
2780 {
2781   {
2782     BI opval = LTSI (tmp_tmp, 0);
2783     CPU (h_nbit) = opval;
2784     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2785   }
2786   {
2787     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2788     CPU (h_zbit) = opval;
2789     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2790   }
2791 SET_H_CBIT_MOVE (0);
2792 SET_H_VBIT_MOVE (0);
2793 {
2794   {
2795     BI opval = 0;
2796     CPU (h_xbit) = opval;
2797     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2798   }
2799   {
2800     BI opval = 0;
2801     SET_H_INSN_PREFIXED_P (opval);
2802     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2803   }
2804 }
2805 }
2806 }
2807
2808   abuf->written = written;
2809 #undef FLD
2810 }
2811   NEXT (vpc);
2812
2813   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2814 {
2815   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2816   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2817 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2818   int UNUSED written = 0;
2819   IADDR UNUSED pc = abuf->addr;
2820   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2821
2822 {
2823   SI tmp_tmp;
2824   tmp_tmp = EXTQISI (({   SI tmp_addr;
2825   QI tmp_tmp_mem;
2826   BI tmp_postinc;
2827   tmp_postinc = FLD (f_memmode);
2828 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2829 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2830 ; if (NEBI (tmp_postinc, 0)) {
2831 {
2832 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2833   tmp_addr = ADDSI (tmp_addr, 1);
2834 }
2835   {
2836     SI opval = tmp_addr;
2837     SET_H_GR (FLD (f_operand1), opval);
2838     written |= (1 << 8);
2839     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2840   }
2841 }
2842 }
2843 ; tmp_tmp_mem; }));
2844 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2845   {
2846     SI opval = tmp_tmp;
2847     SET_H_GR (FLD (f_operand1), opval);
2848     written |= (1 << 8);
2849     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2850   }
2851 } else {
2852   {
2853     SI opval = tmp_tmp;
2854     SET_H_GR (FLD (f_operand2), opval);
2855     written |= (1 << 7);
2856     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2857   }
2858 }
2859 {
2860   {
2861     BI opval = LTSI (tmp_tmp, 0);
2862     CPU (h_nbit) = opval;
2863     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2864   }
2865   {
2866     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2867     CPU (h_zbit) = opval;
2868     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2869   }
2870 SET_H_CBIT_MOVE (0);
2871 SET_H_VBIT_MOVE (0);
2872 {
2873   {
2874     BI opval = 0;
2875     CPU (h_xbit) = opval;
2876     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2877   }
2878   {
2879     BI opval = 0;
2880     SET_H_INSN_PREFIXED_P (opval);
2881     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2882   }
2883 }
2884 }
2885 }
2886
2887   abuf->written = written;
2888 #undef FLD
2889 }
2890   NEXT (vpc);
2891
2892   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2893 {
2894   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2895   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2896 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2897   int UNUSED written = 0;
2898   IADDR UNUSED pc = abuf->addr;
2899   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2900
2901 {
2902   SI tmp_tmp;
2903   tmp_tmp = EXTHISI (({   SI tmp_addr;
2904   HI tmp_tmp_mem;
2905   BI tmp_postinc;
2906   tmp_postinc = FLD (f_memmode);
2907 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2908 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2909 ; if (NEBI (tmp_postinc, 0)) {
2910 {
2911 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2912   tmp_addr = ADDSI (tmp_addr, 2);
2913 }
2914   {
2915     SI opval = tmp_addr;
2916     SET_H_GR (FLD (f_operand1), opval);
2917     written |= (1 << 8);
2918     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2919   }
2920 }
2921 }
2922 ; tmp_tmp_mem; }));
2923 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2924   {
2925     SI opval = tmp_tmp;
2926     SET_H_GR (FLD (f_operand1), opval);
2927     written |= (1 << 8);
2928     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2929   }
2930 } else {
2931   {
2932     SI opval = tmp_tmp;
2933     SET_H_GR (FLD (f_operand2), opval);
2934     written |= (1 << 7);
2935     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2936   }
2937 }
2938 {
2939   {
2940     BI opval = LTSI (tmp_tmp, 0);
2941     CPU (h_nbit) = opval;
2942     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2943   }
2944   {
2945     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2946     CPU (h_zbit) = opval;
2947     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2948   }
2949 SET_H_CBIT_MOVE (0);
2950 SET_H_VBIT_MOVE (0);
2951 {
2952   {
2953     BI opval = 0;
2954     CPU (h_xbit) = opval;
2955     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2956   }
2957   {
2958     BI opval = 0;
2959     SET_H_INSN_PREFIXED_P (opval);
2960     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2961   }
2962 }
2963 }
2964 }
2965
2966   abuf->written = written;
2967 #undef FLD
2968 }
2969   NEXT (vpc);
2970
2971   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2972 {
2973   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2974   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2975 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
2976   int UNUSED written = 0;
2977   IADDR UNUSED pc = abuf->addr;
2978   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2979
2980 {
2981   SI tmp_tmp;
2982   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2983   QI tmp_tmp_mem;
2984   BI tmp_postinc;
2985   tmp_postinc = FLD (f_memmode);
2986 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
2987 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2988 ; if (NEBI (tmp_postinc, 0)) {
2989 {
2990 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2991   tmp_addr = ADDSI (tmp_addr, 1);
2992 }
2993   {
2994     SI opval = tmp_addr;
2995     SET_H_GR (FLD (f_operand1), opval);
2996     written |= (1 << 8);
2997     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2998   }
2999 }
3000 }
3001 ; tmp_tmp_mem; }));
3002 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3003   {
3004     SI opval = tmp_tmp;
3005     SET_H_GR (FLD (f_operand1), opval);
3006     written |= (1 << 8);
3007     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3008   }
3009 } else {
3010   {
3011     SI opval = tmp_tmp;
3012     SET_H_GR (FLD (f_operand2), opval);
3013     written |= (1 << 7);
3014     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3015   }
3016 }
3017 {
3018   {
3019     BI opval = LTSI (tmp_tmp, 0);
3020     CPU (h_nbit) = opval;
3021     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3022   }
3023   {
3024     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3025     CPU (h_zbit) = opval;
3026     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3027   }
3028 SET_H_CBIT_MOVE (0);
3029 SET_H_VBIT_MOVE (0);
3030 {
3031   {
3032     BI opval = 0;
3033     CPU (h_xbit) = opval;
3034     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3035   }
3036   {
3037     BI opval = 0;
3038     SET_H_INSN_PREFIXED_P (opval);
3039     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3040   }
3041 }
3042 }
3043 }
3044
3045   abuf->written = written;
3046 #undef FLD
3047 }
3048   NEXT (vpc);
3049
3050   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
3051 {
3052   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3053   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3054 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
3055   int UNUSED written = 0;
3056   IADDR UNUSED pc = abuf->addr;
3057   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3058
3059 {
3060   SI tmp_tmp;
3061   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
3062   HI tmp_tmp_mem;
3063   BI tmp_postinc;
3064   tmp_postinc = FLD (f_memmode);
3065 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3066 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3067 ; if (NEBI (tmp_postinc, 0)) {
3068 {
3069 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3070   tmp_addr = ADDSI (tmp_addr, 2);
3071 }
3072   {
3073     SI opval = tmp_addr;
3074     SET_H_GR (FLD (f_operand1), opval);
3075     written |= (1 << 8);
3076     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3077   }
3078 }
3079 }
3080 ; tmp_tmp_mem; }));
3081 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3082   {
3083     SI opval = tmp_tmp;
3084     SET_H_GR (FLD (f_operand1), opval);
3085     written |= (1 << 8);
3086     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3087   }
3088 } else {
3089   {
3090     SI opval = tmp_tmp;
3091     SET_H_GR (FLD (f_operand2), opval);
3092     written |= (1 << 7);
3093     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3094   }
3095 }
3096 {
3097   {
3098     BI opval = LTSI (tmp_tmp, 0);
3099     CPU (h_nbit) = opval;
3100     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3101   }
3102   {
3103     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3104     CPU (h_zbit) = opval;
3105     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3106   }
3107 SET_H_CBIT_MOVE (0);
3108 SET_H_VBIT_MOVE (0);
3109 {
3110   {
3111     BI opval = 0;
3112     CPU (h_xbit) = opval;
3113     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3114   }
3115   {
3116     BI opval = 0;
3117     SET_H_INSN_PREFIXED_P (opval);
3118     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3119   }
3120 }
3121 }
3122 }
3123
3124   abuf->written = written;
3125 #undef FLD
3126 }
3127   NEXT (vpc);
3128
3129   CASE (sem, INSN_MOVE_R_SPRV10) : /* move ${Rs},${Pd} */
3130 {
3131   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3132   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3133 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3134   int UNUSED written = 0;
3135   IADDR UNUSED pc = abuf->addr;
3136   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3137
3138 {
3139   SI tmp_tmp;
3140   SI tmp_rno;
3141   tmp_tmp = GET_H_GR (FLD (f_operand1));
3142   tmp_rno = FLD (f_operand2);
3143 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3144 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3145 }
3146  else {
3147   {
3148     SI opval = tmp_tmp;
3149     SET_H_SR (FLD (f_operand2), opval);
3150     written |= (1 << 2);
3151     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3152   }
3153 }
3154 {
3155   {
3156     BI opval = 0;
3157     CPU (h_xbit) = opval;
3158     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3159   }
3160   {
3161     BI opval = 0;
3162     SET_H_INSN_PREFIXED_P (opval);
3163     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3164   }
3165 }
3166 }
3167
3168   abuf->written = written;
3169 #undef FLD
3170 }
3171   NEXT (vpc);
3172
3173   CASE (sem, INSN_MOVE_SPR_RV10) : /* move ${Ps},${Rd-sfield} */
3174 {
3175   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3176   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3177 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3178   int UNUSED written = 0;
3179   IADDR UNUSED pc = abuf->addr;
3180   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3181
3182 {
3183   SI tmp_grno;
3184   SI tmp_prno;
3185   SI tmp_newval;
3186   tmp_prno = FLD (f_operand2);
3187   tmp_newval = GET_H_SR (FLD (f_operand2));
3188 if (EQSI (tmp_prno, 5)) {
3189 {
3190   SI tmp_oldregval;
3191   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3192   {
3193     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3194     SET_H_GR (FLD (f_operand1), opval);
3195     written |= (1 << 4);
3196     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3197   }
3198 }
3199 }
3200  else if (EQSI (tmp_prno, 9)) {
3201   {
3202     SI opval = tmp_newval;
3203     SET_H_GR (FLD (f_operand1), opval);
3204     written |= (1 << 4);
3205     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3206   }
3207 }
3208  else if (EQSI (tmp_prno, 10)) {
3209   {
3210     SI opval = tmp_newval;
3211     SET_H_GR (FLD (f_operand1), opval);
3212     written |= (1 << 4);
3213     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3214   }
3215 }
3216  else if (EQSI (tmp_prno, 11)) {
3217   {
3218     SI opval = tmp_newval;
3219     SET_H_GR (FLD (f_operand1), opval);
3220     written |= (1 << 4);
3221     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3222   }
3223 }
3224  else if (EQSI (tmp_prno, 12)) {
3225   {
3226     SI opval = tmp_newval;
3227     SET_H_GR (FLD (f_operand1), opval);
3228     written |= (1 << 4);
3229     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3230   }
3231 }
3232  else if (EQSI (tmp_prno, 13)) {
3233   {
3234     SI opval = tmp_newval;
3235     SET_H_GR (FLD (f_operand1), opval);
3236     written |= (1 << 4);
3237     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3238   }
3239 }
3240  else if (EQSI (tmp_prno, 0)) {
3241 {
3242   SI tmp_oldregval;
3243   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3244   {
3245     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3246     SET_H_GR (FLD (f_operand1), opval);
3247     written |= (1 << 4);
3248     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3249   }
3250 }
3251 }
3252  else if (EQSI (tmp_prno, 1)) {
3253 {
3254   SI tmp_oldregval;
3255   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3256   {
3257     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3258     SET_H_GR (FLD (f_operand1), opval);
3259     written |= (1 << 4);
3260     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3261   }
3262 }
3263 }
3264  else if (EQSI (tmp_prno, 4)) {
3265 {
3266   SI tmp_oldregval;
3267   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
3268   {
3269     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3270     SET_H_GR (FLD (f_operand1), opval);
3271     written |= (1 << 4);
3272     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3273   }
3274 }
3275 }
3276  else if (EQSI (tmp_prno, 8)) {
3277   {
3278     SI opval = tmp_newval;
3279     SET_H_GR (FLD (f_operand1), opval);
3280     written |= (1 << 4);
3281     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3282   }
3283 }
3284  else if (EQSI (tmp_prno, 7)) {
3285   {
3286     SI opval = tmp_newval;
3287     SET_H_GR (FLD (f_operand1), opval);
3288     written |= (1 << 4);
3289     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3290   }
3291 }
3292  else if (EQSI (tmp_prno, 14)) {
3293   {
3294     SI opval = tmp_newval;
3295     SET_H_GR (FLD (f_operand1), opval);
3296     written |= (1 << 4);
3297     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3298   }
3299 }
3300  else if (EQSI (tmp_prno, 15)) {
3301   {
3302     SI opval = tmp_newval;
3303     SET_H_GR (FLD (f_operand1), opval);
3304     written |= (1 << 4);
3305     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3306   }
3307 }
3308  else {
3309 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3310 }
3311 {
3312   {
3313     BI opval = 0;
3314     CPU (h_xbit) = opval;
3315     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3316   }
3317   {
3318     BI opval = 0;
3319     SET_H_INSN_PREFIXED_P (opval);
3320     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3321   }
3322 }
3323 }
3324
3325   abuf->written = written;
3326 #undef FLD
3327 }
3328   NEXT (vpc);
3329
3330   CASE (sem, INSN_RET_TYPE) : /* ret/reti/retb */
3331 {
3332   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3333   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3334 #define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
3335   int UNUSED written = 0;
3336   IADDR UNUSED pc = abuf->addr;
3337   SEM_BRANCH_INIT
3338   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3339
3340 {
3341   SI tmp_retaddr;
3342   tmp_retaddr = GET_H_SR (FLD (f_operand2));
3343 {
3344   {
3345     BI opval = 0;
3346     CPU (h_xbit) = opval;
3347     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3348   }
3349   {
3350     BI opval = 0;
3351     SET_H_INSN_PREFIXED_P (opval);
3352     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3353   }
3354 }
3355 {
3356   {
3357     USI opval = tmp_retaddr;
3358     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3359     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3360   }
3361 }
3362 }
3363
3364   SEM_BRANCH_FINI (vpc);
3365 #undef FLD
3366 }
3367   NEXT (vpc);
3368
3369   CASE (sem, INSN_MOVE_M_SPRV10) : /* move [${Rs}${inc}],${Pd} */
3370 {
3371   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3372   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3373 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
3374   int UNUSED written = 0;
3375   IADDR UNUSED pc = abuf->addr;
3376   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3377
3378 {
3379   SI tmp_rno;
3380   SI tmp_newval;
3381   tmp_rno = FLD (f_operand2);
3382 if (EQSI (tmp_rno, 5)) {
3383   tmp_newval = EXTHISI (({   SI tmp_addr;
3384   HI tmp_tmp_mem;
3385   BI tmp_postinc;
3386   tmp_postinc = FLD (f_memmode);
3387 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3388 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
3389 ; if (NEBI (tmp_postinc, 0)) {
3390 {
3391 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3392   tmp_addr = ADDSI (tmp_addr, 2);
3393 }
3394   {
3395     SI opval = tmp_addr;
3396     SET_H_GR (FLD (f_operand1), opval);
3397     written |= (1 << 8);
3398     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3399   }
3400 }
3401 }
3402 ; tmp_tmp_mem; }));
3403 }
3404  else if (EQSI (tmp_rno, 9)) {
3405   tmp_newval = ({   SI tmp_addr;
3406   SI tmp_tmp_mem;
3407   BI tmp_postinc;
3408   tmp_postinc = FLD (f_memmode);
3409 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3410 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3411 ; if (NEBI (tmp_postinc, 0)) {
3412 {
3413 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3414   tmp_addr = ADDSI (tmp_addr, 4);
3415 }
3416   {
3417     SI opval = tmp_addr;
3418     SET_H_GR (FLD (f_operand1), opval);
3419     written |= (1 << 8);
3420     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3421   }
3422 }
3423 }
3424 ; tmp_tmp_mem; });
3425 }
3426  else if (EQSI (tmp_rno, 10)) {
3427   tmp_newval = ({   SI tmp_addr;
3428   SI tmp_tmp_mem;
3429   BI tmp_postinc;
3430   tmp_postinc = FLD (f_memmode);
3431 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3432 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3433 ; if (NEBI (tmp_postinc, 0)) {
3434 {
3435 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3436   tmp_addr = ADDSI (tmp_addr, 4);
3437 }
3438   {
3439     SI opval = tmp_addr;
3440     SET_H_GR (FLD (f_operand1), opval);
3441     written |= (1 << 8);
3442     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3443   }
3444 }
3445 }
3446 ; tmp_tmp_mem; });
3447 }
3448  else if (EQSI (tmp_rno, 11)) {
3449   tmp_newval = ({   SI tmp_addr;
3450   SI tmp_tmp_mem;
3451   BI tmp_postinc;
3452   tmp_postinc = FLD (f_memmode);
3453 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3454 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3455 ; if (NEBI (tmp_postinc, 0)) {
3456 {
3457 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3458   tmp_addr = ADDSI (tmp_addr, 4);
3459 }
3460   {
3461     SI opval = tmp_addr;
3462     SET_H_GR (FLD (f_operand1), opval);
3463     written |= (1 << 8);
3464     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3465   }
3466 }
3467 }
3468 ; tmp_tmp_mem; });
3469 }
3470  else if (EQSI (tmp_rno, 12)) {
3471   tmp_newval = ({   SI tmp_addr;
3472   SI tmp_tmp_mem;
3473   BI tmp_postinc;
3474   tmp_postinc = FLD (f_memmode);
3475 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3476 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3477 ; if (NEBI (tmp_postinc, 0)) {
3478 {
3479 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3480   tmp_addr = ADDSI (tmp_addr, 4);
3481 }
3482   {
3483     SI opval = tmp_addr;
3484     SET_H_GR (FLD (f_operand1), opval);
3485     written |= (1 << 8);
3486     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3487   }
3488 }
3489 }
3490 ; tmp_tmp_mem; });
3491 }
3492  else if (EQSI (tmp_rno, 13)) {
3493   tmp_newval = ({   SI tmp_addr;
3494   SI tmp_tmp_mem;
3495   BI tmp_postinc;
3496   tmp_postinc = FLD (f_memmode);
3497 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3498 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3499 ; if (NEBI (tmp_postinc, 0)) {
3500 {
3501 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3502   tmp_addr = ADDSI (tmp_addr, 4);
3503 }
3504   {
3505     SI opval = tmp_addr;
3506     SET_H_GR (FLD (f_operand1), opval);
3507     written |= (1 << 8);
3508     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3509   }
3510 }
3511 }
3512 ; tmp_tmp_mem; });
3513 }
3514  else if (EQSI (tmp_rno, 7)) {
3515   tmp_newval = ({   SI tmp_addr;
3516   SI tmp_tmp_mem;
3517   BI tmp_postinc;
3518   tmp_postinc = FLD (f_memmode);
3519 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3520 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3521 ; if (NEBI (tmp_postinc, 0)) {
3522 {
3523 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3524   tmp_addr = ADDSI (tmp_addr, 4);
3525 }
3526   {
3527     SI opval = tmp_addr;
3528     SET_H_GR (FLD (f_operand1), opval);
3529     written |= (1 << 8);
3530     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3531   }
3532 }
3533 }
3534 ; tmp_tmp_mem; });
3535 }
3536  else if (EQSI (tmp_rno, 14)) {
3537   tmp_newval = ({   SI tmp_addr;
3538   SI tmp_tmp_mem;
3539   BI tmp_postinc;
3540   tmp_postinc = FLD (f_memmode);
3541 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3542 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3543 ; if (NEBI (tmp_postinc, 0)) {
3544 {
3545 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3546   tmp_addr = ADDSI (tmp_addr, 4);
3547 }
3548   {
3549     SI opval = tmp_addr;
3550     SET_H_GR (FLD (f_operand1), opval);
3551     written |= (1 << 8);
3552     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3553   }
3554 }
3555 }
3556 ; tmp_tmp_mem; });
3557 }
3558  else if (EQSI (tmp_rno, 15)) {
3559   tmp_newval = ({   SI tmp_addr;
3560   SI tmp_tmp_mem;
3561   BI tmp_postinc;
3562   tmp_postinc = FLD (f_memmode);
3563 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3564 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3565 ; if (NEBI (tmp_postinc, 0)) {
3566 {
3567 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3568   tmp_addr = ADDSI (tmp_addr, 4);
3569 }
3570   {
3571     SI opval = tmp_addr;
3572     SET_H_GR (FLD (f_operand1), opval);
3573     written |= (1 << 8);
3574     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3575   }
3576 }
3577 }
3578 ; tmp_tmp_mem; });
3579 }
3580  else {
3581 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3582 }
3583   {
3584     SI opval = tmp_newval;
3585     SET_H_SR (FLD (f_operand2), opval);
3586     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3587   }
3588 {
3589   {
3590     BI opval = 0;
3591     CPU (h_xbit) = opval;
3592     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3593   }
3594   {
3595     BI opval = 0;
3596     SET_H_INSN_PREFIXED_P (opval);
3597     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3598   }
3599 }
3600 }
3601
3602   abuf->written = written;
3603 #undef FLD
3604 }
3605   NEXT (vpc);
3606
3607   CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */
3608 {
3609   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3610   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3611 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p5.f
3612   int UNUSED written = 0;
3613   IADDR UNUSED pc = abuf->addr;
3614   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
3615
3616 {
3617   {
3618     SI opval = FLD (f_indir_pc__word);
3619     SET_H_SR (FLD (f_operand2), opval);
3620     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3621   }
3622 {
3623   {
3624     BI opval = 0;
3625     CPU (h_xbit) = opval;
3626     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3627   }
3628   {
3629     BI opval = 0;
3630     SET_H_INSN_PREFIXED_P (opval);
3631     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3632   }
3633 }
3634 }
3635
3636 #undef FLD
3637 }
3638   NEXT (vpc);
3639
3640   CASE (sem, INSN_MOVE_C_SPRV10_P9) : /* move ${const32},${Pd} */
3641 {
3642   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3643   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3644 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3645   int UNUSED written = 0;
3646   IADDR UNUSED pc = abuf->addr;
3647   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3648
3649 {
3650   {
3651     SI opval = FLD (f_indir_pc__dword);
3652     SET_H_SR (FLD (f_operand2), opval);
3653     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3654   }
3655 {
3656   {
3657     BI opval = 0;
3658     CPU (h_xbit) = opval;
3659     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3660   }
3661   {
3662     BI opval = 0;
3663     SET_H_INSN_PREFIXED_P (opval);
3664     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3665   }
3666 }
3667 }
3668
3669 #undef FLD
3670 }
3671   NEXT (vpc);
3672
3673   CASE (sem, INSN_MOVE_C_SPRV10_P10) : /* move ${const32},${Pd} */
3674 {
3675   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3676   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3677 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3678   int UNUSED written = 0;
3679   IADDR UNUSED pc = abuf->addr;
3680   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3681
3682 {
3683   {
3684     SI opval = FLD (f_indir_pc__dword);
3685     SET_H_SR (FLD (f_operand2), opval);
3686     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3687   }
3688 {
3689   {
3690     BI opval = 0;
3691     CPU (h_xbit) = opval;
3692     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3693   }
3694   {
3695     BI opval = 0;
3696     SET_H_INSN_PREFIXED_P (opval);
3697     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3698   }
3699 }
3700 }
3701
3702 #undef FLD
3703 }
3704   NEXT (vpc);
3705
3706   CASE (sem, INSN_MOVE_C_SPRV10_P11) : /* move ${const32},${Pd} */
3707 {
3708   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3709   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3710 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3711   int UNUSED written = 0;
3712   IADDR UNUSED pc = abuf->addr;
3713   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3714
3715 {
3716   {
3717     SI opval = FLD (f_indir_pc__dword);
3718     SET_H_SR (FLD (f_operand2), opval);
3719     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3720   }
3721 {
3722   {
3723     BI opval = 0;
3724     CPU (h_xbit) = opval;
3725     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3726   }
3727   {
3728     BI opval = 0;
3729     SET_H_INSN_PREFIXED_P (opval);
3730     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3731   }
3732 }
3733 }
3734
3735 #undef FLD
3736 }
3737   NEXT (vpc);
3738
3739   CASE (sem, INSN_MOVE_C_SPRV10_P12) : /* move ${const32},${Pd} */
3740 {
3741   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3742   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3743 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3744   int UNUSED written = 0;
3745   IADDR UNUSED pc = abuf->addr;
3746   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3747
3748 {
3749   {
3750     SI opval = FLD (f_indir_pc__dword);
3751     SET_H_SR (FLD (f_operand2), opval);
3752     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3753   }
3754 {
3755   {
3756     BI opval = 0;
3757     CPU (h_xbit) = opval;
3758     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3759   }
3760   {
3761     BI opval = 0;
3762     SET_H_INSN_PREFIXED_P (opval);
3763     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3764   }
3765 }
3766 }
3767
3768 #undef FLD
3769 }
3770   NEXT (vpc);
3771
3772   CASE (sem, INSN_MOVE_C_SPRV10_P13) : /* move ${const32},${Pd} */
3773 {
3774   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3775   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3776 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3777   int UNUSED written = 0;
3778   IADDR UNUSED pc = abuf->addr;
3779   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3780
3781 {
3782   {
3783     SI opval = FLD (f_indir_pc__dword);
3784     SET_H_SR (FLD (f_operand2), opval);
3785     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3786   }
3787 {
3788   {
3789     BI opval = 0;
3790     CPU (h_xbit) = opval;
3791     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3792   }
3793   {
3794     BI opval = 0;
3795     SET_H_INSN_PREFIXED_P (opval);
3796     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3797   }
3798 }
3799 }
3800
3801 #undef FLD
3802 }
3803   NEXT (vpc);
3804
3805   CASE (sem, INSN_MOVE_C_SPRV10_P7) : /* move ${const32},${Pd} */
3806 {
3807   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3808   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3809 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3810   int UNUSED written = 0;
3811   IADDR UNUSED pc = abuf->addr;
3812   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3813
3814 {
3815   {
3816     SI opval = FLD (f_indir_pc__dword);
3817     SET_H_SR (FLD (f_operand2), opval);
3818     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3819   }
3820 {
3821   {
3822     BI opval = 0;
3823     CPU (h_xbit) = opval;
3824     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3825   }
3826   {
3827     BI opval = 0;
3828     SET_H_INSN_PREFIXED_P (opval);
3829     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3830   }
3831 }
3832 }
3833
3834 #undef FLD
3835 }
3836   NEXT (vpc);
3837
3838   CASE (sem, INSN_MOVE_C_SPRV10_P14) : /* move ${const32},${Pd} */
3839 {
3840   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3841   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3842 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3843   int UNUSED written = 0;
3844   IADDR UNUSED pc = abuf->addr;
3845   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3846
3847 {
3848   {
3849     SI opval = FLD (f_indir_pc__dword);
3850     SET_H_SR (FLD (f_operand2), opval);
3851     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3852   }
3853 {
3854   {
3855     BI opval = 0;
3856     CPU (h_xbit) = opval;
3857     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3858   }
3859   {
3860     BI opval = 0;
3861     SET_H_INSN_PREFIXED_P (opval);
3862     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3863   }
3864 }
3865 }
3866
3867 #undef FLD
3868 }
3869   NEXT (vpc);
3870
3871   CASE (sem, INSN_MOVE_C_SPRV10_P15) : /* move ${const32},${Pd} */
3872 {
3873   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3874   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3875 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
3876   int UNUSED written = 0;
3877   IADDR UNUSED pc = abuf->addr;
3878   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3879
3880 {
3881   {
3882     SI opval = FLD (f_indir_pc__dword);
3883     SET_H_SR (FLD (f_operand2), opval);
3884     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3885   }
3886 {
3887   {
3888     BI opval = 0;
3889     CPU (h_xbit) = opval;
3890     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3891   }
3892   {
3893     BI opval = 0;
3894     SET_H_INSN_PREFIXED_P (opval);
3895     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3896   }
3897 }
3898 }
3899
3900 #undef FLD
3901 }
3902   NEXT (vpc);
3903
3904   CASE (sem, INSN_MOVE_SPR_MV10) : /* move ${Ps},[${Rd-sfield}${inc}] */
3905 {
3906   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3907   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3908 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
3909   int UNUSED written = 0;
3910   IADDR UNUSED pc = abuf->addr;
3911   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3912
3913 {
3914   SI tmp_rno;
3915   tmp_rno = FLD (f_operand2);
3916 if (EQSI (tmp_rno, 5)) {
3917 {
3918   SI tmp_addr;
3919   BI tmp_postinc;
3920   tmp_postinc = FLD (f_memmode);
3921   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3922 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
3923 if (EQBI (CPU (h_pbit), 0)) {
3924 {
3925   {
3926     HI opval = GET_H_SR (FLD (f_operand2));
3927     SETMEMHI (current_cpu, pc, tmp_addr, opval);
3928     written |= (1 << 11);
3929     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3930   }
3931   {
3932     BI opval = CPU (h_pbit);
3933     CPU (h_cbit) = opval;
3934     written |= (1 << 10);
3935     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3936   }
3937 }
3938 } else {
3939   {
3940     BI opval = 1;
3941     CPU (h_cbit) = opval;
3942     written |= (1 << 10);
3943     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3944   }
3945 }
3946 } else {
3947   {
3948     HI opval = GET_H_SR (FLD (f_operand2));
3949     SETMEMHI (current_cpu, pc, tmp_addr, opval);
3950     written |= (1 << 11);
3951     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3952   }
3953 }
3954 if (NEBI (tmp_postinc, 0)) {
3955 {
3956 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3957   tmp_addr = ADDSI (tmp_addr, 2);
3958 }
3959   {
3960     SI opval = tmp_addr;
3961     SET_H_GR (FLD (f_operand1), opval);
3962     written |= (1 << 9);
3963     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3964   }
3965 }
3966 }
3967 }
3968 }
3969  else if (EQSI (tmp_rno, 9)) {
3970 {
3971   SI tmp_addr;
3972   BI tmp_postinc;
3973   tmp_postinc = FLD (f_memmode);
3974   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
3975 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
3976 if (EQBI (CPU (h_pbit), 0)) {
3977 {
3978   {
3979     SI opval = GET_H_SR (FLD (f_operand2));
3980     SETMEMSI (current_cpu, pc, tmp_addr, opval);
3981     written |= (1 << 13);
3982     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
3983   }
3984   {
3985     BI opval = CPU (h_pbit);
3986     CPU (h_cbit) = opval;
3987     written |= (1 << 10);
3988     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3989   }
3990 }
3991 } else {
3992   {
3993     BI opval = 1;
3994     CPU (h_cbit) = opval;
3995     written |= (1 << 10);
3996     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
3997   }
3998 }
3999 } else {
4000   {
4001     SI opval = GET_H_SR (FLD (f_operand2));
4002     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4003     written |= (1 << 13);
4004     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4005   }
4006 }
4007 if (NEBI (tmp_postinc, 0)) {
4008 {
4009 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4010   tmp_addr = ADDSI (tmp_addr, 4);
4011 }
4012   {
4013     SI opval = tmp_addr;
4014     SET_H_GR (FLD (f_operand1), opval);
4015     written |= (1 << 9);
4016     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4017   }
4018 }
4019 }
4020 }
4021 }
4022  else if (EQSI (tmp_rno, 10)) {
4023 {
4024   SI tmp_addr;
4025   BI tmp_postinc;
4026   tmp_postinc = FLD (f_memmode);
4027   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4028 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4029 if (EQBI (CPU (h_pbit), 0)) {
4030 {
4031   {
4032     SI opval = GET_H_SR (FLD (f_operand2));
4033     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4034     written |= (1 << 13);
4035     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4036   }
4037   {
4038     BI opval = CPU (h_pbit);
4039     CPU (h_cbit) = opval;
4040     written |= (1 << 10);
4041     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4042   }
4043 }
4044 } else {
4045   {
4046     BI opval = 1;
4047     CPU (h_cbit) = opval;
4048     written |= (1 << 10);
4049     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4050   }
4051 }
4052 } else {
4053   {
4054     SI opval = GET_H_SR (FLD (f_operand2));
4055     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4056     written |= (1 << 13);
4057     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4058   }
4059 }
4060 if (NEBI (tmp_postinc, 0)) {
4061 {
4062 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4063   tmp_addr = ADDSI (tmp_addr, 4);
4064 }
4065   {
4066     SI opval = tmp_addr;
4067     SET_H_GR (FLD (f_operand1), opval);
4068     written |= (1 << 9);
4069     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4070   }
4071 }
4072 }
4073 }
4074 }
4075  else if (EQSI (tmp_rno, 11)) {
4076 {
4077   SI tmp_addr;
4078   BI tmp_postinc;
4079   tmp_postinc = FLD (f_memmode);
4080   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4081 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4082 if (EQBI (CPU (h_pbit), 0)) {
4083 {
4084   {
4085     SI opval = GET_H_SR (FLD (f_operand2));
4086     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4087     written |= (1 << 13);
4088     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4089   }
4090   {
4091     BI opval = CPU (h_pbit);
4092     CPU (h_cbit) = opval;
4093     written |= (1 << 10);
4094     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4095   }
4096 }
4097 } else {
4098   {
4099     BI opval = 1;
4100     CPU (h_cbit) = opval;
4101     written |= (1 << 10);
4102     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4103   }
4104 }
4105 } else {
4106   {
4107     SI opval = GET_H_SR (FLD (f_operand2));
4108     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4109     written |= (1 << 13);
4110     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4111   }
4112 }
4113 if (NEBI (tmp_postinc, 0)) {
4114 {
4115 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4116   tmp_addr = ADDSI (tmp_addr, 4);
4117 }
4118   {
4119     SI opval = tmp_addr;
4120     SET_H_GR (FLD (f_operand1), opval);
4121     written |= (1 << 9);
4122     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4123   }
4124 }
4125 }
4126 }
4127 }
4128  else if (EQSI (tmp_rno, 12)) {
4129 {
4130   SI tmp_addr;
4131   BI tmp_postinc;
4132   tmp_postinc = FLD (f_memmode);
4133   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4134 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4135 if (EQBI (CPU (h_pbit), 0)) {
4136 {
4137   {
4138     SI opval = GET_H_SR (FLD (f_operand2));
4139     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4140     written |= (1 << 13);
4141     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4142   }
4143   {
4144     BI opval = CPU (h_pbit);
4145     CPU (h_cbit) = opval;
4146     written |= (1 << 10);
4147     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4148   }
4149 }
4150 } else {
4151   {
4152     BI opval = 1;
4153     CPU (h_cbit) = opval;
4154     written |= (1 << 10);
4155     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4156   }
4157 }
4158 } else {
4159   {
4160     SI opval = GET_H_SR (FLD (f_operand2));
4161     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4162     written |= (1 << 13);
4163     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4164   }
4165 }
4166 if (NEBI (tmp_postinc, 0)) {
4167 {
4168 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4169   tmp_addr = ADDSI (tmp_addr, 4);
4170 }
4171   {
4172     SI opval = tmp_addr;
4173     SET_H_GR (FLD (f_operand1), opval);
4174     written |= (1 << 9);
4175     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4176   }
4177 }
4178 }
4179 }
4180 }
4181  else if (EQSI (tmp_rno, 13)) {
4182 {
4183   SI tmp_addr;
4184   BI tmp_postinc;
4185   tmp_postinc = FLD (f_memmode);
4186   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4187 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4188 if (EQBI (CPU (h_pbit), 0)) {
4189 {
4190   {
4191     SI opval = GET_H_SR (FLD (f_operand2));
4192     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4193     written |= (1 << 13);
4194     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4195   }
4196   {
4197     BI opval = CPU (h_pbit);
4198     CPU (h_cbit) = opval;
4199     written |= (1 << 10);
4200     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4201   }
4202 }
4203 } else {
4204   {
4205     BI opval = 1;
4206     CPU (h_cbit) = opval;
4207     written |= (1 << 10);
4208     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4209   }
4210 }
4211 } else {
4212   {
4213     SI opval = GET_H_SR (FLD (f_operand2));
4214     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4215     written |= (1 << 13);
4216     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4217   }
4218 }
4219 if (NEBI (tmp_postinc, 0)) {
4220 {
4221 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4222   tmp_addr = ADDSI (tmp_addr, 4);
4223 }
4224   {
4225     SI opval = tmp_addr;
4226     SET_H_GR (FLD (f_operand1), opval);
4227     written |= (1 << 9);
4228     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4229   }
4230 }
4231 }
4232 }
4233 }
4234  else if (EQSI (tmp_rno, 0)) {
4235 {
4236   SI tmp_addr;
4237   BI tmp_postinc;
4238   tmp_postinc = FLD (f_memmode);
4239   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4240 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4241 if (EQBI (CPU (h_pbit), 0)) {
4242 {
4243   {
4244     QI opval = GET_H_SR (FLD (f_operand2));
4245     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4246     written |= (1 << 12);
4247     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4248   }
4249   {
4250     BI opval = CPU (h_pbit);
4251     CPU (h_cbit) = opval;
4252     written |= (1 << 10);
4253     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4254   }
4255 }
4256 } else {
4257   {
4258     BI opval = 1;
4259     CPU (h_cbit) = opval;
4260     written |= (1 << 10);
4261     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4262   }
4263 }
4264 } else {
4265   {
4266     QI opval = GET_H_SR (FLD (f_operand2));
4267     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4268     written |= (1 << 12);
4269     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4270   }
4271 }
4272 if (NEBI (tmp_postinc, 0)) {
4273 {
4274 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4275   tmp_addr = ADDSI (tmp_addr, 1);
4276 }
4277   {
4278     SI opval = tmp_addr;
4279     SET_H_GR (FLD (f_operand1), opval);
4280     written |= (1 << 9);
4281     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4282   }
4283 }
4284 }
4285 }
4286 }
4287  else if (EQSI (tmp_rno, 1)) {
4288 {
4289   SI tmp_addr;
4290   BI tmp_postinc;
4291   tmp_postinc = FLD (f_memmode);
4292   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4293 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4294 if (EQBI (CPU (h_pbit), 0)) {
4295 {
4296   {
4297     QI opval = GET_H_SR (FLD (f_operand2));
4298     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4299     written |= (1 << 12);
4300     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4301   }
4302   {
4303     BI opval = CPU (h_pbit);
4304     CPU (h_cbit) = opval;
4305     written |= (1 << 10);
4306     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4307   }
4308 }
4309 } else {
4310   {
4311     BI opval = 1;
4312     CPU (h_cbit) = opval;
4313     written |= (1 << 10);
4314     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4315   }
4316 }
4317 } else {
4318   {
4319     QI opval = GET_H_SR (FLD (f_operand2));
4320     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4321     written |= (1 << 12);
4322     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4323   }
4324 }
4325 if (NEBI (tmp_postinc, 0)) {
4326 {
4327 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4328   tmp_addr = ADDSI (tmp_addr, 1);
4329 }
4330   {
4331     SI opval = tmp_addr;
4332     SET_H_GR (FLD (f_operand1), opval);
4333     written |= (1 << 9);
4334     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4335   }
4336 }
4337 }
4338 }
4339 }
4340  else if (EQSI (tmp_rno, 4)) {
4341 {
4342   SI tmp_addr;
4343   BI tmp_postinc;
4344   tmp_postinc = FLD (f_memmode);
4345   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4346 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4347 if (EQBI (CPU (h_pbit), 0)) {
4348 {
4349   {
4350     HI opval = GET_H_SR (FLD (f_operand2));
4351     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4352     written |= (1 << 11);
4353     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4354   }
4355   {
4356     BI opval = CPU (h_pbit);
4357     CPU (h_cbit) = opval;
4358     written |= (1 << 10);
4359     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4360   }
4361 }
4362 } else {
4363   {
4364     BI opval = 1;
4365     CPU (h_cbit) = opval;
4366     written |= (1 << 10);
4367     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4368   }
4369 }
4370 } else {
4371   {
4372     HI opval = GET_H_SR (FLD (f_operand2));
4373     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4374     written |= (1 << 11);
4375     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4376   }
4377 }
4378 if (NEBI (tmp_postinc, 0)) {
4379 {
4380 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4381   tmp_addr = ADDSI (tmp_addr, 2);
4382 }
4383   {
4384     SI opval = tmp_addr;
4385     SET_H_GR (FLD (f_operand1), opval);
4386     written |= (1 << 9);
4387     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4388   }
4389 }
4390 }
4391 }
4392 }
4393  else if (EQSI (tmp_rno, 8)) {
4394 {
4395   SI tmp_addr;
4396   BI tmp_postinc;
4397   tmp_postinc = FLD (f_memmode);
4398   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4399 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4400 if (EQBI (CPU (h_pbit), 0)) {
4401 {
4402   {
4403     SI opval = GET_H_SR (FLD (f_operand2));
4404     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4405     written |= (1 << 13);
4406     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4407   }
4408   {
4409     BI opval = CPU (h_pbit);
4410     CPU (h_cbit) = opval;
4411     written |= (1 << 10);
4412     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4413   }
4414 }
4415 } else {
4416   {
4417     BI opval = 1;
4418     CPU (h_cbit) = opval;
4419     written |= (1 << 10);
4420     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4421   }
4422 }
4423 } else {
4424   {
4425     SI opval = GET_H_SR (FLD (f_operand2));
4426     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4427     written |= (1 << 13);
4428     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4429   }
4430 }
4431 if (NEBI (tmp_postinc, 0)) {
4432 {
4433 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4434   tmp_addr = ADDSI (tmp_addr, 4);
4435 }
4436   {
4437     SI opval = tmp_addr;
4438     SET_H_GR (FLD (f_operand1), opval);
4439     written |= (1 << 9);
4440     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4441   }
4442 }
4443 }
4444 }
4445 }
4446  else if (EQSI (tmp_rno, 7)) {
4447 {
4448   SI tmp_addr;
4449   BI tmp_postinc;
4450   tmp_postinc = FLD (f_memmode);
4451   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4452 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4453 if (EQBI (CPU (h_pbit), 0)) {
4454 {
4455   {
4456     SI opval = GET_H_SR (FLD (f_operand2));
4457     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4458     written |= (1 << 13);
4459     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4460   }
4461   {
4462     BI opval = CPU (h_pbit);
4463     CPU (h_cbit) = opval;
4464     written |= (1 << 10);
4465     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4466   }
4467 }
4468 } else {
4469   {
4470     BI opval = 1;
4471     CPU (h_cbit) = opval;
4472     written |= (1 << 10);
4473     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4474   }
4475 }
4476 } else {
4477   {
4478     SI opval = GET_H_SR (FLD (f_operand2));
4479     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4480     written |= (1 << 13);
4481     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4482   }
4483 }
4484 if (NEBI (tmp_postinc, 0)) {
4485 {
4486 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4487   tmp_addr = ADDSI (tmp_addr, 4);
4488 }
4489   {
4490     SI opval = tmp_addr;
4491     SET_H_GR (FLD (f_operand1), opval);
4492     written |= (1 << 9);
4493     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4494   }
4495 }
4496 }
4497 }
4498 }
4499  else if (EQSI (tmp_rno, 14)) {
4500 {
4501   SI tmp_addr;
4502   BI tmp_postinc;
4503   tmp_postinc = FLD (f_memmode);
4504   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4505 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4506 if (EQBI (CPU (h_pbit), 0)) {
4507 {
4508   {
4509     SI opval = GET_H_SR (FLD (f_operand2));
4510     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4511     written |= (1 << 13);
4512     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4513   }
4514   {
4515     BI opval = CPU (h_pbit);
4516     CPU (h_cbit) = opval;
4517     written |= (1 << 10);
4518     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4519   }
4520 }
4521 } else {
4522   {
4523     BI opval = 1;
4524     CPU (h_cbit) = opval;
4525     written |= (1 << 10);
4526     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4527   }
4528 }
4529 } else {
4530   {
4531     SI opval = GET_H_SR (FLD (f_operand2));
4532     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4533     written |= (1 << 13);
4534     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4535   }
4536 }
4537 if (NEBI (tmp_postinc, 0)) {
4538 {
4539 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4540   tmp_addr = ADDSI (tmp_addr, 4);
4541 }
4542   {
4543     SI opval = tmp_addr;
4544     SET_H_GR (FLD (f_operand1), opval);
4545     written |= (1 << 9);
4546     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4547   }
4548 }
4549 }
4550 }
4551 }
4552  else if (EQSI (tmp_rno, 15)) {
4553 {
4554   SI tmp_addr;
4555   BI tmp_postinc;
4556   tmp_postinc = FLD (f_memmode);
4557   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4558 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
4559 if (EQBI (CPU (h_pbit), 0)) {
4560 {
4561   {
4562     SI opval = GET_H_SR (FLD (f_operand2));
4563     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4564     written |= (1 << 13);
4565     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4566   }
4567   {
4568     BI opval = CPU (h_pbit);
4569     CPU (h_cbit) = opval;
4570     written |= (1 << 10);
4571     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4572   }
4573 }
4574 } else {
4575   {
4576     BI opval = 1;
4577     CPU (h_cbit) = opval;
4578     written |= (1 << 10);
4579     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4580   }
4581 }
4582 } else {
4583   {
4584     SI opval = GET_H_SR (FLD (f_operand2));
4585     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4586     written |= (1 << 13);
4587     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4588   }
4589 }
4590 if (NEBI (tmp_postinc, 0)) {
4591 {
4592 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4593   tmp_addr = ADDSI (tmp_addr, 4);
4594 }
4595   {
4596     SI opval = tmp_addr;
4597     SET_H_GR (FLD (f_operand1), opval);
4598     written |= (1 << 9);
4599     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4600   }
4601 }
4602 }
4603 }
4604 }
4605  else {
4606 cgen_rtx_error (current_cpu, "write from unimplemented special register");
4607 }
4608 {
4609   {
4610     BI opval = 0;
4611     CPU (h_xbit) = opval;
4612     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4613   }
4614   {
4615     BI opval = 0;
4616     SET_H_INSN_PREFIXED_P (opval);
4617     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4618   }
4619 }
4620 }
4621
4622   abuf->written = written;
4623 #undef FLD
4624 }
4625   NEXT (vpc);
4626
4627   CASE (sem, INSN_SBFS) : /* sbfs [${Rd-sfield}${inc}] */
4628 {
4629   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4630   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4631 #define FLD(f) abuf->fields.sfmt_empty.f
4632   int UNUSED written = 0;
4633   IADDR UNUSED pc = abuf->addr;
4634   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4635
4636 cgen_rtx_error (current_cpu, "SBFS isn't implemented");
4637
4638 #undef FLD
4639 }
4640   NEXT (vpc);
4641
4642   CASE (sem, INSN_MOVEM_R_M) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
4643 {
4644   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4645   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4646 #define FLD(f) abuf->fields.sfmt_movem_r_m.f
4647   int UNUSED written = 0;
4648   IADDR UNUSED pc = abuf->addr;
4649   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4650
4651 {
4652   SI tmp_addr;
4653   BI tmp_postinc;
4654   tmp_postinc = FLD (f_memmode);
4655 {
4656   SI tmp_dummy;
4657   tmp_dummy = GET_H_GR (FLD (f_operand2));
4658 }
4659   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4660 {
4661 if (GESI (FLD (f_operand2), 15)) {
4662 {
4663   SI tmp_tmp;
4664   tmp_tmp = GET_H_GR (((UINT) 15));
4665   {
4666     SI opval = tmp_tmp;
4667     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4668     written |= (1 << 23);
4669     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4670   }
4671   tmp_addr = ADDSI (tmp_addr, 4);
4672 }
4673 }
4674 if (GESI (FLD (f_operand2), 14)) {
4675 {
4676   SI tmp_tmp;
4677   tmp_tmp = GET_H_GR (((UINT) 14));
4678   {
4679     SI opval = tmp_tmp;
4680     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4681     written |= (1 << 23);
4682     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4683   }
4684   tmp_addr = ADDSI (tmp_addr, 4);
4685 }
4686 }
4687 if (GESI (FLD (f_operand2), 13)) {
4688 {
4689   SI tmp_tmp;
4690   tmp_tmp = GET_H_GR (((UINT) 13));
4691   {
4692     SI opval = tmp_tmp;
4693     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4694     written |= (1 << 23);
4695     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4696   }
4697   tmp_addr = ADDSI (tmp_addr, 4);
4698 }
4699 }
4700 if (GESI (FLD (f_operand2), 12)) {
4701 {
4702   SI tmp_tmp;
4703   tmp_tmp = GET_H_GR (((UINT) 12));
4704   {
4705     SI opval = tmp_tmp;
4706     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4707     written |= (1 << 23);
4708     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4709   }
4710   tmp_addr = ADDSI (tmp_addr, 4);
4711 }
4712 }
4713 if (GESI (FLD (f_operand2), 11)) {
4714 {
4715   SI tmp_tmp;
4716   tmp_tmp = GET_H_GR (((UINT) 11));
4717   {
4718     SI opval = tmp_tmp;
4719     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4720     written |= (1 << 23);
4721     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4722   }
4723   tmp_addr = ADDSI (tmp_addr, 4);
4724 }
4725 }
4726 if (GESI (FLD (f_operand2), 10)) {
4727 {
4728   SI tmp_tmp;
4729   tmp_tmp = GET_H_GR (((UINT) 10));
4730   {
4731     SI opval = tmp_tmp;
4732     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4733     written |= (1 << 23);
4734     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4735   }
4736   tmp_addr = ADDSI (tmp_addr, 4);
4737 }
4738 }
4739 if (GESI (FLD (f_operand2), 9)) {
4740 {
4741   SI tmp_tmp;
4742   tmp_tmp = GET_H_GR (((UINT) 9));
4743   {
4744     SI opval = tmp_tmp;
4745     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4746     written |= (1 << 23);
4747     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4748   }
4749   tmp_addr = ADDSI (tmp_addr, 4);
4750 }
4751 }
4752 if (GESI (FLD (f_operand2), 8)) {
4753 {
4754   SI tmp_tmp;
4755   tmp_tmp = GET_H_GR (((UINT) 8));
4756   {
4757     SI opval = tmp_tmp;
4758     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4759     written |= (1 << 23);
4760     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4761   }
4762   tmp_addr = ADDSI (tmp_addr, 4);
4763 }
4764 }
4765 if (GESI (FLD (f_operand2), 7)) {
4766 {
4767   SI tmp_tmp;
4768   tmp_tmp = GET_H_GR (((UINT) 7));
4769   {
4770     SI opval = tmp_tmp;
4771     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4772     written |= (1 << 23);
4773     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4774   }
4775   tmp_addr = ADDSI (tmp_addr, 4);
4776 }
4777 }
4778 if (GESI (FLD (f_operand2), 6)) {
4779 {
4780   SI tmp_tmp;
4781   tmp_tmp = GET_H_GR (((UINT) 6));
4782   {
4783     SI opval = tmp_tmp;
4784     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4785     written |= (1 << 23);
4786     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4787   }
4788   tmp_addr = ADDSI (tmp_addr, 4);
4789 }
4790 }
4791 if (GESI (FLD (f_operand2), 5)) {
4792 {
4793   SI tmp_tmp;
4794   tmp_tmp = GET_H_GR (((UINT) 5));
4795   {
4796     SI opval = tmp_tmp;
4797     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4798     written |= (1 << 23);
4799     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4800   }
4801   tmp_addr = ADDSI (tmp_addr, 4);
4802 }
4803 }
4804 if (GESI (FLD (f_operand2), 4)) {
4805 {
4806   SI tmp_tmp;
4807   tmp_tmp = GET_H_GR (((UINT) 4));
4808   {
4809     SI opval = tmp_tmp;
4810     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4811     written |= (1 << 23);
4812     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4813   }
4814   tmp_addr = ADDSI (tmp_addr, 4);
4815 }
4816 }
4817 if (GESI (FLD (f_operand2), 3)) {
4818 {
4819   SI tmp_tmp;
4820   tmp_tmp = GET_H_GR (((UINT) 3));
4821   {
4822     SI opval = tmp_tmp;
4823     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4824     written |= (1 << 23);
4825     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4826   }
4827   tmp_addr = ADDSI (tmp_addr, 4);
4828 }
4829 }
4830 if (GESI (FLD (f_operand2), 2)) {
4831 {
4832   SI tmp_tmp;
4833   tmp_tmp = GET_H_GR (((UINT) 2));
4834   {
4835     SI opval = tmp_tmp;
4836     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4837     written |= (1 << 23);
4838     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4839   }
4840   tmp_addr = ADDSI (tmp_addr, 4);
4841 }
4842 }
4843 if (GESI (FLD (f_operand2), 1)) {
4844 {
4845   SI tmp_tmp;
4846   tmp_tmp = GET_H_GR (((UINT) 1));
4847   {
4848     SI opval = tmp_tmp;
4849     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4850     written |= (1 << 23);
4851     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4852   }
4853   tmp_addr = ADDSI (tmp_addr, 4);
4854 }
4855 }
4856 if (GESI (FLD (f_operand2), 0)) {
4857 {
4858   SI tmp_tmp;
4859   tmp_tmp = GET_H_GR (((UINT) 0));
4860   {
4861     SI opval = tmp_tmp;
4862     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4863     written |= (1 << 23);
4864     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4865   }
4866   tmp_addr = ADDSI (tmp_addr, 4);
4867 }
4868 }
4869 }
4870 if (NEBI (tmp_postinc, 0)) {
4871   {
4872     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
4873     SET_H_GR (FLD (f_operand1), opval);
4874     written |= (1 << 22);
4875     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4876   }
4877 }
4878 {
4879   {
4880     BI opval = 0;
4881     CPU (h_xbit) = opval;
4882     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4883   }
4884   {
4885     BI opval = 0;
4886     SET_H_INSN_PREFIXED_P (opval);
4887     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4888   }
4889 }
4890 }
4891
4892   abuf->written = written;
4893 #undef FLD
4894 }
4895   NEXT (vpc);
4896
4897   CASE (sem, INSN_MOVEM_M_R) : /* movem [${Rs}${inc}],${Rd} */
4898 {
4899   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4900   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4901 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
4902   int UNUSED written = 0;
4903   IADDR UNUSED pc = abuf->addr;
4904   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4905
4906 {
4907   SI tmp_addr;
4908   BI tmp_postinc;
4909   tmp_postinc = FLD (f_memmode);
4910   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
4911 {
4912   SI tmp_dummy;
4913   tmp_dummy = GET_H_GR (FLD (f_operand2));
4914 }
4915 {
4916 if (GESI (FLD (f_operand2), 14)) {
4917 {
4918   SI tmp_tmp;
4919   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4920   {
4921     SI opval = tmp_tmp;
4922     SET_H_GR (((UINT) 14), opval);
4923     written |= (1 << 14);
4924     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4925   }
4926   tmp_addr = ADDSI (tmp_addr, 4);
4927 }
4928 }
4929 if (GESI (FLD (f_operand2), 13)) {
4930 {
4931   SI tmp_tmp;
4932   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4933   {
4934     SI opval = tmp_tmp;
4935     SET_H_GR (((UINT) 13), opval);
4936     written |= (1 << 13);
4937     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4938   }
4939   tmp_addr = ADDSI (tmp_addr, 4);
4940 }
4941 }
4942 if (GESI (FLD (f_operand2), 12)) {
4943 {
4944   SI tmp_tmp;
4945   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4946   {
4947     SI opval = tmp_tmp;
4948     SET_H_GR (((UINT) 12), opval);
4949     written |= (1 << 12);
4950     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4951   }
4952   tmp_addr = ADDSI (tmp_addr, 4);
4953 }
4954 }
4955 if (GESI (FLD (f_operand2), 11)) {
4956 {
4957   SI tmp_tmp;
4958   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4959   {
4960     SI opval = tmp_tmp;
4961     SET_H_GR (((UINT) 11), opval);
4962     written |= (1 << 11);
4963     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4964   }
4965   tmp_addr = ADDSI (tmp_addr, 4);
4966 }
4967 }
4968 if (GESI (FLD (f_operand2), 10)) {
4969 {
4970   SI tmp_tmp;
4971   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4972   {
4973     SI opval = tmp_tmp;
4974     SET_H_GR (((UINT) 10), opval);
4975     written |= (1 << 10);
4976     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4977   }
4978   tmp_addr = ADDSI (tmp_addr, 4);
4979 }
4980 }
4981 if (GESI (FLD (f_operand2), 9)) {
4982 {
4983   SI tmp_tmp;
4984   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4985   {
4986     SI opval = tmp_tmp;
4987     SET_H_GR (((UINT) 9), opval);
4988     written |= (1 << 22);
4989     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4990   }
4991   tmp_addr = ADDSI (tmp_addr, 4);
4992 }
4993 }
4994 if (GESI (FLD (f_operand2), 8)) {
4995 {
4996   SI tmp_tmp;
4997   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
4998   {
4999     SI opval = tmp_tmp;
5000     SET_H_GR (((UINT) 8), opval);
5001     written |= (1 << 21);
5002     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5003   }
5004   tmp_addr = ADDSI (tmp_addr, 4);
5005 }
5006 }
5007 if (GESI (FLD (f_operand2), 7)) {
5008 {
5009   SI tmp_tmp;
5010   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5011   {
5012     SI opval = tmp_tmp;
5013     SET_H_GR (((UINT) 7), opval);
5014     written |= (1 << 20);
5015     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5016   }
5017   tmp_addr = ADDSI (tmp_addr, 4);
5018 }
5019 }
5020 if (GESI (FLD (f_operand2), 6)) {
5021 {
5022   SI tmp_tmp;
5023   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5024   {
5025     SI opval = tmp_tmp;
5026     SET_H_GR (((UINT) 6), opval);
5027     written |= (1 << 19);
5028     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5029   }
5030   tmp_addr = ADDSI (tmp_addr, 4);
5031 }
5032 }
5033 if (GESI (FLD (f_operand2), 5)) {
5034 {
5035   SI tmp_tmp;
5036   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5037   {
5038     SI opval = tmp_tmp;
5039     SET_H_GR (((UINT) 5), opval);
5040     written |= (1 << 18);
5041     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5042   }
5043   tmp_addr = ADDSI (tmp_addr, 4);
5044 }
5045 }
5046 if (GESI (FLD (f_operand2), 4)) {
5047 {
5048   SI tmp_tmp;
5049   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5050   {
5051     SI opval = tmp_tmp;
5052     SET_H_GR (((UINT) 4), opval);
5053     written |= (1 << 17);
5054     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5055   }
5056   tmp_addr = ADDSI (tmp_addr, 4);
5057 }
5058 }
5059 if (GESI (FLD (f_operand2), 3)) {
5060 {
5061   SI tmp_tmp;
5062   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5063   {
5064     SI opval = tmp_tmp;
5065     SET_H_GR (((UINT) 3), opval);
5066     written |= (1 << 16);
5067     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5068   }
5069   tmp_addr = ADDSI (tmp_addr, 4);
5070 }
5071 }
5072 if (GESI (FLD (f_operand2), 2)) {
5073 {
5074   SI tmp_tmp;
5075   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5076   {
5077     SI opval = tmp_tmp;
5078     SET_H_GR (((UINT) 2), opval);
5079     written |= (1 << 15);
5080     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5081   }
5082   tmp_addr = ADDSI (tmp_addr, 4);
5083 }
5084 }
5085 if (GESI (FLD (f_operand2), 1)) {
5086 {
5087   SI tmp_tmp;
5088   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5089   {
5090     SI opval = tmp_tmp;
5091     SET_H_GR (((UINT) 1), opval);
5092     written |= (1 << 9);
5093     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5094   }
5095   tmp_addr = ADDSI (tmp_addr, 4);
5096 }
5097 }
5098 if (GESI (FLD (f_operand2), 0)) {
5099 {
5100   SI tmp_tmp;
5101   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5102   {
5103     SI opval = tmp_tmp;
5104     SET_H_GR (((UINT) 0), opval);
5105     written |= (1 << 8);
5106     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5107   }
5108   tmp_addr = ADDSI (tmp_addr, 4);
5109 }
5110 }
5111 }
5112 if (NEBI (tmp_postinc, 0)) {
5113   {
5114     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5115     SET_H_GR (FLD (f_operand1), opval);
5116     written |= (1 << 7);
5117     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5118   }
5119 }
5120 {
5121   {
5122     BI opval = 0;
5123     CPU (h_xbit) = opval;
5124     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5125   }
5126   {
5127     BI opval = 0;
5128     SET_H_INSN_PREFIXED_P (opval);
5129     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5130   }
5131 }
5132 }
5133
5134   abuf->written = written;
5135 #undef FLD
5136 }
5137   NEXT (vpc);
5138
5139   CASE (sem, INSN_MOVEM_M_PC) : /* movem [${Rs}${inc}],${Rd} */
5140 {
5141   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5142   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5143 #define FLD(f) abuf->fields.sfmt_movem_m_r.f
5144   int UNUSED written = 0;
5145   IADDR UNUSED pc = abuf->addr;
5146   SEM_BRANCH_INIT
5147   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5148
5149 {
5150   SI tmp_addr;
5151   BI tmp_postinc;
5152   tmp_postinc = FLD (f_memmode);
5153   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5154 {
5155   {
5156     USI opval = GETMEMSI (current_cpu, pc, tmp_addr);
5157     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
5158     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
5159   }
5160   tmp_addr = ADDSI (tmp_addr, 4);
5161 {
5162   SI tmp_tmp;
5163   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5164   {
5165     SI opval = tmp_tmp;
5166     SET_H_GR (((UINT) 14), opval);
5167     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5168   }
5169   tmp_addr = ADDSI (tmp_addr, 4);
5170 }
5171 {
5172   SI tmp_tmp;
5173   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5174   {
5175     SI opval = tmp_tmp;
5176     SET_H_GR (((UINT) 13), opval);
5177     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5178   }
5179   tmp_addr = ADDSI (tmp_addr, 4);
5180 }
5181 {
5182   SI tmp_tmp;
5183   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5184   {
5185     SI opval = tmp_tmp;
5186     SET_H_GR (((UINT) 12), opval);
5187     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5188   }
5189   tmp_addr = ADDSI (tmp_addr, 4);
5190 }
5191 {
5192   SI tmp_tmp;
5193   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5194   {
5195     SI opval = tmp_tmp;
5196     SET_H_GR (((UINT) 11), opval);
5197     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5198   }
5199   tmp_addr = ADDSI (tmp_addr, 4);
5200 }
5201 {
5202   SI tmp_tmp;
5203   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5204   {
5205     SI opval = tmp_tmp;
5206     SET_H_GR (((UINT) 10), opval);
5207     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5208   }
5209   tmp_addr = ADDSI (tmp_addr, 4);
5210 }
5211 {
5212   SI tmp_tmp;
5213   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5214   {
5215     SI opval = tmp_tmp;
5216     SET_H_GR (((UINT) 9), opval);
5217     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5218   }
5219   tmp_addr = ADDSI (tmp_addr, 4);
5220 }
5221 {
5222   SI tmp_tmp;
5223   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5224   {
5225     SI opval = tmp_tmp;
5226     SET_H_GR (((UINT) 8), opval);
5227     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5228   }
5229   tmp_addr = ADDSI (tmp_addr, 4);
5230 }
5231 {
5232   SI tmp_tmp;
5233   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5234   {
5235     SI opval = tmp_tmp;
5236     SET_H_GR (((UINT) 7), opval);
5237     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5238   }
5239   tmp_addr = ADDSI (tmp_addr, 4);
5240 }
5241 {
5242   SI tmp_tmp;
5243   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5244   {
5245     SI opval = tmp_tmp;
5246     SET_H_GR (((UINT) 6), opval);
5247     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5248   }
5249   tmp_addr = ADDSI (tmp_addr, 4);
5250 }
5251 {
5252   SI tmp_tmp;
5253   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5254   {
5255     SI opval = tmp_tmp;
5256     SET_H_GR (((UINT) 5), opval);
5257     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5258   }
5259   tmp_addr = ADDSI (tmp_addr, 4);
5260 }
5261 {
5262   SI tmp_tmp;
5263   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5264   {
5265     SI opval = tmp_tmp;
5266     SET_H_GR (((UINT) 4), opval);
5267     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5268   }
5269   tmp_addr = ADDSI (tmp_addr, 4);
5270 }
5271 {
5272   SI tmp_tmp;
5273   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5274   {
5275     SI opval = tmp_tmp;
5276     SET_H_GR (((UINT) 3), opval);
5277     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5278   }
5279   tmp_addr = ADDSI (tmp_addr, 4);
5280 }
5281 {
5282   SI tmp_tmp;
5283   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5284   {
5285     SI opval = tmp_tmp;
5286     SET_H_GR (((UINT) 2), opval);
5287     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5288   }
5289   tmp_addr = ADDSI (tmp_addr, 4);
5290 }
5291 {
5292   SI tmp_tmp;
5293   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5294   {
5295     SI opval = tmp_tmp;
5296     SET_H_GR (((UINT) 1), opval);
5297     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5298   }
5299   tmp_addr = ADDSI (tmp_addr, 4);
5300 }
5301 {
5302   SI tmp_tmp;
5303   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5304   {
5305     SI opval = tmp_tmp;
5306     SET_H_GR (((UINT) 0), opval);
5307     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5308   }
5309   tmp_addr = ADDSI (tmp_addr, 4);
5310 }
5311 }
5312 if (NEBI (tmp_postinc, 0)) {
5313   {
5314     SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
5315     SET_H_GR (FLD (f_operand1), opval);
5316     written |= (1 << 5);
5317     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5318   }
5319 }
5320 {
5321   {
5322     BI opval = 0;
5323     CPU (h_xbit) = opval;
5324     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5325   }
5326   {
5327     BI opval = 0;
5328     SET_H_INSN_PREFIXED_P (opval);
5329     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5330   }
5331 }
5332 }
5333
5334   abuf->written = written;
5335   SEM_BRANCH_FINI (vpc);
5336 #undef FLD
5337 }
5338   NEXT (vpc);
5339
5340   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5341 {
5342   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5343   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5344 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5345   int UNUSED written = 0;
5346   IADDR UNUSED pc = abuf->addr;
5347   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5348
5349 {
5350   QI tmp_tmpopd;
5351   QI tmp_tmpops;
5352   BI tmp_carry;
5353   QI tmp_newval;
5354   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5355   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5356   tmp_carry = CPU (h_cbit);
5357   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5358 {
5359   SI tmp_oldregval;
5360   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5361   {
5362     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5363     SET_H_GR (FLD (f_operand2), opval);
5364     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5365   }
5366 }
5367 {
5368   {
5369     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5370     CPU (h_cbit) = opval;
5371     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5372   }
5373   {
5374     BI opval = LTQI (tmp_newval, 0);
5375     CPU (h_nbit) = opval;
5376     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5377   }
5378   {
5379     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5380     CPU (h_zbit) = opval;
5381     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5382   }
5383   {
5384     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5385     CPU (h_vbit) = opval;
5386     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5387   }
5388 {
5389   {
5390     BI opval = 0;
5391     CPU (h_xbit) = opval;
5392     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5393   }
5394   {
5395     BI opval = 0;
5396     SET_H_INSN_PREFIXED_P (opval);
5397     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5398   }
5399 }
5400 }
5401 }
5402
5403 #undef FLD
5404 }
5405   NEXT (vpc);
5406
5407   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5408 {
5409   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5410   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5411 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5412   int UNUSED written = 0;
5413   IADDR UNUSED pc = abuf->addr;
5414   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5415
5416 {
5417   HI tmp_tmpopd;
5418   HI tmp_tmpops;
5419   BI tmp_carry;
5420   HI tmp_newval;
5421   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5422   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5423   tmp_carry = CPU (h_cbit);
5424   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5425 {
5426   SI tmp_oldregval;
5427   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5428   {
5429     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5430     SET_H_GR (FLD (f_operand2), opval);
5431     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5432   }
5433 }
5434 {
5435   {
5436     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5437     CPU (h_cbit) = opval;
5438     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5439   }
5440   {
5441     BI opval = LTHI (tmp_newval, 0);
5442     CPU (h_nbit) = opval;
5443     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5444   }
5445   {
5446     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5447     CPU (h_zbit) = opval;
5448     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5449   }
5450   {
5451     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5452     CPU (h_vbit) = opval;
5453     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5454   }
5455 {
5456   {
5457     BI opval = 0;
5458     CPU (h_xbit) = opval;
5459     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5460   }
5461   {
5462     BI opval = 0;
5463     SET_H_INSN_PREFIXED_P (opval);
5464     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5465   }
5466 }
5467 }
5468 }
5469
5470 #undef FLD
5471 }
5472   NEXT (vpc);
5473
5474   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5475 {
5476   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5477   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5478 #define FLD(f) abuf->fields.sfmt_add_b_r.f
5479   int UNUSED written = 0;
5480   IADDR UNUSED pc = abuf->addr;
5481   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5482
5483 {
5484   SI tmp_tmpopd;
5485   SI tmp_tmpops;
5486   BI tmp_carry;
5487   SI tmp_newval;
5488   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5489   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5490   tmp_carry = CPU (h_cbit);
5491   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5492   {
5493     SI opval = tmp_newval;
5494     SET_H_GR (FLD (f_operand2), opval);
5495     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5496   }
5497 {
5498   {
5499     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5500     CPU (h_cbit) = opval;
5501     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5502   }
5503   {
5504     BI opval = LTSI (tmp_newval, 0);
5505     CPU (h_nbit) = opval;
5506     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5507   }
5508   {
5509     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5510     CPU (h_zbit) = opval;
5511     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5512   }
5513   {
5514     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5515     CPU (h_vbit) = opval;
5516     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5517   }
5518 {
5519   {
5520     BI opval = 0;
5521     CPU (h_xbit) = opval;
5522     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5523   }
5524   {
5525     BI opval = 0;
5526     SET_H_INSN_PREFIXED_P (opval);
5527     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5528   }
5529 }
5530 }
5531 }
5532
5533 #undef FLD
5534 }
5535   NEXT (vpc);
5536
5537   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5538 {
5539   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5540   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5541 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5542   int UNUSED written = 0;
5543   IADDR UNUSED pc = abuf->addr;
5544   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5545
5546 {
5547   QI tmp_tmpopd;
5548   QI tmp_tmpops;
5549   BI tmp_carry;
5550   QI tmp_newval;
5551   tmp_tmpops = ({   SI tmp_addr;
5552   QI tmp_tmp_mem;
5553   BI tmp_postinc;
5554   tmp_postinc = FLD (f_memmode);
5555 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5556 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5557 ; if (NEBI (tmp_postinc, 0)) {
5558 {
5559 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5560   tmp_addr = ADDSI (tmp_addr, 1);
5561 }
5562   {
5563     SI opval = tmp_addr;
5564     SET_H_GR (FLD (f_operand1), opval);
5565     written |= (1 << 12);
5566     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5567   }
5568 }
5569 }
5570 ; tmp_tmp_mem; });
5571   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5572   tmp_carry = CPU (h_cbit);
5573   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5574 {
5575   SI tmp_oldregval;
5576   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5577   {
5578     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5579     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5580     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5581   }
5582 }
5583 {
5584   {
5585     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5586     CPU (h_cbit) = opval;
5587     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5588   }
5589   {
5590     BI opval = LTQI (tmp_newval, 0);
5591     CPU (h_nbit) = opval;
5592     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5593   }
5594   {
5595     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5596     CPU (h_zbit) = opval;
5597     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5598   }
5599   {
5600     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5601     CPU (h_vbit) = opval;
5602     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5603   }
5604 {
5605   {
5606     BI opval = 0;
5607     CPU (h_xbit) = opval;
5608     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5609   }
5610   {
5611     BI opval = 0;
5612     SET_H_INSN_PREFIXED_P (opval);
5613     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5614   }
5615 }
5616 }
5617 }
5618
5619   abuf->written = written;
5620 #undef FLD
5621 }
5622   NEXT (vpc);
5623
5624   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5625 {
5626   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5627   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5628 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5629   int UNUSED written = 0;
5630   IADDR UNUSED pc = abuf->addr;
5631   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5632
5633 {
5634   HI tmp_tmpopd;
5635   HI tmp_tmpops;
5636   BI tmp_carry;
5637   HI tmp_newval;
5638   tmp_tmpops = ({   SI tmp_addr;
5639   HI tmp_tmp_mem;
5640   BI tmp_postinc;
5641   tmp_postinc = FLD (f_memmode);
5642 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5643 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5644 ; if (NEBI (tmp_postinc, 0)) {
5645 {
5646 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5647   tmp_addr = ADDSI (tmp_addr, 2);
5648 }
5649   {
5650     SI opval = tmp_addr;
5651     SET_H_GR (FLD (f_operand1), opval);
5652     written |= (1 << 12);
5653     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5654   }
5655 }
5656 }
5657 ; tmp_tmp_mem; });
5658   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5659   tmp_carry = CPU (h_cbit);
5660   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5661 {
5662   SI tmp_oldregval;
5663   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5664   {
5665     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5666     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5667     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5668   }
5669 }
5670 {
5671   {
5672     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5673     CPU (h_cbit) = opval;
5674     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5675   }
5676   {
5677     BI opval = LTHI (tmp_newval, 0);
5678     CPU (h_nbit) = opval;
5679     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5680   }
5681   {
5682     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5683     CPU (h_zbit) = opval;
5684     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5685   }
5686   {
5687     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5688     CPU (h_vbit) = opval;
5689     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5690   }
5691 {
5692   {
5693     BI opval = 0;
5694     CPU (h_xbit) = opval;
5695     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5696   }
5697   {
5698     BI opval = 0;
5699     SET_H_INSN_PREFIXED_P (opval);
5700     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5701   }
5702 }
5703 }
5704 }
5705
5706   abuf->written = written;
5707 #undef FLD
5708 }
5709   NEXT (vpc);
5710
5711   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
5712 {
5713   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5714   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5715 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5716   int UNUSED written = 0;
5717   IADDR UNUSED pc = abuf->addr;
5718   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5719
5720 {
5721   SI tmp_tmpopd;
5722   SI tmp_tmpops;
5723   BI tmp_carry;
5724   SI tmp_newval;
5725   tmp_tmpops = ({   SI tmp_addr;
5726   SI tmp_tmp_mem;
5727   BI tmp_postinc;
5728   tmp_postinc = FLD (f_memmode);
5729 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
5730 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
5731 ; if (NEBI (tmp_postinc, 0)) {
5732 {
5733 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5734   tmp_addr = ADDSI (tmp_addr, 4);
5735 }
5736   {
5737     SI opval = tmp_addr;
5738     SET_H_GR (FLD (f_operand1), opval);
5739     written |= (1 << 11);
5740     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5741   }
5742 }
5743 }
5744 ; tmp_tmp_mem; });
5745   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5746   tmp_carry = CPU (h_cbit);
5747   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5748   {
5749     SI opval = tmp_newval;
5750     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5751     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5752   }
5753 {
5754   {
5755     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5756     CPU (h_cbit) = opval;
5757     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5758   }
5759   {
5760     BI opval = LTSI (tmp_newval, 0);
5761     CPU (h_nbit) = opval;
5762     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5763   }
5764   {
5765     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5766     CPU (h_zbit) = opval;
5767     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5768   }
5769   {
5770     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5771     CPU (h_vbit) = opval;
5772     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5773   }
5774 {
5775   {
5776     BI opval = 0;
5777     CPU (h_xbit) = opval;
5778     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5779   }
5780   {
5781     BI opval = 0;
5782     SET_H_INSN_PREFIXED_P (opval);
5783     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5784   }
5785 }
5786 }
5787 }
5788
5789   abuf->written = written;
5790 #undef FLD
5791 }
5792   NEXT (vpc);
5793
5794   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
5795 {
5796   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5797   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5798 #define FLD(f) abuf->fields.sfmt_addcbr.f
5799   int UNUSED written = 0;
5800   IADDR UNUSED pc = abuf->addr;
5801   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5802
5803 {
5804   QI tmp_tmpopd;
5805   QI tmp_tmpops;
5806   BI tmp_carry;
5807   QI tmp_newval;
5808   tmp_tmpops = FLD (f_indir_pc__byte);
5809   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5810   tmp_carry = CPU (h_cbit);
5811   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5812 {
5813   SI tmp_oldregval;
5814   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5815   {
5816     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5817     SET_H_GR (FLD (f_operand2), opval);
5818     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5819   }
5820 }
5821 {
5822   {
5823     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5824     CPU (h_cbit) = opval;
5825     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5826   }
5827   {
5828     BI opval = LTQI (tmp_newval, 0);
5829     CPU (h_nbit) = opval;
5830     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5831   }
5832   {
5833     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5834     CPU (h_zbit) = opval;
5835     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5836   }
5837   {
5838     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5839     CPU (h_vbit) = opval;
5840     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5841   }
5842 {
5843   {
5844     BI opval = 0;
5845     CPU (h_xbit) = opval;
5846     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5847   }
5848   {
5849     BI opval = 0;
5850     SET_H_INSN_PREFIXED_P (opval);
5851     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5852   }
5853 }
5854 }
5855 }
5856
5857 #undef FLD
5858 }
5859   NEXT (vpc);
5860
5861   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
5862 {
5863   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5864   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5865 #define FLD(f) abuf->fields.sfmt_addcwr.f
5866   int UNUSED written = 0;
5867   IADDR UNUSED pc = abuf->addr;
5868   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5869
5870 {
5871   HI tmp_tmpopd;
5872   HI tmp_tmpops;
5873   BI tmp_carry;
5874   HI tmp_newval;
5875   tmp_tmpops = FLD (f_indir_pc__word);
5876   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5877   tmp_carry = CPU (h_cbit);
5878   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5879 {
5880   SI tmp_oldregval;
5881   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
5882   {
5883     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5884     SET_H_GR (FLD (f_operand2), opval);
5885     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5886   }
5887 }
5888 {
5889   {
5890     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5891     CPU (h_cbit) = opval;
5892     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5893   }
5894   {
5895     BI opval = LTHI (tmp_newval, 0);
5896     CPU (h_nbit) = opval;
5897     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5898   }
5899   {
5900     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5901     CPU (h_zbit) = opval;
5902     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5903   }
5904   {
5905     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5906     CPU (h_vbit) = opval;
5907     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5908   }
5909 {
5910   {
5911     BI opval = 0;
5912     CPU (h_xbit) = opval;
5913     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5914   }
5915   {
5916     BI opval = 0;
5917     SET_H_INSN_PREFIXED_P (opval);
5918     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5919   }
5920 }
5921 }
5922 }
5923
5924 #undef FLD
5925 }
5926   NEXT (vpc);
5927
5928   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
5929 {
5930   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5931   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5932 #define FLD(f) abuf->fields.sfmt_addcdr.f
5933   int UNUSED written = 0;
5934   IADDR UNUSED pc = abuf->addr;
5935   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
5936
5937 {
5938   SI tmp_tmpopd;
5939   SI tmp_tmpops;
5940   BI tmp_carry;
5941   SI tmp_newval;
5942   tmp_tmpops = FLD (f_indir_pc__dword);
5943   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5944   tmp_carry = CPU (h_cbit);
5945   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5946   {
5947     SI opval = tmp_newval;
5948     SET_H_GR (FLD (f_operand2), opval);
5949     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5950   }
5951 {
5952   {
5953     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5954     CPU (h_cbit) = opval;
5955     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5956   }
5957   {
5958     BI opval = LTSI (tmp_newval, 0);
5959     CPU (h_nbit) = opval;
5960     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5961   }
5962   {
5963     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5964     CPU (h_zbit) = opval;
5965     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5966   }
5967   {
5968     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5969     CPU (h_vbit) = opval;
5970     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5971   }
5972 {
5973   {
5974     BI opval = 0;
5975     CPU (h_xbit) = opval;
5976     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5977   }
5978   {
5979     BI opval = 0;
5980     SET_H_INSN_PREFIXED_P (opval);
5981     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5982   }
5983 }
5984 }
5985 }
5986
5987 #undef FLD
5988 }
5989   NEXT (vpc);
5990
5991   CASE (sem, INSN_ADDCPC) : /* add.d ${sconst32},PC */
5992 {
5993   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5994   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5995 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
5996   int UNUSED written = 0;
5997   IADDR UNUSED pc = abuf->addr;
5998   SEM_BRANCH_INIT
5999   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6000
6001 {
6002   SI tmp_newpc;
6003   SI tmp_oldpc;
6004   SI tmp_offs;
6005   tmp_offs = FLD (f_indir_pc__dword);
6006   tmp_oldpc = ADDSI (pc, 6);
6007   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6008   {
6009     USI opval = tmp_newpc;
6010     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6011     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6012   }
6013 {
6014   {
6015     BI opval = ORIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (tmp_offs, 0), GESI (tmp_newpc, 0))));
6016     CPU (h_cbit) = opval;
6017     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6018   }
6019   {
6020     BI opval = LTSI (tmp_newpc, 0);
6021     CPU (h_nbit) = opval;
6022     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6023   }
6024   {
6025     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6026     CPU (h_zbit) = opval;
6027     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6028   }
6029   {
6030     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (tmp_offs, 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6031     CPU (h_vbit) = opval;
6032     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6033   }
6034 {
6035   {
6036     BI opval = 0;
6037     CPU (h_xbit) = opval;
6038     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6039   }
6040   {
6041     BI opval = 0;
6042     SET_H_INSN_PREFIXED_P (opval);
6043     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6044   }
6045 }
6046 }
6047 }
6048
6049   SEM_BRANCH_FINI (vpc);
6050 #undef FLD
6051 }
6052   NEXT (vpc);
6053
6054   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6055 {
6056   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6057   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6058 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6059   int UNUSED written = 0;
6060   IADDR UNUSED pc = abuf->addr;
6061   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6062
6063 {
6064   SI tmp_tmpopd;
6065   SI tmp_tmpops;
6066   BI tmp_carry;
6067   SI tmp_newval;
6068   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6069   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6070   tmp_carry = CPU (h_cbit);
6071   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6072   {
6073     SI opval = tmp_newval;
6074     SET_H_GR (FLD (f_operand2), opval);
6075     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6076   }
6077 {
6078   {
6079     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6080     CPU (h_cbit) = opval;
6081     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6082   }
6083   {
6084     BI opval = LTSI (tmp_newval, 0);
6085     CPU (h_nbit) = opval;
6086     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6087   }
6088   {
6089     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6090     CPU (h_zbit) = opval;
6091     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6092   }
6093   {
6094     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6095     CPU (h_vbit) = opval;
6096     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6097   }
6098 {
6099   {
6100     BI opval = 0;
6101     CPU (h_xbit) = opval;
6102     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6103   }
6104   {
6105     BI opval = 0;
6106     SET_H_INSN_PREFIXED_P (opval);
6107     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6108   }
6109 }
6110 }
6111 }
6112
6113 #undef FLD
6114 }
6115   NEXT (vpc);
6116
6117   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6118 {
6119   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6120   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6121 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6122   int UNUSED written = 0;
6123   IADDR UNUSED pc = abuf->addr;
6124   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6125
6126 {
6127   SI tmp_tmpopd;
6128   SI tmp_tmpops;
6129   BI tmp_carry;
6130   SI tmp_newval;
6131   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6132   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6133   tmp_carry = CPU (h_cbit);
6134   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6135   {
6136     SI opval = tmp_newval;
6137     SET_H_GR (FLD (f_operand2), opval);
6138     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6139   }
6140 {
6141   {
6142     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6143     CPU (h_cbit) = opval;
6144     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6145   }
6146   {
6147     BI opval = LTSI (tmp_newval, 0);
6148     CPU (h_nbit) = opval;
6149     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6150   }
6151   {
6152     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6153     CPU (h_zbit) = opval;
6154     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6155   }
6156   {
6157     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6158     CPU (h_vbit) = opval;
6159     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6160   }
6161 {
6162   {
6163     BI opval = 0;
6164     CPU (h_xbit) = opval;
6165     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6166   }
6167   {
6168     BI opval = 0;
6169     SET_H_INSN_PREFIXED_P (opval);
6170     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6171   }
6172 }
6173 }
6174 }
6175
6176 #undef FLD
6177 }
6178   NEXT (vpc);
6179
6180   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6181 {
6182   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6183   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6184 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6185   int UNUSED written = 0;
6186   IADDR UNUSED pc = abuf->addr;
6187   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6188
6189 {
6190   SI tmp_tmpopd;
6191   SI tmp_tmpops;
6192   BI tmp_carry;
6193   SI tmp_newval;
6194   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6195   QI tmp_tmp_mem;
6196   BI tmp_postinc;
6197   tmp_postinc = FLD (f_memmode);
6198 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6199 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6200 ; if (NEBI (tmp_postinc, 0)) {
6201 {
6202 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6203   tmp_addr = ADDSI (tmp_addr, 1);
6204 }
6205   {
6206     SI opval = tmp_addr;
6207     SET_H_GR (FLD (f_operand1), opval);
6208     written |= (1 << 11);
6209     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6210   }
6211 }
6212 }
6213 ; tmp_tmp_mem; }));
6214   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6215   tmp_carry = CPU (h_cbit);
6216   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6217   {
6218     SI opval = tmp_newval;
6219     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6220     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6221   }
6222 {
6223   {
6224     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6225     CPU (h_cbit) = opval;
6226     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6227   }
6228   {
6229     BI opval = LTSI (tmp_newval, 0);
6230     CPU (h_nbit) = opval;
6231     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6232   }
6233   {
6234     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6235     CPU (h_zbit) = opval;
6236     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6237   }
6238   {
6239     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6240     CPU (h_vbit) = opval;
6241     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6242   }
6243 {
6244   {
6245     BI opval = 0;
6246     CPU (h_xbit) = opval;
6247     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6248   }
6249   {
6250     BI opval = 0;
6251     SET_H_INSN_PREFIXED_P (opval);
6252     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6253   }
6254 }
6255 }
6256 }
6257
6258   abuf->written = written;
6259 #undef FLD
6260 }
6261   NEXT (vpc);
6262
6263   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6264 {
6265   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6266   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6267 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6268   int UNUSED written = 0;
6269   IADDR UNUSED pc = abuf->addr;
6270   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6271
6272 {
6273   SI tmp_tmpopd;
6274   SI tmp_tmpops;
6275   BI tmp_carry;
6276   SI tmp_newval;
6277   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6278   HI tmp_tmp_mem;
6279   BI tmp_postinc;
6280   tmp_postinc = FLD (f_memmode);
6281 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6282 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6283 ; if (NEBI (tmp_postinc, 0)) {
6284 {
6285 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6286   tmp_addr = ADDSI (tmp_addr, 2);
6287 }
6288   {
6289     SI opval = tmp_addr;
6290     SET_H_GR (FLD (f_operand1), opval);
6291     written |= (1 << 11);
6292     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6293   }
6294 }
6295 }
6296 ; tmp_tmp_mem; }));
6297   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6298   tmp_carry = CPU (h_cbit);
6299   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6300   {
6301     SI opval = tmp_newval;
6302     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6303     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6304   }
6305 {
6306   {
6307     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6308     CPU (h_cbit) = opval;
6309     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6310   }
6311   {
6312     BI opval = LTSI (tmp_newval, 0);
6313     CPU (h_nbit) = opval;
6314     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6315   }
6316   {
6317     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6318     CPU (h_zbit) = opval;
6319     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6320   }
6321   {
6322     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6323     CPU (h_vbit) = opval;
6324     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6325   }
6326 {
6327   {
6328     BI opval = 0;
6329     CPU (h_xbit) = opval;
6330     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6331   }
6332   {
6333     BI opval = 0;
6334     SET_H_INSN_PREFIXED_P (opval);
6335     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6336   }
6337 }
6338 }
6339 }
6340
6341   abuf->written = written;
6342 #undef FLD
6343 }
6344   NEXT (vpc);
6345
6346   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6347 {
6348   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6349   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6350 #define FLD(f) abuf->fields.sfmt_addcbr.f
6351   int UNUSED written = 0;
6352   IADDR UNUSED pc = abuf->addr;
6353   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6354
6355 {
6356   SI tmp_tmpopd;
6357   SI tmp_tmpops;
6358   BI tmp_carry;
6359   SI tmp_newval;
6360   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6361   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6362   tmp_carry = CPU (h_cbit);
6363   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6364   {
6365     SI opval = tmp_newval;
6366     SET_H_GR (FLD (f_operand2), opval);
6367     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6368   }
6369 {
6370   {
6371     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6372     CPU (h_cbit) = opval;
6373     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6374   }
6375   {
6376     BI opval = LTSI (tmp_newval, 0);
6377     CPU (h_nbit) = opval;
6378     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6379   }
6380   {
6381     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6382     CPU (h_zbit) = opval;
6383     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6384   }
6385   {
6386     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6387     CPU (h_vbit) = opval;
6388     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6389   }
6390 {
6391   {
6392     BI opval = 0;
6393     CPU (h_xbit) = opval;
6394     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6395   }
6396   {
6397     BI opval = 0;
6398     SET_H_INSN_PREFIXED_P (opval);
6399     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6400   }
6401 }
6402 }
6403 }
6404
6405 #undef FLD
6406 }
6407   NEXT (vpc);
6408
6409   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6410 {
6411   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6412   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6413 #define FLD(f) abuf->fields.sfmt_addcwr.f
6414   int UNUSED written = 0;
6415   IADDR UNUSED pc = abuf->addr;
6416   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6417
6418 {
6419   SI tmp_tmpopd;
6420   SI tmp_tmpops;
6421   BI tmp_carry;
6422   SI tmp_newval;
6423   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6424   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6425   tmp_carry = CPU (h_cbit);
6426   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6427   {
6428     SI opval = tmp_newval;
6429     SET_H_GR (FLD (f_operand2), opval);
6430     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6431   }
6432 {
6433   {
6434     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6435     CPU (h_cbit) = opval;
6436     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6437   }
6438   {
6439     BI opval = LTSI (tmp_newval, 0);
6440     CPU (h_nbit) = opval;
6441     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6442   }
6443   {
6444     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6445     CPU (h_zbit) = opval;
6446     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6447   }
6448   {
6449     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6450     CPU (h_vbit) = opval;
6451     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6452   }
6453 {
6454   {
6455     BI opval = 0;
6456     CPU (h_xbit) = opval;
6457     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6458   }
6459   {
6460     BI opval = 0;
6461     SET_H_INSN_PREFIXED_P (opval);
6462     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6463   }
6464 }
6465 }
6466 }
6467
6468 #undef FLD
6469 }
6470   NEXT (vpc);
6471
6472   CASE (sem, INSN_ADDSPCPC) : /* adds.w [PC],PC */
6473 {
6474   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6475   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6476 #define FLD(f) abuf->fields.sfmt_empty.f
6477   int UNUSED written = 0;
6478   IADDR UNUSED pc = abuf->addr;
6479   SEM_BRANCH_INIT
6480   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6481
6482 {
6483   SI tmp_newpc;
6484   SI tmp_oldpc;
6485   HI tmp_offs;
6486 if (NOTBI (GET_H_INSN_PREFIXED_P ())) {
6487 cgen_rtx_error (current_cpu, "Unexpected adds.w [PC],PC without prefix");
6488 }
6489   tmp_offs = GETMEMHI (current_cpu, pc, CPU (h_prefixreg_pre_v32));
6490   tmp_oldpc = ADDSI (pc, 2);
6491   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
6492   {
6493     USI opval = tmp_newpc;
6494     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
6495     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
6496   }
6497 {
6498   {
6499     BI opval = ORIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (EXTHISI (tmp_offs), 0), GESI (tmp_newpc, 0))));
6500     CPU (h_cbit) = opval;
6501     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6502   }
6503   {
6504     BI opval = LTSI (tmp_newpc, 0);
6505     CPU (h_nbit) = opval;
6506     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6507   }
6508   {
6509     BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6510     CPU (h_zbit) = opval;
6511     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6512   }
6513   {
6514     BI opval = ORIF (ANDIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (EXTHISI (tmp_offs), 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
6515     CPU (h_vbit) = opval;
6516     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6517   }
6518 {
6519   {
6520     BI opval = 0;
6521     CPU (h_xbit) = opval;
6522     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6523   }
6524   {
6525     BI opval = 0;
6526     SET_H_INSN_PREFIXED_P (opval);
6527     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6528   }
6529 }
6530 }
6531 }
6532
6533   SEM_BRANCH_FINI (vpc);
6534 #undef FLD
6535 }
6536   NEXT (vpc);
6537
6538   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6539 {
6540   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6541   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6542 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6543   int UNUSED written = 0;
6544   IADDR UNUSED pc = abuf->addr;
6545   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6546
6547 {
6548   SI tmp_tmpopd;
6549   SI tmp_tmpops;
6550   BI tmp_carry;
6551   SI tmp_newval;
6552   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6553   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6554   tmp_carry = CPU (h_cbit);
6555   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6556   {
6557     SI opval = tmp_newval;
6558     SET_H_GR (FLD (f_operand2), opval);
6559     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6560   }
6561 {
6562   {
6563     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6564     CPU (h_cbit) = opval;
6565     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6566   }
6567   {
6568     BI opval = LTSI (tmp_newval, 0);
6569     CPU (h_nbit) = opval;
6570     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6571   }
6572   {
6573     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6574     CPU (h_zbit) = opval;
6575     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6576   }
6577   {
6578     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6579     CPU (h_vbit) = opval;
6580     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6581   }
6582 {
6583   {
6584     BI opval = 0;
6585     CPU (h_xbit) = opval;
6586     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6587   }
6588   {
6589     BI opval = 0;
6590     SET_H_INSN_PREFIXED_P (opval);
6591     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6592   }
6593 }
6594 }
6595 }
6596
6597 #undef FLD
6598 }
6599   NEXT (vpc);
6600
6601   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6602 {
6603   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6604   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6605 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6606   int UNUSED written = 0;
6607   IADDR UNUSED pc = abuf->addr;
6608   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6609
6610 {
6611   SI tmp_tmpopd;
6612   SI tmp_tmpops;
6613   BI tmp_carry;
6614   SI tmp_newval;
6615   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6616   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6617   tmp_carry = CPU (h_cbit);
6618   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6619   {
6620     SI opval = tmp_newval;
6621     SET_H_GR (FLD (f_operand2), opval);
6622     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6623   }
6624 {
6625   {
6626     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6627     CPU (h_cbit) = opval;
6628     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6629   }
6630   {
6631     BI opval = LTSI (tmp_newval, 0);
6632     CPU (h_nbit) = opval;
6633     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6634   }
6635   {
6636     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6637     CPU (h_zbit) = opval;
6638     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6639   }
6640   {
6641     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6642     CPU (h_vbit) = opval;
6643     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6644   }
6645 {
6646   {
6647     BI opval = 0;
6648     CPU (h_xbit) = opval;
6649     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6650   }
6651   {
6652     BI opval = 0;
6653     SET_H_INSN_PREFIXED_P (opval);
6654     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6655   }
6656 }
6657 }
6658 }
6659
6660 #undef FLD
6661 }
6662   NEXT (vpc);
6663
6664   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6665 {
6666   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6667   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6668 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6669   int UNUSED written = 0;
6670   IADDR UNUSED pc = abuf->addr;
6671   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6672
6673 {
6674   SI tmp_tmpopd;
6675   SI tmp_tmpops;
6676   BI tmp_carry;
6677   SI tmp_newval;
6678   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6679   QI tmp_tmp_mem;
6680   BI tmp_postinc;
6681   tmp_postinc = FLD (f_memmode);
6682 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6683 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6684 ; if (NEBI (tmp_postinc, 0)) {
6685 {
6686 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6687   tmp_addr = ADDSI (tmp_addr, 1);
6688 }
6689   {
6690     SI opval = tmp_addr;
6691     SET_H_GR (FLD (f_operand1), opval);
6692     written |= (1 << 11);
6693     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6694   }
6695 }
6696 }
6697 ; tmp_tmp_mem; }));
6698   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6699   tmp_carry = CPU (h_cbit);
6700   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6701   {
6702     SI opval = tmp_newval;
6703     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6704     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6705   }
6706 {
6707   {
6708     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6709     CPU (h_cbit) = opval;
6710     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6711   }
6712   {
6713     BI opval = LTSI (tmp_newval, 0);
6714     CPU (h_nbit) = opval;
6715     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6716   }
6717   {
6718     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6719     CPU (h_zbit) = opval;
6720     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6721   }
6722   {
6723     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6724     CPU (h_vbit) = opval;
6725     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6726   }
6727 {
6728   {
6729     BI opval = 0;
6730     CPU (h_xbit) = opval;
6731     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6732   }
6733   {
6734     BI opval = 0;
6735     SET_H_INSN_PREFIXED_P (opval);
6736     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6737   }
6738 }
6739 }
6740 }
6741
6742   abuf->written = written;
6743 #undef FLD
6744 }
6745   NEXT (vpc);
6746
6747   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6748 {
6749   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6750   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6751 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6752   int UNUSED written = 0;
6753   IADDR UNUSED pc = abuf->addr;
6754   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6755
6756 {
6757   SI tmp_tmpopd;
6758   SI tmp_tmpops;
6759   BI tmp_carry;
6760   SI tmp_newval;
6761   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6762   HI tmp_tmp_mem;
6763   BI tmp_postinc;
6764   tmp_postinc = FLD (f_memmode);
6765 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
6766 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6767 ; if (NEBI (tmp_postinc, 0)) {
6768 {
6769 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6770   tmp_addr = ADDSI (tmp_addr, 2);
6771 }
6772   {
6773     SI opval = tmp_addr;
6774     SET_H_GR (FLD (f_operand1), opval);
6775     written |= (1 << 11);
6776     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6777   }
6778 }
6779 }
6780 ; tmp_tmp_mem; }));
6781   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6782   tmp_carry = CPU (h_cbit);
6783   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6784   {
6785     SI opval = tmp_newval;
6786     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6787     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6788   }
6789 {
6790   {
6791     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6792     CPU (h_cbit) = opval;
6793     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6794   }
6795   {
6796     BI opval = LTSI (tmp_newval, 0);
6797     CPU (h_nbit) = opval;
6798     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6799   }
6800   {
6801     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6802     CPU (h_zbit) = opval;
6803     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6804   }
6805   {
6806     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6807     CPU (h_vbit) = opval;
6808     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6809   }
6810 {
6811   {
6812     BI opval = 0;
6813     CPU (h_xbit) = opval;
6814     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6815   }
6816   {
6817     BI opval = 0;
6818     SET_H_INSN_PREFIXED_P (opval);
6819     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6820   }
6821 }
6822 }
6823 }
6824
6825   abuf->written = written;
6826 #undef FLD
6827 }
6828   NEXT (vpc);
6829
6830   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
6831 {
6832   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6833   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6834 #define FLD(f) abuf->fields.sfmt_addcbr.f
6835   int UNUSED written = 0;
6836   IADDR UNUSED pc = abuf->addr;
6837   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6838
6839 {
6840   SI tmp_tmpopd;
6841   SI tmp_tmpops;
6842   BI tmp_carry;
6843   SI tmp_newval;
6844   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6845   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6846   tmp_carry = CPU (h_cbit);
6847   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6848   {
6849     SI opval = tmp_newval;
6850     SET_H_GR (FLD (f_operand2), opval);
6851     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6852   }
6853 {
6854   {
6855     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6856     CPU (h_cbit) = opval;
6857     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6858   }
6859   {
6860     BI opval = LTSI (tmp_newval, 0);
6861     CPU (h_nbit) = opval;
6862     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6863   }
6864   {
6865     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6866     CPU (h_zbit) = opval;
6867     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6868   }
6869   {
6870     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6871     CPU (h_vbit) = opval;
6872     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6873   }
6874 {
6875   {
6876     BI opval = 0;
6877     CPU (h_xbit) = opval;
6878     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6879   }
6880   {
6881     BI opval = 0;
6882     SET_H_INSN_PREFIXED_P (opval);
6883     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6884   }
6885 }
6886 }
6887 }
6888
6889 #undef FLD
6890 }
6891   NEXT (vpc);
6892
6893   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
6894 {
6895   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6896   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6897 #define FLD(f) abuf->fields.sfmt_addcwr.f
6898   int UNUSED written = 0;
6899   IADDR UNUSED pc = abuf->addr;
6900   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6901
6902 {
6903   SI tmp_tmpopd;
6904   SI tmp_tmpops;
6905   BI tmp_carry;
6906   SI tmp_newval;
6907   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6908   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6909   tmp_carry = CPU (h_cbit);
6910   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6911   {
6912     SI opval = tmp_newval;
6913     SET_H_GR (FLD (f_operand2), opval);
6914     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6915   }
6916 {
6917   {
6918     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6919     CPU (h_cbit) = opval;
6920     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6921   }
6922   {
6923     BI opval = LTSI (tmp_newval, 0);
6924     CPU (h_nbit) = opval;
6925     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6926   }
6927   {
6928     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6929     CPU (h_zbit) = opval;
6930     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6931   }
6932   {
6933     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6934     CPU (h_vbit) = opval;
6935     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6936   }
6937 {
6938   {
6939     BI opval = 0;
6940     CPU (h_xbit) = opval;
6941     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6942   }
6943   {
6944     BI opval = 0;
6945     SET_H_INSN_PREFIXED_P (opval);
6946     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6947   }
6948 }
6949 }
6950 }
6951
6952 #undef FLD
6953 }
6954   NEXT (vpc);
6955
6956   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
6957 {
6958   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6959   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6960 #define FLD(f) abuf->fields.sfmt_add_b_r.f
6961   int UNUSED written = 0;
6962   IADDR UNUSED pc = abuf->addr;
6963   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6964
6965 {
6966   QI tmp_tmpopd;
6967   QI tmp_tmpops;
6968   BI tmp_carry;
6969   QI tmp_newval;
6970   tmp_tmpops = GET_H_GR (FLD (f_operand1));
6971   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6972   tmp_carry = CPU (h_cbit);
6973   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6974 {
6975   SI tmp_oldregval;
6976   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
6977   {
6978     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6979     SET_H_GR (FLD (f_operand2), opval);
6980     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6981   }
6982 }
6983 {
6984   {
6985     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
6986     CPU (h_cbit) = opval;
6987     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6988   }
6989   {
6990     BI opval = LTQI (tmp_newval, 0);
6991     CPU (h_nbit) = opval;
6992     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6993   }
6994   {
6995     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6996     CPU (h_zbit) = opval;
6997     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6998   }
6999   {
7000     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7001     CPU (h_vbit) = opval;
7002     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7003   }
7004 {
7005   {
7006     BI opval = 0;
7007     CPU (h_xbit) = opval;
7008     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7009   }
7010   {
7011     BI opval = 0;
7012     SET_H_INSN_PREFIXED_P (opval);
7013     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7014   }
7015 }
7016 }
7017 }
7018
7019 #undef FLD
7020 }
7021   NEXT (vpc);
7022
7023   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
7024 {
7025   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7026   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7027 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7028   int UNUSED written = 0;
7029   IADDR UNUSED pc = abuf->addr;
7030   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7031
7032 {
7033   HI tmp_tmpopd;
7034   HI tmp_tmpops;
7035   BI tmp_carry;
7036   HI tmp_newval;
7037   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7038   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7039   tmp_carry = CPU (h_cbit);
7040   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7041 {
7042   SI tmp_oldregval;
7043   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7044   {
7045     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7046     SET_H_GR (FLD (f_operand2), opval);
7047     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7048   }
7049 }
7050 {
7051   {
7052     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7053     CPU (h_cbit) = opval;
7054     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7055   }
7056   {
7057     BI opval = LTHI (tmp_newval, 0);
7058     CPU (h_nbit) = opval;
7059     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7060   }
7061   {
7062     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7063     CPU (h_zbit) = opval;
7064     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7065   }
7066   {
7067     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7068     CPU (h_vbit) = opval;
7069     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7070   }
7071 {
7072   {
7073     BI opval = 0;
7074     CPU (h_xbit) = opval;
7075     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7076   }
7077   {
7078     BI opval = 0;
7079     SET_H_INSN_PREFIXED_P (opval);
7080     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7081   }
7082 }
7083 }
7084 }
7085
7086 #undef FLD
7087 }
7088   NEXT (vpc);
7089
7090   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7091 {
7092   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7093   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7094 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7095   int UNUSED written = 0;
7096   IADDR UNUSED pc = abuf->addr;
7097   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7098
7099 {
7100   SI tmp_tmpopd;
7101   SI tmp_tmpops;
7102   BI tmp_carry;
7103   SI tmp_newval;
7104   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7105   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7106   tmp_carry = CPU (h_cbit);
7107   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7108   {
7109     SI opval = tmp_newval;
7110     SET_H_GR (FLD (f_operand2), opval);
7111     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7112   }
7113 {
7114   {
7115     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7116     CPU (h_cbit) = opval;
7117     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7118   }
7119   {
7120     BI opval = LTSI (tmp_newval, 0);
7121     CPU (h_nbit) = opval;
7122     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7123   }
7124   {
7125     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7126     CPU (h_zbit) = opval;
7127     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7128   }
7129   {
7130     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7131     CPU (h_vbit) = opval;
7132     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7133   }
7134 {
7135   {
7136     BI opval = 0;
7137     CPU (h_xbit) = opval;
7138     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7139   }
7140   {
7141     BI opval = 0;
7142     SET_H_INSN_PREFIXED_P (opval);
7143     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7144   }
7145 }
7146 }
7147 }
7148
7149 #undef FLD
7150 }
7151   NEXT (vpc);
7152
7153   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7154 {
7155   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7156   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7157 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7158   int UNUSED written = 0;
7159   IADDR UNUSED pc = abuf->addr;
7160   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7161
7162 {
7163   QI tmp_tmpopd;
7164   QI tmp_tmpops;
7165   BI tmp_carry;
7166   QI tmp_newval;
7167   tmp_tmpops = ({   SI tmp_addr;
7168   QI tmp_tmp_mem;
7169   BI tmp_postinc;
7170   tmp_postinc = FLD (f_memmode);
7171 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7172 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7173 ; if (NEBI (tmp_postinc, 0)) {
7174 {
7175 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7176   tmp_addr = ADDSI (tmp_addr, 1);
7177 }
7178   {
7179     SI opval = tmp_addr;
7180     SET_H_GR (FLD (f_operand1), opval);
7181     written |= (1 << 12);
7182     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7183   }
7184 }
7185 }
7186 ; tmp_tmp_mem; });
7187   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7188   tmp_carry = CPU (h_cbit);
7189   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7190 {
7191   SI tmp_oldregval;
7192   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7193   {
7194     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7195     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7196     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7197   }
7198 }
7199 {
7200   {
7201     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7202     CPU (h_cbit) = opval;
7203     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7204   }
7205   {
7206     BI opval = LTQI (tmp_newval, 0);
7207     CPU (h_nbit) = opval;
7208     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7209   }
7210   {
7211     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7212     CPU (h_zbit) = opval;
7213     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7214   }
7215   {
7216     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7217     CPU (h_vbit) = opval;
7218     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7219   }
7220 {
7221   {
7222     BI opval = 0;
7223     CPU (h_xbit) = opval;
7224     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7225   }
7226   {
7227     BI opval = 0;
7228     SET_H_INSN_PREFIXED_P (opval);
7229     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7230   }
7231 }
7232 }
7233 }
7234
7235   abuf->written = written;
7236 #undef FLD
7237 }
7238   NEXT (vpc);
7239
7240   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7241 {
7242   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7243   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7244 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7245   int UNUSED written = 0;
7246   IADDR UNUSED pc = abuf->addr;
7247   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7248
7249 {
7250   HI tmp_tmpopd;
7251   HI tmp_tmpops;
7252   BI tmp_carry;
7253   HI tmp_newval;
7254   tmp_tmpops = ({   SI tmp_addr;
7255   HI tmp_tmp_mem;
7256   BI tmp_postinc;
7257   tmp_postinc = FLD (f_memmode);
7258 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7259 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7260 ; if (NEBI (tmp_postinc, 0)) {
7261 {
7262 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7263   tmp_addr = ADDSI (tmp_addr, 2);
7264 }
7265   {
7266     SI opval = tmp_addr;
7267     SET_H_GR (FLD (f_operand1), opval);
7268     written |= (1 << 12);
7269     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7270   }
7271 }
7272 }
7273 ; tmp_tmp_mem; });
7274   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7275   tmp_carry = CPU (h_cbit);
7276   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7277 {
7278   SI tmp_oldregval;
7279   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7280   {
7281     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7282     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7283     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7284   }
7285 }
7286 {
7287   {
7288     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7289     CPU (h_cbit) = opval;
7290     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7291   }
7292   {
7293     BI opval = LTHI (tmp_newval, 0);
7294     CPU (h_nbit) = opval;
7295     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7296   }
7297   {
7298     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7299     CPU (h_zbit) = opval;
7300     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7301   }
7302   {
7303     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7304     CPU (h_vbit) = opval;
7305     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7306   }
7307 {
7308   {
7309     BI opval = 0;
7310     CPU (h_xbit) = opval;
7311     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7312   }
7313   {
7314     BI opval = 0;
7315     SET_H_INSN_PREFIXED_P (opval);
7316     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7317   }
7318 }
7319 }
7320 }
7321
7322   abuf->written = written;
7323 #undef FLD
7324 }
7325   NEXT (vpc);
7326
7327   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7328 {
7329   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7330   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7331 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7332   int UNUSED written = 0;
7333   IADDR UNUSED pc = abuf->addr;
7334   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7335
7336 {
7337   SI tmp_tmpopd;
7338   SI tmp_tmpops;
7339   BI tmp_carry;
7340   SI tmp_newval;
7341   tmp_tmpops = ({   SI tmp_addr;
7342   SI tmp_tmp_mem;
7343   BI tmp_postinc;
7344   tmp_postinc = FLD (f_memmode);
7345 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7346 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7347 ; if (NEBI (tmp_postinc, 0)) {
7348 {
7349 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7350   tmp_addr = ADDSI (tmp_addr, 4);
7351 }
7352   {
7353     SI opval = tmp_addr;
7354     SET_H_GR (FLD (f_operand1), opval);
7355     written |= (1 << 11);
7356     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7357   }
7358 }
7359 }
7360 ; tmp_tmp_mem; });
7361   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7362   tmp_carry = CPU (h_cbit);
7363   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7364   {
7365     SI opval = tmp_newval;
7366     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7367     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7368   }
7369 {
7370   {
7371     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7372     CPU (h_cbit) = opval;
7373     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7374   }
7375   {
7376     BI opval = LTSI (tmp_newval, 0);
7377     CPU (h_nbit) = opval;
7378     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7379   }
7380   {
7381     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7382     CPU (h_zbit) = opval;
7383     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7384   }
7385   {
7386     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7387     CPU (h_vbit) = opval;
7388     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7389   }
7390 {
7391   {
7392     BI opval = 0;
7393     CPU (h_xbit) = opval;
7394     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7395   }
7396   {
7397     BI opval = 0;
7398     SET_H_INSN_PREFIXED_P (opval);
7399     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7400   }
7401 }
7402 }
7403 }
7404
7405   abuf->written = written;
7406 #undef FLD
7407 }
7408   NEXT (vpc);
7409
7410   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7411 {
7412   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7413   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7414 #define FLD(f) abuf->fields.sfmt_addcbr.f
7415   int UNUSED written = 0;
7416   IADDR UNUSED pc = abuf->addr;
7417   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7418
7419 {
7420   QI tmp_tmpopd;
7421   QI tmp_tmpops;
7422   BI tmp_carry;
7423   QI tmp_newval;
7424   tmp_tmpops = FLD (f_indir_pc__byte);
7425   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7426   tmp_carry = CPU (h_cbit);
7427   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7428 {
7429   SI tmp_oldregval;
7430   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7431   {
7432     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7433     SET_H_GR (FLD (f_operand2), opval);
7434     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7435   }
7436 }
7437 {
7438   {
7439     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7440     CPU (h_cbit) = opval;
7441     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7442   }
7443   {
7444     BI opval = LTQI (tmp_newval, 0);
7445     CPU (h_nbit) = opval;
7446     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7447   }
7448   {
7449     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7450     CPU (h_zbit) = opval;
7451     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7452   }
7453   {
7454     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7455     CPU (h_vbit) = opval;
7456     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7457   }
7458 {
7459   {
7460     BI opval = 0;
7461     CPU (h_xbit) = opval;
7462     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7463   }
7464   {
7465     BI opval = 0;
7466     SET_H_INSN_PREFIXED_P (opval);
7467     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7468   }
7469 }
7470 }
7471 }
7472
7473 #undef FLD
7474 }
7475   NEXT (vpc);
7476
7477   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7478 {
7479   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7480   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7481 #define FLD(f) abuf->fields.sfmt_addcwr.f
7482   int UNUSED written = 0;
7483   IADDR UNUSED pc = abuf->addr;
7484   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7485
7486 {
7487   HI tmp_tmpopd;
7488   HI tmp_tmpops;
7489   BI tmp_carry;
7490   HI tmp_newval;
7491   tmp_tmpops = FLD (f_indir_pc__word);
7492   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7493   tmp_carry = CPU (h_cbit);
7494   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7495 {
7496   SI tmp_oldregval;
7497   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
7498   {
7499     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7500     SET_H_GR (FLD (f_operand2), opval);
7501     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7502   }
7503 }
7504 {
7505   {
7506     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7507     CPU (h_cbit) = opval;
7508     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7509   }
7510   {
7511     BI opval = LTHI (tmp_newval, 0);
7512     CPU (h_nbit) = opval;
7513     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7514   }
7515   {
7516     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7517     CPU (h_zbit) = opval;
7518     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7519   }
7520   {
7521     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7522     CPU (h_vbit) = opval;
7523     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7524   }
7525 {
7526   {
7527     BI opval = 0;
7528     CPU (h_xbit) = opval;
7529     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7530   }
7531   {
7532     BI opval = 0;
7533     SET_H_INSN_PREFIXED_P (opval);
7534     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7535   }
7536 }
7537 }
7538 }
7539
7540 #undef FLD
7541 }
7542   NEXT (vpc);
7543
7544   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7545 {
7546   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7547   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7548 #define FLD(f) abuf->fields.sfmt_addcdr.f
7549   int UNUSED written = 0;
7550   IADDR UNUSED pc = abuf->addr;
7551   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7552
7553 {
7554   SI tmp_tmpopd;
7555   SI tmp_tmpops;
7556   BI tmp_carry;
7557   SI tmp_newval;
7558   tmp_tmpops = FLD (f_indir_pc__dword);
7559   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7560   tmp_carry = CPU (h_cbit);
7561   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7562   {
7563     SI opval = tmp_newval;
7564     SET_H_GR (FLD (f_operand2), opval);
7565     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7566   }
7567 {
7568   {
7569     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7570     CPU (h_cbit) = opval;
7571     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7572   }
7573   {
7574     BI opval = LTSI (tmp_newval, 0);
7575     CPU (h_nbit) = opval;
7576     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7577   }
7578   {
7579     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7580     CPU (h_zbit) = opval;
7581     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7582   }
7583   {
7584     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7585     CPU (h_vbit) = opval;
7586     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7587   }
7588 {
7589   {
7590     BI opval = 0;
7591     CPU (h_xbit) = opval;
7592     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7593   }
7594   {
7595     BI opval = 0;
7596     SET_H_INSN_PREFIXED_P (opval);
7597     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7598   }
7599 }
7600 }
7601 }
7602
7603 #undef FLD
7604 }
7605   NEXT (vpc);
7606
7607   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7608 {
7609   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7610   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7611 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7612   int UNUSED written = 0;
7613   IADDR UNUSED pc = abuf->addr;
7614   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7615
7616 {
7617   SI tmp_tmpopd;
7618   SI tmp_tmpops;
7619   BI tmp_carry;
7620   SI tmp_newval;
7621   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7622   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7623   tmp_carry = CPU (h_cbit);
7624   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7625   {
7626     SI opval = tmp_newval;
7627     SET_H_GR (FLD (f_operand2), opval);
7628     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7629   }
7630 {
7631   {
7632     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7633     CPU (h_cbit) = opval;
7634     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7635   }
7636   {
7637     BI opval = LTSI (tmp_newval, 0);
7638     CPU (h_nbit) = opval;
7639     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7640   }
7641   {
7642     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7643     CPU (h_zbit) = opval;
7644     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7645   }
7646   {
7647     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7648     CPU (h_vbit) = opval;
7649     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7650   }
7651 {
7652   {
7653     BI opval = 0;
7654     CPU (h_xbit) = opval;
7655     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7656   }
7657   {
7658     BI opval = 0;
7659     SET_H_INSN_PREFIXED_P (opval);
7660     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7661   }
7662 }
7663 }
7664 }
7665
7666 #undef FLD
7667 }
7668   NEXT (vpc);
7669
7670   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7671 {
7672   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7673   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7674 #define FLD(f) abuf->fields.sfmt_add_b_r.f
7675   int UNUSED written = 0;
7676   IADDR UNUSED pc = abuf->addr;
7677   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7678
7679 {
7680   SI tmp_tmpopd;
7681   SI tmp_tmpops;
7682   BI tmp_carry;
7683   SI tmp_newval;
7684   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7685   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7686   tmp_carry = CPU (h_cbit);
7687   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7688   {
7689     SI opval = tmp_newval;
7690     SET_H_GR (FLD (f_operand2), opval);
7691     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7692   }
7693 {
7694   {
7695     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7696     CPU (h_cbit) = opval;
7697     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7698   }
7699   {
7700     BI opval = LTSI (tmp_newval, 0);
7701     CPU (h_nbit) = opval;
7702     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7703   }
7704   {
7705     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7706     CPU (h_zbit) = opval;
7707     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7708   }
7709   {
7710     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7711     CPU (h_vbit) = opval;
7712     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7713   }
7714 {
7715   {
7716     BI opval = 0;
7717     CPU (h_xbit) = opval;
7718     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7719   }
7720   {
7721     BI opval = 0;
7722     SET_H_INSN_PREFIXED_P (opval);
7723     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7724   }
7725 }
7726 }
7727 }
7728
7729 #undef FLD
7730 }
7731   NEXT (vpc);
7732
7733   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7734 {
7735   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7736   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7737 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7738   int UNUSED written = 0;
7739   IADDR UNUSED pc = abuf->addr;
7740   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7741
7742 {
7743   SI tmp_tmpopd;
7744   SI tmp_tmpops;
7745   BI tmp_carry;
7746   SI tmp_newval;
7747   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7748   QI tmp_tmp_mem;
7749   BI tmp_postinc;
7750   tmp_postinc = FLD (f_memmode);
7751 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7752 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7753 ; if (NEBI (tmp_postinc, 0)) {
7754 {
7755 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7756   tmp_addr = ADDSI (tmp_addr, 1);
7757 }
7758   {
7759     SI opval = tmp_addr;
7760     SET_H_GR (FLD (f_operand1), opval);
7761     written |= (1 << 11);
7762     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7763   }
7764 }
7765 }
7766 ; tmp_tmp_mem; }));
7767   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7768   tmp_carry = CPU (h_cbit);
7769   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7770   {
7771     SI opval = tmp_newval;
7772     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7773     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7774   }
7775 {
7776   {
7777     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7778     CPU (h_cbit) = opval;
7779     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7780   }
7781   {
7782     BI opval = LTSI (tmp_newval, 0);
7783     CPU (h_nbit) = opval;
7784     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7785   }
7786   {
7787     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7788     CPU (h_zbit) = opval;
7789     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7790   }
7791   {
7792     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7793     CPU (h_vbit) = opval;
7794     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7795   }
7796 {
7797   {
7798     BI opval = 0;
7799     CPU (h_xbit) = opval;
7800     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7801   }
7802   {
7803     BI opval = 0;
7804     SET_H_INSN_PREFIXED_P (opval);
7805     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7806   }
7807 }
7808 }
7809 }
7810
7811   abuf->written = written;
7812 #undef FLD
7813 }
7814   NEXT (vpc);
7815
7816   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
7817 {
7818   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7819   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7820 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7821   int UNUSED written = 0;
7822   IADDR UNUSED pc = abuf->addr;
7823   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7824
7825 {
7826   SI tmp_tmpopd;
7827   SI tmp_tmpops;
7828   BI tmp_carry;
7829   SI tmp_newval;
7830   tmp_tmpops = EXTHISI (({   SI tmp_addr;
7831   HI tmp_tmp_mem;
7832   BI tmp_postinc;
7833   tmp_postinc = FLD (f_memmode);
7834 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
7835 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7836 ; if (NEBI (tmp_postinc, 0)) {
7837 {
7838 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7839   tmp_addr = ADDSI (tmp_addr, 2);
7840 }
7841   {
7842     SI opval = tmp_addr;
7843     SET_H_GR (FLD (f_operand1), opval);
7844     written |= (1 << 11);
7845     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7846   }
7847 }
7848 }
7849 ; tmp_tmp_mem; }));
7850   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7851   tmp_carry = CPU (h_cbit);
7852   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7853   {
7854     SI opval = tmp_newval;
7855     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7856     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7857   }
7858 {
7859   {
7860     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7861     CPU (h_cbit) = opval;
7862     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7863   }
7864   {
7865     BI opval = LTSI (tmp_newval, 0);
7866     CPU (h_nbit) = opval;
7867     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7868   }
7869   {
7870     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7871     CPU (h_zbit) = opval;
7872     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7873   }
7874   {
7875     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7876     CPU (h_vbit) = opval;
7877     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7878   }
7879 {
7880   {
7881     BI opval = 0;
7882     CPU (h_xbit) = opval;
7883     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7884   }
7885   {
7886     BI opval = 0;
7887     SET_H_INSN_PREFIXED_P (opval);
7888     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7889   }
7890 }
7891 }
7892 }
7893
7894   abuf->written = written;
7895 #undef FLD
7896 }
7897   NEXT (vpc);
7898
7899   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
7900 {
7901   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7902   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7903 #define FLD(f) abuf->fields.sfmt_addcbr.f
7904   int UNUSED written = 0;
7905   IADDR UNUSED pc = abuf->addr;
7906   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7907
7908 {
7909   SI tmp_tmpopd;
7910   SI tmp_tmpops;
7911   BI tmp_carry;
7912   SI tmp_newval;
7913   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7914   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7915   tmp_carry = CPU (h_cbit);
7916   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7917   {
7918     SI opval = tmp_newval;
7919     SET_H_GR (FLD (f_operand2), opval);
7920     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7921   }
7922 {
7923   {
7924     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7925     CPU (h_cbit) = opval;
7926     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7927   }
7928   {
7929     BI opval = LTSI (tmp_newval, 0);
7930     CPU (h_nbit) = opval;
7931     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7932   }
7933   {
7934     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7935     CPU (h_zbit) = opval;
7936     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7937   }
7938   {
7939     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7940     CPU (h_vbit) = opval;
7941     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7942   }
7943 {
7944   {
7945     BI opval = 0;
7946     CPU (h_xbit) = opval;
7947     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7948   }
7949   {
7950     BI opval = 0;
7951     SET_H_INSN_PREFIXED_P (opval);
7952     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7953   }
7954 }
7955 }
7956 }
7957
7958 #undef FLD
7959 }
7960   NEXT (vpc);
7961
7962   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
7963 {
7964   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7965   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7966 #define FLD(f) abuf->fields.sfmt_addcwr.f
7967   int UNUSED written = 0;
7968   IADDR UNUSED pc = abuf->addr;
7969   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7970
7971 {
7972   SI tmp_tmpopd;
7973   SI tmp_tmpops;
7974   BI tmp_carry;
7975   SI tmp_newval;
7976   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7977   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7978   tmp_carry = CPU (h_cbit);
7979   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7980   {
7981     SI opval = tmp_newval;
7982     SET_H_GR (FLD (f_operand2), opval);
7983     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7984   }
7985 {
7986   {
7987     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7988     CPU (h_cbit) = opval;
7989     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7990   }
7991   {
7992     BI opval = LTSI (tmp_newval, 0);
7993     CPU (h_nbit) = opval;
7994     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7995   }
7996   {
7997     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7998     CPU (h_zbit) = opval;
7999     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8000   }
8001   {
8002     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8003     CPU (h_vbit) = opval;
8004     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8005   }
8006 {
8007   {
8008     BI opval = 0;
8009     CPU (h_xbit) = opval;
8010     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8011   }
8012   {
8013     BI opval = 0;
8014     SET_H_INSN_PREFIXED_P (opval);
8015     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8016   }
8017 }
8018 }
8019 }
8020
8021 #undef FLD
8022 }
8023   NEXT (vpc);
8024
8025   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
8026 {
8027   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8028   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8029 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8030   int UNUSED written = 0;
8031   IADDR UNUSED pc = abuf->addr;
8032   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8033
8034 {
8035   SI tmp_tmpopd;
8036   SI tmp_tmpops;
8037   BI tmp_carry;
8038   SI tmp_newval;
8039   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8040   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8041   tmp_carry = CPU (h_cbit);
8042   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8043   {
8044     SI opval = tmp_newval;
8045     SET_H_GR (FLD (f_operand2), opval);
8046     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8047   }
8048 {
8049   {
8050     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8051     CPU (h_cbit) = opval;
8052     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8053   }
8054   {
8055     BI opval = LTSI (tmp_newval, 0);
8056     CPU (h_nbit) = opval;
8057     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8058   }
8059   {
8060     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8061     CPU (h_zbit) = opval;
8062     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8063   }
8064   {
8065     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8066     CPU (h_vbit) = opval;
8067     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8068   }
8069 {
8070   {
8071     BI opval = 0;
8072     CPU (h_xbit) = opval;
8073     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8074   }
8075   {
8076     BI opval = 0;
8077     SET_H_INSN_PREFIXED_P (opval);
8078     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8079   }
8080 }
8081 }
8082 }
8083
8084 #undef FLD
8085 }
8086   NEXT (vpc);
8087
8088   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8089 {
8090   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8091   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8092 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8093   int UNUSED written = 0;
8094   IADDR UNUSED pc = abuf->addr;
8095   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8096
8097 {
8098   SI tmp_tmpopd;
8099   SI tmp_tmpops;
8100   BI tmp_carry;
8101   SI tmp_newval;
8102   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8103   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8104   tmp_carry = CPU (h_cbit);
8105   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8106   {
8107     SI opval = tmp_newval;
8108     SET_H_GR (FLD (f_operand2), opval);
8109     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8110   }
8111 {
8112   {
8113     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8114     CPU (h_cbit) = opval;
8115     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8116   }
8117   {
8118     BI opval = LTSI (tmp_newval, 0);
8119     CPU (h_nbit) = opval;
8120     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8121   }
8122   {
8123     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8124     CPU (h_zbit) = opval;
8125     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8126   }
8127   {
8128     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8129     CPU (h_vbit) = opval;
8130     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8131   }
8132 {
8133   {
8134     BI opval = 0;
8135     CPU (h_xbit) = opval;
8136     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8137   }
8138   {
8139     BI opval = 0;
8140     SET_H_INSN_PREFIXED_P (opval);
8141     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8142   }
8143 }
8144 }
8145 }
8146
8147 #undef FLD
8148 }
8149   NEXT (vpc);
8150
8151   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8152 {
8153   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8154   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8155 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8156   int UNUSED written = 0;
8157   IADDR UNUSED pc = abuf->addr;
8158   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8159
8160 {
8161   SI tmp_tmpopd;
8162   SI tmp_tmpops;
8163   BI tmp_carry;
8164   SI tmp_newval;
8165   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8166   QI tmp_tmp_mem;
8167   BI tmp_postinc;
8168   tmp_postinc = FLD (f_memmode);
8169 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8170 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8171 ; if (NEBI (tmp_postinc, 0)) {
8172 {
8173 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8174   tmp_addr = ADDSI (tmp_addr, 1);
8175 }
8176   {
8177     SI opval = tmp_addr;
8178     SET_H_GR (FLD (f_operand1), opval);
8179     written |= (1 << 11);
8180     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8181   }
8182 }
8183 }
8184 ; tmp_tmp_mem; }));
8185   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8186   tmp_carry = CPU (h_cbit);
8187   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8188   {
8189     SI opval = tmp_newval;
8190     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8191     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8192   }
8193 {
8194   {
8195     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8196     CPU (h_cbit) = opval;
8197     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8198   }
8199   {
8200     BI opval = LTSI (tmp_newval, 0);
8201     CPU (h_nbit) = opval;
8202     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8203   }
8204   {
8205     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8206     CPU (h_zbit) = opval;
8207     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8208   }
8209   {
8210     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8211     CPU (h_vbit) = opval;
8212     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8213   }
8214 {
8215   {
8216     BI opval = 0;
8217     CPU (h_xbit) = opval;
8218     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8219   }
8220   {
8221     BI opval = 0;
8222     SET_H_INSN_PREFIXED_P (opval);
8223     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8224   }
8225 }
8226 }
8227 }
8228
8229   abuf->written = written;
8230 #undef FLD
8231 }
8232   NEXT (vpc);
8233
8234   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8235 {
8236   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8237   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8238 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8239   int UNUSED written = 0;
8240   IADDR UNUSED pc = abuf->addr;
8241   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8242
8243 {
8244   SI tmp_tmpopd;
8245   SI tmp_tmpops;
8246   BI tmp_carry;
8247   SI tmp_newval;
8248   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8249   HI tmp_tmp_mem;
8250   BI tmp_postinc;
8251   tmp_postinc = FLD (f_memmode);
8252 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8253 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8254 ; if (NEBI (tmp_postinc, 0)) {
8255 {
8256 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8257   tmp_addr = ADDSI (tmp_addr, 2);
8258 }
8259   {
8260     SI opval = tmp_addr;
8261     SET_H_GR (FLD (f_operand1), opval);
8262     written |= (1 << 11);
8263     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8264   }
8265 }
8266 }
8267 ; tmp_tmp_mem; }));
8268   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8269   tmp_carry = CPU (h_cbit);
8270   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8271   {
8272     SI opval = tmp_newval;
8273     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8274     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8275   }
8276 {
8277   {
8278     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8279     CPU (h_cbit) = opval;
8280     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8281   }
8282   {
8283     BI opval = LTSI (tmp_newval, 0);
8284     CPU (h_nbit) = opval;
8285     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8286   }
8287   {
8288     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8289     CPU (h_zbit) = opval;
8290     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8291   }
8292   {
8293     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8294     CPU (h_vbit) = opval;
8295     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8296   }
8297 {
8298   {
8299     BI opval = 0;
8300     CPU (h_xbit) = opval;
8301     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8302   }
8303   {
8304     BI opval = 0;
8305     SET_H_INSN_PREFIXED_P (opval);
8306     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8307   }
8308 }
8309 }
8310 }
8311
8312   abuf->written = written;
8313 #undef FLD
8314 }
8315   NEXT (vpc);
8316
8317   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8318 {
8319   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8320   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8321 #define FLD(f) abuf->fields.sfmt_addcbr.f
8322   int UNUSED written = 0;
8323   IADDR UNUSED pc = abuf->addr;
8324   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8325
8326 {
8327   SI tmp_tmpopd;
8328   SI tmp_tmpops;
8329   BI tmp_carry;
8330   SI tmp_newval;
8331   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8332   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8333   tmp_carry = CPU (h_cbit);
8334   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8335   {
8336     SI opval = tmp_newval;
8337     SET_H_GR (FLD (f_operand2), opval);
8338     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8339   }
8340 {
8341   {
8342     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8343     CPU (h_cbit) = opval;
8344     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8345   }
8346   {
8347     BI opval = LTSI (tmp_newval, 0);
8348     CPU (h_nbit) = opval;
8349     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8350   }
8351   {
8352     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8353     CPU (h_zbit) = opval;
8354     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8355   }
8356   {
8357     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8358     CPU (h_vbit) = opval;
8359     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8360   }
8361 {
8362   {
8363     BI opval = 0;
8364     CPU (h_xbit) = opval;
8365     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8366   }
8367   {
8368     BI opval = 0;
8369     SET_H_INSN_PREFIXED_P (opval);
8370     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8371   }
8372 }
8373 }
8374 }
8375
8376 #undef FLD
8377 }
8378   NEXT (vpc);
8379
8380   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8381 {
8382   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8383   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8384 #define FLD(f) abuf->fields.sfmt_addcwr.f
8385   int UNUSED written = 0;
8386   IADDR UNUSED pc = abuf->addr;
8387   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8388
8389 {
8390   SI tmp_tmpopd;
8391   SI tmp_tmpops;
8392   BI tmp_carry;
8393   SI tmp_newval;
8394   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8395   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8396   tmp_carry = CPU (h_cbit);
8397   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8398   {
8399     SI opval = tmp_newval;
8400     SET_H_GR (FLD (f_operand2), opval);
8401     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8402   }
8403 {
8404   {
8405     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8406     CPU (h_cbit) = opval;
8407     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8408   }
8409   {
8410     BI opval = LTSI (tmp_newval, 0);
8411     CPU (h_nbit) = opval;
8412     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8413   }
8414   {
8415     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8416     CPU (h_zbit) = opval;
8417     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8418   }
8419   {
8420     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8421     CPU (h_vbit) = opval;
8422     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8423   }
8424 {
8425   {
8426     BI opval = 0;
8427     CPU (h_xbit) = opval;
8428     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8429   }
8430   {
8431     BI opval = 0;
8432     SET_H_INSN_PREFIXED_P (opval);
8433     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8434   }
8435 }
8436 }
8437 }
8438
8439 #undef FLD
8440 }
8441   NEXT (vpc);
8442
8443   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8444 {
8445   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8446   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8447 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8448   int UNUSED written = 0;
8449   IADDR UNUSED pc = abuf->addr;
8450   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8451
8452 {
8453   {
8454     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8455     SET_H_GR (FLD (f_operand1), opval);
8456     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8457   }
8458 {
8459   {
8460     BI opval = 0;
8461     CPU (h_xbit) = opval;
8462     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8463   }
8464   {
8465     BI opval = 0;
8466     SET_H_INSN_PREFIXED_P (opval);
8467     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8468   }
8469 }
8470 }
8471
8472 #undef FLD
8473 }
8474   NEXT (vpc);
8475
8476   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8477 {
8478   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8479   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8480 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8481   int UNUSED written = 0;
8482   IADDR UNUSED pc = abuf->addr;
8483   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8484
8485 {
8486   {
8487     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8488     SET_H_GR (FLD (f_operand1), opval);
8489     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8490   }
8491 {
8492   {
8493     BI opval = 0;
8494     CPU (h_xbit) = opval;
8495     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8496   }
8497   {
8498     BI opval = 0;
8499     SET_H_INSN_PREFIXED_P (opval);
8500     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8501   }
8502 }
8503 }
8504
8505 #undef FLD
8506 }
8507   NEXT (vpc);
8508
8509   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8510 {
8511   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8512   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8513 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8514   int UNUSED written = 0;
8515   IADDR UNUSED pc = abuf->addr;
8516   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8517
8518 {
8519   {
8520     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
8521     SET_H_GR (FLD (f_operand1), opval);
8522     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8523   }
8524 {
8525   {
8526     BI opval = 0;
8527     CPU (h_xbit) = opval;
8528     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8529   }
8530   {
8531     BI opval = 0;
8532     SET_H_INSN_PREFIXED_P (opval);
8533     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8534   }
8535 }
8536 }
8537
8538 #undef FLD
8539 }
8540   NEXT (vpc);
8541
8542   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
8543 {
8544   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8545   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8546 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8547   int UNUSED written = 0;
8548   IADDR UNUSED pc = abuf->addr;
8549   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8550
8551 {
8552   QI tmp_tmpopd;
8553   QI tmp_tmpops;
8554   BI tmp_carry;
8555   QI tmp_newval;
8556   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8557   tmp_tmpopd = 0;
8558   tmp_carry = CPU (h_cbit);
8559   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8560 {
8561   SI tmp_oldregval;
8562   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8563   {
8564     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
8565     SET_H_GR (FLD (f_operand2), opval);
8566     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8567   }
8568 }
8569 {
8570   {
8571     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8572     CPU (h_cbit) = opval;
8573     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8574   }
8575   {
8576     BI opval = LTQI (tmp_newval, 0);
8577     CPU (h_nbit) = opval;
8578     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8579   }
8580   {
8581     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8582     CPU (h_zbit) = opval;
8583     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8584   }
8585   {
8586     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8587     CPU (h_vbit) = opval;
8588     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8589   }
8590 {
8591   {
8592     BI opval = 0;
8593     CPU (h_xbit) = opval;
8594     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8595   }
8596   {
8597     BI opval = 0;
8598     SET_H_INSN_PREFIXED_P (opval);
8599     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8600   }
8601 }
8602 }
8603 }
8604
8605 #undef FLD
8606 }
8607   NEXT (vpc);
8608
8609   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
8610 {
8611   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8612   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8613 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8614   int UNUSED written = 0;
8615   IADDR UNUSED pc = abuf->addr;
8616   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8617
8618 {
8619   HI tmp_tmpopd;
8620   HI tmp_tmpops;
8621   BI tmp_carry;
8622   HI tmp_newval;
8623   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8624   tmp_tmpopd = 0;
8625   tmp_carry = CPU (h_cbit);
8626   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8627 {
8628   SI tmp_oldregval;
8629   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
8630   {
8631     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
8632     SET_H_GR (FLD (f_operand2), opval);
8633     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8634   }
8635 }
8636 {
8637   {
8638     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8639     CPU (h_cbit) = opval;
8640     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8641   }
8642   {
8643     BI opval = LTHI (tmp_newval, 0);
8644     CPU (h_nbit) = opval;
8645     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8646   }
8647   {
8648     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8649     CPU (h_zbit) = opval;
8650     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8651   }
8652   {
8653     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8654     CPU (h_vbit) = opval;
8655     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8656   }
8657 {
8658   {
8659     BI opval = 0;
8660     CPU (h_xbit) = opval;
8661     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8662   }
8663   {
8664     BI opval = 0;
8665     SET_H_INSN_PREFIXED_P (opval);
8666     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8667   }
8668 }
8669 }
8670 }
8671
8672 #undef FLD
8673 }
8674   NEXT (vpc);
8675
8676   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
8677 {
8678   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8679   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8680 #define FLD(f) abuf->fields.sfmt_add_b_r.f
8681   int UNUSED written = 0;
8682   IADDR UNUSED pc = abuf->addr;
8683   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8684
8685 {
8686   SI tmp_tmpopd;
8687   SI tmp_tmpops;
8688   BI tmp_carry;
8689   SI tmp_newval;
8690   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8691   tmp_tmpopd = 0;
8692   tmp_carry = CPU (h_cbit);
8693   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8694   {
8695     SI opval = tmp_newval;
8696     SET_H_GR (FLD (f_operand2), opval);
8697     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8698   }
8699 {
8700   {
8701     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8702     CPU (h_cbit) = opval;
8703     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8704   }
8705   {
8706     BI opval = LTSI (tmp_newval, 0);
8707     CPU (h_nbit) = opval;
8708     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8709   }
8710   {
8711     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8712     CPU (h_zbit) = opval;
8713     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8714   }
8715   {
8716     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8717     CPU (h_vbit) = opval;
8718     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8719   }
8720 {
8721   {
8722     BI opval = 0;
8723     CPU (h_xbit) = opval;
8724     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8725   }
8726   {
8727     BI opval = 0;
8728     SET_H_INSN_PREFIXED_P (opval);
8729     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8730   }
8731 }
8732 }
8733 }
8734
8735 #undef FLD
8736 }
8737   NEXT (vpc);
8738
8739   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
8740 {
8741   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8742   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8743 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8744   int UNUSED written = 0;
8745   IADDR UNUSED pc = abuf->addr;
8746   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8747
8748 {
8749   QI tmp_tmpd;
8750   tmp_tmpd = ({   SI tmp_addr;
8751   QI tmp_tmp_mem;
8752   BI tmp_postinc;
8753   tmp_postinc = FLD (f_memmode);
8754 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8755 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8756 ; if (NEBI (tmp_postinc, 0)) {
8757 {
8758 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8759   tmp_addr = ADDSI (tmp_addr, 1);
8760 }
8761   {
8762     SI opval = tmp_addr;
8763     SET_H_GR (FLD (f_operand1), opval);
8764     written |= (1 << 8);
8765     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8766   }
8767 }
8768 }
8769 ; tmp_tmp_mem; });
8770 {
8771   QI tmp_tmpopd;
8772   QI tmp_tmpops;
8773   BI tmp_carry;
8774   QI tmp_newval;
8775   tmp_tmpops = 0;
8776   tmp_tmpopd = tmp_tmpd;
8777   tmp_carry = CPU (h_cbit);
8778   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8779 ((void) 0); /*nop*/
8780 {
8781   {
8782     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8783     CPU (h_cbit) = opval;
8784     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8785   }
8786   {
8787     BI opval = LTQI (tmp_newval, 0);
8788     CPU (h_nbit) = opval;
8789     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8790   }
8791   {
8792     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8793     CPU (h_zbit) = opval;
8794     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8795   }
8796   {
8797     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8798     CPU (h_vbit) = opval;
8799     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8800   }
8801 {
8802   {
8803     BI opval = 0;
8804     CPU (h_xbit) = opval;
8805     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8806   }
8807   {
8808     BI opval = 0;
8809     SET_H_INSN_PREFIXED_P (opval);
8810     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8811   }
8812 }
8813 }
8814 }
8815 }
8816
8817   abuf->written = written;
8818 #undef FLD
8819 }
8820   NEXT (vpc);
8821
8822   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
8823 {
8824   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8825   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8826 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8827   int UNUSED written = 0;
8828   IADDR UNUSED pc = abuf->addr;
8829   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8830
8831 {
8832   HI tmp_tmpd;
8833   tmp_tmpd = ({   SI tmp_addr;
8834   HI tmp_tmp_mem;
8835   BI tmp_postinc;
8836   tmp_postinc = FLD (f_memmode);
8837 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8838 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8839 ; if (NEBI (tmp_postinc, 0)) {
8840 {
8841 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8842   tmp_addr = ADDSI (tmp_addr, 2);
8843 }
8844   {
8845     SI opval = tmp_addr;
8846     SET_H_GR (FLD (f_operand1), opval);
8847     written |= (1 << 8);
8848     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8849   }
8850 }
8851 }
8852 ; tmp_tmp_mem; });
8853 {
8854   HI tmp_tmpopd;
8855   HI tmp_tmpops;
8856   BI tmp_carry;
8857   HI tmp_newval;
8858   tmp_tmpops = 0;
8859   tmp_tmpopd = tmp_tmpd;
8860   tmp_carry = CPU (h_cbit);
8861   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8862 ((void) 0); /*nop*/
8863 {
8864   {
8865     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8866     CPU (h_cbit) = opval;
8867     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8868   }
8869   {
8870     BI opval = LTHI (tmp_newval, 0);
8871     CPU (h_nbit) = opval;
8872     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8873   }
8874   {
8875     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8876     CPU (h_zbit) = opval;
8877     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8878   }
8879   {
8880     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8881     CPU (h_vbit) = opval;
8882     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8883   }
8884 {
8885   {
8886     BI opval = 0;
8887     CPU (h_xbit) = opval;
8888     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8889   }
8890   {
8891     BI opval = 0;
8892     SET_H_INSN_PREFIXED_P (opval);
8893     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8894   }
8895 }
8896 }
8897 }
8898 }
8899
8900   abuf->written = written;
8901 #undef FLD
8902 }
8903   NEXT (vpc);
8904
8905   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
8906 {
8907   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8908   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8909 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
8910   int UNUSED written = 0;
8911   IADDR UNUSED pc = abuf->addr;
8912   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8913
8914 {
8915   SI tmp_tmpd;
8916   tmp_tmpd = ({   SI tmp_addr;
8917   SI tmp_tmp_mem;
8918   BI tmp_postinc;
8919   tmp_postinc = FLD (f_memmode);
8920 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
8921 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
8922 ; if (NEBI (tmp_postinc, 0)) {
8923 {
8924 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8925   tmp_addr = ADDSI (tmp_addr, 4);
8926 }
8927   {
8928     SI opval = tmp_addr;
8929     SET_H_GR (FLD (f_operand1), opval);
8930     written |= (1 << 8);
8931     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8932   }
8933 }
8934 }
8935 ; tmp_tmp_mem; });
8936 {
8937   SI tmp_tmpopd;
8938   SI tmp_tmpops;
8939   BI tmp_carry;
8940   SI tmp_newval;
8941   tmp_tmpops = 0;
8942   tmp_tmpopd = tmp_tmpd;
8943   tmp_carry = CPU (h_cbit);
8944   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8945 ((void) 0); /*nop*/
8946 {
8947   {
8948     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8949     CPU (h_cbit) = opval;
8950     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8951   }
8952   {
8953     BI opval = LTSI (tmp_newval, 0);
8954     CPU (h_nbit) = opval;
8955     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8956   }
8957   {
8958     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8959     CPU (h_zbit) = opval;
8960     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8961   }
8962   {
8963     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8964     CPU (h_vbit) = opval;
8965     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8966   }
8967 {
8968   {
8969     BI opval = 0;
8970     CPU (h_xbit) = opval;
8971     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8972   }
8973   {
8974     BI opval = 0;
8975     SET_H_INSN_PREFIXED_P (opval);
8976     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8977   }
8978 }
8979 }
8980 }
8981 }
8982
8983   abuf->written = written;
8984 #undef FLD
8985 }
8986   NEXT (vpc);
8987
8988   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
8989 {
8990   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8991   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8992 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
8993   int UNUSED written = 0;
8994   IADDR UNUSED pc = abuf->addr;
8995   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8996
8997 {
8998   QI tmp_tmpd;
8999   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9000 {
9001   SI tmp_addr;
9002   BI tmp_postinc;
9003   tmp_postinc = FLD (f_memmode);
9004   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9005 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9006 if (EQBI (CPU (h_pbit), 0)) {
9007 {
9008   {
9009     QI opval = tmp_tmpd;
9010     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9011     written |= (1 << 10);
9012     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9013   }
9014   {
9015     BI opval = CPU (h_pbit);
9016     CPU (h_cbit) = opval;
9017     written |= (1 << 9);
9018     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9019   }
9020 }
9021 } else {
9022   {
9023     BI opval = 1;
9024     CPU (h_cbit) = opval;
9025     written |= (1 << 9);
9026     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9027   }
9028 }
9029 } else {
9030   {
9031     QI opval = tmp_tmpd;
9032     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9033     written |= (1 << 10);
9034     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9035   }
9036 }
9037 if (NEBI (tmp_postinc, 0)) {
9038 {
9039 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9040   tmp_addr = ADDSI (tmp_addr, 1);
9041 }
9042   {
9043     SI opval = tmp_addr;
9044     SET_H_GR (FLD (f_operand1), opval);
9045     written |= (1 << 8);
9046     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9047   }
9048 }
9049 }
9050 }
9051 {
9052   {
9053     BI opval = 0;
9054     CPU (h_xbit) = opval;
9055     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9056   }
9057   {
9058     BI opval = 0;
9059     SET_H_INSN_PREFIXED_P (opval);
9060     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9061   }
9062 }
9063 }
9064
9065   abuf->written = written;
9066 #undef FLD
9067 }
9068   NEXT (vpc);
9069
9070   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9071 {
9072   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9073   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9074 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9075   int UNUSED written = 0;
9076   IADDR UNUSED pc = abuf->addr;
9077   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9078
9079 {
9080   HI tmp_tmpd;
9081   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9082 {
9083   SI tmp_addr;
9084   BI tmp_postinc;
9085   tmp_postinc = FLD (f_memmode);
9086   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9087 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9088 if (EQBI (CPU (h_pbit), 0)) {
9089 {
9090   {
9091     HI opval = tmp_tmpd;
9092     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9093     written |= (1 << 10);
9094     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9095   }
9096   {
9097     BI opval = CPU (h_pbit);
9098     CPU (h_cbit) = opval;
9099     written |= (1 << 9);
9100     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9101   }
9102 }
9103 } else {
9104   {
9105     BI opval = 1;
9106     CPU (h_cbit) = opval;
9107     written |= (1 << 9);
9108     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9109   }
9110 }
9111 } else {
9112   {
9113     HI opval = tmp_tmpd;
9114     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9115     written |= (1 << 10);
9116     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9117   }
9118 }
9119 if (NEBI (tmp_postinc, 0)) {
9120 {
9121 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9122   tmp_addr = ADDSI (tmp_addr, 2);
9123 }
9124   {
9125     SI opval = tmp_addr;
9126     SET_H_GR (FLD (f_operand1), opval);
9127     written |= (1 << 8);
9128     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9129   }
9130 }
9131 }
9132 }
9133 {
9134   {
9135     BI opval = 0;
9136     CPU (h_xbit) = opval;
9137     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9138   }
9139   {
9140     BI opval = 0;
9141     SET_H_INSN_PREFIXED_P (opval);
9142     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9143   }
9144 }
9145 }
9146
9147   abuf->written = written;
9148 #undef FLD
9149 }
9150   NEXT (vpc);
9151
9152   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9153 {
9154   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9155   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9156 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
9157   int UNUSED written = 0;
9158   IADDR UNUSED pc = abuf->addr;
9159   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9160
9161 {
9162   SI tmp_tmpd;
9163   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9164 {
9165   SI tmp_addr;
9166   BI tmp_postinc;
9167   tmp_postinc = FLD (f_memmode);
9168   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9169 if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
9170 if (EQBI (CPU (h_pbit), 0)) {
9171 {
9172   {
9173     SI opval = tmp_tmpd;
9174     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9175     written |= (1 << 10);
9176     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9177   }
9178   {
9179     BI opval = CPU (h_pbit);
9180     CPU (h_cbit) = opval;
9181     written |= (1 << 9);
9182     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9183   }
9184 }
9185 } else {
9186   {
9187     BI opval = 1;
9188     CPU (h_cbit) = opval;
9189     written |= (1 << 9);
9190     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9191   }
9192 }
9193 } else {
9194   {
9195     SI opval = tmp_tmpd;
9196     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9197     written |= (1 << 10);
9198     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9199   }
9200 }
9201 if (NEBI (tmp_postinc, 0)) {
9202 {
9203 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9204   tmp_addr = ADDSI (tmp_addr, 4);
9205 }
9206   {
9207     SI opval = tmp_addr;
9208     SET_H_GR (FLD (f_operand1), opval);
9209     written |= (1 << 8);
9210     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9211   }
9212 }
9213 }
9214 }
9215 {
9216   {
9217     BI opval = 0;
9218     CPU (h_xbit) = opval;
9219     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9220   }
9221   {
9222     BI opval = 0;
9223     SET_H_INSN_PREFIXED_P (opval);
9224     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9225   }
9226 }
9227 }
9228
9229   abuf->written = written;
9230 #undef FLD
9231 }
9232   NEXT (vpc);
9233
9234   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9235 {
9236   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9237   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9238 #define FLD(f) abuf->fields.sfmt_muls_b.f
9239   int UNUSED written = 0;
9240   IADDR UNUSED pc = abuf->addr;
9241   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9242
9243 {
9244   DI tmp_src1;
9245   DI tmp_src2;
9246   DI tmp_tmpr;
9247   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9248   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9249   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9250   {
9251     SI opval = TRUNCDISI (tmp_tmpr);
9252     SET_H_GR (FLD (f_operand2), opval);
9253     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9254   }
9255   {
9256     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9257     SET_H_SR (((UINT) 7), opval);
9258     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9259   }
9260 {
9261   {
9262     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9263     CPU (h_cbit) = opval;
9264     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9265   }
9266   {
9267     BI opval = LTDI (tmp_tmpr, 0);
9268     CPU (h_nbit) = opval;
9269     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9270   }
9271   {
9272     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9273     CPU (h_zbit) = opval;
9274     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9275   }
9276   {
9277     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9278     CPU (h_vbit) = opval;
9279     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9280   }
9281 {
9282   {
9283     BI opval = 0;
9284     CPU (h_xbit) = opval;
9285     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9286   }
9287   {
9288     BI opval = 0;
9289     SET_H_INSN_PREFIXED_P (opval);
9290     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9291   }
9292 }
9293 }
9294 }
9295
9296 #undef FLD
9297 }
9298   NEXT (vpc);
9299
9300   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9301 {
9302   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9303   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9304 #define FLD(f) abuf->fields.sfmt_muls_b.f
9305   int UNUSED written = 0;
9306   IADDR UNUSED pc = abuf->addr;
9307   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9308
9309 {
9310   DI tmp_src1;
9311   DI tmp_src2;
9312   DI tmp_tmpr;
9313   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9314   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9315   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9316   {
9317     SI opval = TRUNCDISI (tmp_tmpr);
9318     SET_H_GR (FLD (f_operand2), opval);
9319     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9320   }
9321   {
9322     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9323     SET_H_SR (((UINT) 7), opval);
9324     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9325   }
9326 {
9327   {
9328     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9329     CPU (h_cbit) = opval;
9330     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9331   }
9332   {
9333     BI opval = LTDI (tmp_tmpr, 0);
9334     CPU (h_nbit) = opval;
9335     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9336   }
9337   {
9338     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9339     CPU (h_zbit) = opval;
9340     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9341   }
9342   {
9343     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9344     CPU (h_vbit) = opval;
9345     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9346   }
9347 {
9348   {
9349     BI opval = 0;
9350     CPU (h_xbit) = opval;
9351     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9352   }
9353   {
9354     BI opval = 0;
9355     SET_H_INSN_PREFIXED_P (opval);
9356     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9357   }
9358 }
9359 }
9360 }
9361
9362 #undef FLD
9363 }
9364   NEXT (vpc);
9365
9366   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9367 {
9368   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9369   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9370 #define FLD(f) abuf->fields.sfmt_muls_b.f
9371   int UNUSED written = 0;
9372   IADDR UNUSED pc = abuf->addr;
9373   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9374
9375 {
9376   DI tmp_src1;
9377   DI tmp_src2;
9378   DI tmp_tmpr;
9379   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9380   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9381   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9382   {
9383     SI opval = TRUNCDISI (tmp_tmpr);
9384     SET_H_GR (FLD (f_operand2), opval);
9385     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9386   }
9387   {
9388     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9389     SET_H_SR (((UINT) 7), opval);
9390     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9391   }
9392 {
9393   {
9394     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9395     CPU (h_cbit) = opval;
9396     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9397   }
9398   {
9399     BI opval = LTDI (tmp_tmpr, 0);
9400     CPU (h_nbit) = opval;
9401     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9402   }
9403   {
9404     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9405     CPU (h_zbit) = opval;
9406     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9407   }
9408   {
9409     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9410     CPU (h_vbit) = opval;
9411     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9412   }
9413 {
9414   {
9415     BI opval = 0;
9416     CPU (h_xbit) = opval;
9417     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9418   }
9419   {
9420     BI opval = 0;
9421     SET_H_INSN_PREFIXED_P (opval);
9422     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9423   }
9424 }
9425 }
9426 }
9427
9428 #undef FLD
9429 }
9430   NEXT (vpc);
9431
9432   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9433 {
9434   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9435   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9436 #define FLD(f) abuf->fields.sfmt_muls_b.f
9437   int UNUSED written = 0;
9438   IADDR UNUSED pc = abuf->addr;
9439   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9440
9441 {
9442   DI tmp_src1;
9443   DI tmp_src2;
9444   DI tmp_tmpr;
9445   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9446   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9447   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9448   {
9449     SI opval = TRUNCDISI (tmp_tmpr);
9450     SET_H_GR (FLD (f_operand2), opval);
9451     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9452   }
9453   {
9454     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9455     SET_H_SR (((UINT) 7), opval);
9456     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9457   }
9458 {
9459   {
9460     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9461     CPU (h_cbit) = opval;
9462     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9463   }
9464   {
9465     BI opval = LTDI (tmp_tmpr, 0);
9466     CPU (h_nbit) = opval;
9467     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9468   }
9469   {
9470     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9471     CPU (h_zbit) = opval;
9472     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9473   }
9474   {
9475     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9476     CPU (h_vbit) = opval;
9477     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9478   }
9479 {
9480   {
9481     BI opval = 0;
9482     CPU (h_xbit) = opval;
9483     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9484   }
9485   {
9486     BI opval = 0;
9487     SET_H_INSN_PREFIXED_P (opval);
9488     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9489   }
9490 }
9491 }
9492 }
9493
9494 #undef FLD
9495 }
9496   NEXT (vpc);
9497
9498   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9499 {
9500   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9501   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9502 #define FLD(f) abuf->fields.sfmt_muls_b.f
9503   int UNUSED written = 0;
9504   IADDR UNUSED pc = abuf->addr;
9505   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9506
9507 {
9508   DI tmp_src1;
9509   DI tmp_src2;
9510   DI tmp_tmpr;
9511   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9512   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9513   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9514   {
9515     SI opval = TRUNCDISI (tmp_tmpr);
9516     SET_H_GR (FLD (f_operand2), opval);
9517     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9518   }
9519   {
9520     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9521     SET_H_SR (((UINT) 7), opval);
9522     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9523   }
9524 {
9525   {
9526     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9527     CPU (h_cbit) = opval;
9528     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9529   }
9530   {
9531     BI opval = LTDI (tmp_tmpr, 0);
9532     CPU (h_nbit) = opval;
9533     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9534   }
9535   {
9536     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9537     CPU (h_zbit) = opval;
9538     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9539   }
9540   {
9541     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9542     CPU (h_vbit) = opval;
9543     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9544   }
9545 {
9546   {
9547     BI opval = 0;
9548     CPU (h_xbit) = opval;
9549     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9550   }
9551   {
9552     BI opval = 0;
9553     SET_H_INSN_PREFIXED_P (opval);
9554     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9555   }
9556 }
9557 }
9558 }
9559
9560 #undef FLD
9561 }
9562   NEXT (vpc);
9563
9564   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
9565 {
9566   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9567   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9568 #define FLD(f) abuf->fields.sfmt_muls_b.f
9569   int UNUSED written = 0;
9570   IADDR UNUSED pc = abuf->addr;
9571   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9572
9573 {
9574   DI tmp_src1;
9575   DI tmp_src2;
9576   DI tmp_tmpr;
9577   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9578   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9579   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9580   {
9581     SI opval = TRUNCDISI (tmp_tmpr);
9582     SET_H_GR (FLD (f_operand2), opval);
9583     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9584   }
9585   {
9586     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9587     SET_H_SR (((UINT) 7), opval);
9588     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9589   }
9590 {
9591   {
9592     BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
9593     CPU (h_cbit) = opval;
9594     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9595   }
9596   {
9597     BI opval = LTDI (tmp_tmpr, 0);
9598     CPU (h_nbit) = opval;
9599     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9600   }
9601   {
9602     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9603     CPU (h_zbit) = opval;
9604     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9605   }
9606   {
9607     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9608     CPU (h_vbit) = opval;
9609     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9610   }
9611 {
9612   {
9613     BI opval = 0;
9614     CPU (h_xbit) = opval;
9615     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9616   }
9617   {
9618     BI opval = 0;
9619     SET_H_INSN_PREFIXED_P (opval);
9620     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9621   }
9622 }
9623 }
9624 }
9625
9626 #undef FLD
9627 }
9628   NEXT (vpc);
9629
9630   CASE (sem, INSN_MSTEP) : /* mstep $Rs,$Rd */
9631 {
9632   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9633   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9634 #define FLD(f) abuf->fields.sfmt_muls_b.f
9635   int UNUSED written = 0;
9636   IADDR UNUSED pc = abuf->addr;
9637   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9638
9639 {
9640   SI tmp_tmpd;
9641   SI tmp_tmps;
9642   tmp_tmps = GET_H_GR (FLD (f_operand1));
9643   tmp_tmpd = ADDSI (SLLSI (GET_H_GR (FLD (f_operand2)), 1), ((CPU (h_nbit)) ? (tmp_tmps) : (0)));
9644   {
9645     SI opval = tmp_tmpd;
9646     SET_H_GR (FLD (f_operand2), opval);
9647     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9648   }
9649 {
9650   {
9651     BI opval = LTSI (tmp_tmpd, 0);
9652     CPU (h_nbit) = opval;
9653     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9654   }
9655   {
9656     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9657     CPU (h_zbit) = opval;
9658     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9659   }
9660 SET_H_CBIT_MOVE (0);
9661 SET_H_VBIT_MOVE (0);
9662 {
9663   {
9664     BI opval = 0;
9665     CPU (h_xbit) = opval;
9666     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9667   }
9668   {
9669     BI opval = 0;
9670     SET_H_INSN_PREFIXED_P (opval);
9671     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9672   }
9673 }
9674 }
9675 }
9676
9677 #undef FLD
9678 }
9679   NEXT (vpc);
9680
9681   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
9682 {
9683   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9684   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9685 #define FLD(f) abuf->fields.sfmt_muls_b.f
9686   int UNUSED written = 0;
9687   IADDR UNUSED pc = abuf->addr;
9688   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9689
9690 {
9691   SI tmp_tmp;
9692   SI tmp_tmps;
9693   SI tmp_tmpd;
9694   tmp_tmps = GET_H_GR (FLD (f_operand1));
9695   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
9696   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
9697   {
9698     SI opval = tmp_tmpd;
9699     SET_H_GR (FLD (f_operand2), opval);
9700     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9701   }
9702 {
9703   {
9704     BI opval = LTSI (tmp_tmpd, 0);
9705     CPU (h_nbit) = opval;
9706     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9707   }
9708   {
9709     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9710     CPU (h_zbit) = opval;
9711     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9712   }
9713 SET_H_CBIT_MOVE (0);
9714 SET_H_VBIT_MOVE (0);
9715 {
9716   {
9717     BI opval = 0;
9718     CPU (h_xbit) = opval;
9719     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9720   }
9721   {
9722     BI opval = 0;
9723     SET_H_INSN_PREFIXED_P (opval);
9724     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9725   }
9726 }
9727 }
9728 }
9729
9730 #undef FLD
9731 }
9732   NEXT (vpc);
9733
9734   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
9735 {
9736   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9737   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9738 #define FLD(f) abuf->fields.sfmt_muls_b.f
9739   int UNUSED written = 0;
9740   IADDR UNUSED pc = abuf->addr;
9741   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9742
9743 {
9744   SI tmp_tmpd;
9745   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
9746   {
9747     SI opval = tmp_tmpd;
9748     SET_H_GR (FLD (f_operand2), opval);
9749     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9750   }
9751 {
9752   {
9753     BI opval = LTSI (tmp_tmpd, 0);
9754     CPU (h_nbit) = opval;
9755     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9756   }
9757   {
9758     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9759     CPU (h_zbit) = opval;
9760     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9761   }
9762 SET_H_CBIT_MOVE (0);
9763 SET_H_VBIT_MOVE (0);
9764 {
9765   {
9766     BI opval = 0;
9767     CPU (h_xbit) = opval;
9768     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9769   }
9770   {
9771     BI opval = 0;
9772     SET_H_INSN_PREFIXED_P (opval);
9773     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9774   }
9775 }
9776 }
9777 }
9778
9779 #undef FLD
9780 }
9781   NEXT (vpc);
9782
9783   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
9784 {
9785   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9786   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9787 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9788   int UNUSED written = 0;
9789   IADDR UNUSED pc = abuf->addr;
9790   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9791
9792 {
9793   QI tmp_tmpd;
9794   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9795 {
9796   SI tmp_oldregval;
9797   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
9798   {
9799     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
9800     SET_H_GR (FLD (f_operand2), opval);
9801     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9802   }
9803 }
9804 {
9805   {
9806     BI opval = LTQI (tmp_tmpd, 0);
9807     CPU (h_nbit) = opval;
9808     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9809   }
9810   {
9811     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9812     CPU (h_zbit) = opval;
9813     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9814   }
9815 SET_H_CBIT_MOVE (0);
9816 SET_H_VBIT_MOVE (0);
9817 {
9818   {
9819     BI opval = 0;
9820     CPU (h_xbit) = opval;
9821     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9822   }
9823   {
9824     BI opval = 0;
9825     SET_H_INSN_PREFIXED_P (opval);
9826     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9827   }
9828 }
9829 }
9830 }
9831
9832 #undef FLD
9833 }
9834   NEXT (vpc);
9835
9836   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
9837 {
9838   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9839   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9840 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9841   int UNUSED written = 0;
9842   IADDR UNUSED pc = abuf->addr;
9843   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9844
9845 {
9846   HI tmp_tmpd;
9847   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9848 {
9849   SI tmp_oldregval;
9850   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
9851   {
9852     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
9853     SET_H_GR (FLD (f_operand2), opval);
9854     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9855   }
9856 }
9857 {
9858   {
9859     BI opval = LTHI (tmp_tmpd, 0);
9860     CPU (h_nbit) = opval;
9861     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9862   }
9863   {
9864     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9865     CPU (h_zbit) = opval;
9866     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9867   }
9868 SET_H_CBIT_MOVE (0);
9869 SET_H_VBIT_MOVE (0);
9870 {
9871   {
9872     BI opval = 0;
9873     CPU (h_xbit) = opval;
9874     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9875   }
9876   {
9877     BI opval = 0;
9878     SET_H_INSN_PREFIXED_P (opval);
9879     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9880   }
9881 }
9882 }
9883 }
9884
9885 #undef FLD
9886 }
9887   NEXT (vpc);
9888
9889   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
9890 {
9891   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9892   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9893 #define FLD(f) abuf->fields.sfmt_add_b_r.f
9894   int UNUSED written = 0;
9895   IADDR UNUSED pc = abuf->addr;
9896   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9897
9898 {
9899   SI tmp_tmpd;
9900   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
9901   {
9902     SI opval = tmp_tmpd;
9903     SET_H_GR (FLD (f_operand2), opval);
9904     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9905   }
9906 {
9907   {
9908     BI opval = LTSI (tmp_tmpd, 0);
9909     CPU (h_nbit) = opval;
9910     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9911   }
9912   {
9913     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9914     CPU (h_zbit) = opval;
9915     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9916   }
9917 SET_H_CBIT_MOVE (0);
9918 SET_H_VBIT_MOVE (0);
9919 {
9920   {
9921     BI opval = 0;
9922     CPU (h_xbit) = opval;
9923     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9924   }
9925   {
9926     BI opval = 0;
9927     SET_H_INSN_PREFIXED_P (opval);
9928     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9929   }
9930 }
9931 }
9932 }
9933
9934 #undef FLD
9935 }
9936   NEXT (vpc);
9937
9938   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
9939 {
9940   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9941   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9942 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
9943   int UNUSED written = 0;
9944   IADDR UNUSED pc = abuf->addr;
9945   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9946
9947 {
9948   QI tmp_tmpd;
9949   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
9950   QI tmp_tmp_mem;
9951   BI tmp_postinc;
9952   tmp_postinc = FLD (f_memmode);
9953 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
9954 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
9955 ; if (NEBI (tmp_postinc, 0)) {
9956 {
9957 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9958   tmp_addr = ADDSI (tmp_addr, 1);
9959 }
9960   {
9961     SI opval = tmp_addr;
9962     SET_H_GR (FLD (f_operand1), opval);
9963     written |= (1 << 11);
9964     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9965   }
9966 }
9967 }
9968 ; tmp_tmp_mem; }));
9969 {
9970   SI tmp_oldregval;
9971   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
9972   {
9973     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
9974     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
9975     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9976   }
9977 }
9978 {
9979   {
9980     BI opval = LTQI (tmp_tmpd, 0);
9981     CPU (h_nbit) = opval;
9982     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9983   }
9984   {
9985     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9986     CPU (h_zbit) = opval;
9987     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9988   }
9989 SET_H_CBIT_MOVE (0);
9990 SET_H_VBIT_MOVE (0);
9991 {
9992   {
9993     BI opval = 0;
9994     CPU (h_xbit) = opval;
9995     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9996   }
9997   {
9998     BI opval = 0;
9999     SET_H_INSN_PREFIXED_P (opval);
10000     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10001   }
10002 }
10003 }
10004 }
10005
10006   abuf->written = written;
10007 #undef FLD
10008 }
10009   NEXT (vpc);
10010
10011   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10012 {
10013   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10014   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10015 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10016   int UNUSED written = 0;
10017   IADDR UNUSED pc = abuf->addr;
10018   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10019
10020 {
10021   HI tmp_tmpd;
10022   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10023   HI tmp_tmp_mem;
10024   BI tmp_postinc;
10025   tmp_postinc = FLD (f_memmode);
10026 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10027 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10028 ; if (NEBI (tmp_postinc, 0)) {
10029 {
10030 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10031   tmp_addr = ADDSI (tmp_addr, 2);
10032 }
10033   {
10034     SI opval = tmp_addr;
10035     SET_H_GR (FLD (f_operand1), opval);
10036     written |= (1 << 11);
10037     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10038   }
10039 }
10040 }
10041 ; tmp_tmp_mem; }));
10042 {
10043   SI tmp_oldregval;
10044   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10045   {
10046     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10047     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10048     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10049   }
10050 }
10051 {
10052   {
10053     BI opval = LTHI (tmp_tmpd, 0);
10054     CPU (h_nbit) = opval;
10055     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10056   }
10057   {
10058     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10059     CPU (h_zbit) = opval;
10060     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10061   }
10062 SET_H_CBIT_MOVE (0);
10063 SET_H_VBIT_MOVE (0);
10064 {
10065   {
10066     BI opval = 0;
10067     CPU (h_xbit) = opval;
10068     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10069   }
10070   {
10071     BI opval = 0;
10072     SET_H_INSN_PREFIXED_P (opval);
10073     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10074   }
10075 }
10076 }
10077 }
10078
10079   abuf->written = written;
10080 #undef FLD
10081 }
10082   NEXT (vpc);
10083
10084   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10085 {
10086   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10087   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10088 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10089   int UNUSED written = 0;
10090   IADDR UNUSED pc = abuf->addr;
10091   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10092
10093 {
10094   SI tmp_tmpd;
10095   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10096   SI tmp_tmp_mem;
10097   BI tmp_postinc;
10098   tmp_postinc = FLD (f_memmode);
10099 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10100 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10101 ; if (NEBI (tmp_postinc, 0)) {
10102 {
10103 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10104   tmp_addr = ADDSI (tmp_addr, 4);
10105 }
10106   {
10107     SI opval = tmp_addr;
10108     SET_H_GR (FLD (f_operand1), opval);
10109     written |= (1 << 10);
10110     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10111   }
10112 }
10113 }
10114 ; tmp_tmp_mem; }));
10115   {
10116     SI opval = tmp_tmpd;
10117     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10118     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10119   }
10120 {
10121   {
10122     BI opval = LTSI (tmp_tmpd, 0);
10123     CPU (h_nbit) = opval;
10124     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10125   }
10126   {
10127     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10128     CPU (h_zbit) = opval;
10129     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10130   }
10131 SET_H_CBIT_MOVE (0);
10132 SET_H_VBIT_MOVE (0);
10133 {
10134   {
10135     BI opval = 0;
10136     CPU (h_xbit) = opval;
10137     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10138   }
10139   {
10140     BI opval = 0;
10141     SET_H_INSN_PREFIXED_P (opval);
10142     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10143   }
10144 }
10145 }
10146 }
10147
10148   abuf->written = written;
10149 #undef FLD
10150 }
10151   NEXT (vpc);
10152
10153   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10154 {
10155   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10156   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10157 #define FLD(f) abuf->fields.sfmt_addcbr.f
10158   int UNUSED written = 0;
10159   IADDR UNUSED pc = abuf->addr;
10160   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10161
10162 {
10163   QI tmp_tmpd;
10164   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10165 {
10166   SI tmp_oldregval;
10167   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10168   {
10169     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10170     SET_H_GR (FLD (f_operand2), opval);
10171     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10172   }
10173 }
10174 {
10175   {
10176     BI opval = LTQI (tmp_tmpd, 0);
10177     CPU (h_nbit) = opval;
10178     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10179   }
10180   {
10181     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10182     CPU (h_zbit) = opval;
10183     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10184   }
10185 SET_H_CBIT_MOVE (0);
10186 SET_H_VBIT_MOVE (0);
10187 {
10188   {
10189     BI opval = 0;
10190     CPU (h_xbit) = opval;
10191     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10192   }
10193   {
10194     BI opval = 0;
10195     SET_H_INSN_PREFIXED_P (opval);
10196     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10197   }
10198 }
10199 }
10200 }
10201
10202 #undef FLD
10203 }
10204   NEXT (vpc);
10205
10206   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10207 {
10208   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10209   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10210 #define FLD(f) abuf->fields.sfmt_addcwr.f
10211   int UNUSED written = 0;
10212   IADDR UNUSED pc = abuf->addr;
10213   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10214
10215 {
10216   HI tmp_tmpd;
10217   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10218 {
10219   SI tmp_oldregval;
10220   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10221   {
10222     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10223     SET_H_GR (FLD (f_operand2), opval);
10224     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10225   }
10226 }
10227 {
10228   {
10229     BI opval = LTHI (tmp_tmpd, 0);
10230     CPU (h_nbit) = opval;
10231     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10232   }
10233   {
10234     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10235     CPU (h_zbit) = opval;
10236     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10237   }
10238 SET_H_CBIT_MOVE (0);
10239 SET_H_VBIT_MOVE (0);
10240 {
10241   {
10242     BI opval = 0;
10243     CPU (h_xbit) = opval;
10244     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10245   }
10246   {
10247     BI opval = 0;
10248     SET_H_INSN_PREFIXED_P (opval);
10249     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10250   }
10251 }
10252 }
10253 }
10254
10255 #undef FLD
10256 }
10257   NEXT (vpc);
10258
10259   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10260 {
10261   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10262   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10263 #define FLD(f) abuf->fields.sfmt_addcdr.f
10264   int UNUSED written = 0;
10265   IADDR UNUSED pc = abuf->addr;
10266   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10267
10268 {
10269   SI tmp_tmpd;
10270   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10271   {
10272     SI opval = tmp_tmpd;
10273     SET_H_GR (FLD (f_operand2), opval);
10274     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10275   }
10276 {
10277   {
10278     BI opval = LTSI (tmp_tmpd, 0);
10279     CPU (h_nbit) = opval;
10280     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10281   }
10282   {
10283     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10284     CPU (h_zbit) = opval;
10285     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10286   }
10287 SET_H_CBIT_MOVE (0);
10288 SET_H_VBIT_MOVE (0);
10289 {
10290   {
10291     BI opval = 0;
10292     CPU (h_xbit) = opval;
10293     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10294   }
10295   {
10296     BI opval = 0;
10297     SET_H_INSN_PREFIXED_P (opval);
10298     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10299   }
10300 }
10301 }
10302 }
10303
10304 #undef FLD
10305 }
10306   NEXT (vpc);
10307
10308   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10309 {
10310   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10311   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10312 #define FLD(f) abuf->fields.sfmt_andq.f
10313   int UNUSED written = 0;
10314   IADDR UNUSED pc = abuf->addr;
10315   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10316
10317 {
10318   SI tmp_tmpd;
10319   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10320   {
10321     SI opval = tmp_tmpd;
10322     SET_H_GR (FLD (f_operand2), opval);
10323     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10324   }
10325 {
10326   {
10327     BI opval = LTSI (tmp_tmpd, 0);
10328     CPU (h_nbit) = opval;
10329     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10330   }
10331   {
10332     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10333     CPU (h_zbit) = opval;
10334     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10335   }
10336 SET_H_CBIT_MOVE (0);
10337 SET_H_VBIT_MOVE (0);
10338 {
10339   {
10340     BI opval = 0;
10341     CPU (h_xbit) = opval;
10342     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10343   }
10344   {
10345     BI opval = 0;
10346     SET_H_INSN_PREFIXED_P (opval);
10347     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10348   }
10349 }
10350 }
10351 }
10352
10353 #undef FLD
10354 }
10355   NEXT (vpc);
10356
10357   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10358 {
10359   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10360   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10361 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10362   int UNUSED written = 0;
10363   IADDR UNUSED pc = abuf->addr;
10364   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10365
10366 {
10367   QI tmp_tmpd;
10368   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10369 {
10370   SI tmp_oldregval;
10371   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10372   {
10373     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10374     SET_H_GR (FLD (f_operand2), opval);
10375     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10376   }
10377 }
10378 {
10379   {
10380     BI opval = LTQI (tmp_tmpd, 0);
10381     CPU (h_nbit) = opval;
10382     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10383   }
10384   {
10385     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10386     CPU (h_zbit) = opval;
10387     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10388   }
10389 SET_H_CBIT_MOVE (0);
10390 SET_H_VBIT_MOVE (0);
10391 {
10392   {
10393     BI opval = 0;
10394     CPU (h_xbit) = opval;
10395     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10396   }
10397   {
10398     BI opval = 0;
10399     SET_H_INSN_PREFIXED_P (opval);
10400     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10401   }
10402 }
10403 }
10404 }
10405
10406 #undef FLD
10407 }
10408   NEXT (vpc);
10409
10410   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10411 {
10412   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10413   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10414 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10415   int UNUSED written = 0;
10416   IADDR UNUSED pc = abuf->addr;
10417   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10418
10419 {
10420   HI tmp_tmpd;
10421   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10422 {
10423   SI tmp_oldregval;
10424   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10425   {
10426     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10427     SET_H_GR (FLD (f_operand2), opval);
10428     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10429   }
10430 }
10431 {
10432   {
10433     BI opval = LTHI (tmp_tmpd, 0);
10434     CPU (h_nbit) = opval;
10435     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10436   }
10437   {
10438     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10439     CPU (h_zbit) = opval;
10440     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10441   }
10442 SET_H_CBIT_MOVE (0);
10443 SET_H_VBIT_MOVE (0);
10444 {
10445   {
10446     BI opval = 0;
10447     CPU (h_xbit) = opval;
10448     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10449   }
10450   {
10451     BI opval = 0;
10452     SET_H_INSN_PREFIXED_P (opval);
10453     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10454   }
10455 }
10456 }
10457 }
10458
10459 #undef FLD
10460 }
10461   NEXT (vpc);
10462
10463   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10464 {
10465   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10466   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10467 #define FLD(f) abuf->fields.sfmt_add_b_r.f
10468   int UNUSED written = 0;
10469   IADDR UNUSED pc = abuf->addr;
10470   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10471
10472 {
10473   SI tmp_tmpd;
10474   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10475   {
10476     SI opval = tmp_tmpd;
10477     SET_H_GR (FLD (f_operand2), opval);
10478     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10479   }
10480 {
10481   {
10482     BI opval = LTSI (tmp_tmpd, 0);
10483     CPU (h_nbit) = opval;
10484     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10485   }
10486   {
10487     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10488     CPU (h_zbit) = opval;
10489     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10490   }
10491 SET_H_CBIT_MOVE (0);
10492 SET_H_VBIT_MOVE (0);
10493 {
10494   {
10495     BI opval = 0;
10496     CPU (h_xbit) = opval;
10497     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10498   }
10499   {
10500     BI opval = 0;
10501     SET_H_INSN_PREFIXED_P (opval);
10502     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10503   }
10504 }
10505 }
10506 }
10507
10508 #undef FLD
10509 }
10510   NEXT (vpc);
10511
10512   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
10513 {
10514   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10515   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10516 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10517   int UNUSED written = 0;
10518   IADDR UNUSED pc = abuf->addr;
10519   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10520
10521 {
10522   QI tmp_tmpd;
10523   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10524   QI tmp_tmp_mem;
10525   BI tmp_postinc;
10526   tmp_postinc = FLD (f_memmode);
10527 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10528 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10529 ; if (NEBI (tmp_postinc, 0)) {
10530 {
10531 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10532   tmp_addr = ADDSI (tmp_addr, 1);
10533 }
10534   {
10535     SI opval = tmp_addr;
10536     SET_H_GR (FLD (f_operand1), opval);
10537     written |= (1 << 11);
10538     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10539   }
10540 }
10541 }
10542 ; tmp_tmp_mem; }));
10543 {
10544   SI tmp_oldregval;
10545   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10546   {
10547     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10548     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10549     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10550   }
10551 }
10552 {
10553   {
10554     BI opval = LTQI (tmp_tmpd, 0);
10555     CPU (h_nbit) = opval;
10556     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10557   }
10558   {
10559     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10560     CPU (h_zbit) = opval;
10561     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10562   }
10563 SET_H_CBIT_MOVE (0);
10564 SET_H_VBIT_MOVE (0);
10565 {
10566   {
10567     BI opval = 0;
10568     CPU (h_xbit) = opval;
10569     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10570   }
10571   {
10572     BI opval = 0;
10573     SET_H_INSN_PREFIXED_P (opval);
10574     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10575   }
10576 }
10577 }
10578 }
10579
10580   abuf->written = written;
10581 #undef FLD
10582 }
10583   NEXT (vpc);
10584
10585   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
10586 {
10587   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10588   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10589 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10590   int UNUSED written = 0;
10591   IADDR UNUSED pc = abuf->addr;
10592   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10593
10594 {
10595   HI tmp_tmpd;
10596   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10597   HI tmp_tmp_mem;
10598   BI tmp_postinc;
10599   tmp_postinc = FLD (f_memmode);
10600 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10601 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10602 ; if (NEBI (tmp_postinc, 0)) {
10603 {
10604 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10605   tmp_addr = ADDSI (tmp_addr, 2);
10606 }
10607   {
10608     SI opval = tmp_addr;
10609     SET_H_GR (FLD (f_operand1), opval);
10610     written |= (1 << 11);
10611     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10612   }
10613 }
10614 }
10615 ; tmp_tmp_mem; }));
10616 {
10617   SI tmp_oldregval;
10618   tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10619   {
10620     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10621     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10622     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10623   }
10624 }
10625 {
10626   {
10627     BI opval = LTHI (tmp_tmpd, 0);
10628     CPU (h_nbit) = opval;
10629     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10630   }
10631   {
10632     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10633     CPU (h_zbit) = opval;
10634     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10635   }
10636 SET_H_CBIT_MOVE (0);
10637 SET_H_VBIT_MOVE (0);
10638 {
10639   {
10640     BI opval = 0;
10641     CPU (h_xbit) = opval;
10642     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10643   }
10644   {
10645     BI opval = 0;
10646     SET_H_INSN_PREFIXED_P (opval);
10647     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10648   }
10649 }
10650 }
10651 }
10652
10653   abuf->written = written;
10654 #undef FLD
10655 }
10656   NEXT (vpc);
10657
10658   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
10659 {
10660   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10661   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10662 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10663   int UNUSED written = 0;
10664   IADDR UNUSED pc = abuf->addr;
10665   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10666
10667 {
10668   SI tmp_tmpd;
10669   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10670   SI tmp_tmp_mem;
10671   BI tmp_postinc;
10672   tmp_postinc = FLD (f_memmode);
10673 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
10674 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10675 ; if (NEBI (tmp_postinc, 0)) {
10676 {
10677 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10678   tmp_addr = ADDSI (tmp_addr, 4);
10679 }
10680   {
10681     SI opval = tmp_addr;
10682     SET_H_GR (FLD (f_operand1), opval);
10683     written |= (1 << 10);
10684     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10685   }
10686 }
10687 }
10688 ; tmp_tmp_mem; }));
10689   {
10690     SI opval = tmp_tmpd;
10691     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10692     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10693   }
10694 {
10695   {
10696     BI opval = LTSI (tmp_tmpd, 0);
10697     CPU (h_nbit) = opval;
10698     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10699   }
10700   {
10701     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10702     CPU (h_zbit) = opval;
10703     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10704   }
10705 SET_H_CBIT_MOVE (0);
10706 SET_H_VBIT_MOVE (0);
10707 {
10708   {
10709     BI opval = 0;
10710     CPU (h_xbit) = opval;
10711     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10712   }
10713   {
10714     BI opval = 0;
10715     SET_H_INSN_PREFIXED_P (opval);
10716     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10717   }
10718 }
10719 }
10720 }
10721
10722   abuf->written = written;
10723 #undef FLD
10724 }
10725   NEXT (vpc);
10726
10727   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
10728 {
10729   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10730   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10731 #define FLD(f) abuf->fields.sfmt_addcbr.f
10732   int UNUSED written = 0;
10733   IADDR UNUSED pc = abuf->addr;
10734   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10735
10736 {
10737   QI tmp_tmpd;
10738   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10739 {
10740   SI tmp_oldregval;
10741   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10742   {
10743     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10744     SET_H_GR (FLD (f_operand2), opval);
10745     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10746   }
10747 }
10748 {
10749   {
10750     BI opval = LTQI (tmp_tmpd, 0);
10751     CPU (h_nbit) = opval;
10752     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10753   }
10754   {
10755     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10756     CPU (h_zbit) = opval;
10757     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10758   }
10759 SET_H_CBIT_MOVE (0);
10760 SET_H_VBIT_MOVE (0);
10761 {
10762   {
10763     BI opval = 0;
10764     CPU (h_xbit) = opval;
10765     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10766   }
10767   {
10768     BI opval = 0;
10769     SET_H_INSN_PREFIXED_P (opval);
10770     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10771   }
10772 }
10773 }
10774 }
10775
10776 #undef FLD
10777 }
10778   NEXT (vpc);
10779
10780   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
10781 {
10782   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10783   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10784 #define FLD(f) abuf->fields.sfmt_addcwr.f
10785   int UNUSED written = 0;
10786   IADDR UNUSED pc = abuf->addr;
10787   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10788
10789 {
10790   HI tmp_tmpd;
10791   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10792 {
10793   SI tmp_oldregval;
10794   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
10795   {
10796     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10797     SET_H_GR (FLD (f_operand2), opval);
10798     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10799   }
10800 }
10801 {
10802   {
10803     BI opval = LTHI (tmp_tmpd, 0);
10804     CPU (h_nbit) = opval;
10805     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10806   }
10807   {
10808     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10809     CPU (h_zbit) = opval;
10810     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10811   }
10812 SET_H_CBIT_MOVE (0);
10813 SET_H_VBIT_MOVE (0);
10814 {
10815   {
10816     BI opval = 0;
10817     CPU (h_xbit) = opval;
10818     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10819   }
10820   {
10821     BI opval = 0;
10822     SET_H_INSN_PREFIXED_P (opval);
10823     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10824   }
10825 }
10826 }
10827 }
10828
10829 #undef FLD
10830 }
10831   NEXT (vpc);
10832
10833   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
10834 {
10835   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10836   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10837 #define FLD(f) abuf->fields.sfmt_addcdr.f
10838   int UNUSED written = 0;
10839   IADDR UNUSED pc = abuf->addr;
10840   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10841
10842 {
10843   SI tmp_tmpd;
10844   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10845   {
10846     SI opval = tmp_tmpd;
10847     SET_H_GR (FLD (f_operand2), opval);
10848     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10849   }
10850 {
10851   {
10852     BI opval = LTSI (tmp_tmpd, 0);
10853     CPU (h_nbit) = opval;
10854     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10855   }
10856   {
10857     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10858     CPU (h_zbit) = opval;
10859     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10860   }
10861 SET_H_CBIT_MOVE (0);
10862 SET_H_VBIT_MOVE (0);
10863 {
10864   {
10865     BI opval = 0;
10866     CPU (h_xbit) = opval;
10867     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10868   }
10869   {
10870     BI opval = 0;
10871     SET_H_INSN_PREFIXED_P (opval);
10872     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10873   }
10874 }
10875 }
10876 }
10877
10878 #undef FLD
10879 }
10880   NEXT (vpc);
10881
10882   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
10883 {
10884   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10885   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10886 #define FLD(f) abuf->fields.sfmt_andq.f
10887   int UNUSED written = 0;
10888   IADDR UNUSED pc = abuf->addr;
10889   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10890
10891 {
10892   SI tmp_tmpd;
10893   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10894   {
10895     SI opval = tmp_tmpd;
10896     SET_H_GR (FLD (f_operand2), opval);
10897     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10898   }
10899 {
10900   {
10901     BI opval = LTSI (tmp_tmpd, 0);
10902     CPU (h_nbit) = opval;
10903     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10904   }
10905   {
10906     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10907     CPU (h_zbit) = opval;
10908     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10909   }
10910 SET_H_CBIT_MOVE (0);
10911 SET_H_VBIT_MOVE (0);
10912 {
10913   {
10914     BI opval = 0;
10915     CPU (h_xbit) = opval;
10916     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10917   }
10918   {
10919     BI opval = 0;
10920     SET_H_INSN_PREFIXED_P (opval);
10921     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10922   }
10923 }
10924 }
10925 }
10926
10927 #undef FLD
10928 }
10929   NEXT (vpc);
10930
10931   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
10932 {
10933   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10934   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10935 #define FLD(f) abuf->fields.sfmt_muls_b.f
10936   int UNUSED written = 0;
10937   IADDR UNUSED pc = abuf->addr;
10938   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10939
10940 {
10941   SI tmp_tmpd;
10942   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10943   {
10944     SI opval = tmp_tmpd;
10945     SET_H_GR (FLD (f_operand2), opval);
10946     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10947   }
10948 {
10949   {
10950     BI opval = LTSI (tmp_tmpd, 0);
10951     CPU (h_nbit) = opval;
10952     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10953   }
10954   {
10955     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10956     CPU (h_zbit) = opval;
10957     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10958   }
10959 SET_H_CBIT_MOVE (0);
10960 SET_H_VBIT_MOVE (0);
10961 {
10962   {
10963     BI opval = 0;
10964     CPU (h_xbit) = opval;
10965     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10966   }
10967   {
10968     BI opval = 0;
10969     SET_H_INSN_PREFIXED_P (opval);
10970     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10971   }
10972 }
10973 }
10974 }
10975
10976 #undef FLD
10977 }
10978   NEXT (vpc);
10979
10980   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
10981 {
10982   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10983   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10984 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
10985   int UNUSED written = 0;
10986   IADDR UNUSED pc = abuf->addr;
10987   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10988
10989 {
10990   SI tmp_tmps;
10991   SI tmp_tmpd;
10992   tmp_tmps = GET_H_GR (FLD (f_operand1));
10993   tmp_tmpd = ({   SI tmp_tmpcode;
10994   SI tmp_tmpval;
10995   SI tmp_tmpres;
10996   tmp_tmpcode = FLD (f_operand2);
10997 ;   tmp_tmpval = tmp_tmps;
10998 ; if (EQSI (tmp_tmpcode, 0)) {
10999   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
11000 }
11001  else if (EQSI (tmp_tmpcode, 1)) {
11002   tmp_tmpres = ({   SI tmp_tmpr;
11003   tmp_tmpr = tmp_tmpval;
11004 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11005 }
11006  else if (EQSI (tmp_tmpcode, 2)) {
11007   tmp_tmpres = ({   SI tmp_tmpb;
11008   tmp_tmpb = tmp_tmpval;
11009 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11010 }
11011  else if (EQSI (tmp_tmpcode, 3)) {
11012   tmp_tmpres = ({   SI tmp_tmpr;
11013   tmp_tmpr = ({   SI tmp_tmpb;
11014   tmp_tmpb = tmp_tmpval;
11015 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11016 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11017 }
11018  else if (EQSI (tmp_tmpcode, 4)) {
11019   tmp_tmpres = ({   SI tmp_tmpb;
11020   tmp_tmpb = tmp_tmpval;
11021 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11022 }
11023  else if (EQSI (tmp_tmpcode, 5)) {
11024   tmp_tmpres = ({   SI tmp_tmpr;
11025   tmp_tmpr = ({   SI tmp_tmpb;
11026   tmp_tmpb = tmp_tmpval;
11027 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11028 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11029 }
11030  else if (EQSI (tmp_tmpcode, 6)) {
11031   tmp_tmpres = ({   SI tmp_tmpb;
11032   tmp_tmpb = ({   SI tmp_tmpb;
11033   tmp_tmpb = tmp_tmpval;
11034 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11035 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11036 }
11037  else if (EQSI (tmp_tmpcode, 7)) {
11038   tmp_tmpres = ({   SI tmp_tmpr;
11039   tmp_tmpr = ({   SI tmp_tmpb;
11040   tmp_tmpb = ({   SI tmp_tmpb;
11041   tmp_tmpb = tmp_tmpval;
11042 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11043 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11044 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11045 }
11046  else if (EQSI (tmp_tmpcode, 8)) {
11047   tmp_tmpres = INVSI (tmp_tmpval);
11048 }
11049  else if (EQSI (tmp_tmpcode, 9)) {
11050   tmp_tmpres = ({   SI tmp_tmpr;
11051   tmp_tmpr = INVSI (tmp_tmpval);
11052 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11053 }
11054  else if (EQSI (tmp_tmpcode, 10)) {
11055   tmp_tmpres = ({   SI tmp_tmpb;
11056   tmp_tmpb = INVSI (tmp_tmpval);
11057 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11058 }
11059  else if (EQSI (tmp_tmpcode, 11)) {
11060   tmp_tmpres = ({   SI tmp_tmpr;
11061   tmp_tmpr = ({   SI tmp_tmpb;
11062   tmp_tmpb = INVSI (tmp_tmpval);
11063 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11064 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11065 }
11066  else if (EQSI (tmp_tmpcode, 12)) {
11067   tmp_tmpres = ({   SI tmp_tmpb;
11068   tmp_tmpb = INVSI (tmp_tmpval);
11069 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11070 }
11071  else if (EQSI (tmp_tmpcode, 13)) {
11072   tmp_tmpres = ({   SI tmp_tmpr;
11073   tmp_tmpr = ({   SI tmp_tmpb;
11074   tmp_tmpb = INVSI (tmp_tmpval);
11075 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11076 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11077 }
11078  else if (EQSI (tmp_tmpcode, 14)) {
11079   tmp_tmpres = ({   SI tmp_tmpb;
11080   tmp_tmpb = ({   SI tmp_tmpb;
11081   tmp_tmpb = INVSI (tmp_tmpval);
11082 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11083 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11084 }
11085  else if (EQSI (tmp_tmpcode, 15)) {
11086   tmp_tmpres = ({   SI tmp_tmpr;
11087   tmp_tmpr = ({   SI tmp_tmpb;
11088   tmp_tmpb = ({   SI tmp_tmpb;
11089   tmp_tmpb = INVSI (tmp_tmpval);
11090 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11091 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11092 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11093 }
11094 ; tmp_tmpres; });
11095   {
11096     SI opval = tmp_tmpd;
11097     SET_H_GR (FLD (f_operand1), opval);
11098     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11099   }
11100 {
11101   {
11102     BI opval = LTSI (tmp_tmpd, 0);
11103     CPU (h_nbit) = opval;
11104     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11105   }
11106   {
11107     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11108     CPU (h_zbit) = opval;
11109     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11110   }
11111 SET_H_CBIT_MOVE (0);
11112 SET_H_VBIT_MOVE (0);
11113 {
11114   {
11115     BI opval = 0;
11116     CPU (h_xbit) = opval;
11117     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11118   }
11119   {
11120     BI opval = 0;
11121     SET_H_INSN_PREFIXED_P (opval);
11122     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11123   }
11124 }
11125 }
11126 }
11127
11128 #undef FLD
11129 }
11130   NEXT (vpc);
11131
11132   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11133 {
11134   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11135   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11136 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11137   int UNUSED written = 0;
11138   IADDR UNUSED pc = abuf->addr;
11139   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11140
11141 {
11142   QI tmp_tmpd;
11143   SI tmp_cnt1;
11144   SI tmp_cnt2;
11145   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11146   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11147   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11148 {
11149   SI tmp_oldregval;
11150   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11151   {
11152     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11153     SET_H_GR (FLD (f_operand2), opval);
11154     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11155   }
11156 }
11157 {
11158   {
11159     BI opval = LTQI (tmp_tmpd, 0);
11160     CPU (h_nbit) = opval;
11161     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11162   }
11163   {
11164     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11165     CPU (h_zbit) = opval;
11166     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11167   }
11168 SET_H_CBIT_MOVE (0);
11169 SET_H_VBIT_MOVE (0);
11170 {
11171   {
11172     BI opval = 0;
11173     CPU (h_xbit) = opval;
11174     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11175   }
11176   {
11177     BI opval = 0;
11178     SET_H_INSN_PREFIXED_P (opval);
11179     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11180   }
11181 }
11182 }
11183 }
11184
11185 #undef FLD
11186 }
11187   NEXT (vpc);
11188
11189   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11190 {
11191   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11192   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11193 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11194   int UNUSED written = 0;
11195   IADDR UNUSED pc = abuf->addr;
11196   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11197
11198 {
11199   HI tmp_tmpd;
11200   SI tmp_cnt1;
11201   SI tmp_cnt2;
11202   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11203   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11204   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11205 {
11206   SI tmp_oldregval;
11207   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11208   {
11209     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11210     SET_H_GR (FLD (f_operand2), opval);
11211     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11212   }
11213 }
11214 {
11215   {
11216     BI opval = LTHI (tmp_tmpd, 0);
11217     CPU (h_nbit) = opval;
11218     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11219   }
11220   {
11221     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11222     CPU (h_zbit) = opval;
11223     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11224   }
11225 SET_H_CBIT_MOVE (0);
11226 SET_H_VBIT_MOVE (0);
11227 {
11228   {
11229     BI opval = 0;
11230     CPU (h_xbit) = opval;
11231     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11232   }
11233   {
11234     BI opval = 0;
11235     SET_H_INSN_PREFIXED_P (opval);
11236     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11237   }
11238 }
11239 }
11240 }
11241
11242 #undef FLD
11243 }
11244   NEXT (vpc);
11245
11246   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11247 {
11248   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11249   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11250 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11251   int UNUSED written = 0;
11252   IADDR UNUSED pc = abuf->addr;
11253   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11254
11255 {
11256   SI tmp_tmpd;
11257   SI tmp_cnt1;
11258   SI tmp_cnt2;
11259   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11260   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11261   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11262   {
11263     SI opval = tmp_tmpd;
11264     SET_H_GR (FLD (f_operand2), opval);
11265     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11266   }
11267 {
11268   {
11269     BI opval = LTSI (tmp_tmpd, 0);
11270     CPU (h_nbit) = opval;
11271     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11272   }
11273   {
11274     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11275     CPU (h_zbit) = opval;
11276     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11277   }
11278 SET_H_CBIT_MOVE (0);
11279 SET_H_VBIT_MOVE (0);
11280 {
11281   {
11282     BI opval = 0;
11283     CPU (h_xbit) = opval;
11284     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11285   }
11286   {
11287     BI opval = 0;
11288     SET_H_INSN_PREFIXED_P (opval);
11289     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11290   }
11291 }
11292 }
11293 }
11294
11295 #undef FLD
11296 }
11297   NEXT (vpc);
11298
11299   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11300 {
11301   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11302   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11303 #define FLD(f) abuf->fields.sfmt_asrq.f
11304   int UNUSED written = 0;
11305   IADDR UNUSED pc = abuf->addr;
11306   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11307
11308 {
11309   SI tmp_tmpd;
11310   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11311   {
11312     SI opval = tmp_tmpd;
11313     SET_H_GR (FLD (f_operand2), opval);
11314     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11315   }
11316 {
11317   {
11318     BI opval = LTSI (tmp_tmpd, 0);
11319     CPU (h_nbit) = opval;
11320     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11321   }
11322   {
11323     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11324     CPU (h_zbit) = opval;
11325     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11326   }
11327 SET_H_CBIT_MOVE (0);
11328 SET_H_VBIT_MOVE (0);
11329 {
11330   {
11331     BI opval = 0;
11332     CPU (h_xbit) = opval;
11333     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11334   }
11335   {
11336     BI opval = 0;
11337     SET_H_INSN_PREFIXED_P (opval);
11338     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11339   }
11340 }
11341 }
11342 }
11343
11344 #undef FLD
11345 }
11346   NEXT (vpc);
11347
11348   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11349 {
11350   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11351   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11352 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11353   int UNUSED written = 0;
11354   IADDR UNUSED pc = abuf->addr;
11355   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11356
11357 {
11358   SI tmp_tmpd;
11359   SI tmp_cnt;
11360   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11361   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11362 {
11363   SI tmp_oldregval;
11364   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11365   {
11366     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11367     SET_H_GR (FLD (f_operand2), opval);
11368     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11369   }
11370 }
11371 {
11372   {
11373     BI opval = LTQI (tmp_tmpd, 0);
11374     CPU (h_nbit) = opval;
11375     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11376   }
11377   {
11378     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11379     CPU (h_zbit) = opval;
11380     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11381   }
11382 SET_H_CBIT_MOVE (0);
11383 SET_H_VBIT_MOVE (0);
11384 {
11385   {
11386     BI opval = 0;
11387     CPU (h_xbit) = opval;
11388     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11389   }
11390   {
11391     BI opval = 0;
11392     SET_H_INSN_PREFIXED_P (opval);
11393     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11394   }
11395 }
11396 }
11397 }
11398
11399 #undef FLD
11400 }
11401   NEXT (vpc);
11402
11403   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11404 {
11405   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11406   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11407 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11408   int UNUSED written = 0;
11409   IADDR UNUSED pc = abuf->addr;
11410   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11411
11412 {
11413   SI tmp_tmpd;
11414   SI tmp_cnt;
11415   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11416   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11417 {
11418   SI tmp_oldregval;
11419   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11420   {
11421     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11422     SET_H_GR (FLD (f_operand2), opval);
11423     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11424   }
11425 }
11426 {
11427   {
11428     BI opval = LTHI (tmp_tmpd, 0);
11429     CPU (h_nbit) = opval;
11430     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11431   }
11432   {
11433     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11434     CPU (h_zbit) = opval;
11435     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11436   }
11437 SET_H_CBIT_MOVE (0);
11438 SET_H_VBIT_MOVE (0);
11439 {
11440   {
11441     BI opval = 0;
11442     CPU (h_xbit) = opval;
11443     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11444   }
11445   {
11446     BI opval = 0;
11447     SET_H_INSN_PREFIXED_P (opval);
11448     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11449   }
11450 }
11451 }
11452 }
11453
11454 #undef FLD
11455 }
11456   NEXT (vpc);
11457
11458   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11459 {
11460   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11461   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11462 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11463   int UNUSED written = 0;
11464   IADDR UNUSED pc = abuf->addr;
11465   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11466
11467 {
11468   SI tmp_tmpd;
11469   SI tmp_cnt;
11470   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11471   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11472   {
11473     SI opval = tmp_tmpd;
11474     SET_H_GR (FLD (f_operand2), opval);
11475     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11476   }
11477 {
11478   {
11479     BI opval = LTSI (tmp_tmpd, 0);
11480     CPU (h_nbit) = opval;
11481     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11482   }
11483   {
11484     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11485     CPU (h_zbit) = opval;
11486     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11487   }
11488 SET_H_CBIT_MOVE (0);
11489 SET_H_VBIT_MOVE (0);
11490 {
11491   {
11492     BI opval = 0;
11493     CPU (h_xbit) = opval;
11494     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11495   }
11496   {
11497     BI opval = 0;
11498     SET_H_INSN_PREFIXED_P (opval);
11499     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11500   }
11501 }
11502 }
11503 }
11504
11505 #undef FLD
11506 }
11507   NEXT (vpc);
11508
11509   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
11510 {
11511   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11512   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11513 #define FLD(f) abuf->fields.sfmt_asrq.f
11514   int UNUSED written = 0;
11515   IADDR UNUSED pc = abuf->addr;
11516   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11517
11518 {
11519   SI tmp_tmpd;
11520   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11521   {
11522     SI opval = tmp_tmpd;
11523     SET_H_GR (FLD (f_operand2), opval);
11524     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11525   }
11526 {
11527   {
11528     BI opval = LTSI (tmp_tmpd, 0);
11529     CPU (h_nbit) = opval;
11530     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11531   }
11532   {
11533     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11534     CPU (h_zbit) = opval;
11535     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11536   }
11537 SET_H_CBIT_MOVE (0);
11538 SET_H_VBIT_MOVE (0);
11539 {
11540   {
11541     BI opval = 0;
11542     CPU (h_xbit) = opval;
11543     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11544   }
11545   {
11546     BI opval = 0;
11547     SET_H_INSN_PREFIXED_P (opval);
11548     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11549   }
11550 }
11551 }
11552 }
11553
11554 #undef FLD
11555 }
11556   NEXT (vpc);
11557
11558   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
11559 {
11560   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11561   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11562 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11563   int UNUSED written = 0;
11564   IADDR UNUSED pc = abuf->addr;
11565   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11566
11567 {
11568   SI tmp_tmpd;
11569   SI tmp_cnt;
11570   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11571   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11572 {
11573   SI tmp_oldregval;
11574   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11575   {
11576     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11577     SET_H_GR (FLD (f_operand2), opval);
11578     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11579   }
11580 }
11581 {
11582   {
11583     BI opval = LTQI (tmp_tmpd, 0);
11584     CPU (h_nbit) = opval;
11585     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11586   }
11587   {
11588     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11589     CPU (h_zbit) = opval;
11590     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11591   }
11592 SET_H_CBIT_MOVE (0);
11593 SET_H_VBIT_MOVE (0);
11594 {
11595   {
11596     BI opval = 0;
11597     CPU (h_xbit) = opval;
11598     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11599   }
11600   {
11601     BI opval = 0;
11602     SET_H_INSN_PREFIXED_P (opval);
11603     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11604   }
11605 }
11606 }
11607 }
11608
11609 #undef FLD
11610 }
11611   NEXT (vpc);
11612
11613   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
11614 {
11615   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11616   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11617 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11618   int UNUSED written = 0;
11619   IADDR UNUSED pc = abuf->addr;
11620   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11621
11622 {
11623   SI tmp_tmpd;
11624   SI tmp_cnt;
11625   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11626   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11627 {
11628   SI tmp_oldregval;
11629   tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
11630   {
11631     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11632     SET_H_GR (FLD (f_operand2), opval);
11633     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11634   }
11635 }
11636 {
11637   {
11638     BI opval = LTHI (tmp_tmpd, 0);
11639     CPU (h_nbit) = opval;
11640     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11641   }
11642   {
11643     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11644     CPU (h_zbit) = opval;
11645     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11646   }
11647 SET_H_CBIT_MOVE (0);
11648 SET_H_VBIT_MOVE (0);
11649 {
11650   {
11651     BI opval = 0;
11652     CPU (h_xbit) = opval;
11653     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11654   }
11655   {
11656     BI opval = 0;
11657     SET_H_INSN_PREFIXED_P (opval);
11658     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11659   }
11660 }
11661 }
11662 }
11663
11664 #undef FLD
11665 }
11666   NEXT (vpc);
11667
11668   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
11669 {
11670   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11671   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11672 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11673   int UNUSED written = 0;
11674   IADDR UNUSED pc = abuf->addr;
11675   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11676
11677 {
11678   SI tmp_tmpd;
11679   SI tmp_cnt;
11680   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11681   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11682   {
11683     SI opval = tmp_tmpd;
11684     SET_H_GR (FLD (f_operand2), opval);
11685     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11686   }
11687 {
11688   {
11689     BI opval = LTSI (tmp_tmpd, 0);
11690     CPU (h_nbit) = opval;
11691     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11692   }
11693   {
11694     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11695     CPU (h_zbit) = opval;
11696     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11697   }
11698 SET_H_CBIT_MOVE (0);
11699 SET_H_VBIT_MOVE (0);
11700 {
11701   {
11702     BI opval = 0;
11703     CPU (h_xbit) = opval;
11704     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11705   }
11706   {
11707     BI opval = 0;
11708     SET_H_INSN_PREFIXED_P (opval);
11709     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11710   }
11711 }
11712 }
11713 }
11714
11715 #undef FLD
11716 }
11717   NEXT (vpc);
11718
11719   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
11720 {
11721   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11722   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11723 #define FLD(f) abuf->fields.sfmt_asrq.f
11724   int UNUSED written = 0;
11725   IADDR UNUSED pc = abuf->addr;
11726   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11727
11728 {
11729   SI tmp_tmpd;
11730   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11731   {
11732     SI opval = tmp_tmpd;
11733     SET_H_GR (FLD (f_operand2), opval);
11734     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11735   }
11736 {
11737   {
11738     BI opval = LTSI (tmp_tmpd, 0);
11739     CPU (h_nbit) = opval;
11740     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11741   }
11742   {
11743     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11744     CPU (h_zbit) = opval;
11745     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11746   }
11747 SET_H_CBIT_MOVE (0);
11748 SET_H_VBIT_MOVE (0);
11749 {
11750   {
11751     BI opval = 0;
11752     CPU (h_xbit) = opval;
11753     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11754   }
11755   {
11756     BI opval = 0;
11757     SET_H_INSN_PREFIXED_P (opval);
11758     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11759   }
11760 }
11761 }
11762 }
11763
11764 #undef FLD
11765 }
11766   NEXT (vpc);
11767
11768   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
11769 {
11770   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11771   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11772 #define FLD(f) abuf->fields.sfmt_add_b_r.f
11773   int UNUSED written = 0;
11774   IADDR UNUSED pc = abuf->addr;
11775   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11776
11777 {
11778   SI tmp_tmpd;
11779   SI tmp_cnt;
11780   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
11781 {
11782   {
11783     BI opval = LTSI (tmp_tmpd, 0);
11784     CPU (h_nbit) = opval;
11785     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11786   }
11787   {
11788     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11789     CPU (h_zbit) = opval;
11790     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11791   }
11792 SET_H_CBIT_MOVE (0);
11793 SET_H_VBIT_MOVE (0);
11794 {
11795   {
11796     BI opval = 0;
11797     CPU (h_xbit) = opval;
11798     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11799   }
11800   {
11801     BI opval = 0;
11802     SET_H_INSN_PREFIXED_P (opval);
11803     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11804   }
11805 }
11806 }
11807 }
11808
11809 #undef FLD
11810 }
11811   NEXT (vpc);
11812
11813   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
11814 {
11815   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11816   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11817 #define FLD(f) abuf->fields.sfmt_asrq.f
11818   int UNUSED written = 0;
11819   IADDR UNUSED pc = abuf->addr;
11820   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11821
11822 {
11823   SI tmp_tmpd;
11824   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
11825 {
11826   {
11827     BI opval = LTSI (tmp_tmpd, 0);
11828     CPU (h_nbit) = opval;
11829     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11830   }
11831   {
11832     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11833     CPU (h_zbit) = opval;
11834     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11835   }
11836 SET_H_CBIT_MOVE (0);
11837 SET_H_VBIT_MOVE (0);
11838 {
11839   {
11840     BI opval = 0;
11841     CPU (h_xbit) = opval;
11842     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11843   }
11844   {
11845     BI opval = 0;
11846     SET_H_INSN_PREFIXED_P (opval);
11847     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11848   }
11849 }
11850 }
11851 }
11852
11853 #undef FLD
11854 }
11855   NEXT (vpc);
11856
11857   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
11858 {
11859   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11860   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11861 #define FLD(f) abuf->fields.sfmt_setf.f
11862   int UNUSED written = 0;
11863   IADDR UNUSED pc = abuf->addr;
11864   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11865
11866 {
11867   SI tmp_tmp;
11868   tmp_tmp = FLD (f_dstsrc);
11869 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
11870   {
11871     BI opval = 1;
11872     CPU (h_cbit) = opval;
11873     written |= (1 << 1);
11874     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
11875   }
11876 }
11877 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
11878   {
11879     BI opval = 1;
11880     CPU (h_vbit) = opval;
11881     written |= (1 << 7);
11882     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
11883   }
11884 }
11885 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
11886   {
11887     BI opval = 1;
11888     CPU (h_zbit) = opval;
11889     written |= (1 << 9);
11890     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11891   }
11892 }
11893 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
11894   {
11895     BI opval = 1;
11896     CPU (h_nbit) = opval;
11897     written |= (1 << 3);
11898     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11899   }
11900 }
11901 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11902   {
11903     BI opval = 1;
11904     CPU (h_xbit) = opval;
11905     written |= (1 << 8);
11906     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11907   }
11908 }
11909 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
11910   {
11911     BI opval = 1;
11912     SET_H_IBIT (opval);
11913     written |= (1 << 2);
11914     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
11915   }
11916 }
11917 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
11918   {
11919     BI opval = 1;
11920     SET_H_UBIT (opval);
11921     written |= (1 << 6);
11922     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
11923   }
11924 }
11925 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
11926   {
11927     BI opval = 1;
11928     CPU (h_pbit) = opval;
11929     written |= (1 << 4);
11930     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
11931   }
11932 }
11933   {
11934     BI opval = 0;
11935     SET_H_INSN_PREFIXED_P (opval);
11936     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11937   }
11938 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11939   {
11940     BI opval = 0;
11941     CPU (h_xbit) = opval;
11942     written |= (1 << 8);
11943     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11944   }
11945 }
11946 }
11947
11948   abuf->written = written;
11949 #undef FLD
11950 }
11951   NEXT (vpc);
11952
11953   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
11954 {
11955   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11956   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11957 #define FLD(f) abuf->fields.sfmt_setf.f
11958   int UNUSED written = 0;
11959   IADDR UNUSED pc = abuf->addr;
11960   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11961
11962 {
11963   SI tmp_tmp;
11964   tmp_tmp = FLD (f_dstsrc);
11965 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
11966   {
11967     BI opval = 0;
11968     CPU (h_cbit) = opval;
11969     written |= (1 << 1);
11970     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
11971   }
11972 }
11973 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
11974   {
11975     BI opval = 0;
11976     CPU (h_vbit) = opval;
11977     written |= (1 << 7);
11978     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
11979   }
11980 }
11981 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
11982   {
11983     BI opval = 0;
11984     CPU (h_zbit) = opval;
11985     written |= (1 << 9);
11986     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11987   }
11988 }
11989 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
11990   {
11991     BI opval = 0;
11992     CPU (h_nbit) = opval;
11993     written |= (1 << 3);
11994     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11995   }
11996 }
11997 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
11998   {
11999     BI opval = 0;
12000     CPU (h_xbit) = opval;
12001     written |= (1 << 8);
12002     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12003   }
12004 }
12005 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12006   {
12007     BI opval = 0;
12008     SET_H_IBIT (opval);
12009     written |= (1 << 2);
12010     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12011   }
12012 }
12013 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12014   {
12015     BI opval = 0;
12016     SET_H_UBIT (opval);
12017     written |= (1 << 6);
12018     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12019   }
12020 }
12021 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12022   {
12023     BI opval = 0;
12024     CPU (h_pbit) = opval;
12025     written |= (1 << 4);
12026     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12027   }
12028 }
12029 {
12030   {
12031     BI opval = 0;
12032     CPU (h_xbit) = opval;
12033     written |= (1 << 8);
12034     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12035   }
12036   {
12037     BI opval = 0;
12038     SET_H_INSN_PREFIXED_P (opval);
12039     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12040   }
12041 }
12042 }
12043
12044   abuf->written = written;
12045 #undef FLD
12046 }
12047   NEXT (vpc);
12048
12049   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12050 {
12051   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12052   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12053 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12054   int UNUSED written = 0;
12055   IADDR UNUSED pc = abuf->addr;
12056   SEM_BRANCH_INIT
12057   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12058
12059 {
12060   BI tmp_truthval;
12061   tmp_truthval = ({   SI tmp_tmpcond;
12062   BI tmp_condres;
12063   tmp_tmpcond = FLD (f_operand2);
12064 ; if (EQSI (tmp_tmpcond, 0)) {
12065   tmp_condres = NOTBI (CPU (h_cbit));
12066 }
12067  else if (EQSI (tmp_tmpcond, 1)) {
12068   tmp_condres = CPU (h_cbit);
12069 }
12070  else if (EQSI (tmp_tmpcond, 2)) {
12071   tmp_condres = NOTBI (CPU (h_zbit));
12072 }
12073  else if (EQSI (tmp_tmpcond, 3)) {
12074   tmp_condres = CPU (h_zbit);
12075 }
12076  else if (EQSI (tmp_tmpcond, 4)) {
12077   tmp_condres = NOTBI (CPU (h_vbit));
12078 }
12079  else if (EQSI (tmp_tmpcond, 5)) {
12080   tmp_condres = CPU (h_vbit);
12081 }
12082  else if (EQSI (tmp_tmpcond, 6)) {
12083   tmp_condres = NOTBI (CPU (h_nbit));
12084 }
12085  else if (EQSI (tmp_tmpcond, 7)) {
12086   tmp_condres = CPU (h_nbit);
12087 }
12088  else if (EQSI (tmp_tmpcond, 8)) {
12089   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12090 }
12091  else if (EQSI (tmp_tmpcond, 9)) {
12092   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12093 }
12094  else if (EQSI (tmp_tmpcond, 10)) {
12095   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12096 }
12097  else if (EQSI (tmp_tmpcond, 11)) {
12098   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12099 }
12100  else if (EQSI (tmp_tmpcond, 12)) {
12101   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12102 }
12103  else if (EQSI (tmp_tmpcond, 13)) {
12104   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12105 }
12106  else if (EQSI (tmp_tmpcond, 14)) {
12107   tmp_condres = 1;
12108 }
12109  else if (EQSI (tmp_tmpcond, 15)) {
12110   tmp_condres = CPU (h_pbit);
12111 }
12112 ; tmp_condres; });
12113 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12114 {
12115   {
12116     BI opval = 0;
12117     CPU (h_xbit) = opval;
12118     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12119   }
12120   {
12121     BI opval = 0;
12122     SET_H_INSN_PREFIXED_P (opval);
12123     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12124   }
12125 }
12126 if (tmp_truthval) {
12127 {
12128   {
12129     USI opval = FLD (i_o_pcrel);
12130     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12131     written |= (1 << 8);
12132     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12133   }
12134 }
12135 }
12136 }
12137
12138   abuf->written = written;
12139   SEM_BRANCH_FINI (vpc);
12140 #undef FLD
12141 }
12142   NEXT (vpc);
12143
12144   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12145 {
12146   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12147   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12148 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12149   int UNUSED written = 0;
12150   IADDR UNUSED pc = abuf->addr;
12151   SEM_BRANCH_INIT
12152   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12153
12154 {
12155 {
12156   {
12157     BI opval = 0;
12158     CPU (h_xbit) = opval;
12159     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12160   }
12161   {
12162     BI opval = 0;
12163     SET_H_INSN_PREFIXED_P (opval);
12164     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12165   }
12166 }
12167 {
12168   {
12169     USI opval = FLD (i_o_pcrel);
12170     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12171     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12172   }
12173 }
12174 }
12175
12176   SEM_BRANCH_FINI (vpc);
12177 #undef FLD
12178 }
12179   NEXT (vpc);
12180
12181   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12182 {
12183   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12184   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12185 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12186   int UNUSED written = 0;
12187   IADDR UNUSED pc = abuf->addr;
12188   SEM_BRANCH_INIT
12189   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12190
12191 {
12192   BI tmp_truthval;
12193   tmp_truthval = ({   SI tmp_tmpcond;
12194   BI tmp_condres;
12195   tmp_tmpcond = FLD (f_operand2);
12196 ; if (EQSI (tmp_tmpcond, 0)) {
12197   tmp_condres = NOTBI (CPU (h_cbit));
12198 }
12199  else if (EQSI (tmp_tmpcond, 1)) {
12200   tmp_condres = CPU (h_cbit);
12201 }
12202  else if (EQSI (tmp_tmpcond, 2)) {
12203   tmp_condres = NOTBI (CPU (h_zbit));
12204 }
12205  else if (EQSI (tmp_tmpcond, 3)) {
12206   tmp_condres = CPU (h_zbit);
12207 }
12208  else if (EQSI (tmp_tmpcond, 4)) {
12209   tmp_condres = NOTBI (CPU (h_vbit));
12210 }
12211  else if (EQSI (tmp_tmpcond, 5)) {
12212   tmp_condres = CPU (h_vbit);
12213 }
12214  else if (EQSI (tmp_tmpcond, 6)) {
12215   tmp_condres = NOTBI (CPU (h_nbit));
12216 }
12217  else if (EQSI (tmp_tmpcond, 7)) {
12218   tmp_condres = CPU (h_nbit);
12219 }
12220  else if (EQSI (tmp_tmpcond, 8)) {
12221   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12222 }
12223  else if (EQSI (tmp_tmpcond, 9)) {
12224   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12225 }
12226  else if (EQSI (tmp_tmpcond, 10)) {
12227   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12228 }
12229  else if (EQSI (tmp_tmpcond, 11)) {
12230   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12231 }
12232  else if (EQSI (tmp_tmpcond, 12)) {
12233   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12234 }
12235  else if (EQSI (tmp_tmpcond, 13)) {
12236   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12237 }
12238  else if (EQSI (tmp_tmpcond, 14)) {
12239   tmp_condres = 1;
12240 }
12241  else if (EQSI (tmp_tmpcond, 15)) {
12242   tmp_condres = CPU (h_pbit);
12243 }
12244 ; tmp_condres; });
12245 crisv10f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12246 {
12247   {
12248     BI opval = 0;
12249     CPU (h_xbit) = opval;
12250     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12251   }
12252   {
12253     BI opval = 0;
12254     SET_H_INSN_PREFIXED_P (opval);
12255     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12256   }
12257 }
12258 if (tmp_truthval) {
12259 {
12260   {
12261     USI opval = FLD (i_o_word_pcrel);
12262     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12263     written |= (1 << 8);
12264     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12265   }
12266 }
12267 }
12268 }
12269
12270   abuf->written = written;
12271   SEM_BRANCH_FINI (vpc);
12272 #undef FLD
12273 }
12274   NEXT (vpc);
12275
12276   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12277 {
12278   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12279   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12280 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12281   int UNUSED written = 0;
12282   IADDR UNUSED pc = abuf->addr;
12283   SEM_BRANCH_INIT
12284   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12285
12286 {
12287 {
12288   {
12289     BI opval = 0;
12290     CPU (h_xbit) = opval;
12291     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12292   }
12293   {
12294     BI opval = 0;
12295     SET_H_INSN_PREFIXED_P (opval);
12296     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12297   }
12298 }
12299 {
12300   {
12301     USI opval = FLD (i_o_word_pcrel);
12302     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12303     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12304   }
12305 }
12306 }
12307
12308   SEM_BRANCH_FINI (vpc);
12309 #undef FLD
12310 }
12311   NEXT (vpc);
12312
12313   CASE (sem, INSN_JUMP_R) : /* jump/jsr/jir ${Rs} */
12314 {
12315   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12316   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12317 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12318   int UNUSED written = 0;
12319   IADDR UNUSED pc = abuf->addr;
12320   SEM_BRANCH_INIT
12321   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12322
12323 {
12324   {
12325     SI opval = ADDSI (pc, 2);
12326     SET_H_SR (FLD (f_operand2), opval);
12327     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12328   }
12329   {
12330     USI opval = GET_H_GR (FLD (f_operand1));
12331     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12332     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12333   }
12334 {
12335   {
12336     BI opval = 0;
12337     CPU (h_xbit) = opval;
12338     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12339   }
12340   {
12341     BI opval = 0;
12342     SET_H_INSN_PREFIXED_P (opval);
12343     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12344   }
12345 }
12346 }
12347
12348   SEM_BRANCH_FINI (vpc);
12349 #undef FLD
12350 }
12351   NEXT (vpc);
12352
12353   CASE (sem, INSN_JUMP_M) : /* jump/jsr/jir [${Rs}${inc}] */
12354 {
12355   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12356   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12357 #define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
12358   int UNUSED written = 0;
12359   IADDR UNUSED pc = abuf->addr;
12360   SEM_BRANCH_INIT
12361   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12362
12363 {
12364   {
12365     SI opval = ADDSI (pc, 2);
12366     SET_H_SR (FLD (f_operand2), opval);
12367     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12368   }
12369   {
12370     USI opval = ({   SI tmp_addr;
12371   SI tmp_tmp_mem;
12372   BI tmp_postinc;
12373   tmp_postinc = FLD (f_memmode);
12374 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12375 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
12376 ; if (NEBI (tmp_postinc, 0)) {
12377 {
12378 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12379   tmp_addr = ADDSI (tmp_addr, 4);
12380 }
12381   {
12382     SI opval = tmp_addr;
12383     SET_H_GR (FLD (f_operand1), opval);
12384     written |= (1 << 7);
12385     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12386   }
12387 }
12388 }
12389 ; tmp_tmp_mem; });
12390     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12391     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12392   }
12393 {
12394   {
12395     BI opval = 0;
12396     CPU (h_xbit) = opval;
12397     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12398   }
12399   {
12400     BI opval = 0;
12401     SET_H_INSN_PREFIXED_P (opval);
12402     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12403   }
12404 }
12405 }
12406
12407   abuf->written = written;
12408   SEM_BRANCH_FINI (vpc);
12409 #undef FLD
12410 }
12411   NEXT (vpc);
12412
12413   CASE (sem, INSN_JUMP_C) : /* jump/jsr/jir ${const32} */
12414 {
12415   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12416   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12417 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
12418   int UNUSED written = 0;
12419   IADDR UNUSED pc = abuf->addr;
12420   SEM_BRANCH_INIT
12421   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12422
12423 {
12424   {
12425     SI opval = ADDSI (pc, 6);
12426     SET_H_SR (FLD (f_operand2), opval);
12427     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12428   }
12429   {
12430     USI opval = FLD (f_indir_pc__dword);
12431     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12432     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12433   }
12434 {
12435   {
12436     BI opval = 0;
12437     CPU (h_xbit) = opval;
12438     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12439   }
12440   {
12441     BI opval = 0;
12442     SET_H_INSN_PREFIXED_P (opval);
12443     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12444   }
12445 }
12446 }
12447
12448   SEM_BRANCH_FINI (vpc);
12449 #undef FLD
12450 }
12451   NEXT (vpc);
12452
12453   CASE (sem, INSN_BREAK) : /* break $n */
12454 {
12455   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12456   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12457 #define FLD(f) abuf->fields.sfmt_break.f
12458   int UNUSED written = 0;
12459   IADDR UNUSED pc = abuf->addr;
12460   SEM_BRANCH_INIT
12461   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12462
12463 {
12464 {
12465   {
12466     BI opval = 0;
12467     CPU (h_xbit) = opval;
12468     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12469   }
12470   {
12471     BI opval = 0;
12472     SET_H_INSN_PREFIXED_P (opval);
12473     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12474   }
12475 }
12476   {
12477     USI opval = crisv10f_break_handler (current_cpu, FLD (f_u4), pc);
12478     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12479     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12480   }
12481 }
12482
12483   SEM_BRANCH_FINI (vpc);
12484 #undef FLD
12485 }
12486   NEXT (vpc);
12487
12488   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
12489 {
12490   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12491   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12492 #define FLD(f) abuf->fields.sfmt_muls_b.f
12493   int UNUSED written = 0;
12494   IADDR UNUSED pc = abuf->addr;
12495   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12496
12497 {
12498   SI tmp_tmpopd;
12499   SI tmp_tmpops;
12500   SI tmp_newval;
12501   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
12502   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12503   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12504   {
12505     SI opval = tmp_newval;
12506     SET_H_GR (FLD (f_operand2), opval);
12507     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12508   }
12509 {
12510   {
12511     BI opval = LTSI (tmp_newval, 0);
12512     CPU (h_nbit) = opval;
12513     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12514   }
12515   {
12516     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12517     CPU (h_zbit) = opval;
12518     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12519   }
12520 SET_H_CBIT_MOVE (0);
12521 SET_H_VBIT_MOVE (0);
12522 {
12523   {
12524     BI opval = 0;
12525     CPU (h_xbit) = opval;
12526     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12527   }
12528   {
12529     BI opval = 0;
12530     SET_H_INSN_PREFIXED_P (opval);
12531     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12532   }
12533 }
12534 }
12535 }
12536
12537 #undef FLD
12538 }
12539   NEXT (vpc);
12540
12541   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
12542 {
12543   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12544   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12545 #define FLD(f) abuf->fields.sfmt_muls_b.f
12546   int UNUSED written = 0;
12547   IADDR UNUSED pc = abuf->addr;
12548   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12549
12550 {
12551   SI tmp_tmpopd;
12552   SI tmp_tmpops;
12553   SI tmp_newval;
12554   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
12555   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12556   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12557   {
12558     SI opval = tmp_newval;
12559     SET_H_GR (FLD (f_operand2), opval);
12560     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12561   }
12562 {
12563   {
12564     BI opval = LTSI (tmp_newval, 0);
12565     CPU (h_nbit) = opval;
12566     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12567   }
12568   {
12569     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12570     CPU (h_zbit) = opval;
12571     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12572   }
12573 SET_H_CBIT_MOVE (0);
12574 SET_H_VBIT_MOVE (0);
12575 {
12576   {
12577     BI opval = 0;
12578     CPU (h_xbit) = opval;
12579     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12580   }
12581   {
12582     BI opval = 0;
12583     SET_H_INSN_PREFIXED_P (opval);
12584     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12585   }
12586 }
12587 }
12588 }
12589
12590 #undef FLD
12591 }
12592   NEXT (vpc);
12593
12594   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
12595 {
12596   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12597   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12598 #define FLD(f) abuf->fields.sfmt_muls_b.f
12599   int UNUSED written = 0;
12600   IADDR UNUSED pc = abuf->addr;
12601   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12602
12603 {
12604   SI tmp_tmpopd;
12605   SI tmp_tmpops;
12606   SI tmp_newval;
12607   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
12608   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12609   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12610   {
12611     SI opval = tmp_newval;
12612     SET_H_GR (FLD (f_operand2), opval);
12613     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12614   }
12615 {
12616   {
12617     BI opval = LTSI (tmp_newval, 0);
12618     CPU (h_nbit) = opval;
12619     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12620   }
12621   {
12622     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12623     CPU (h_zbit) = opval;
12624     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12625   }
12626 SET_H_CBIT_MOVE (0);
12627 SET_H_VBIT_MOVE (0);
12628 {
12629   {
12630     BI opval = 0;
12631     CPU (h_xbit) = opval;
12632     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12633   }
12634   {
12635     BI opval = 0;
12636     SET_H_INSN_PREFIXED_P (opval);
12637     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12638   }
12639 }
12640 }
12641 }
12642
12643 #undef FLD
12644 }
12645   NEXT (vpc);
12646
12647   CASE (sem, INSN_BOUND_M_B_M) : /* bound-m.b [${Rs}${inc}],${Rd} */
12648 {
12649   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12650   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12651 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12652   int UNUSED written = 0;
12653   IADDR UNUSED pc = abuf->addr;
12654   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12655
12656 {
12657   SI tmp_tmpopd;
12658   SI tmp_tmpops;
12659   SI tmp_newval;
12660   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
12661   QI tmp_tmp_mem;
12662   BI tmp_postinc;
12663   tmp_postinc = FLD (f_memmode);
12664 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12665 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
12666 ; if (NEBI (tmp_postinc, 0)) {
12667 {
12668 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12669   tmp_addr = ADDSI (tmp_addr, 1);
12670 }
12671   {
12672     SI opval = tmp_addr;
12673     SET_H_GR (FLD (f_operand1), opval);
12674     written |= (1 << 9);
12675     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12676   }
12677 }
12678 }
12679 ; tmp_tmp_mem; }));
12680   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12681   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12682 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12683   {
12684     SI opval = tmp_newval;
12685     SET_H_GR (FLD (f_operand1), opval);
12686     written |= (1 << 9);
12687     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12688   }
12689 } else {
12690   {
12691     SI opval = tmp_newval;
12692     SET_H_GR (FLD (f_operand2), opval);
12693     written |= (1 << 8);
12694     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12695   }
12696 }
12697 {
12698   {
12699     BI opval = LTSI (tmp_newval, 0);
12700     CPU (h_nbit) = opval;
12701     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12702   }
12703   {
12704     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12705     CPU (h_zbit) = opval;
12706     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12707   }
12708 SET_H_CBIT_MOVE (0);
12709 SET_H_VBIT_MOVE (0);
12710 {
12711   {
12712     BI opval = 0;
12713     CPU (h_xbit) = opval;
12714     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12715   }
12716   {
12717     BI opval = 0;
12718     SET_H_INSN_PREFIXED_P (opval);
12719     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12720   }
12721 }
12722 }
12723 }
12724
12725   abuf->written = written;
12726 #undef FLD
12727 }
12728   NEXT (vpc);
12729
12730   CASE (sem, INSN_BOUND_M_W_M) : /* bound-m.w [${Rs}${inc}],${Rd} */
12731 {
12732   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12733   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12734 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12735   int UNUSED written = 0;
12736   IADDR UNUSED pc = abuf->addr;
12737   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12738
12739 {
12740   SI tmp_tmpopd;
12741   SI tmp_tmpops;
12742   SI tmp_newval;
12743   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
12744   HI tmp_tmp_mem;
12745   BI tmp_postinc;
12746   tmp_postinc = FLD (f_memmode);
12747 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12748 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
12749 ; if (NEBI (tmp_postinc, 0)) {
12750 {
12751 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12752   tmp_addr = ADDSI (tmp_addr, 2);
12753 }
12754   {
12755     SI opval = tmp_addr;
12756     SET_H_GR (FLD (f_operand1), opval);
12757     written |= (1 << 9);
12758     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12759   }
12760 }
12761 }
12762 ; tmp_tmp_mem; }));
12763   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12764   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12765 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12766   {
12767     SI opval = tmp_newval;
12768     SET_H_GR (FLD (f_operand1), opval);
12769     written |= (1 << 9);
12770     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12771   }
12772 } else {
12773   {
12774     SI opval = tmp_newval;
12775     SET_H_GR (FLD (f_operand2), opval);
12776     written |= (1 << 8);
12777     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12778   }
12779 }
12780 {
12781   {
12782     BI opval = LTSI (tmp_newval, 0);
12783     CPU (h_nbit) = opval;
12784     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12785   }
12786   {
12787     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12788     CPU (h_zbit) = opval;
12789     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12790   }
12791 SET_H_CBIT_MOVE (0);
12792 SET_H_VBIT_MOVE (0);
12793 {
12794   {
12795     BI opval = 0;
12796     CPU (h_xbit) = opval;
12797     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12798   }
12799   {
12800     BI opval = 0;
12801     SET_H_INSN_PREFIXED_P (opval);
12802     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12803   }
12804 }
12805 }
12806 }
12807
12808   abuf->written = written;
12809 #undef FLD
12810 }
12811   NEXT (vpc);
12812
12813   CASE (sem, INSN_BOUND_M_D_M) : /* bound-m.d [${Rs}${inc}],${Rd} */
12814 {
12815   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12816   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12817 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
12818   int UNUSED written = 0;
12819   IADDR UNUSED pc = abuf->addr;
12820   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12821
12822 {
12823   SI tmp_tmpopd;
12824   SI tmp_tmpops;
12825   SI tmp_newval;
12826   tmp_tmpops = ({   SI tmp_addr;
12827   SI tmp_tmp_mem;
12828   BI tmp_postinc;
12829   tmp_postinc = FLD (f_memmode);
12830 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
12831 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
12832 ; if (NEBI (tmp_postinc, 0)) {
12833 {
12834 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
12835   tmp_addr = ADDSI (tmp_addr, 4);
12836 }
12837   {
12838     SI opval = tmp_addr;
12839     SET_H_GR (FLD (f_operand1), opval);
12840     written |= (1 << 9);
12841     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12842   }
12843 }
12844 }
12845 ; tmp_tmp_mem; });
12846   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12847   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12848 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
12849   {
12850     SI opval = tmp_newval;
12851     SET_H_GR (FLD (f_operand1), opval);
12852     written |= (1 << 9);
12853     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12854   }
12855 } else {
12856   {
12857     SI opval = tmp_newval;
12858     SET_H_GR (FLD (f_operand2), opval);
12859     written |= (1 << 8);
12860     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12861   }
12862 }
12863 {
12864   {
12865     BI opval = LTSI (tmp_newval, 0);
12866     CPU (h_nbit) = opval;
12867     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12868   }
12869   {
12870     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12871     CPU (h_zbit) = opval;
12872     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12873   }
12874 SET_H_CBIT_MOVE (0);
12875 SET_H_VBIT_MOVE (0);
12876 {
12877   {
12878     BI opval = 0;
12879     CPU (h_xbit) = opval;
12880     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12881   }
12882   {
12883     BI opval = 0;
12884     SET_H_INSN_PREFIXED_P (opval);
12885     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12886   }
12887 }
12888 }
12889 }
12890
12891   abuf->written = written;
12892 #undef FLD
12893 }
12894   NEXT (vpc);
12895
12896   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
12897 {
12898   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12899   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12900 #define FLD(f) abuf->fields.sfmt_bound_cb.f
12901   int UNUSED written = 0;
12902   IADDR UNUSED pc = abuf->addr;
12903   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12904
12905 {
12906   SI tmp_tmpopd;
12907   SI tmp_tmpops;
12908   SI tmp_newval;
12909   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
12910   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12911   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12912   {
12913     SI opval = tmp_newval;
12914     SET_H_GR (FLD (f_operand2), opval);
12915     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12916   }
12917 {
12918   {
12919     BI opval = LTSI (tmp_newval, 0);
12920     CPU (h_nbit) = opval;
12921     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12922   }
12923   {
12924     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12925     CPU (h_zbit) = opval;
12926     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12927   }
12928 SET_H_CBIT_MOVE (0);
12929 SET_H_VBIT_MOVE (0);
12930 {
12931   {
12932     BI opval = 0;
12933     CPU (h_xbit) = opval;
12934     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12935   }
12936   {
12937     BI opval = 0;
12938     SET_H_INSN_PREFIXED_P (opval);
12939     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12940   }
12941 }
12942 }
12943 }
12944
12945 #undef FLD
12946 }
12947   NEXT (vpc);
12948
12949   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
12950 {
12951   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12952   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12953 #define FLD(f) abuf->fields.sfmt_bound_cw.f
12954   int UNUSED written = 0;
12955   IADDR UNUSED pc = abuf->addr;
12956   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12957
12958 {
12959   SI tmp_tmpopd;
12960   SI tmp_tmpops;
12961   SI tmp_newval;
12962   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
12963   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
12964   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
12965   {
12966     SI opval = tmp_newval;
12967     SET_H_GR (FLD (f_operand2), opval);
12968     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12969   }
12970 {
12971   {
12972     BI opval = LTSI (tmp_newval, 0);
12973     CPU (h_nbit) = opval;
12974     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12975   }
12976   {
12977     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12978     CPU (h_zbit) = opval;
12979     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12980   }
12981 SET_H_CBIT_MOVE (0);
12982 SET_H_VBIT_MOVE (0);
12983 {
12984   {
12985     BI opval = 0;
12986     CPU (h_xbit) = opval;
12987     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12988   }
12989   {
12990     BI opval = 0;
12991     SET_H_INSN_PREFIXED_P (opval);
12992     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12993   }
12994 }
12995 }
12996 }
12997
12998 #undef FLD
12999 }
13000   NEXT (vpc);
13001
13002   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13003 {
13004   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13006 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13007   int UNUSED written = 0;
13008   IADDR UNUSED pc = abuf->addr;
13009   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13010
13011 {
13012   SI tmp_tmpopd;
13013   SI tmp_tmpops;
13014   SI tmp_newval;
13015   tmp_tmpops = FLD (f_indir_pc__dword);
13016   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13017   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13018   {
13019     SI opval = tmp_newval;
13020     SET_H_GR (FLD (f_operand2), opval);
13021     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13022   }
13023 {
13024   {
13025     BI opval = LTSI (tmp_newval, 0);
13026     CPU (h_nbit) = opval;
13027     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13028   }
13029   {
13030     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13031     CPU (h_zbit) = opval;
13032     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13033   }
13034 SET_H_CBIT_MOVE (0);
13035 SET_H_VBIT_MOVE (0);
13036 {
13037   {
13038     BI opval = 0;
13039     CPU (h_xbit) = opval;
13040     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13041   }
13042   {
13043     BI opval = 0;
13044     SET_H_INSN_PREFIXED_P (opval);
13045     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13046   }
13047 }
13048 }
13049 }
13050
13051 #undef FLD
13052 }
13053   NEXT (vpc);
13054
13055   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13056 {
13057   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13058   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13059 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13060   int UNUSED written = 0;
13061   IADDR UNUSED pc = abuf->addr;
13062   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13063
13064 {
13065   BI tmp_truthval;
13066   tmp_truthval = ({   SI tmp_tmpcond;
13067   BI tmp_condres;
13068   tmp_tmpcond = FLD (f_operand2);
13069 ; if (EQSI (tmp_tmpcond, 0)) {
13070   tmp_condres = NOTBI (CPU (h_cbit));
13071 }
13072  else if (EQSI (tmp_tmpcond, 1)) {
13073   tmp_condres = CPU (h_cbit);
13074 }
13075  else if (EQSI (tmp_tmpcond, 2)) {
13076   tmp_condres = NOTBI (CPU (h_zbit));
13077 }
13078  else if (EQSI (tmp_tmpcond, 3)) {
13079   tmp_condres = CPU (h_zbit);
13080 }
13081  else if (EQSI (tmp_tmpcond, 4)) {
13082   tmp_condres = NOTBI (CPU (h_vbit));
13083 }
13084  else if (EQSI (tmp_tmpcond, 5)) {
13085   tmp_condres = CPU (h_vbit);
13086 }
13087  else if (EQSI (tmp_tmpcond, 6)) {
13088   tmp_condres = NOTBI (CPU (h_nbit));
13089 }
13090  else if (EQSI (tmp_tmpcond, 7)) {
13091   tmp_condres = CPU (h_nbit);
13092 }
13093  else if (EQSI (tmp_tmpcond, 8)) {
13094   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13095 }
13096  else if (EQSI (tmp_tmpcond, 9)) {
13097   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13098 }
13099  else if (EQSI (tmp_tmpcond, 10)) {
13100   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13101 }
13102  else if (EQSI (tmp_tmpcond, 11)) {
13103   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13104 }
13105  else if (EQSI (tmp_tmpcond, 12)) {
13106   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13107 }
13108  else if (EQSI (tmp_tmpcond, 13)) {
13109   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13110 }
13111  else if (EQSI (tmp_tmpcond, 14)) {
13112   tmp_condres = 1;
13113 }
13114  else if (EQSI (tmp_tmpcond, 15)) {
13115   tmp_condres = CPU (h_pbit);
13116 }
13117 ; tmp_condres; });
13118   {
13119     SI opval = ZEXTBISI (tmp_truthval);
13120     SET_H_GR (FLD (f_operand1), opval);
13121     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13122   }
13123 {
13124   {
13125     BI opval = 0;
13126     CPU (h_xbit) = opval;
13127     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13128   }
13129   {
13130     BI opval = 0;
13131     SET_H_INSN_PREFIXED_P (opval);
13132     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13133   }
13134 }
13135 }
13136
13137 #undef FLD
13138 }
13139   NEXT (vpc);
13140
13141   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13142 {
13143   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13144   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13145 #define FLD(f) abuf->fields.sfmt_muls_b.f
13146   int UNUSED written = 0;
13147   IADDR UNUSED pc = abuf->addr;
13148   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13149
13150 {
13151   SI tmp_tmpd;
13152   SI tmp_tmp;
13153   tmp_tmp = GET_H_GR (FLD (f_operand1));
13154   tmp_tmpd = 0;
13155 {
13156 if (GESI (tmp_tmp, 0)) {
13157 {
13158   tmp_tmp = SLLSI (tmp_tmp, 1);
13159   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13160 }
13161 }
13162 if (GESI (tmp_tmp, 0)) {
13163 {
13164   tmp_tmp = SLLSI (tmp_tmp, 1);
13165   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13166 }
13167 }
13168 if (GESI (tmp_tmp, 0)) {
13169 {
13170   tmp_tmp = SLLSI (tmp_tmp, 1);
13171   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13172 }
13173 }
13174 if (GESI (tmp_tmp, 0)) {
13175 {
13176   tmp_tmp = SLLSI (tmp_tmp, 1);
13177   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13178 }
13179 }
13180 if (GESI (tmp_tmp, 0)) {
13181 {
13182   tmp_tmp = SLLSI (tmp_tmp, 1);
13183   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13184 }
13185 }
13186 if (GESI (tmp_tmp, 0)) {
13187 {
13188   tmp_tmp = SLLSI (tmp_tmp, 1);
13189   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13190 }
13191 }
13192 if (GESI (tmp_tmp, 0)) {
13193 {
13194   tmp_tmp = SLLSI (tmp_tmp, 1);
13195   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13196 }
13197 }
13198 if (GESI (tmp_tmp, 0)) {
13199 {
13200   tmp_tmp = SLLSI (tmp_tmp, 1);
13201   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13202 }
13203 }
13204 if (GESI (tmp_tmp, 0)) {
13205 {
13206   tmp_tmp = SLLSI (tmp_tmp, 1);
13207   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13208 }
13209 }
13210 if (GESI (tmp_tmp, 0)) {
13211 {
13212   tmp_tmp = SLLSI (tmp_tmp, 1);
13213   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13214 }
13215 }
13216 if (GESI (tmp_tmp, 0)) {
13217 {
13218   tmp_tmp = SLLSI (tmp_tmp, 1);
13219   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13220 }
13221 }
13222 if (GESI (tmp_tmp, 0)) {
13223 {
13224   tmp_tmp = SLLSI (tmp_tmp, 1);
13225   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13226 }
13227 }
13228 if (GESI (tmp_tmp, 0)) {
13229 {
13230   tmp_tmp = SLLSI (tmp_tmp, 1);
13231   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13232 }
13233 }
13234 if (GESI (tmp_tmp, 0)) {
13235 {
13236   tmp_tmp = SLLSI (tmp_tmp, 1);
13237   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13238 }
13239 }
13240 if (GESI (tmp_tmp, 0)) {
13241 {
13242   tmp_tmp = SLLSI (tmp_tmp, 1);
13243   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13244 }
13245 }
13246 if (GESI (tmp_tmp, 0)) {
13247 {
13248   tmp_tmp = SLLSI (tmp_tmp, 1);
13249   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13250 }
13251 }
13252 if (GESI (tmp_tmp, 0)) {
13253 {
13254   tmp_tmp = SLLSI (tmp_tmp, 1);
13255   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13256 }
13257 }
13258 if (GESI (tmp_tmp, 0)) {
13259 {
13260   tmp_tmp = SLLSI (tmp_tmp, 1);
13261   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13262 }
13263 }
13264 if (GESI (tmp_tmp, 0)) {
13265 {
13266   tmp_tmp = SLLSI (tmp_tmp, 1);
13267   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13268 }
13269 }
13270 if (GESI (tmp_tmp, 0)) {
13271 {
13272   tmp_tmp = SLLSI (tmp_tmp, 1);
13273   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13274 }
13275 }
13276 if (GESI (tmp_tmp, 0)) {
13277 {
13278   tmp_tmp = SLLSI (tmp_tmp, 1);
13279   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13280 }
13281 }
13282 if (GESI (tmp_tmp, 0)) {
13283 {
13284   tmp_tmp = SLLSI (tmp_tmp, 1);
13285   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13286 }
13287 }
13288 if (GESI (tmp_tmp, 0)) {
13289 {
13290   tmp_tmp = SLLSI (tmp_tmp, 1);
13291   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13292 }
13293 }
13294 if (GESI (tmp_tmp, 0)) {
13295 {
13296   tmp_tmp = SLLSI (tmp_tmp, 1);
13297   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13298 }
13299 }
13300 if (GESI (tmp_tmp, 0)) {
13301 {
13302   tmp_tmp = SLLSI (tmp_tmp, 1);
13303   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13304 }
13305 }
13306 if (GESI (tmp_tmp, 0)) {
13307 {
13308   tmp_tmp = SLLSI (tmp_tmp, 1);
13309   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13310 }
13311 }
13312 if (GESI (tmp_tmp, 0)) {
13313 {
13314   tmp_tmp = SLLSI (tmp_tmp, 1);
13315   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13316 }
13317 }
13318 if (GESI (tmp_tmp, 0)) {
13319 {
13320   tmp_tmp = SLLSI (tmp_tmp, 1);
13321   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13322 }
13323 }
13324 if (GESI (tmp_tmp, 0)) {
13325 {
13326   tmp_tmp = SLLSI (tmp_tmp, 1);
13327   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13328 }
13329 }
13330 if (GESI (tmp_tmp, 0)) {
13331 {
13332   tmp_tmp = SLLSI (tmp_tmp, 1);
13333   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13334 }
13335 }
13336 if (GESI (tmp_tmp, 0)) {
13337 {
13338   tmp_tmp = SLLSI (tmp_tmp, 1);
13339   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13340 }
13341 }
13342 if (GESI (tmp_tmp, 0)) {
13343 {
13344   tmp_tmp = SLLSI (tmp_tmp, 1);
13345   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13346 }
13347 }
13348 }
13349   {
13350     SI opval = tmp_tmpd;
13351     SET_H_GR (FLD (f_operand2), opval);
13352     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13353   }
13354 {
13355   {
13356     BI opval = LTSI (tmp_tmpd, 0);
13357     CPU (h_nbit) = opval;
13358     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13359   }
13360   {
13361     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13362     CPU (h_zbit) = opval;
13363     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13364   }
13365 SET_H_CBIT_MOVE (0);
13366 SET_H_VBIT_MOVE (0);
13367 {
13368   {
13369     BI opval = 0;
13370     CPU (h_xbit) = opval;
13371     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13372   }
13373   {
13374     BI opval = 0;
13375     SET_H_INSN_PREFIXED_P (opval);
13376     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13377   }
13378 }
13379 }
13380 }
13381
13382 #undef FLD
13383 }
13384   NEXT (vpc);
13385
13386   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13387 {
13388   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13389   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13390 #define FLD(f) abuf->fields.sfmt_addoq.f
13391   int UNUSED written = 0;
13392   IADDR UNUSED pc = abuf->addr;
13393   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13394
13395 {
13396   {
13397     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13398     CPU (h_prefixreg_pre_v32) = opval;
13399     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13400   }
13401   {
13402     BI opval = 1;
13403     SET_H_INSN_PREFIXED_P (opval);
13404     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13405   }
13406 }
13407
13408 #undef FLD
13409 }
13410   NEXT (vpc);
13411
13412   CASE (sem, INSN_BDAPQPC) : /* bdapq $o,PC */
13413 {
13414   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13415   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13416 #define FLD(f) abuf->fields.sfmt_addoq.f
13417   int UNUSED written = 0;
13418   IADDR UNUSED pc = abuf->addr;
13419   SEM_BRANCH_INIT
13420   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13421
13422 {
13423   {
13424     SI opval = ADDSI (ADDSI (pc, 2), FLD (f_s8));
13425     CPU (h_prefixreg_pre_v32) = opval;
13426     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13427   }
13428   {
13429     BI opval = 1;
13430     SET_H_INSN_PREFIXED_P (opval);
13431     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13432   }
13433 cris_flush_simulator_decode_cache (current_cpu, pc);
13434 }
13435
13436   SEM_BRANCH_FINI (vpc);
13437 #undef FLD
13438 }
13439   NEXT (vpc);
13440
13441   CASE (sem, INSN_BDAP_32_PC) : /* bdap ${sconst32},PC */
13442 {
13443   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13444   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13445 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
13446   int UNUSED written = 0;
13447   IADDR UNUSED pc = abuf->addr;
13448   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13449
13450 {
13451   SI tmp_newpc;
13452   SI tmp_oldpc;
13453   SI tmp_offs;
13454   tmp_offs = FLD (f_indir_pc__dword);
13455   tmp_oldpc = ADDSI (pc, 6);
13456   tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
13457   {
13458     SI opval = tmp_newpc;
13459     CPU (h_prefixreg_pre_v32) = opval;
13460     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13461   }
13462   {
13463     BI opval = 1;
13464     SET_H_INSN_PREFIXED_P (opval);
13465     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13466   }
13467 }
13468
13469 #undef FLD
13470 }
13471   NEXT (vpc);
13472
13473   CASE (sem, INSN_MOVE_M_PCPLUS_P0) : /* move [PC+],P0 */
13474 {
13475   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13476   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13477 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
13478   int UNUSED written = 0;
13479   IADDR UNUSED pc = abuf->addr;
13480   SEM_BRANCH_INIT
13481   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13482
13483 if (GET_H_INSN_PREFIXED_P ()) {
13484 {
13485   QI tmp_dummy;
13486   tmp_dummy = ({   SI tmp_addr;
13487   QI tmp_tmp_mem;
13488   BI tmp_postinc;
13489   tmp_postinc = FLD (f_memmode);
13490 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (pc) : (CPU (h_prefixreg_pre_v32)));
13491 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13492 ; if (NEBI (tmp_postinc, 0)) {
13493 {
13494 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13495   tmp_addr = ADDSI (tmp_addr, 1);
13496 }
13497   {
13498     USI opval = tmp_addr;
13499     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13500     written |= (1 << 5);
13501     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13502   }
13503 }
13504 }
13505 ; tmp_tmp_mem; });
13506 {
13507   {
13508     BI opval = 0;
13509     CPU (h_xbit) = opval;
13510     written |= (1 << 7);
13511     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13512   }
13513   {
13514     BI opval = 0;
13515     SET_H_INSN_PREFIXED_P (opval);
13516     written |= (1 << 6);
13517     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13518   }
13519 }
13520 }
13521 } else {
13522 cgen_rtx_error (current_cpu, "move [PC+],P0 without prefix is not implemented");
13523 }
13524
13525   abuf->written = written;
13526   SEM_BRANCH_FINI (vpc);
13527 #undef FLD
13528 }
13529   NEXT (vpc);
13530
13531   CASE (sem, INSN_MOVE_M_SPPLUS_P8) : /* move [SP+],P8 */
13532 {
13533   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13534   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13535 #define FLD(f) abuf->fields.sfmt_move_m_spplus_p8.f
13536   int UNUSED written = 0;
13537   IADDR UNUSED pc = abuf->addr;
13538   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13539
13540 if (GET_H_INSN_PREFIXED_P ()) {
13541 {
13542   SI tmp_dummy;
13543   tmp_dummy = ({   SI tmp_addr;
13544   SI tmp_tmp_mem;
13545   BI tmp_postinc;
13546   tmp_postinc = FLD (f_memmode);
13547 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (((UINT) 14))) : (CPU (h_prefixreg_pre_v32)));
13548 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13549 ; if (NEBI (tmp_postinc, 0)) {
13550 {
13551 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13552   tmp_addr = ADDSI (tmp_addr, 4);
13553 }
13554   {
13555     SI opval = tmp_addr;
13556     SET_H_GR (((UINT) 14), opval);
13557     written |= (1 << 5);
13558     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13559   }
13560 }
13561 }
13562 ; tmp_tmp_mem; });
13563 {
13564   {
13565     BI opval = 0;
13566     CPU (h_xbit) = opval;
13567     written |= (1 << 7);
13568     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13569   }
13570   {
13571     BI opval = 0;
13572     SET_H_INSN_PREFIXED_P (opval);
13573     written |= (1 << 6);
13574     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13575   }
13576 }
13577 }
13578 } else {
13579 cgen_rtx_error (current_cpu, "move [SP+],P8 without prefix is not implemented");
13580 }
13581
13582   abuf->written = written;
13583 #undef FLD
13584 }
13585   NEXT (vpc);
13586
13587   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13588 {
13589   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13590   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13591 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13592   int UNUSED written = 0;
13593   IADDR UNUSED pc = abuf->addr;
13594   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13595
13596 {
13597   QI tmp_tmps;
13598   tmp_tmps = ({   SI tmp_addr;
13599   QI tmp_tmp_mem;
13600   BI tmp_postinc;
13601   tmp_postinc = FLD (f_memmode);
13602 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13603 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13604 ; if (NEBI (tmp_postinc, 0)) {
13605 {
13606 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13607   tmp_addr = ADDSI (tmp_addr, 1);
13608 }
13609   {
13610     SI opval = tmp_addr;
13611     SET_H_GR (FLD (f_operand1), opval);
13612     written |= (1 << 6);
13613     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13614   }
13615 }
13616 }
13617 ; tmp_tmp_mem; });
13618   {
13619     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13620     CPU (h_prefixreg_pre_v32) = opval;
13621     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13622   }
13623   {
13624     BI opval = 1;
13625     SET_H_INSN_PREFIXED_P (opval);
13626     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13627   }
13628 }
13629
13630   abuf->written = written;
13631 #undef FLD
13632 }
13633   NEXT (vpc);
13634
13635   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
13636 {
13637   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13638   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13639 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13640   int UNUSED written = 0;
13641   IADDR UNUSED pc = abuf->addr;
13642   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13643
13644 {
13645   HI tmp_tmps;
13646   tmp_tmps = ({   SI tmp_addr;
13647   HI tmp_tmp_mem;
13648   BI tmp_postinc;
13649   tmp_postinc = FLD (f_memmode);
13650 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13651 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
13652 ; if (NEBI (tmp_postinc, 0)) {
13653 {
13654 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13655   tmp_addr = ADDSI (tmp_addr, 2);
13656 }
13657   {
13658     SI opval = tmp_addr;
13659     SET_H_GR (FLD (f_operand1), opval);
13660     written |= (1 << 6);
13661     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13662   }
13663 }
13664 }
13665 ; tmp_tmp_mem; });
13666   {
13667     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
13668     CPU (h_prefixreg_pre_v32) = opval;
13669     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13670   }
13671   {
13672     BI opval = 1;
13673     SET_H_INSN_PREFIXED_P (opval);
13674     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13675   }
13676 }
13677
13678   abuf->written = written;
13679 #undef FLD
13680 }
13681   NEXT (vpc);
13682
13683   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
13684 {
13685   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13686   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13687 #define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
13688   int UNUSED written = 0;
13689   IADDR UNUSED pc = abuf->addr;
13690   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13691
13692 {
13693   SI tmp_tmps;
13694   tmp_tmps = ({   SI tmp_addr;
13695   SI tmp_tmp_mem;
13696   BI tmp_postinc;
13697   tmp_postinc = FLD (f_memmode);
13698 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13699 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13700 ; if (NEBI (tmp_postinc, 0)) {
13701 {
13702 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13703   tmp_addr = ADDSI (tmp_addr, 4);
13704 }
13705   {
13706     SI opval = tmp_addr;
13707     SET_H_GR (FLD (f_operand1), opval);
13708     written |= (1 << 6);
13709     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13710   }
13711 }
13712 }
13713 ; tmp_tmp_mem; });
13714   {
13715     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
13716     CPU (h_prefixreg_pre_v32) = opval;
13717     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13718   }
13719   {
13720     BI opval = 1;
13721     SET_H_INSN_PREFIXED_P (opval);
13722     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13723   }
13724 }
13725
13726   abuf->written = written;
13727 #undef FLD
13728 }
13729   NEXT (vpc);
13730
13731   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
13732 {
13733   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13734   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13735 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13736   int UNUSED written = 0;
13737   IADDR UNUSED pc = abuf->addr;
13738   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13739
13740 {
13741   {
13742     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
13743     CPU (h_prefixreg_pre_v32) = opval;
13744     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13745   }
13746   {
13747     BI opval = 1;
13748     SET_H_INSN_PREFIXED_P (opval);
13749     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13750   }
13751 }
13752
13753 #undef FLD
13754 }
13755   NEXT (vpc);
13756
13757   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
13758 {
13759   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13760   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13761 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13762   int UNUSED written = 0;
13763   IADDR UNUSED pc = abuf->addr;
13764   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13765
13766 {
13767   {
13768     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
13769     CPU (h_prefixreg_pre_v32) = opval;
13770     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13771   }
13772   {
13773     BI opval = 1;
13774     SET_H_INSN_PREFIXED_P (opval);
13775     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13776   }
13777 }
13778
13779 #undef FLD
13780 }
13781   NEXT (vpc);
13782
13783   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
13784 {
13785   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13786   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13787 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13788   int UNUSED written = 0;
13789   IADDR UNUSED pc = abuf->addr;
13790   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13791
13792 {
13793   {
13794     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
13795     CPU (h_prefixreg_pre_v32) = opval;
13796     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13797   }
13798   {
13799     BI opval = 1;
13800     SET_H_INSN_PREFIXED_P (opval);
13801     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13802   }
13803 }
13804
13805 #undef FLD
13806 }
13807   NEXT (vpc);
13808
13809   CASE (sem, INSN_DIP_M) : /* dip [${Rs}${inc}] */
13810 {
13811   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13812   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13813 #define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
13814   int UNUSED written = 0;
13815   IADDR UNUSED pc = abuf->addr;
13816   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13817
13818 {
13819   SI tmp_tmps;
13820   tmp_tmps = ({   SI tmp_addr;
13821   SI tmp_tmp_mem;
13822   BI tmp_postinc;
13823   tmp_postinc = FLD (f_memmode);
13824 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
13825 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13826 ; if (NEBI (tmp_postinc, 0)) {
13827 {
13828 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13829   tmp_addr = ADDSI (tmp_addr, 4);
13830 }
13831   {
13832     SI opval = tmp_addr;
13833     SET_H_GR (FLD (f_operand1), opval);
13834     written |= (1 << 5);
13835     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13836   }
13837 }
13838 }
13839 ; tmp_tmp_mem; });
13840   {
13841     SI opval = tmp_tmps;
13842     CPU (h_prefixreg_pre_v32) = opval;
13843     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13844   }
13845   {
13846     BI opval = 1;
13847     SET_H_INSN_PREFIXED_P (opval);
13848     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13849   }
13850 }
13851
13852   abuf->written = written;
13853 #undef FLD
13854 }
13855   NEXT (vpc);
13856
13857   CASE (sem, INSN_DIP_C) : /* dip [PC+] */
13858 {
13859   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13860   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13861 #define FLD(f) abuf->fields.sfmt_move_c_sprv10_p9.f
13862   int UNUSED written = 0;
13863   IADDR UNUSED pc = abuf->addr;
13864   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13865
13866 {
13867   {
13868     SI opval = FLD (f_indir_pc__dword);
13869     CPU (h_prefixreg_pre_v32) = opval;
13870     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13871   }
13872   {
13873     BI opval = 1;
13874     SET_H_INSN_PREFIXED_P (opval);
13875     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13876   }
13877 }
13878
13879 #undef FLD
13880 }
13881   NEXT (vpc);
13882
13883   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
13884 {
13885   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13886   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13887 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13888   int UNUSED written = 0;
13889   IADDR UNUSED pc = abuf->addr;
13890   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13891
13892 {
13893   {
13894     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13895     CPU (h_prefixreg_pre_v32) = opval;
13896     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13897   }
13898   {
13899     BI opval = 1;
13900     SET_H_INSN_PREFIXED_P (opval);
13901     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13902   }
13903 }
13904
13905 #undef FLD
13906 }
13907   NEXT (vpc);
13908
13909   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
13910 {
13911   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13912   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13913 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13914   int UNUSED written = 0;
13915   IADDR UNUSED pc = abuf->addr;
13916   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13917
13918 {
13919   {
13920     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13921     CPU (h_prefixreg_pre_v32) = opval;
13922     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13923   }
13924   {
13925     BI opval = 1;
13926     SET_H_INSN_PREFIXED_P (opval);
13927     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13928   }
13929 }
13930
13931 #undef FLD
13932 }
13933   NEXT (vpc);
13934
13935   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
13936 {
13937   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13938   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13939 #define FLD(f) abuf->fields.sfmt_add_b_r.f
13940   int UNUSED written = 0;
13941   IADDR UNUSED pc = abuf->addr;
13942   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13943
13944 {
13945   {
13946     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
13947     CPU (h_prefixreg_pre_v32) = opval;
13948     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13949   }
13950   {
13951     BI opval = 1;
13952     SET_H_INSN_PREFIXED_P (opval);
13953     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13954   }
13955 }
13956
13957 #undef FLD
13958 }
13959   NEXT (vpc);
13960
13961   CASE (sem, INSN_BIAP_PC_B_R) : /* biap-pc.b ${Rs-dfield}.m,PC */
13962 {
13963   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13964   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13965 #define FLD(f) abuf->fields.sfmt_addoq.f
13966   int UNUSED written = 0;
13967   IADDR UNUSED pc = abuf->addr;
13968   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13969
13970 {
13971   {
13972     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13973     CPU (h_prefixreg_pre_v32) = opval;
13974     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13975   }
13976   {
13977     BI opval = 1;
13978     SET_H_INSN_PREFIXED_P (opval);
13979     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13980   }
13981 }
13982
13983 #undef FLD
13984 }
13985   NEXT (vpc);
13986
13987   CASE (sem, INSN_BIAP_PC_W_R) : /* biap-pc.w ${Rs-dfield}.m,PC */
13988 {
13989   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13990   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13991 #define FLD(f) abuf->fields.sfmt_addoq.f
13992   int UNUSED written = 0;
13993   IADDR UNUSED pc = abuf->addr;
13994   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13995
13996 {
13997   {
13998     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13999     CPU (h_prefixreg_pre_v32) = opval;
14000     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14001   }
14002   {
14003     BI opval = 1;
14004     SET_H_INSN_PREFIXED_P (opval);
14005     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14006   }
14007 }
14008
14009 #undef FLD
14010 }
14011   NEXT (vpc);
14012
14013   CASE (sem, INSN_BIAP_PC_D_R) : /* biap-pc.d ${Rs-dfield}.m,PC */
14014 {
14015   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14016   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14017 #define FLD(f) abuf->fields.sfmt_addoq.f
14018   int UNUSED written = 0;
14019   IADDR UNUSED pc = abuf->addr;
14020   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14021
14022 {
14023   {
14024     SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14025     CPU (h_prefixreg_pre_v32) = opval;
14026     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14027   }
14028   {
14029     BI opval = 1;
14030     SET_H_INSN_PREFIXED_P (opval);
14031     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14032   }
14033 }
14034
14035 #undef FLD
14036 }
14037   NEXT (vpc);
14038
14039
14040     }
14041   ENDSWITCH (sem) /* End of semantic switch.  */
14042
14043   /* At this point `vpc' contains the next insn to execute.  */
14044 }
14045
14046 #undef DEFINE_SWITCH
14047 #endif /* DEFINE_SWITCH */