]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
0b21549783b2afea5c8296652aebf385a0ff48b4
5 #include "gdb/callback.h"
6 #include "gdb/remote-sim.h"
10 #include "gdb/sim-d10v.h"
11 #include "gdb/signals.h"
18 #endif /* HAVE_STRING_H */
19 #endif /* HAVE_STRINGS_H */
25 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
28 static SIM_OPEN_KIND sim_kind
;
31 /* Set this to true to get the previous segment layout. */
33 int old_segment_mapping
;
35 host_callback
*d10v_callback
;
36 unsigned long ins_type_counters
[ (int)INS_MAX
];
40 static int init_text_p
= 0;
41 /* non-zero if we opened prog_bfd */
42 static int prog_bfd_was_opened_p
;
48 static long hash (long insn
, int format
);
49 static struct hash_entry
*lookup_hash (uint32 ins
, int size
);
50 static void get_operands (struct simops
*s
, uint32 ins
);
51 static void do_long (uint32 ins
);
52 static void do_2_short (uint16 ins1
, uint16 ins2
, enum _leftright leftright
);
53 static void do_parallel (uint16 ins1
, uint16 ins2
);
54 static char *add_commas (char *buf
, int sizeof_buf
, unsigned long value
);
55 extern void sim_set_profile (int n
);
56 extern void sim_set_profile_size (int n
);
57 static INLINE uint8
*map_memory (unsigned phys_addr
);
60 #if defined(__GNUC__) && defined(__OPTIMIZE__)
61 #define INLINE __inline__
70 struct hash_entry
*next
;
77 struct hash_entry hash_table
[MAX_HASH
+1];
80 hash (long insn
, int format
)
82 if (format
& LONG_OPCODE
)
83 return ((insn
& 0x3F000000) >> 24);
85 return((insn
& 0x7E00) >> 9);
88 INLINE
static struct hash_entry
*
89 lookup_hash (uint32 ins
, int size
)
94 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
96 h
= &hash_table
[(ins
& 0x7E00) >> 9];
98 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
102 State
.exception
= SIGILL
;
103 State
.pc_changed
= 1; /* Don't increment the PC. */
112 get_operands (struct simops
*s
, uint32 ins
)
114 int i
, shift
, bits
, flags
;
116 for (i
=0; i
< s
->numops
; i
++)
118 shift
= s
->operands
[3*i
];
119 bits
= s
->operands
[3*i
+1];
120 flags
= s
->operands
[3*i
+2];
121 mask
= 0x7FFFFFFF >> (31 - bits
);
122 OP
[i
] = (ins
>> shift
) & mask
;
124 /* FIXME: for tracing, update values that need to be updated each
125 instruction decode cycle */
126 State
.trace
.psw
= PSW
;
133 if (!init_text_p
&& prog_bfd
!= NULL
)
136 for (s
= prog_bfd
->sections
; s
; s
= s
->next
)
137 if (strcmp (bfd_get_section_name (prog_bfd
, s
), ".text") == 0)
140 text_start
= bfd_get_section_vma (prog_bfd
, s
);
141 text_end
= text_start
+ bfd_section_size (prog_bfd
, s
);
146 return (PC
<< 2) + text_start
;
152 struct hash_entry
*h
;
154 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
155 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_long 0x%x\n", ins
);
157 h
= lookup_hash (ins
, 1);
160 get_operands (h
->ops
, ins
);
161 State
.ins_type
= INS_LONG
;
162 ins_type_counters
[ (int)State
.ins_type
]++;
167 do_2_short (uint16 ins1
, uint16 ins2
, enum _leftright leftright
)
169 struct hash_entry
*h
;
170 enum _ins_type first
, second
;
173 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
174 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_2_short 0x%x (%s) -> 0x%x\n",
175 ins1
, (leftright
) ? "left" : "right", ins2
);
178 if (leftright
== LEFT_FIRST
)
182 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
188 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
191 /* Issue the first instruction */
192 h
= lookup_hash (ins1
, 0);
195 get_operands (h
->ops
, ins1
);
196 State
.ins_type
= first
;
197 ins_type_counters
[ (int)State
.ins_type
]++;
200 /* Issue the second instruction (if the PC hasn't changed) */
201 if (!State
.pc_changed
&& !State
.exception
)
203 /* finish any existing instructions */
205 h
= lookup_hash (ins2
, 0);
208 get_operands (h
->ops
, ins2
);
209 State
.ins_type
= second
;
210 ins_type_counters
[ (int)State
.ins_type
]++;
211 ins_type_counters
[ (int)INS_CYCLES
]++;
214 else if (!State
.exception
)
215 ins_type_counters
[ (int)INS_COND_JUMP
]++;
219 do_parallel (uint16 ins1
, uint16 ins2
)
221 struct hash_entry
*h1
, *h2
;
223 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
224 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
226 ins_type_counters
[ (int)INS_PARALLEL
]++;
227 h1
= lookup_hash (ins1
, 0);
230 h2
= lookup_hash (ins2
, 0);
234 if (h1
->ops
->exec_type
== PARONLY
)
236 get_operands (h1
->ops
, ins1
);
237 State
.ins_type
= INS_LEFT_COND_TEST
;
238 ins_type_counters
[ (int)State
.ins_type
]++;
242 ins_type_counters
[ (int)INS_COND_TRUE
]++;
243 get_operands (h2
->ops
, ins2
);
244 State
.ins_type
= INS_RIGHT_COND_EXE
;
245 ins_type_counters
[ (int)State
.ins_type
]++;
249 ins_type_counters
[ (int)INS_COND_FALSE
]++;
251 else if (h2
->ops
->exec_type
== PARONLY
)
253 get_operands (h2
->ops
, ins2
);
254 State
.ins_type
= INS_RIGHT_COND_TEST
;
255 ins_type_counters
[ (int)State
.ins_type
]++;
259 ins_type_counters
[ (int)INS_COND_TRUE
]++;
260 get_operands (h1
->ops
, ins1
);
261 State
.ins_type
= INS_LEFT_COND_EXE
;
262 ins_type_counters
[ (int)State
.ins_type
]++;
266 ins_type_counters
[ (int)INS_COND_FALSE
]++;
270 get_operands (h1
->ops
, ins1
);
271 State
.ins_type
= INS_LEFT_PARALLEL
;
272 ins_type_counters
[ (int)State
.ins_type
]++;
274 if (!State
.exception
)
276 get_operands (h2
->ops
, ins2
);
277 State
.ins_type
= INS_RIGHT_PARALLEL
;
278 ins_type_counters
[ (int)State
.ins_type
]++;
285 add_commas (char *buf
, int sizeof_buf
, unsigned long value
)
288 char *endbuf
= buf
+ sizeof_buf
- 1;
298 *--endbuf
= (value
% 10) + '0';
299 } while ((value
/= 10) != 0);
308 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
310 if (State
.mem
.insn
[i
])
311 free (State
.mem
.insn
[i
]);
313 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
315 if (State
.mem
.data
[i
])
316 free (State
.mem
.data
[i
]);
318 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
320 if (State
.mem
.unif
[i
])
321 free (State
.mem
.unif
[i
]);
323 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
325 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
328 /* For tracing - leave info on last access around. */
329 static char *last_segname
= "invalid";
330 static char *last_from
= "invalid";
331 static char *last_to
= "invalid";
335 IMAP0_OFFSET
= 0xff00,
336 DMAP0_OFFSET
= 0xff08,
337 DMAP2_SHADDOW
= 0xff04,
338 DMAP2_OFFSET
= 0xff0c
342 set_dmap_register (int reg_nr
, unsigned long value
)
344 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
345 + DMAP0_OFFSET
+ 2 * reg_nr
);
346 WRITE_16 (raw
, value
);
348 if ((d10v_debug
& DEBUG_MEMORY
))
350 (*d10v_callback
->printf_filtered
)
351 (d10v_callback
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
357 dmap_register (void *regcache
, int reg_nr
)
359 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
360 + DMAP0_OFFSET
+ 2 * reg_nr
);
361 return READ_16 (raw
);
365 set_imap_register (int reg_nr
, unsigned long value
)
367 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
368 + IMAP0_OFFSET
+ 2 * reg_nr
);
369 WRITE_16 (raw
, value
);
371 if ((d10v_debug
& DEBUG_MEMORY
))
373 (*d10v_callback
->printf_filtered
)
374 (d10v_callback
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
380 imap_register (void *regcache
, int reg_nr
)
382 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
383 + IMAP0_OFFSET
+ 2 * reg_nr
);
384 return READ_16 (raw
);
399 return HELD_SP (HELD_SPU_IDX
);
408 return HELD_SP (HELD_SPI_IDX
);
412 set_spi_register (unsigned long value
)
415 SET_GPR (SP_IDX
, value
);
416 SET_HELD_SP (HELD_SPI_IDX
, value
);
420 set_spu_register (unsigned long value
)
423 SET_GPR (SP_IDX
, value
);
424 SET_HELD_SP (HELD_SPU_IDX
, value
);
427 /* Given a virtual address in the DMAP address space, translate it
428 into a physical address. */
431 sim_d10v_translate_dmap_addr (unsigned long offset
,
435 unsigned long (*dmap_register
) (void *regcache
,
440 last_from
= "logical-data";
441 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
443 /* Logical address out side of data segments, not supported */
446 regno
= (offset
/ DMAP_BLOCK_SIZE
);
447 offset
= (offset
% DMAP_BLOCK_SIZE
);
448 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
450 /* Don't cross a BLOCK boundary */
451 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
453 map
= dmap_register (regcache
, regno
);
456 /* Always maps to data memory */
457 int iospi
= (offset
/ 0x1000) % 4;
458 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
459 last_to
= "io-space";
460 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
464 int sp
= ((map
& 0x3000) >> 12);
465 int segno
= (map
& 0x3ff);
468 case 0: /* 00: Unified memory */
469 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
472 case 1: /* 01: Instruction Memory */
473 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
474 last_to
= "chip-insn";
476 case 2: /* 10: Internal data memory */
477 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
478 last_to
= "chip-data";
480 case 3: /* 11: Reserved */
487 /* Given a virtual address in the IMAP address space, translate it
488 into a physical address. */
491 sim_d10v_translate_imap_addr (unsigned long offset
,
495 unsigned long (*imap_register
) (void *regcache
,
502 last_from
= "logical-insn";
503 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
505 /* Logical address outside of IMAP segments, not supported */
508 regno
= (offset
/ IMAP_BLOCK_SIZE
);
509 offset
= (offset
% IMAP_BLOCK_SIZE
);
510 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
512 /* Don't cross a BLOCK boundary */
513 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
515 map
= imap_register (regcache
, regno
);
516 sp
= (map
& 0x3000) >> 12;
517 segno
= (map
& 0x007f);
520 case 0: /* 00: unified memory */
521 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
524 case 1: /* 01: instruction memory */
525 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
526 last_to
= "chip-insn";
531 case 3: /* 11: for testing - instruction memory */
532 offset
= (offset
% 0x800);
533 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
534 if (offset
+ nr_bytes
> 0x800)
535 /* don't cross VM boundary */
536 nr_bytes
= 0x800 - offset
;
537 last_to
= "test-insn";
544 sim_d10v_translate_addr (unsigned long memaddr
,
546 unsigned long *targ_addr
,
548 unsigned long (*dmap_register
) (void *regcache
,
550 unsigned long (*imap_register
) (void *regcache
,
557 last_from
= "unknown";
560 seg
= (memaddr
>> 24);
561 off
= (memaddr
& 0xffffffL
);
563 /* However, if we've asked to use the previous generation of segment
564 mapping, rearrange the segments as follows. */
566 if (old_segment_mapping
)
570 case 0x00: /* DMAP translated memory */
573 case 0x01: /* IMAP translated memory */
576 case 0x10: /* On-chip data memory */
579 case 0x11: /* On-chip insn memory */
582 case 0x12: /* Unified memory */
590 case 0x00: /* Physical unified memory */
591 last_from
= "phys-unified";
593 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
594 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
595 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
598 case 0x01: /* Physical instruction memory */
599 last_from
= "phys-insn";
600 last_to
= "chip-insn";
601 phys
= SIM_D10V_MEMORY_INSN
+ off
;
602 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
603 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
606 case 0x02: /* Physical data memory segment */
607 last_from
= "phys-data";
608 last_to
= "chip-data";
609 phys
= SIM_D10V_MEMORY_DATA
+ off
;
610 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
611 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
614 case 0x10: /* in logical data address segment */
615 nr_bytes
= sim_d10v_translate_dmap_addr (off
, nr_bytes
, &phys
, regcache
,
619 case 0x11: /* in logical instruction address segment */
620 nr_bytes
= sim_d10v_translate_imap_addr (off
, nr_bytes
, &phys
, regcache
,
632 /* Return a pointer into the raw buffer designated by phys_addr. It
633 is assumed that the client has already ensured that the access
634 isn't going to cross a segment boundary. */
637 map_memory (unsigned phys_addr
)
642 int segment
= ((phys_addr
>> 24) & 0xff);
647 case 0x00: /* Unified memory */
649 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
650 last_segname
= "umem";
654 case 0x01: /* On-chip insn memory */
656 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
657 last_segname
= "imem";
661 case 0x02: /* On-chip data memory */
663 if ((phys_addr
& 0xff00) == 0xff00)
665 phys_addr
= (phys_addr
& 0xffff);
666 if (phys_addr
== DMAP2_SHADDOW
)
668 phys_addr
= DMAP2_OFFSET
;
669 last_segname
= "dmap";
672 last_segname
= "reg";
675 last_segname
= "dmem";
676 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
682 last_segname
= "scrap";
683 return State
.mem
.fault
;
688 *memory
= calloc (1, SEGMENT_SIZE
);
691 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Malloc failed.\n");
692 return State
.mem
.fault
;
696 offset
= (phys_addr
% SEGMENT_SIZE
);
697 raw
= *memory
+ offset
;
701 /* Transfer data to/from simulated memory. Since a bug in either the
702 simulated program or in gdb or the simulator itself may cause a
703 bogus address to be passed in, we need to do some sanity checking
704 on addresses to make sure they are within bounds. When an address
705 fails the bounds check, treat it as a zero length read/write rather
706 than aborting the entire run. */
709 xfer_mem (SIM_ADDR virt
,
710 unsigned char *buffer
,
717 phys_size
= sim_d10v_translate_addr (virt
, size
, &phys
, NULL
,
718 dmap_register
, imap_register
);
722 memory
= map_memory (phys
);
725 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
727 (*d10v_callback
->printf_filtered
)
729 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
730 (write_p
? "write" : "read"),
731 phys_size
, virt
, last_from
,
733 (long) memory
, last_segname
);
739 memcpy (memory
, buffer
, phys_size
);
743 memcpy (buffer
, memory
, phys_size
);
751 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
753 /* FIXME: this should be performing a virtual transfer */
754 return xfer_mem( addr
, buffer
, size
, 1);
758 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
760 /* FIXME: this should be performing a virtual transfer */
761 return xfer_mem( addr
, buffer
, size
, 0);
766 sim_open (SIM_OPEN_KIND kind
, host_callback
*callback
, struct bfd
*abfd
, char **argv
)
769 struct hash_entry
*h
;
770 static int init_p
= 0;
774 d10v_callback
= callback
;
776 old_segment_mapping
= 0;
778 /* NOTE: This argument parsing is only effective when this function
779 is called by GDB. Standalone argument parsing is handled by
781 for (p
= argv
+ 1; *p
; ++p
)
783 if (strcmp (*p
, "-oldseg") == 0)
784 old_segment_mapping
= 1;
786 else if (strcmp (*p
, "-t") == 0)
788 else if (strncmp (*p
, "-t", 2) == 0)
789 d10v_debug
= atoi (*p
+ 2);
792 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: unsupported option(s): %s\n",*p
);
795 /* put all the opcodes in the hash table */
798 for (s
= Simops
; s
->func
; s
++)
800 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
802 /* go to the last entry in the chain */
808 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
810 perror ("malloc failure");
816 h
->opcode
= s
->opcode
;
817 h
->size
= s
->is_long
;
821 /* reset the processor state */
822 if (!State
.mem
.data
[0])
824 sim_create_inferior ((SIM_DESC
) 1, NULL
, NULL
, NULL
);
826 /* Fudge our descriptor. */
832 sim_close (SIM_DESC sd
, int quitting
)
834 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
836 bfd_close (prog_bfd
);
838 prog_bfd_was_opened_p
= 0;
843 sim_set_profile (int n
)
845 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile %d\n",n
);
849 sim_set_profile_size (int n
)
851 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile_size %d\n",n
);
855 dmem_addr (uint16 offset
)
861 /* Note: DMEM address range is 0..0x10000. Calling code can compute
862 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
863 is uint16 this is modulo'ed onto 0x0e5d. */
865 phys_size
= sim_d10v_translate_dmap_addr (offset
, 1, &phys
, NULL
,
869 mem
= State
.mem
.fault
;
872 mem
= map_memory (phys
);
874 if ((d10v_debug
& DEBUG_MEMORY
))
876 (*d10v_callback
->printf_filtered
)
878 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
880 phys
, phys_size
, last_to
,
881 (long) mem
, last_segname
);
888 imem_addr (uint32 offset
)
892 int phys_size
= sim_d10v_translate_imap_addr (offset
, 1, &phys
, NULL
,
896 return State
.mem
.fault
;
898 mem
= map_memory (phys
);
900 if ((d10v_debug
& DEBUG_MEMORY
))
902 (*d10v_callback
->printf_filtered
)
904 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
906 phys
, phys_size
, last_to
,
907 (long) mem
, last_segname
);
913 static int stop_simulator
= 0;
916 sim_stop (SIM_DESC sd
)
923 /* Run (or resume) the program. */
925 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
930 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
945 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
946 JMP (AE_VECTOR_START
);
952 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
953 JMP (RIE_VECTOR_START
);
963 iaddr
= imem_addr ((uint32
)PC
<< 2);
964 if (iaddr
== State
.mem
.fault
)
966 State
.exception
= SIGBUS
;
970 inst
= get_longword( iaddr
);
972 State
.pc_changed
= 0;
973 ins_type_counters
[ (int)INS_CYCLES
]++;
975 switch (inst
& 0xC0000000)
978 /* long instruction */
979 do_long (inst
& 0x3FFFFFFF);
983 do_2_short ( inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
987 do_2_short ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
990 do_parallel ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
994 /* If the PC of the current instruction matches RPT_E then
995 schedule a branch to the loop start. If one of those
996 instructions happens to be a branch, than that instruction
998 if (!State
.pc_changed
)
1000 if (PSW_RP
&& PC
== RPT_E
)
1002 /* Note: The behavour of a branch instruction at RPT_E
1003 is implementation dependant, this simulator takes the
1004 branch. Branching to RPT_E is valid, the instruction
1005 must be executed before the loop is taken. */
1014 SET_RPT_C (RPT_C
- 1);
1022 /* Check for a breakpoint trap on this instruction. This
1023 overrides any pending branches or loops */
1024 if (PSW_DB
&& PC
== IBA
)
1028 SET_PSW (PSW
& PSW_SM_BIT
);
1029 SET_PC (SDBT_VECTOR_START
);
1032 /* Writeback all the DATA / PC changes */
1035 while ( !State
.exception
&& !stop_simulator
);
1037 if (step
&& !State
.exception
)
1038 State
.exception
= SIGTRAP
;
1042 sim_set_trace (void)
1050 sim_info (SIM_DESC sd
, int verbose
)
1057 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1058 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1059 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1060 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1061 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1063 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1064 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1065 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1066 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1067 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1069 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1070 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1071 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1072 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1073 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1074 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1075 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1076 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1077 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1078 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1080 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1081 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1082 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1083 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1084 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1085 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1087 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1088 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1089 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1090 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1091 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1092 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1093 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1095 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1096 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1097 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1098 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1099 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1100 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1101 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1104 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1105 "executed %*s long instruction(s)\n",
1106 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1109 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1110 "executed %*s parallel instruction(s)\n",
1111 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1114 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1115 "executed %*s instruction(s) encoded L->R\n",
1116 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1119 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1120 "executed %*s instruction(s) encoded R->L\n",
1121 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1124 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1125 "executed %*s unknown instruction(s)\n",
1126 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1129 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1130 "executed %*s instruction(s) due to EXExxx condition being true\n",
1131 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1134 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1135 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1136 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1139 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1140 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1141 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1143 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1144 "executed %*s cycle(s)\n",
1145 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1147 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1148 "executed %*s total instructions\n",
1149 size
, add_commas (buf1
, sizeof (buf1
), total
));
1153 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
1155 bfd_vma start_address
;
1157 /* reset all state information */
1158 memset (&State
.regs
, 0, (uintptr_t)&State
.mem
- (uintptr_t)&State
.regs
);
1160 /* There was a hack here to copy the values of argc and argv into r0
1161 and r1. The values were also saved into some high memory that
1162 won't be overwritten by the stack (0x7C00). The reason for doing
1163 this was to allow the 'run' program to accept arguments. Without
1164 the hack, this is not possible anymore. If the simulator is run
1165 from the debugger, arguments cannot be passed in, so this makes
1170 start_address
= bfd_get_start_address (abfd
);
1172 start_address
= 0xffc0 << 2;
1175 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_create_inferior: PC=0x%lx\n", (long) start_address
);
1177 SET_CREG (PC_CR
, start_address
>> 2);
1179 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1180 initializes imap0 and imap1 to 0x1000 as part of its ROM
1182 if (old_segment_mapping
)
1184 /* External memory startup. This is the HARD reset state. */
1185 set_imap_register (0, 0x0000);
1186 set_imap_register (1, 0x007f);
1187 set_dmap_register (0, 0x2000);
1188 set_dmap_register (1, 0x2000);
1189 set_dmap_register (2, 0x0000); /* Old DMAP */
1190 set_dmap_register (3, 0x0000);
1194 /* Internal memory startup. This is the ROM intialized state. */
1195 set_imap_register (0, 0x1000);
1196 set_imap_register (1, 0x1000);
1197 set_dmap_register (0, 0x2000);
1198 set_dmap_register (1, 0x2000);
1199 set_dmap_register (2, 0x2000); /* DMAP2 initial internal value is
1200 0x2000 on the new board. */
1201 set_dmap_register (3, 0x0000);
1210 sim_set_callbacks (host_callback
*p
)
1216 sim_trace (SIM_DESC sd
)
1218 sim_resume (sd
, 0, 0);
1224 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
1226 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
1228 switch (State
.exception
)
1230 case SIG_D10V_STOP
: /* stop instruction */
1231 *reason
= sim_exited
;
1235 case SIG_D10V_EXIT
: /* exit trap */
1236 *reason
= sim_exited
;
1241 *reason
= sim_stopped
;
1242 *sigrc
= GDB_SIGNAL_BUS
;
1245 default: /* some signal */
1246 *reason
= sim_stopped
;
1247 if (stop_simulator
&& !State
.exception
)
1248 *sigrc
= GDB_SIGNAL_INT
;
1250 *sigrc
= State
.exception
;
1258 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1261 switch ((enum sim_d10v_regs
) rn
)
1263 case SIM_D10V_R0_REGNUM
:
1264 case SIM_D10V_R1_REGNUM
:
1265 case SIM_D10V_R2_REGNUM
:
1266 case SIM_D10V_R3_REGNUM
:
1267 case SIM_D10V_R4_REGNUM
:
1268 case SIM_D10V_R5_REGNUM
:
1269 case SIM_D10V_R6_REGNUM
:
1270 case SIM_D10V_R7_REGNUM
:
1271 case SIM_D10V_R8_REGNUM
:
1272 case SIM_D10V_R9_REGNUM
:
1273 case SIM_D10V_R10_REGNUM
:
1274 case SIM_D10V_R11_REGNUM
:
1275 case SIM_D10V_R12_REGNUM
:
1276 case SIM_D10V_R13_REGNUM
:
1277 case SIM_D10V_R14_REGNUM
:
1278 case SIM_D10V_R15_REGNUM
:
1279 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1282 case SIM_D10V_CR0_REGNUM
:
1283 case SIM_D10V_CR1_REGNUM
:
1284 case SIM_D10V_CR2_REGNUM
:
1285 case SIM_D10V_CR3_REGNUM
:
1286 case SIM_D10V_CR4_REGNUM
:
1287 case SIM_D10V_CR5_REGNUM
:
1288 case SIM_D10V_CR6_REGNUM
:
1289 case SIM_D10V_CR7_REGNUM
:
1290 case SIM_D10V_CR8_REGNUM
:
1291 case SIM_D10V_CR9_REGNUM
:
1292 case SIM_D10V_CR10_REGNUM
:
1293 case SIM_D10V_CR11_REGNUM
:
1294 case SIM_D10V_CR12_REGNUM
:
1295 case SIM_D10V_CR13_REGNUM
:
1296 case SIM_D10V_CR14_REGNUM
:
1297 case SIM_D10V_CR15_REGNUM
:
1298 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1301 case SIM_D10V_A0_REGNUM
:
1302 case SIM_D10V_A1_REGNUM
:
1303 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1306 case SIM_D10V_SPI_REGNUM
:
1307 /* PSW_SM indicates that the current SP is the USER
1309 WRITE_16 (memory
, spi_register ());
1312 case SIM_D10V_SPU_REGNUM
:
1313 /* PSW_SM indicates that the current SP is the USER
1315 WRITE_16 (memory
, spu_register ());
1318 case SIM_D10V_IMAP0_REGNUM
:
1319 case SIM_D10V_IMAP1_REGNUM
:
1320 WRITE_16 (memory
, imap_register (NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1323 case SIM_D10V_DMAP0_REGNUM
:
1324 case SIM_D10V_DMAP1_REGNUM
:
1325 case SIM_D10V_DMAP2_REGNUM
:
1326 case SIM_D10V_DMAP3_REGNUM
:
1327 WRITE_16 (memory
, dmap_register (NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1330 case SIM_D10V_TS2_DMAP_REGNUM
:
1341 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1344 switch ((enum sim_d10v_regs
) rn
)
1346 case SIM_D10V_R0_REGNUM
:
1347 case SIM_D10V_R1_REGNUM
:
1348 case SIM_D10V_R2_REGNUM
:
1349 case SIM_D10V_R3_REGNUM
:
1350 case SIM_D10V_R4_REGNUM
:
1351 case SIM_D10V_R5_REGNUM
:
1352 case SIM_D10V_R6_REGNUM
:
1353 case SIM_D10V_R7_REGNUM
:
1354 case SIM_D10V_R8_REGNUM
:
1355 case SIM_D10V_R9_REGNUM
:
1356 case SIM_D10V_R10_REGNUM
:
1357 case SIM_D10V_R11_REGNUM
:
1358 case SIM_D10V_R12_REGNUM
:
1359 case SIM_D10V_R13_REGNUM
:
1360 case SIM_D10V_R14_REGNUM
:
1361 case SIM_D10V_R15_REGNUM
:
1362 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1365 case SIM_D10V_CR0_REGNUM
:
1366 case SIM_D10V_CR1_REGNUM
:
1367 case SIM_D10V_CR2_REGNUM
:
1368 case SIM_D10V_CR3_REGNUM
:
1369 case SIM_D10V_CR4_REGNUM
:
1370 case SIM_D10V_CR5_REGNUM
:
1371 case SIM_D10V_CR6_REGNUM
:
1372 case SIM_D10V_CR7_REGNUM
:
1373 case SIM_D10V_CR8_REGNUM
:
1374 case SIM_D10V_CR9_REGNUM
:
1375 case SIM_D10V_CR10_REGNUM
:
1376 case SIM_D10V_CR11_REGNUM
:
1377 case SIM_D10V_CR12_REGNUM
:
1378 case SIM_D10V_CR13_REGNUM
:
1379 case SIM_D10V_CR14_REGNUM
:
1380 case SIM_D10V_CR15_REGNUM
:
1381 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1384 case SIM_D10V_A0_REGNUM
:
1385 case SIM_D10V_A1_REGNUM
:
1386 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1389 case SIM_D10V_SPI_REGNUM
:
1390 /* PSW_SM indicates that the current SP is the USER
1392 set_spi_register (READ_16 (memory
));
1395 case SIM_D10V_SPU_REGNUM
:
1396 set_spu_register (READ_16 (memory
));
1399 case SIM_D10V_IMAP0_REGNUM
:
1400 case SIM_D10V_IMAP1_REGNUM
:
1401 set_imap_register (rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1404 case SIM_D10V_DMAP0_REGNUM
:
1405 case SIM_D10V_DMAP1_REGNUM
:
1406 case SIM_D10V_DMAP2_REGNUM
:
1407 case SIM_D10V_DMAP3_REGNUM
:
1408 set_dmap_register (rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1411 case SIM_D10V_TS2_DMAP_REGNUM
:
1424 sim_do_command (SIM_DESC sd
, const char *cmd
)
1426 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_do_command: %s\n",cmd
);
1430 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
1432 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
1434 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
1436 bfd_close (prog_bfd
);
1437 prog_bfd_was_opened_p
= 0;
1439 prog_bfd
= sim_load_file (sd
, myname
, d10v_callback
, prog
, abfd
,
1440 sim_kind
== SIM_OPEN_DEBUG
,
1441 1/*LMA*/, sim_write
);
1442 if (prog_bfd
== NULL
)
1444 prog_bfd_was_opened_p
= abfd
== NULL
;