]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
5 #include "gdb/callback.h"
6 #include "gdb/remote-sim.h"
9 #include "sim-options.h"
11 #include "gdb/sim-d10v.h"
12 #include "gdb/signals.h"
19 #endif /* HAVE_STRING_H */
20 #endif /* HAVE_STRINGS_H */
26 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
30 /* Set this to true to get the previous segment layout. */
32 int old_segment_mapping
;
34 host_callback
*d10v_callback
;
35 unsigned long ins_type_counters
[ (int)INS_MAX
];
39 static long hash (long insn
, int format
);
40 static struct hash_entry
*lookup_hash (uint32 ins
, int size
);
41 static void get_operands (struct simops
*s
, uint32 ins
);
42 static void do_long (uint32 ins
);
43 static void do_2_short (uint16 ins1
, uint16 ins2
, enum _leftright leftright
);
44 static void do_parallel (uint16 ins1
, uint16 ins2
);
45 static char *add_commas (char *buf
, int sizeof_buf
, unsigned long value
);
46 extern void sim_set_profile (int n
);
47 extern void sim_set_profile_size (int n
);
48 static INLINE uint8
*map_memory (unsigned phys_addr
);
53 struct hash_entry
*next
;
60 struct hash_entry hash_table
[MAX_HASH
+1];
63 hash (long insn
, int format
)
65 if (format
& LONG_OPCODE
)
66 return ((insn
& 0x3F000000) >> 24);
68 return((insn
& 0x7E00) >> 9);
71 INLINE
static struct hash_entry
*
72 lookup_hash (uint32 ins
, int size
)
77 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
79 h
= &hash_table
[(ins
& 0x7E00) >> 9];
81 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
85 State
.exception
= SIGILL
;
86 State
.pc_changed
= 1; /* Don't increment the PC. */
95 get_operands (struct simops
*s
, uint32 ins
)
97 int i
, shift
, bits
, flags
;
99 for (i
=0; i
< s
->numops
; i
++)
101 shift
= s
->operands
[3*i
];
102 bits
= s
->operands
[3*i
+1];
103 flags
= s
->operands
[3*i
+2];
104 mask
= 0x7FFFFFFF >> (31 - bits
);
105 OP
[i
] = (ins
>> shift
) & mask
;
107 /* FIXME: for tracing, update values that need to be updated each
108 instruction decode cycle */
109 State
.trace
.psw
= PSW
;
115 struct hash_entry
*h
;
117 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
118 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_long 0x%x\n", ins
);
120 h
= lookup_hash (ins
, 1);
123 get_operands (h
->ops
, ins
);
124 State
.ins_type
= INS_LONG
;
125 ins_type_counters
[ (int)State
.ins_type
]++;
130 do_2_short (uint16 ins1
, uint16 ins2
, enum _leftright leftright
)
132 struct hash_entry
*h
;
133 enum _ins_type first
, second
;
136 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
137 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_2_short 0x%x (%s) -> 0x%x\n",
138 ins1
, (leftright
) ? "left" : "right", ins2
);
141 if (leftright
== LEFT_FIRST
)
145 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
151 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
154 /* Issue the first instruction */
155 h
= lookup_hash (ins1
, 0);
158 get_operands (h
->ops
, ins1
);
159 State
.ins_type
= first
;
160 ins_type_counters
[ (int)State
.ins_type
]++;
163 /* Issue the second instruction (if the PC hasn't changed) */
164 if (!State
.pc_changed
&& !State
.exception
)
166 /* finish any existing instructions */
168 h
= lookup_hash (ins2
, 0);
171 get_operands (h
->ops
, ins2
);
172 State
.ins_type
= second
;
173 ins_type_counters
[ (int)State
.ins_type
]++;
174 ins_type_counters
[ (int)INS_CYCLES
]++;
177 else if (!State
.exception
)
178 ins_type_counters
[ (int)INS_COND_JUMP
]++;
182 do_parallel (uint16 ins1
, uint16 ins2
)
184 struct hash_entry
*h1
, *h2
;
186 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
187 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
189 ins_type_counters
[ (int)INS_PARALLEL
]++;
190 h1
= lookup_hash (ins1
, 0);
193 h2
= lookup_hash (ins2
, 0);
197 if (h1
->ops
->exec_type
== PARONLY
)
199 get_operands (h1
->ops
, ins1
);
200 State
.ins_type
= INS_LEFT_COND_TEST
;
201 ins_type_counters
[ (int)State
.ins_type
]++;
205 ins_type_counters
[ (int)INS_COND_TRUE
]++;
206 get_operands (h2
->ops
, ins2
);
207 State
.ins_type
= INS_RIGHT_COND_EXE
;
208 ins_type_counters
[ (int)State
.ins_type
]++;
212 ins_type_counters
[ (int)INS_COND_FALSE
]++;
214 else if (h2
->ops
->exec_type
== PARONLY
)
216 get_operands (h2
->ops
, ins2
);
217 State
.ins_type
= INS_RIGHT_COND_TEST
;
218 ins_type_counters
[ (int)State
.ins_type
]++;
222 ins_type_counters
[ (int)INS_COND_TRUE
]++;
223 get_operands (h1
->ops
, ins1
);
224 State
.ins_type
= INS_LEFT_COND_EXE
;
225 ins_type_counters
[ (int)State
.ins_type
]++;
229 ins_type_counters
[ (int)INS_COND_FALSE
]++;
233 get_operands (h1
->ops
, ins1
);
234 State
.ins_type
= INS_LEFT_PARALLEL
;
235 ins_type_counters
[ (int)State
.ins_type
]++;
237 if (!State
.exception
)
239 get_operands (h2
->ops
, ins2
);
240 State
.ins_type
= INS_RIGHT_PARALLEL
;
241 ins_type_counters
[ (int)State
.ins_type
]++;
248 add_commas (char *buf
, int sizeof_buf
, unsigned long value
)
251 char *endbuf
= buf
+ sizeof_buf
- 1;
261 *--endbuf
= (value
% 10) + '0';
262 } while ((value
/= 10) != 0);
271 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
273 if (State
.mem
.insn
[i
])
274 free (State
.mem
.insn
[i
]);
276 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
278 if (State
.mem
.data
[i
])
279 free (State
.mem
.data
[i
]);
281 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
283 if (State
.mem
.unif
[i
])
284 free (State
.mem
.unif
[i
]);
286 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
288 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
291 /* For tracing - leave info on last access around. */
292 static char *last_segname
= "invalid";
293 static char *last_from
= "invalid";
294 static char *last_to
= "invalid";
298 IMAP0_OFFSET
= 0xff00,
299 DMAP0_OFFSET
= 0xff08,
300 DMAP2_SHADDOW
= 0xff04,
301 DMAP2_OFFSET
= 0xff0c
305 set_dmap_register (int reg_nr
, unsigned long value
)
307 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
308 + DMAP0_OFFSET
+ 2 * reg_nr
);
309 WRITE_16 (raw
, value
);
311 if ((d10v_debug
& DEBUG_MEMORY
))
313 (*d10v_callback
->printf_filtered
)
314 (d10v_callback
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
320 dmap_register (void *regcache
, int reg_nr
)
322 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
323 + DMAP0_OFFSET
+ 2 * reg_nr
);
324 return READ_16 (raw
);
328 set_imap_register (int reg_nr
, unsigned long value
)
330 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
331 + IMAP0_OFFSET
+ 2 * reg_nr
);
332 WRITE_16 (raw
, value
);
334 if ((d10v_debug
& DEBUG_MEMORY
))
336 (*d10v_callback
->printf_filtered
)
337 (d10v_callback
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
343 imap_register (void *regcache
, int reg_nr
)
345 uint8
*raw
= map_memory (SIM_D10V_MEMORY_DATA
346 + IMAP0_OFFSET
+ 2 * reg_nr
);
347 return READ_16 (raw
);
362 return HELD_SP (HELD_SPU_IDX
);
371 return HELD_SP (HELD_SPI_IDX
);
375 set_spi_register (unsigned long value
)
378 SET_GPR (SP_IDX
, value
);
379 SET_HELD_SP (HELD_SPI_IDX
, value
);
383 set_spu_register (unsigned long value
)
386 SET_GPR (SP_IDX
, value
);
387 SET_HELD_SP (HELD_SPU_IDX
, value
);
390 /* Given a virtual address in the DMAP address space, translate it
391 into a physical address. */
394 sim_d10v_translate_dmap_addr (unsigned long offset
,
398 unsigned long (*dmap_register
) (void *regcache
,
403 last_from
= "logical-data";
404 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
406 /* Logical address out side of data segments, not supported */
409 regno
= (offset
/ DMAP_BLOCK_SIZE
);
410 offset
= (offset
% DMAP_BLOCK_SIZE
);
411 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
413 /* Don't cross a BLOCK boundary */
414 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
416 map
= dmap_register (regcache
, regno
);
419 /* Always maps to data memory */
420 int iospi
= (offset
/ 0x1000) % 4;
421 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
422 last_to
= "io-space";
423 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
427 int sp
= ((map
& 0x3000) >> 12);
428 int segno
= (map
& 0x3ff);
431 case 0: /* 00: Unified memory */
432 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
435 case 1: /* 01: Instruction Memory */
436 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
437 last_to
= "chip-insn";
439 case 2: /* 10: Internal data memory */
440 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
441 last_to
= "chip-data";
443 case 3: /* 11: Reserved */
450 /* Given a virtual address in the IMAP address space, translate it
451 into a physical address. */
454 sim_d10v_translate_imap_addr (unsigned long offset
,
458 unsigned long (*imap_register
) (void *regcache
,
465 last_from
= "logical-insn";
466 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
468 /* Logical address outside of IMAP segments, not supported */
471 regno
= (offset
/ IMAP_BLOCK_SIZE
);
472 offset
= (offset
% IMAP_BLOCK_SIZE
);
473 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
475 /* Don't cross a BLOCK boundary */
476 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
478 map
= imap_register (regcache
, regno
);
479 sp
= (map
& 0x3000) >> 12;
480 segno
= (map
& 0x007f);
483 case 0: /* 00: unified memory */
484 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
487 case 1: /* 01: instruction memory */
488 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
489 last_to
= "chip-insn";
494 case 3: /* 11: for testing - instruction memory */
495 offset
= (offset
% 0x800);
496 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
497 if (offset
+ nr_bytes
> 0x800)
498 /* don't cross VM boundary */
499 nr_bytes
= 0x800 - offset
;
500 last_to
= "test-insn";
507 sim_d10v_translate_addr (unsigned long memaddr
,
509 unsigned long *targ_addr
,
511 unsigned long (*dmap_register
) (void *regcache
,
513 unsigned long (*imap_register
) (void *regcache
,
520 last_from
= "unknown";
523 seg
= (memaddr
>> 24);
524 off
= (memaddr
& 0xffffffL
);
526 /* However, if we've asked to use the previous generation of segment
527 mapping, rearrange the segments as follows. */
529 if (old_segment_mapping
)
533 case 0x00: /* DMAP translated memory */
536 case 0x01: /* IMAP translated memory */
539 case 0x10: /* On-chip data memory */
542 case 0x11: /* On-chip insn memory */
545 case 0x12: /* Unified memory */
553 case 0x00: /* Physical unified memory */
554 last_from
= "phys-unified";
556 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
557 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
558 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
561 case 0x01: /* Physical instruction memory */
562 last_from
= "phys-insn";
563 last_to
= "chip-insn";
564 phys
= SIM_D10V_MEMORY_INSN
+ off
;
565 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
566 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
569 case 0x02: /* Physical data memory segment */
570 last_from
= "phys-data";
571 last_to
= "chip-data";
572 phys
= SIM_D10V_MEMORY_DATA
+ off
;
573 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
574 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
577 case 0x10: /* in logical data address segment */
578 nr_bytes
= sim_d10v_translate_dmap_addr (off
, nr_bytes
, &phys
, regcache
,
582 case 0x11: /* in logical instruction address segment */
583 nr_bytes
= sim_d10v_translate_imap_addr (off
, nr_bytes
, &phys
, regcache
,
595 /* Return a pointer into the raw buffer designated by phys_addr. It
596 is assumed that the client has already ensured that the access
597 isn't going to cross a segment boundary. */
600 map_memory (unsigned phys_addr
)
605 int segment
= ((phys_addr
>> 24) & 0xff);
610 case 0x00: /* Unified memory */
612 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
613 last_segname
= "umem";
617 case 0x01: /* On-chip insn memory */
619 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
620 last_segname
= "imem";
624 case 0x02: /* On-chip data memory */
626 if ((phys_addr
& 0xff00) == 0xff00)
628 phys_addr
= (phys_addr
& 0xffff);
629 if (phys_addr
== DMAP2_SHADDOW
)
631 phys_addr
= DMAP2_OFFSET
;
632 last_segname
= "dmap";
635 last_segname
= "reg";
638 last_segname
= "dmem";
639 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
645 last_segname
= "scrap";
646 return State
.mem
.fault
;
651 *memory
= calloc (1, SEGMENT_SIZE
);
654 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Malloc failed.\n");
655 return State
.mem
.fault
;
659 offset
= (phys_addr
% SEGMENT_SIZE
);
660 raw
= *memory
+ offset
;
664 /* Transfer data to/from simulated memory. Since a bug in either the
665 simulated program or in gdb or the simulator itself may cause a
666 bogus address to be passed in, we need to do some sanity checking
667 on addresses to make sure they are within bounds. When an address
668 fails the bounds check, treat it as a zero length read/write rather
669 than aborting the entire run. */
672 xfer_mem (SIM_ADDR virt
,
673 unsigned char *buffer
,
680 phys_size
= sim_d10v_translate_addr (virt
, size
, &phys
, NULL
,
681 dmap_register
, imap_register
);
685 memory
= map_memory (phys
);
688 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
690 (*d10v_callback
->printf_filtered
)
692 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
693 (write_p
? "write" : "read"),
694 phys_size
, virt
, last_from
,
696 (long) memory
, last_segname
);
702 memcpy (memory
, buffer
, phys_size
);
706 memcpy (buffer
, memory
, phys_size
);
714 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
716 /* FIXME: this should be performing a virtual transfer */
717 return xfer_mem( addr
, buffer
, size
, 1);
721 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
723 /* FIXME: this should be performing a virtual transfer */
724 return xfer_mem( addr
, buffer
, size
, 0);
728 free_state (SIM_DESC sd
)
730 if (STATE_MODULES (sd
) != NULL
)
731 sim_module_uninstall (sd
);
732 sim_cpu_free_all (sd
);
736 SIM_DESC trace_sd
= NULL
;
739 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
742 struct hash_entry
*h
;
743 static int init_p
= 0;
745 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
746 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
748 /* The cpu data is kept in a separately allocated chunk of memory. */
749 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
755 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
761 /* getopt will print the error message so we just have to exit if this fails.
762 FIXME: Hmmm... in the case of gdb we need getopt to call
764 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
770 /* Check for/establish the a reference program image. */
771 if (sim_analyze_program (sd
,
772 (STATE_PROG_ARGV (sd
) != NULL
773 ? *STATE_PROG_ARGV (sd
)
774 : NULL
), abfd
) != SIM_RC_OK
)
780 /* Configure/verify the target byte order and other runtime
781 configuration options. */
782 if (sim_config (sd
) != SIM_RC_OK
)
784 sim_module_uninstall (sd
);
788 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
790 /* Uninstall the modules to avoid memory leaks,
791 file descriptor leaks, etc. */
792 sim_module_uninstall (sd
);
798 old_segment_mapping
= 0;
800 /* NOTE: This argument parsing is only effective when this function
801 is called by GDB. Standalone argument parsing is handled by
803 for (p
= argv
+ 1; *p
; ++p
)
805 if (strcmp (*p
, "-oldseg") == 0)
806 old_segment_mapping
= 1;
808 else if (strcmp (*p
, "-t") == 0)
810 else if (strncmp (*p
, "-t", 2) == 0)
811 d10v_debug
= atoi (*p
+ 2);
815 /* put all the opcodes in the hash table */
818 for (s
= Simops
; s
->func
; s
++)
820 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
822 /* go to the last entry in the chain */
828 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
830 perror ("malloc failure");
836 h
->opcode
= s
->opcode
;
837 h
->size
= s
->is_long
;
841 /* reset the processor state */
842 if (!State
.mem
.data
[0])
844 sim_create_inferior ((SIM_DESC
) 1, NULL
, NULL
, NULL
);
851 sim_close (SIM_DESC sd
, int quitting
)
857 dmem_addr (uint16 offset
)
863 /* Note: DMEM address range is 0..0x10000. Calling code can compute
864 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
865 is uint16 this is modulo'ed onto 0x0e5d. */
867 phys_size
= sim_d10v_translate_dmap_addr (offset
, 1, &phys
, NULL
,
871 mem
= State
.mem
.fault
;
874 mem
= map_memory (phys
);
876 if ((d10v_debug
& DEBUG_MEMORY
))
878 (*d10v_callback
->printf_filtered
)
880 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
882 phys
, phys_size
, last_to
,
883 (long) mem
, last_segname
);
890 imem_addr (uint32 offset
)
894 int phys_size
= sim_d10v_translate_imap_addr (offset
, 1, &phys
, NULL
,
898 return State
.mem
.fault
;
900 mem
= map_memory (phys
);
902 if ((d10v_debug
& DEBUG_MEMORY
))
904 (*d10v_callback
->printf_filtered
)
906 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
908 phys
, phys_size
, last_to
,
909 (long) mem
, last_segname
);
915 static int stop_simulator
= 0;
918 sim_stop (SIM_DESC sd
)
925 /* Run (or resume) the program. */
927 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
932 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
947 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
948 JMP (AE_VECTOR_START
);
954 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
955 JMP (RIE_VECTOR_START
);
965 iaddr
= imem_addr ((uint32
)PC
<< 2);
966 if (iaddr
== State
.mem
.fault
)
968 State
.exception
= SIGBUS
;
972 inst
= get_longword( iaddr
);
974 State
.pc_changed
= 0;
975 ins_type_counters
[ (int)INS_CYCLES
]++;
977 switch (inst
& 0xC0000000)
980 /* long instruction */
981 do_long (inst
& 0x3FFFFFFF);
985 do_2_short ( inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
989 do_2_short ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
992 do_parallel ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
996 /* If the PC of the current instruction matches RPT_E then
997 schedule a branch to the loop start. If one of those
998 instructions happens to be a branch, than that instruction
1000 if (!State
.pc_changed
)
1002 if (PSW_RP
&& PC
== RPT_E
)
1004 /* Note: The behavour of a branch instruction at RPT_E
1005 is implementation dependant, this simulator takes the
1006 branch. Branching to RPT_E is valid, the instruction
1007 must be executed before the loop is taken. */
1016 SET_RPT_C (RPT_C
- 1);
1024 /* Check for a breakpoint trap on this instruction. This
1025 overrides any pending branches or loops */
1026 if (PSW_DB
&& PC
== IBA
)
1030 SET_PSW (PSW
& PSW_SM_BIT
);
1031 SET_PC (SDBT_VECTOR_START
);
1034 /* Writeback all the DATA / PC changes */
1037 while ( !State
.exception
&& !stop_simulator
);
1039 if (step
&& !State
.exception
)
1040 State
.exception
= SIGTRAP
;
1044 sim_info (SIM_DESC sd
, int verbose
)
1051 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1052 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1053 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1054 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1055 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1057 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1058 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1059 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1060 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1061 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1063 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1064 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1065 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1066 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1067 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1068 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1069 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1070 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1071 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1072 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1074 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1075 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1076 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1077 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1078 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1079 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1081 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1082 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1083 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1084 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1085 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1086 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1087 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1089 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1090 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1091 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1092 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1093 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1094 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1095 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1098 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1099 "executed %*s long instruction(s)\n",
1100 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1103 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1104 "executed %*s parallel instruction(s)\n",
1105 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1108 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1109 "executed %*s instruction(s) encoded L->R\n",
1110 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1113 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1114 "executed %*s instruction(s) encoded R->L\n",
1115 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1118 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1119 "executed %*s unknown instruction(s)\n",
1120 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1123 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1124 "executed %*s instruction(s) due to EXExxx condition being true\n",
1125 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1128 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1129 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1130 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1133 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1134 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1135 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1137 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1138 "executed %*s cycle(s)\n",
1139 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1141 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1142 "executed %*s total instructions\n",
1143 size
, add_commas (buf1
, sizeof (buf1
), total
));
1147 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
1149 bfd_vma start_address
;
1151 /* reset all state information */
1152 memset (&State
.regs
, 0, (uintptr_t)&State
.mem
- (uintptr_t)&State
.regs
);
1154 /* There was a hack here to copy the values of argc and argv into r0
1155 and r1. The values were also saved into some high memory that
1156 won't be overwritten by the stack (0x7C00). The reason for doing
1157 this was to allow the 'run' program to accept arguments. Without
1158 the hack, this is not possible anymore. If the simulator is run
1159 from the debugger, arguments cannot be passed in, so this makes
1164 start_address
= bfd_get_start_address (abfd
);
1166 start_address
= 0xffc0 << 2;
1169 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_create_inferior: PC=0x%lx\n", (long) start_address
);
1171 SET_CREG (PC_CR
, start_address
>> 2);
1173 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1174 initializes imap0 and imap1 to 0x1000 as part of its ROM
1176 if (old_segment_mapping
)
1178 /* External memory startup. This is the HARD reset state. */
1179 set_imap_register (0, 0x0000);
1180 set_imap_register (1, 0x007f);
1181 set_dmap_register (0, 0x2000);
1182 set_dmap_register (1, 0x2000);
1183 set_dmap_register (2, 0x0000); /* Old DMAP */
1184 set_dmap_register (3, 0x0000);
1188 /* Internal memory startup. This is the ROM intialized state. */
1189 set_imap_register (0, 0x1000);
1190 set_imap_register (1, 0x1000);
1191 set_dmap_register (0, 0x2000);
1192 set_dmap_register (1, 0x2000);
1193 set_dmap_register (2, 0x2000); /* DMAP2 initial internal value is
1194 0x2000 on the new board. */
1195 set_dmap_register (3, 0x0000);
1203 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
1205 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
1207 switch (State
.exception
)
1209 case SIG_D10V_STOP
: /* stop instruction */
1210 *reason
= sim_exited
;
1214 case SIG_D10V_EXIT
: /* exit trap */
1215 *reason
= sim_exited
;
1220 *reason
= sim_stopped
;
1221 *sigrc
= GDB_SIGNAL_BUS
;
1224 default: /* some signal */
1225 *reason
= sim_stopped
;
1226 if (stop_simulator
&& !State
.exception
)
1227 *sigrc
= GDB_SIGNAL_INT
;
1229 *sigrc
= State
.exception
;
1237 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1240 switch ((enum sim_d10v_regs
) rn
)
1242 case SIM_D10V_R0_REGNUM
:
1243 case SIM_D10V_R1_REGNUM
:
1244 case SIM_D10V_R2_REGNUM
:
1245 case SIM_D10V_R3_REGNUM
:
1246 case SIM_D10V_R4_REGNUM
:
1247 case SIM_D10V_R5_REGNUM
:
1248 case SIM_D10V_R6_REGNUM
:
1249 case SIM_D10V_R7_REGNUM
:
1250 case SIM_D10V_R8_REGNUM
:
1251 case SIM_D10V_R9_REGNUM
:
1252 case SIM_D10V_R10_REGNUM
:
1253 case SIM_D10V_R11_REGNUM
:
1254 case SIM_D10V_R12_REGNUM
:
1255 case SIM_D10V_R13_REGNUM
:
1256 case SIM_D10V_R14_REGNUM
:
1257 case SIM_D10V_R15_REGNUM
:
1258 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1261 case SIM_D10V_CR0_REGNUM
:
1262 case SIM_D10V_CR1_REGNUM
:
1263 case SIM_D10V_CR2_REGNUM
:
1264 case SIM_D10V_CR3_REGNUM
:
1265 case SIM_D10V_CR4_REGNUM
:
1266 case SIM_D10V_CR5_REGNUM
:
1267 case SIM_D10V_CR6_REGNUM
:
1268 case SIM_D10V_CR7_REGNUM
:
1269 case SIM_D10V_CR8_REGNUM
:
1270 case SIM_D10V_CR9_REGNUM
:
1271 case SIM_D10V_CR10_REGNUM
:
1272 case SIM_D10V_CR11_REGNUM
:
1273 case SIM_D10V_CR12_REGNUM
:
1274 case SIM_D10V_CR13_REGNUM
:
1275 case SIM_D10V_CR14_REGNUM
:
1276 case SIM_D10V_CR15_REGNUM
:
1277 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1280 case SIM_D10V_A0_REGNUM
:
1281 case SIM_D10V_A1_REGNUM
:
1282 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1285 case SIM_D10V_SPI_REGNUM
:
1286 /* PSW_SM indicates that the current SP is the USER
1288 WRITE_16 (memory
, spi_register ());
1291 case SIM_D10V_SPU_REGNUM
:
1292 /* PSW_SM indicates that the current SP is the USER
1294 WRITE_16 (memory
, spu_register ());
1297 case SIM_D10V_IMAP0_REGNUM
:
1298 case SIM_D10V_IMAP1_REGNUM
:
1299 WRITE_16 (memory
, imap_register (NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1302 case SIM_D10V_DMAP0_REGNUM
:
1303 case SIM_D10V_DMAP1_REGNUM
:
1304 case SIM_D10V_DMAP2_REGNUM
:
1305 case SIM_D10V_DMAP3_REGNUM
:
1306 WRITE_16 (memory
, dmap_register (NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1309 case SIM_D10V_TS2_DMAP_REGNUM
:
1320 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1323 switch ((enum sim_d10v_regs
) rn
)
1325 case SIM_D10V_R0_REGNUM
:
1326 case SIM_D10V_R1_REGNUM
:
1327 case SIM_D10V_R2_REGNUM
:
1328 case SIM_D10V_R3_REGNUM
:
1329 case SIM_D10V_R4_REGNUM
:
1330 case SIM_D10V_R5_REGNUM
:
1331 case SIM_D10V_R6_REGNUM
:
1332 case SIM_D10V_R7_REGNUM
:
1333 case SIM_D10V_R8_REGNUM
:
1334 case SIM_D10V_R9_REGNUM
:
1335 case SIM_D10V_R10_REGNUM
:
1336 case SIM_D10V_R11_REGNUM
:
1337 case SIM_D10V_R12_REGNUM
:
1338 case SIM_D10V_R13_REGNUM
:
1339 case SIM_D10V_R14_REGNUM
:
1340 case SIM_D10V_R15_REGNUM
:
1341 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1344 case SIM_D10V_CR0_REGNUM
:
1345 case SIM_D10V_CR1_REGNUM
:
1346 case SIM_D10V_CR2_REGNUM
:
1347 case SIM_D10V_CR3_REGNUM
:
1348 case SIM_D10V_CR4_REGNUM
:
1349 case SIM_D10V_CR5_REGNUM
:
1350 case SIM_D10V_CR6_REGNUM
:
1351 case SIM_D10V_CR7_REGNUM
:
1352 case SIM_D10V_CR8_REGNUM
:
1353 case SIM_D10V_CR9_REGNUM
:
1354 case SIM_D10V_CR10_REGNUM
:
1355 case SIM_D10V_CR11_REGNUM
:
1356 case SIM_D10V_CR12_REGNUM
:
1357 case SIM_D10V_CR13_REGNUM
:
1358 case SIM_D10V_CR14_REGNUM
:
1359 case SIM_D10V_CR15_REGNUM
:
1360 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1363 case SIM_D10V_A0_REGNUM
:
1364 case SIM_D10V_A1_REGNUM
:
1365 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1368 case SIM_D10V_SPI_REGNUM
:
1369 /* PSW_SM indicates that the current SP is the USER
1371 set_spi_register (READ_16 (memory
));
1374 case SIM_D10V_SPU_REGNUM
:
1375 set_spu_register (READ_16 (memory
));
1378 case SIM_D10V_IMAP0_REGNUM
:
1379 case SIM_D10V_IMAP1_REGNUM
:
1380 set_imap_register (rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1383 case SIM_D10V_DMAP0_REGNUM
:
1384 case SIM_D10V_DMAP1_REGNUM
:
1385 case SIM_D10V_DMAP2_REGNUM
:
1386 case SIM_D10V_DMAP3_REGNUM
:
1387 set_dmap_register (rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1390 case SIM_D10V_TS2_DMAP_REGNUM
: