]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
5 #include "remote-sim.h"
9 #define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
10 #define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
11 #define UMEM_SIZE 17 /* Each unified memory segment is 17 bits */
12 #define UMEM_SEGMENTS 128 /* Number of segments in unified memory region */
14 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
17 static SIM_OPEN_KIND sim_kind
;
19 host_callback
*d10v_callback
;
20 unsigned long ins_type_counters
[ (int)INS_MAX
];
24 static int init_text_p
= 0;
25 /* non-zero if we opened prog_bfd */
26 static int prog_bfd_was_opened_p
;
32 static long hash
PARAMS ((long insn
, int format
));
33 static struct hash_entry
*lookup_hash
PARAMS ((uint32 ins
, int size
));
34 static void get_operands
PARAMS ((struct simops
*s
, uint32 ins
));
35 static void do_long
PARAMS ((uint32 ins
));
36 static void do_2_short
PARAMS ((uint16 ins1
, uint16 ins2
, enum _leftright leftright
));
37 static void do_parallel
PARAMS ((uint16 ins1
, uint16 ins2
));
38 static char *add_commas
PARAMS ((char *buf
, int sizeof_buf
, unsigned long value
));
39 extern void sim_set_profile
PARAMS ((int n
));
40 extern void sim_set_profile_size
PARAMS ((int n
));
43 #if defined(__GNUC__) && defined(__OPTIMIZE__)
44 #define INLINE __inline__
53 struct hash_entry
*next
;
60 struct hash_entry hash_table
[MAX_HASH
+1];
67 if (format
& LONG_OPCODE
)
68 return ((insn
& 0x3F000000) >> 24);
70 return((insn
& 0x7E00) >> 9);
73 INLINE
static struct hash_entry
*
74 lookup_hash (ins
, size
)
81 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
83 h
= &hash_table
[(ins
& 0x7E00) >> 9];
85 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
89 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR looking up hash for %x at PC %x\n",ins
, PC
);
98 get_operands (struct simops
*s
, uint32 ins
)
100 int i
, shift
, bits
, flags
;
102 for (i
=0; i
< s
->numops
; i
++)
104 shift
= s
->operands
[3*i
];
105 bits
= s
->operands
[3*i
+1];
106 flags
= s
->operands
[3*i
+2];
107 mask
= 0x7FFFFFFF >> (31 - bits
);
108 OP
[i
] = (ins
>> shift
) & mask
;
110 /* FIXME: for tracing, update values that need to be updated each
111 instruction decode cycle */
112 State
.trace
.psw
= PSW
;
119 if (!init_text_p
&& prog_bfd
!= NULL
)
122 for (s
= prog_bfd
->sections
; s
; s
= s
->next
)
123 if (strcmp (bfd_get_section_name (prog_bfd
, s
), ".text") == 0)
126 text_start
= bfd_get_section_vma (prog_bfd
, s
);
127 text_end
= text_start
+ bfd_section_size (prog_bfd
, s
);
132 return (PC
<< 2) + text_start
;
139 struct hash_entry
*h
;
141 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
142 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_long 0x%x\n", ins
);
144 h
= lookup_hash (ins
, 1);
145 get_operands (h
->ops
, ins
);
146 State
.ins_type
= INS_LONG
;
147 ins_type_counters
[ (int)State
.ins_type
]++;
152 do_2_short (ins1
, ins2
, leftright
)
154 enum _leftright leftright
;
156 struct hash_entry
*h
;
157 enum _ins_type first
, second
;
160 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
161 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_2_short 0x%x (%s) -> 0x%x\n",
162 ins1
, (leftright
) ? "left" : "right", ins2
);
165 if (leftright
== LEFT_FIRST
)
169 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
175 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
178 /* Issue the first instruction */
179 h
= lookup_hash (ins1
, 0);
180 get_operands (h
->ops
, ins1
);
181 State
.ins_type
= first
;
182 ins_type_counters
[ (int)State
.ins_type
]++;
185 /* Issue the second instruction (if the PC hasn't changed) */
186 if (!State
.pc_changed
&& !State
.exception
)
188 /* finish any existing instructions */
190 h
= lookup_hash (ins2
, 0);
191 get_operands (h
->ops
, ins2
);
192 State
.ins_type
= second
;
193 ins_type_counters
[ (int)State
.ins_type
]++;
194 ins_type_counters
[ (int)INS_CYCLES
]++;
197 else if (!State
.exception
)
198 ins_type_counters
[ (int)INS_COND_JUMP
]++;
202 do_parallel (ins1
, ins2
)
205 struct hash_entry
*h1
, *h2
;
207 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
208 (*d10v_callback
->printf_filtered
) (d10v_callback
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
210 ins_type_counters
[ (int)INS_PARALLEL
]++;
211 h1
= lookup_hash (ins1
, 0);
212 h2
= lookup_hash (ins2
, 0);
214 if (h1
->ops
->exec_type
== PARONLY
)
216 get_operands (h1
->ops
, ins1
);
217 State
.ins_type
= INS_LEFT_COND_TEST
;
218 ins_type_counters
[ (int)State
.ins_type
]++;
222 ins_type_counters
[ (int)INS_COND_TRUE
]++;
223 get_operands (h2
->ops
, ins2
);
224 State
.ins_type
= INS_RIGHT_COND_EXE
;
225 ins_type_counters
[ (int)State
.ins_type
]++;
229 ins_type_counters
[ (int)INS_COND_FALSE
]++;
231 else if (h2
->ops
->exec_type
== PARONLY
)
233 get_operands (h2
->ops
, ins2
);
234 State
.ins_type
= INS_RIGHT_COND_TEST
;
235 ins_type_counters
[ (int)State
.ins_type
]++;
239 ins_type_counters
[ (int)INS_COND_TRUE
]++;
240 get_operands (h1
->ops
, ins1
);
241 State
.ins_type
= INS_LEFT_COND_EXE
;
242 ins_type_counters
[ (int)State
.ins_type
]++;
246 ins_type_counters
[ (int)INS_COND_FALSE
]++;
250 get_operands (h1
->ops
, ins1
);
251 State
.ins_type
= INS_LEFT_PARALLEL
;
252 ins_type_counters
[ (int)State
.ins_type
]++;
254 if (!State
.exception
)
256 get_operands (h2
->ops
, ins2
);
257 State
.ins_type
= INS_RIGHT_PARALLEL
;
258 ins_type_counters
[ (int)State
.ins_type
]++;
265 add_commas(buf
, sizeof_buf
, value
)
271 char *endbuf
= buf
+ sizeof_buf
- 1;
281 *--endbuf
= (value
% 10) + '0';
282 } while ((value
/= 10) != 0);
296 for (i
=0;i
<UMEM_SEGMENTS
;i
++)
300 free (State
.umem
[i
]);
301 State
.umem
[i
] = NULL
;
308 State
.imem
= (uint8
*)calloc(1,1<<IMEM_SIZE
);
309 State
.dmem
= (uint8
*)calloc(1,1<<DMEM_SIZE
);
310 for (i
=1;i
<(UMEM_SEGMENTS
-1);i
++)
311 State
.umem
[i
] = NULL
;
312 State
.umem
[0] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
313 State
.umem
[1] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
314 State
.umem
[2] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
315 State
.umem
[UMEM_SEGMENTS
-1] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
316 if (!State
.imem
|| !State
.dmem
|| !State
.umem
[0] || !State
.umem
[1] || !State
.umem
[2] || !State
.umem
[UMEM_SEGMENTS
-1] )
318 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Memory allocation failed.\n");
323 if ((d10v_debug
& DEBUG_MEMSIZE
) != 0)
326 (*d10v_callback
->printf_filtered
) (d10v_callback
,
327 "Allocated %s bytes instruction memory and\n",
328 add_commas (buffer
, sizeof (buffer
), (1UL<<IMEM_SIZE
)));
330 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %s bytes data memory.\n",
331 add_commas (buffer
, sizeof (buffer
), (1UL<<IMEM_SIZE
)));
336 /* Transfer data to/from simulated memory. Since a bug in either the
337 simulated program or in gdb or the simulator itself may cause a
338 bogus address to be passed in, we need to do some sanity checking
339 on addresses to make sure they are within bounds. When an address
340 fails the bounds check, treat it as a zero length read/write rather
341 than aborting the entire run. */
344 xfer_mem (SIM_ADDR addr
,
345 unsigned char *buffer
,
349 unsigned char *memory
;
350 int segment
= ((addr
>> 24) & 0xff);
351 addr
= (addr
& 0x00ffffff);
354 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
358 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_write %d bytes to 0x%02x:%06x\n", size
, segment
, addr
);
362 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_read %d bytes from 0x%2x:%6x\n", size
, segment
, addr
);
367 /* to access data, we use the following mapping
368 0x00xxxxxx: Logical data address segment (DMAP translated memory)
369 0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
370 0x10xxxxxx: Physical data memory segment (On-chip data memory)
371 0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
372 0x12xxxxxx: Phisical unified memory segment (Unified memory)
377 case 0x00: /* DMAP translated memory */
380 for (byte
= 0; byte
< size
; byte
++)
382 uint8
*mem
= dmem_addr (addr
+ byte
);
393 case 0x01: /* IMAP translated memory */
396 for (byte
= 0; byte
< size
; byte
++)
398 uint8
*mem
= imem_addr (addr
+ byte
);
409 case 0x10: /* On-chip data memory */
411 addr
&= ((1 << DMEM_SIZE
) - 1);
412 if ((addr
+ size
) > (1 << DMEM_SIZE
))
414 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: data address 0x%x is outside range 0-0x%x.\n",
415 addr
+ size
- 1, (1 << DMEM_SIZE
) - 1);
418 memory
= State
.dmem
+ addr
;
422 case 0x11: /* On-chip insn memory */
424 addr
&= ((1 << IMEM_SIZE
) - 1);
425 if ((addr
+ size
) > (1 << IMEM_SIZE
))
427 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: instruction address 0x%x is outside range 0-0x%x.\n",
428 addr
+ size
- 1, (1 << IMEM_SIZE
) - 1);
431 memory
= State
.imem
+ addr
;
435 case 0x12: /* Unified memory */
437 int startsegment
, startoffset
; /* Segment and offset within segment where xfer starts */
438 int endsegment
, endoffset
; /* Segment and offset within segment where xfer ends */
440 startsegment
= addr
>> UMEM_SIZE
;
441 startoffset
= addr
& ((1 << UMEM_SIZE
) - 1);
442 endsegment
= (addr
+ size
) >> UMEM_SIZE
;
443 endoffset
= (addr
+ size
) & ((1 << UMEM_SIZE
) - 1);
445 /* FIXME: We do not currently implement xfers across segments,
446 so detect this case and fail gracefully. */
448 if ((startsegment
!= endsegment
) && !((endsegment
== (startsegment
+ 1)) && endoffset
== 0))
450 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: Unimplemented support for transfers across unified memory segment boundaries\n");
453 if (!State
.umem
[startsegment
])
456 if ((d10v_debug
& DEBUG_MEMSIZE
) != 0)
458 (*d10v_callback
->printf_filtered
) (d10v_callback
,"Allocating %s bytes unified memory to region %d\n",
459 add_commas (buffer
, sizeof (buffer
), (1UL<<IMEM_SIZE
)), startsegment
);
462 State
.umem
[startsegment
] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
464 if (!State
.umem
[startsegment
])
466 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: Memory allocation of 0x%x bytes failed.\n", 1<<UMEM_SIZE
);
469 memory
= State
.umem
[startsegment
] + startoffset
;
475 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: address 0x%lx is not in valid range\n", (long) addr
);
476 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x00xxxxxx: Logical data address segment (DMAP translated memory)\n");
477 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x01xxxxxx: Logical instruction address segment (IMAP translated memory)\n");
478 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x10xxxxxx: Physical data memory segment (On-chip data memory)\n");
479 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)\n");
480 (*d10v_callback
->printf_filtered
) (d10v_callback
, "0x12xxxxxx: Phisical unified memory segment (Unified memory)\n");
487 memcpy (memory
, buffer
, size
);
491 memcpy (buffer
, memory
, size
);
499 sim_write (sd
, addr
, buffer
, size
)
502 unsigned char *buffer
;
505 /* FIXME: this should be performing a virtual transfer */
506 return xfer_mem( addr
, buffer
, size
, 1);
510 sim_read (sd
, addr
, buffer
, size
)
513 unsigned char *buffer
;
516 /* FIXME: this should be performing a virtual transfer */
517 return xfer_mem( addr
, buffer
, size
, 0);
522 sim_open (kind
, callback
, abfd
, argv
)
524 host_callback
*callback
;
529 struct hash_entry
*h
;
530 static int init_p
= 0;
534 d10v_callback
= callback
;
537 for (p
= argv
+ 1; *p
; ++p
)
540 if (strcmp (*p
, "-t") == 0)
544 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: unsupported option(s): %s\n",*p
);
547 /* put all the opcodes in the hash table */
550 for (s
= Simops
; s
->func
; s
++)
552 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
554 /* go to the last entry in the chain */
560 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
562 perror ("malloc failure");
568 h
->opcode
= s
->opcode
;
569 h
->size
= s
->is_long
;
573 /* reset the processor state */
576 sim_create_inferior ((SIM_DESC
) 1, NULL
, NULL
, NULL
);
578 /* Fudge our descriptor. */
584 sim_close (sd
, quitting
)
588 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
590 bfd_close (prog_bfd
);
592 prog_bfd_was_opened_p
= 0;
600 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile %d\n",n
);
604 sim_set_profile_size (n
)
607 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_set_profile_size %d\n",n
);
621 if ( (addr
& 0xfff0) != 0xff00)
623 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
624 (long)addr
, (long)decode_pc ());
625 State
.exception
= SIGBUS
;
628 return State
.dmem
+ addr
;
635 /* instruction memory */
636 return (DMAP
& 0xf) * 0x4000 + State
.imem
+ (addr
- 0x8000);
641 /* this is ugly because we allocate unified memory in 128K segments and */
642 /* dmap addresses 16k segments */
643 seg
= (DMAP
& 0x3ff) >> 3;
644 if (State
.umem
[seg
] == NULL
)
647 (*d10v_callback
->printf_filtered
) (d10v_callback
,"Allocating %d bytes unified memory to region %d\n", 1<<UMEM_SIZE
, seg
);
649 State
.umem
[seg
] = (uint8
*)calloc(1,1<<UMEM_SIZE
);
650 if (!State
.umem
[seg
])
652 (*d10v_callback
->printf_filtered
) (d10v_callback
,
653 "ERROR: alloc failed. unified memory region %d unmapped, pc = 0x%lx\n",
654 seg
, (long)decode_pc ());
655 State
.exception
= SIGBUS
;
658 return State
.umem
[seg
] + (DMAP
& 7) * 0x4000 + (addr
- 0x8000);
661 return State
.dmem
+ addr
;
666 imem_addr (uint32 pc
)
676 return State
.imem
+ pc
;
678 if (State
.umem
[imap
& 0xff] == NULL
)
681 /* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */
682 pc
&= (1 << UMEM_SIZE
) - 1;
684 return State
.umem
[imap
& 0xff] + pc
;
688 static int stop_simulator
= 0;
699 /* Run (or resume) the program. */
701 sim_resume (sd
, step
, siggnal
)
708 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
715 iaddr
= imem_addr ((uint32
)PC
<< 2);
718 State
.exception
= SIGBUS
;
722 inst
= get_longword( iaddr
);
724 State
.pc_changed
= 0;
725 ins_type_counters
[ (int)INS_CYCLES
]++;
727 switch (inst
& 0xC0000000)
730 /* long instruction */
731 do_long (inst
& 0x3FFFFFFF);
735 do_2_short ( inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
739 do_2_short ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
742 do_parallel ((inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
746 /* If the PC of the current instruction matches RPT_E then
747 schedule a branch to the loop start. If one of those
748 instructions happens to be a branch, than that instruction
750 if (!State
.pc_changed
)
752 if (PSW_RP
&& PC
== RPT_E
)
754 /* Note: The behavour of a branch instruction at RPT_E
755 is implementation dependant, this simulator takes the
756 branch. Branching to RPT_E is valid, the instruction
757 must be executed before the loop is taken. */
766 SET_RPT_C (RPT_C
- 1);
774 /* Check for a breakpoint trap on this instruction. This
775 overrides any pending branches or loops */
776 if (PSW_DB
&& PC
== IBA
)
780 SET_PSW (PSW
& PSW_SM_BIT
);
781 SET_PC (SDBT_VECTOR_START
);
784 /* Writeback all the DATA / PC changes */
788 while ( !State
.exception
&& !stop_simulator
);
790 if (step
&& !State
.exception
)
791 State
.exception
= SIGTRAP
;
801 sim_resume (sd
, 0, 0);
806 sim_info (sd
, verbose
)
815 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
816 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
817 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
818 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
819 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
821 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
822 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
823 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
824 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
825 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
827 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
828 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
829 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
830 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
831 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
832 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
833 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
834 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
835 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
836 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
838 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
839 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
840 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
841 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
842 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
843 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
845 (*d10v_callback
->printf_filtered
) (d10v_callback
,
846 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
847 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
848 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
849 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
850 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
851 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
853 (*d10v_callback
->printf_filtered
) (d10v_callback
,
854 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
855 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
856 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
857 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
858 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
859 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
862 (*d10v_callback
->printf_filtered
) (d10v_callback
,
863 "executed %*s long instruction(s)\n",
864 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
867 (*d10v_callback
->printf_filtered
) (d10v_callback
,
868 "executed %*s parallel instruction(s)\n",
869 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
872 (*d10v_callback
->printf_filtered
) (d10v_callback
,
873 "executed %*s instruction(s) encoded L->R\n",
874 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
877 (*d10v_callback
->printf_filtered
) (d10v_callback
,
878 "executed %*s instruction(s) encoded R->L\n",
879 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
882 (*d10v_callback
->printf_filtered
) (d10v_callback
,
883 "executed %*s unknown instruction(s)\n",
884 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
887 (*d10v_callback
->printf_filtered
) (d10v_callback
,
888 "executed %*s instruction(s) due to EXExxx condition being true\n",
889 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
892 (*d10v_callback
->printf_filtered
) (d10v_callback
,
893 "skipped %*s instruction(s) due to EXExxx condition being false\n",
894 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
897 (*d10v_callback
->printf_filtered
) (d10v_callback
,
898 "skipped %*s instruction(s) due to conditional branch succeeding\n",
899 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
901 (*d10v_callback
->printf_filtered
) (d10v_callback
,
902 "executed %*s cycle(s)\n",
903 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
905 (*d10v_callback
->printf_filtered
) (d10v_callback
,
906 "executed %*s total instructions\n",
907 size
, add_commas (buf1
, sizeof (buf1
), total
));
911 sim_create_inferior (sd
, abfd
, argv
, env
)
917 bfd_vma start_address
;
919 /* reset all state information */
920 memset (&State
.regs
, 0, (int)&State
.imem
- (int)&State
.regs
[0]);
924 /* a hack to set r0/r1 with argc/argv */
925 /* some high memory that won't be overwritten by the stack soon */
926 bfd_vma addr
= 0x7C00;
931 int size
= strlen (argv
[i
]) + 1;
932 SW (addr
+ 2*i
, addr
+ p
);
933 sim_write (sd
, addr
+ 0, argv
[i
], size
);
943 start_address
= bfd_get_start_address (abfd
);
945 start_address
= 0xffc0 << 2;
948 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_create_inferior: PC=0x%lx\n", (long) start_address
);
950 SET_CREG (PC_CR
, start_address
>> 2);
952 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
953 /* resets imap0 and imap1 to 0x1000. */
973 sim_set_callbacks (p
)
980 sim_stop_reason (sd
, reason
, sigrc
)
982 enum sim_stop
*reason
;
985 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
987 switch (State
.exception
)
989 case SIG_D10V_STOP
: /* stop instruction */
990 *reason
= sim_exited
;
994 case SIG_D10V_EXIT
: /* exit trap */
995 *reason
= sim_exited
;
999 default: /* some signal */
1000 *reason
= sim_stopped
;
1001 if (stop_simulator
&& !State
.exception
)
1004 *sigrc
= State
.exception
;
1012 sim_fetch_register (sd
, rn
, memory
, length
)
1015 unsigned char *memory
;
1019 WRITE_64 (memory
, ACC (rn
-35));
1021 WRITE_16 (memory
, IMAP0
);
1023 WRITE_16 (memory
, IMAP1
);
1025 WRITE_16 (memory
, DMAP
);
1027 WRITE_16 (memory
, CREG (rn
- 16));
1029 WRITE_16 (memory
, GPR (rn
));
1034 sim_store_register (sd
, rn
, memory
, length
)
1037 unsigned char *memory
;
1041 SET_ACC (rn
-35, READ_64 (memory
) & MASK40
);
1043 SET_DMAP( READ_16(memory
) );
1045 SET_IMAP1( READ_16(memory
) );
1047 SET_IMAP0( READ_16(memory
) );
1049 SET_CREG (rn
- 16, READ_16 (memory
));
1051 SET_GPR (rn
, READ_16 (memory
));
1058 sim_do_command (sd
, cmd
)
1062 (*d10v_callback
->printf_filtered
) (d10v_callback
, "sim_do_command: %s\n",cmd
);
1066 sim_load (sd
, prog
, abfd
, from_tty
)
1072 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
1074 if (prog_bfd
!= NULL
&& prog_bfd_was_opened_p
)
1076 bfd_close (prog_bfd
);
1077 prog_bfd_was_opened_p
= 0;
1079 prog_bfd
= sim_load_file (sd
, myname
, d10v_callback
, prog
, abfd
,
1080 sim_kind
== SIM_OPEN_DEBUG
,
1081 1/*LMA*/, sim_write
);
1082 if (prog_bfd
== NULL
)
1084 prog_bfd_was_opened_p
= abfd
== NULL
;