]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
5 #include "gdb/callback.h"
6 #include "gdb/remote-sim.h"
9 #include "sim-options.h"
11 #include "gdb/sim-d10v.h"
12 #include "gdb/signals.h"
19 #endif /* HAVE_STRING_H */
20 #endif /* HAVE_STRINGS_H */
26 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
30 /* Set this to true to get the previous segment layout. */
32 int old_segment_mapping
;
34 unsigned long ins_type_counters
[ (int)INS_MAX
];
38 static long hash (long insn
, int format
);
39 static struct hash_entry
*lookup_hash (SIM_DESC
, SIM_CPU
*, uint32 ins
, int size
);
40 static void get_operands (struct simops
*s
, uint32 ins
);
41 static void do_long (SIM_DESC
, SIM_CPU
*, uint32 ins
);
42 static void do_2_short (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
, enum _leftright leftright
);
43 static void do_parallel (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
);
44 static char *add_commas (char *buf
, int sizeof_buf
, unsigned long value
);
45 static INLINE uint8
*map_memory (SIM_DESC
, SIM_CPU
*, unsigned phys_addr
);
50 struct hash_entry
*next
;
57 struct hash_entry hash_table
[MAX_HASH
+1];
60 hash (long insn
, int format
)
62 if (format
& LONG_OPCODE
)
63 return ((insn
& 0x3F000000) >> 24);
65 return((insn
& 0x7E00) >> 9);
68 INLINE
static struct hash_entry
*
69 lookup_hash (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
, int size
)
74 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
76 h
= &hash_table
[(ins
& 0x7E00) >> 9];
78 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
81 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGILL
);
88 get_operands (struct simops
*s
, uint32 ins
)
90 int i
, shift
, bits
, flags
;
92 for (i
=0; i
< s
->numops
; i
++)
94 shift
= s
->operands
[3*i
];
95 bits
= s
->operands
[3*i
+1];
96 flags
= s
->operands
[3*i
+2];
97 mask
= 0x7FFFFFFF >> (31 - bits
);
98 OP
[i
] = (ins
>> shift
) & mask
;
100 /* FIXME: for tracing, update values that need to be updated each
101 instruction decode cycle */
102 State
.trace
.psw
= PSW
;
106 do_long (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
)
108 struct hash_entry
*h
;
110 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
111 sim_io_printf (sd
, "do_long 0x%x\n", ins
);
113 h
= lookup_hash (sd
, cpu
, ins
, 1);
116 get_operands (h
->ops
, ins
);
117 State
.ins_type
= INS_LONG
;
118 ins_type_counters
[ (int)State
.ins_type
]++;
119 (h
->ops
->func
) (sd
, cpu
);
123 do_2_short (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
, enum _leftright leftright
)
125 struct hash_entry
*h
;
126 enum _ins_type first
, second
;
129 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
130 sim_io_printf (sd
, "do_2_short 0x%x (%s) -> 0x%x\n", ins1
,
131 leftright
? "left" : "right", ins2
);
134 if (leftright
== LEFT_FIRST
)
138 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
144 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
147 /* Issue the first instruction */
148 h
= lookup_hash (sd
, cpu
, ins1
, 0);
151 get_operands (h
->ops
, ins1
);
152 State
.ins_type
= first
;
153 ins_type_counters
[ (int)State
.ins_type
]++;
154 (h
->ops
->func
) (sd
, cpu
);
156 /* Issue the second instruction (if the PC hasn't changed) */
157 if (!State
.pc_changed
)
159 /* finish any existing instructions */
161 h
= lookup_hash (sd
, cpu
, ins2
, 0);
164 get_operands (h
->ops
, ins2
);
165 State
.ins_type
= second
;
166 ins_type_counters
[ (int)State
.ins_type
]++;
167 ins_type_counters
[ (int)INS_CYCLES
]++;
168 (h
->ops
->func
) (sd
, cpu
);
171 ins_type_counters
[ (int)INS_COND_JUMP
]++;
175 do_parallel (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
)
177 struct hash_entry
*h1
, *h2
;
179 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
180 sim_io_printf (sd
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
182 ins_type_counters
[ (int)INS_PARALLEL
]++;
183 h1
= lookup_hash (sd
, cpu
, ins1
, 0);
186 h2
= lookup_hash (sd
, cpu
, ins2
, 0);
190 if (h1
->ops
->exec_type
== PARONLY
)
192 get_operands (h1
->ops
, ins1
);
193 State
.ins_type
= INS_LEFT_COND_TEST
;
194 ins_type_counters
[ (int)State
.ins_type
]++;
195 (h1
->ops
->func
) (sd
, cpu
);
198 ins_type_counters
[ (int)INS_COND_TRUE
]++;
199 get_operands (h2
->ops
, ins2
);
200 State
.ins_type
= INS_RIGHT_COND_EXE
;
201 ins_type_counters
[ (int)State
.ins_type
]++;
202 (h2
->ops
->func
) (sd
, cpu
);
205 ins_type_counters
[ (int)INS_COND_FALSE
]++;
207 else if (h2
->ops
->exec_type
== PARONLY
)
209 get_operands (h2
->ops
, ins2
);
210 State
.ins_type
= INS_RIGHT_COND_TEST
;
211 ins_type_counters
[ (int)State
.ins_type
]++;
212 (h2
->ops
->func
) (sd
, cpu
);
215 ins_type_counters
[ (int)INS_COND_TRUE
]++;
216 get_operands (h1
->ops
, ins1
);
217 State
.ins_type
= INS_LEFT_COND_EXE
;
218 ins_type_counters
[ (int)State
.ins_type
]++;
219 (h1
->ops
->func
) (sd
, cpu
);
222 ins_type_counters
[ (int)INS_COND_FALSE
]++;
226 get_operands (h1
->ops
, ins1
);
227 State
.ins_type
= INS_LEFT_PARALLEL
;
228 ins_type_counters
[ (int)State
.ins_type
]++;
229 (h1
->ops
->func
) (sd
, cpu
);
230 get_operands (h2
->ops
, ins2
);
231 State
.ins_type
= INS_RIGHT_PARALLEL
;
232 ins_type_counters
[ (int)State
.ins_type
]++;
233 (h2
->ops
->func
) (sd
, cpu
);
238 add_commas (char *buf
, int sizeof_buf
, unsigned long value
)
241 char *endbuf
= buf
+ sizeof_buf
- 1;
251 *--endbuf
= (value
% 10) + '0';
252 } while ((value
/= 10) != 0);
261 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
263 if (State
.mem
.insn
[i
])
264 free (State
.mem
.insn
[i
]);
266 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
268 if (State
.mem
.data
[i
])
269 free (State
.mem
.data
[i
]);
271 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
273 if (State
.mem
.unif
[i
])
274 free (State
.mem
.unif
[i
]);
276 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
278 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
281 /* For tracing - leave info on last access around. */
282 static char *last_segname
= "invalid";
283 static char *last_from
= "invalid";
284 static char *last_to
= "invalid";
288 IMAP0_OFFSET
= 0xff00,
289 DMAP0_OFFSET
= 0xff08,
290 DMAP2_SHADDOW
= 0xff04,
291 DMAP2_OFFSET
= 0xff0c
295 set_dmap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
297 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
298 + DMAP0_OFFSET
+ 2 * reg_nr
);
299 WRITE_16 (raw
, value
);
301 if ((d10v_debug
& DEBUG_MEMORY
))
303 sim_io_printf (sd
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
309 dmap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
311 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
312 + DMAP0_OFFSET
+ 2 * reg_nr
);
313 return READ_16 (raw
);
317 set_imap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
319 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
320 + IMAP0_OFFSET
+ 2 * reg_nr
);
321 WRITE_16 (raw
, value
);
323 if ((d10v_debug
& DEBUG_MEMORY
))
325 sim_io_printf (sd
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
331 imap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
333 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
334 + IMAP0_OFFSET
+ 2 * reg_nr
);
335 return READ_16 (raw
);
350 return HELD_SP (HELD_SPU_IDX
);
359 return HELD_SP (HELD_SPI_IDX
);
363 set_spi_register (unsigned long value
)
366 SET_GPR (SP_IDX
, value
);
367 SET_HELD_SP (HELD_SPI_IDX
, value
);
371 set_spu_register (unsigned long value
)
374 SET_GPR (SP_IDX
, value
);
375 SET_HELD_SP (HELD_SPU_IDX
, value
);
378 /* Given a virtual address in the DMAP address space, translate it
379 into a physical address. */
382 sim_d10v_translate_dmap_addr (SIM_DESC sd
,
384 unsigned long offset
,
388 unsigned long (*dmap_register
) (SIM_DESC
,
395 last_from
= "logical-data";
396 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
398 /* Logical address out side of data segments, not supported */
401 regno
= (offset
/ DMAP_BLOCK_SIZE
);
402 offset
= (offset
% DMAP_BLOCK_SIZE
);
403 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
405 /* Don't cross a BLOCK boundary */
406 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
408 map
= dmap_register (sd
, cpu
, regcache
, regno
);
411 /* Always maps to data memory */
412 int iospi
= (offset
/ 0x1000) % 4;
413 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
414 last_to
= "io-space";
415 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
419 int sp
= ((map
& 0x3000) >> 12);
420 int segno
= (map
& 0x3ff);
423 case 0: /* 00: Unified memory */
424 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
427 case 1: /* 01: Instruction Memory */
428 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
429 last_to
= "chip-insn";
431 case 2: /* 10: Internal data memory */
432 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
433 last_to
= "chip-data";
435 case 3: /* 11: Reserved */
442 /* Given a virtual address in the IMAP address space, translate it
443 into a physical address. */
446 sim_d10v_translate_imap_addr (SIM_DESC sd
,
448 unsigned long offset
,
452 unsigned long (*imap_register
) (SIM_DESC
,
461 last_from
= "logical-insn";
462 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
464 /* Logical address outside of IMAP segments, not supported */
467 regno
= (offset
/ IMAP_BLOCK_SIZE
);
468 offset
= (offset
% IMAP_BLOCK_SIZE
);
469 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
471 /* Don't cross a BLOCK boundary */
472 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
474 map
= imap_register (sd
, cpu
, regcache
, regno
);
475 sp
= (map
& 0x3000) >> 12;
476 segno
= (map
& 0x007f);
479 case 0: /* 00: unified memory */
480 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
483 case 1: /* 01: instruction memory */
484 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
485 last_to
= "chip-insn";
490 case 3: /* 11: for testing - instruction memory */
491 offset
= (offset
% 0x800);
492 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
493 if (offset
+ nr_bytes
> 0x800)
494 /* don't cross VM boundary */
495 nr_bytes
= 0x800 - offset
;
496 last_to
= "test-insn";
503 sim_d10v_translate_addr (SIM_DESC sd
,
505 unsigned long memaddr
,
507 unsigned long *targ_addr
,
509 unsigned long (*dmap_register
) (SIM_DESC
,
513 unsigned long (*imap_register
) (SIM_DESC
,
522 last_from
= "unknown";
525 seg
= (memaddr
>> 24);
526 off
= (memaddr
& 0xffffffL
);
528 /* However, if we've asked to use the previous generation of segment
529 mapping, rearrange the segments as follows. */
531 if (old_segment_mapping
)
535 case 0x00: /* DMAP translated memory */
538 case 0x01: /* IMAP translated memory */
541 case 0x10: /* On-chip data memory */
544 case 0x11: /* On-chip insn memory */
547 case 0x12: /* Unified memory */
555 case 0x00: /* Physical unified memory */
556 last_from
= "phys-unified";
558 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
559 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
560 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
563 case 0x01: /* Physical instruction memory */
564 last_from
= "phys-insn";
565 last_to
= "chip-insn";
566 phys
= SIM_D10V_MEMORY_INSN
+ off
;
567 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
568 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
571 case 0x02: /* Physical data memory segment */
572 last_from
= "phys-data";
573 last_to
= "chip-data";
574 phys
= SIM_D10V_MEMORY_DATA
+ off
;
575 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
576 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
579 case 0x10: /* in logical data address segment */
580 nr_bytes
= sim_d10v_translate_dmap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
581 regcache
, dmap_register
);
584 case 0x11: /* in logical instruction address segment */
585 nr_bytes
= sim_d10v_translate_imap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
586 regcache
, imap_register
);
597 /* Return a pointer into the raw buffer designated by phys_addr. It
598 is assumed that the client has already ensured that the access
599 isn't going to cross a segment boundary. */
602 map_memory (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned phys_addr
)
607 int segment
= ((phys_addr
>> 24) & 0xff);
612 case 0x00: /* Unified memory */
614 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
615 last_segname
= "umem";
619 case 0x01: /* On-chip insn memory */
621 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
622 last_segname
= "imem";
626 case 0x02: /* On-chip data memory */
628 if ((phys_addr
& 0xff00) == 0xff00)
630 phys_addr
= (phys_addr
& 0xffff);
631 if (phys_addr
== DMAP2_SHADDOW
)
633 phys_addr
= DMAP2_OFFSET
;
634 last_segname
= "dmap";
637 last_segname
= "reg";
640 last_segname
= "dmem";
641 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
647 last_segname
= "scrap";
648 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
652 *memory
= xcalloc (1, SEGMENT_SIZE
);
654 offset
= (phys_addr
% SEGMENT_SIZE
);
655 raw
= *memory
+ offset
;
659 /* Transfer data to/from simulated memory. Since a bug in either the
660 simulated program or in gdb or the simulator itself may cause a
661 bogus address to be passed in, we need to do some sanity checking
662 on addresses to make sure they are within bounds. When an address
663 fails the bounds check, treat it as a zero length read/write rather
664 than aborting the entire run. */
667 xfer_mem (SIM_DESC sd
,
669 unsigned char *buffer
,
676 phys_size
= sim_d10v_translate_addr (sd
, NULL
, virt
, size
, &phys
, NULL
,
677 dmap_register
, imap_register
);
681 memory
= map_memory (sd
, NULL
, phys
);
684 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
688 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
689 write_p
? "write" : "read",
690 phys_size
, virt
, last_from
,
692 (long) memory
, last_segname
);
698 memcpy (memory
, buffer
, phys_size
);
702 memcpy (buffer
, memory
, phys_size
);
710 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
712 /* FIXME: this should be performing a virtual transfer */
713 return xfer_mem (sd
, addr
, buffer
, size
, 1);
717 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
719 /* FIXME: this should be performing a virtual transfer */
720 return xfer_mem (sd
, addr
, buffer
, size
, 0);
724 d10v_pc_get (sim_cpu
*cpu
)
730 d10v_pc_set (sim_cpu
*cpu
, sim_cia pc
)
732 SIM_DESC sd
= CPU_STATE (cpu
);
737 free_state (SIM_DESC sd
)
739 if (STATE_MODULES (sd
) != NULL
)
740 sim_module_uninstall (sd
);
741 sim_cpu_free_all (sd
);
746 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
749 struct hash_entry
*h
;
750 static int init_p
= 0;
753 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
754 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
756 /* The cpu data is kept in a separately allocated chunk of memory. */
757 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
763 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
769 /* getopt will print the error message so we just have to exit if this fails.
770 FIXME: Hmmm... in the case of gdb we need getopt to call
772 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
778 /* Check for/establish the a reference program image. */
779 if (sim_analyze_program (sd
,
780 (STATE_PROG_ARGV (sd
) != NULL
781 ? *STATE_PROG_ARGV (sd
)
782 : NULL
), abfd
) != SIM_RC_OK
)
788 /* Configure/verify the target byte order and other runtime
789 configuration options. */
790 if (sim_config (sd
) != SIM_RC_OK
)
792 sim_module_uninstall (sd
);
796 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
798 /* Uninstall the modules to avoid memory leaks,
799 file descriptor leaks, etc. */
800 sim_module_uninstall (sd
);
804 /* CPU specific initialization. */
805 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
807 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
809 CPU_PC_FETCH (cpu
) = d10v_pc_get
;
810 CPU_PC_STORE (cpu
) = d10v_pc_set
;
813 old_segment_mapping
= 0;
815 /* NOTE: This argument parsing is only effective when this function
816 is called by GDB. Standalone argument parsing is handled by
818 for (p
= argv
+ 1; *p
; ++p
)
820 if (strcmp (*p
, "-oldseg") == 0)
821 old_segment_mapping
= 1;
823 else if (strcmp (*p
, "-t") == 0)
825 else if (strncmp (*p
, "-t", 2) == 0)
826 d10v_debug
= atoi (*p
+ 2);
830 /* put all the opcodes in the hash table */
833 for (s
= Simops
; s
->func
; s
++)
835 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
837 /* go to the last entry in the chain */
843 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
845 perror ("malloc failure");
851 h
->opcode
= s
->opcode
;
852 h
->size
= s
->is_long
;
856 /* reset the processor state */
857 if (!State
.mem
.data
[0])
859 sim_create_inferior ((SIM_DESC
) 1, NULL
, NULL
, NULL
);
865 dmem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 offset
)
871 /* Note: DMEM address range is 0..0x10000. Calling code can compute
872 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
873 is uint16 this is modulo'ed onto 0x0e5d. */
875 phys_size
= sim_d10v_translate_dmap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
878 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
879 mem
= map_memory (sd
, cpu
, phys
);
881 if ((d10v_debug
& DEBUG_MEMORY
))
885 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
887 phys
, phys_size
, last_to
,
888 (long) mem
, last_segname
);
895 imem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 offset
)
899 int phys_size
= sim_d10v_translate_imap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
902 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
903 mem
= map_memory (sd
, cpu
, phys
);
905 if ((d10v_debug
& DEBUG_MEMORY
))
909 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
911 phys
, phys_size
, last_to
,
912 (long) mem
, last_segname
);
919 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
924 /* TODO: Unindent this block. */
926 iaddr
= imem_addr (sd
, cpu
, (uint32
)PC
<< 2);
928 inst
= get_longword( iaddr
);
930 State
.pc_changed
= 0;
931 ins_type_counters
[ (int)INS_CYCLES
]++;
933 switch (inst
& 0xC0000000)
936 /* long instruction */
937 do_long (sd
, cpu
, inst
& 0x3FFFFFFF);
941 do_2_short (sd
, cpu
, inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
945 do_2_short (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
948 do_parallel (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
952 /* If the PC of the current instruction matches RPT_E then
953 schedule a branch to the loop start. If one of those
954 instructions happens to be a branch, than that instruction
956 if (!State
.pc_changed
)
958 if (PSW_RP
&& PC
== RPT_E
)
960 /* Note: The behavour of a branch instruction at RPT_E
961 is implementation dependant, this simulator takes the
962 branch. Branching to RPT_E is valid, the instruction
963 must be executed before the loop is taken. */
972 SET_RPT_C (RPT_C
- 1);
980 /* Check for a breakpoint trap on this instruction. This
981 overrides any pending branches or loops */
982 if (PSW_DB
&& PC
== IBA
)
986 SET_PSW (PSW
& PSW_SM_BIT
);
987 SET_PC (SDBT_VECTOR_START
);
990 /* Writeback all the DATA / PC changes */
996 sim_engine_run (SIM_DESC sd
,
997 int next_cpu_nr
, /* ignore */
998 int nr_cpus
, /* ignore */
1003 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1005 cpu
= STATE_CPU (sd
, 0);
1011 case GDB_SIGNAL_BUS
:
1014 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1015 JMP (AE_VECTOR_START
);
1018 case GDB_SIGNAL_ILL
:
1021 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1022 JMP (RIE_VECTOR_START
);
1026 /* just ignore it */
1032 step_once (sd
, cpu
);
1033 if (sim_events_tick (sd
))
1034 sim_events_process (sd
);
1039 sim_info (SIM_DESC sd
, int verbose
)
1046 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1047 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1048 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1049 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1050 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1052 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1053 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1054 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1055 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1056 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1058 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1059 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1060 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1061 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1062 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1063 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1064 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1065 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1066 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1067 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1069 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1070 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1071 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1072 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1073 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1074 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1077 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1078 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1079 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1080 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1081 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1082 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1085 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1086 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1087 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1088 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1089 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1090 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1094 "executed %*s long instruction(s)\n",
1095 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1099 "executed %*s parallel instruction(s)\n",
1100 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1104 "executed %*s instruction(s) encoded L->R\n",
1105 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1109 "executed %*s instruction(s) encoded R->L\n",
1110 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1114 "executed %*s unknown instruction(s)\n",
1115 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1119 "executed %*s instruction(s) due to EXExxx condition being true\n",
1120 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1124 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1125 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1129 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1130 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1133 "executed %*s cycle(s)\n",
1134 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1137 "executed %*s total instructions\n",
1138 size
, add_commas (buf1
, sizeof (buf1
), total
));
1142 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
1144 bfd_vma start_address
;
1146 /* reset all state information */
1147 memset (&State
.regs
, 0, (uintptr_t)&State
.mem
- (uintptr_t)&State
.regs
);
1149 /* There was a hack here to copy the values of argc and argv into r0
1150 and r1. The values were also saved into some high memory that
1151 won't be overwritten by the stack (0x7C00). The reason for doing
1152 this was to allow the 'run' program to accept arguments. Without
1153 the hack, this is not possible anymore. If the simulator is run
1154 from the debugger, arguments cannot be passed in, so this makes
1159 start_address
= bfd_get_start_address (abfd
);
1161 start_address
= 0xffc0 << 2;
1164 sim_io_printf (sd
, "sim_create_inferior: PC=0x%lx\n", (long) start_address
);
1167 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1168 SET_CREG (PC_CR
, start_address
>> 2);
1171 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1172 initializes imap0 and imap1 to 0x1000 as part of its ROM
1174 if (old_segment_mapping
)
1176 /* External memory startup. This is the HARD reset state. */
1177 set_imap_register (sd
, 0, 0x0000);
1178 set_imap_register (sd
, 1, 0x007f);
1179 set_dmap_register (sd
, 0, 0x2000);
1180 set_dmap_register (sd
, 1, 0x2000);
1181 set_dmap_register (sd
, 2, 0x0000); /* Old DMAP */
1182 set_dmap_register (sd
, 3, 0x0000);
1186 /* Internal memory startup. This is the ROM intialized state. */
1187 set_imap_register (sd
, 0, 0x1000);
1188 set_imap_register (sd
, 1, 0x1000);
1189 set_dmap_register (sd
, 0, 0x2000);
1190 set_dmap_register (sd
, 1, 0x2000);
1191 set_dmap_register (sd
, 2, 0x2000); /* DMAP2 initial internal value is
1192 0x2000 on the new board. */
1193 set_dmap_register (sd
, 3, 0x0000);
1201 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1203 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1205 switch ((enum sim_d10v_regs
) rn
)
1207 case SIM_D10V_R0_REGNUM
:
1208 case SIM_D10V_R1_REGNUM
:
1209 case SIM_D10V_R2_REGNUM
:
1210 case SIM_D10V_R3_REGNUM
:
1211 case SIM_D10V_R4_REGNUM
:
1212 case SIM_D10V_R5_REGNUM
:
1213 case SIM_D10V_R6_REGNUM
:
1214 case SIM_D10V_R7_REGNUM
:
1215 case SIM_D10V_R8_REGNUM
:
1216 case SIM_D10V_R9_REGNUM
:
1217 case SIM_D10V_R10_REGNUM
:
1218 case SIM_D10V_R11_REGNUM
:
1219 case SIM_D10V_R12_REGNUM
:
1220 case SIM_D10V_R13_REGNUM
:
1221 case SIM_D10V_R14_REGNUM
:
1222 case SIM_D10V_R15_REGNUM
:
1223 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1226 case SIM_D10V_CR0_REGNUM
:
1227 case SIM_D10V_CR1_REGNUM
:
1228 case SIM_D10V_CR2_REGNUM
:
1229 case SIM_D10V_CR3_REGNUM
:
1230 case SIM_D10V_CR4_REGNUM
:
1231 case SIM_D10V_CR5_REGNUM
:
1232 case SIM_D10V_CR6_REGNUM
:
1233 case SIM_D10V_CR7_REGNUM
:
1234 case SIM_D10V_CR8_REGNUM
:
1235 case SIM_D10V_CR9_REGNUM
:
1236 case SIM_D10V_CR10_REGNUM
:
1237 case SIM_D10V_CR11_REGNUM
:
1238 case SIM_D10V_CR12_REGNUM
:
1239 case SIM_D10V_CR13_REGNUM
:
1240 case SIM_D10V_CR14_REGNUM
:
1241 case SIM_D10V_CR15_REGNUM
:
1242 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1245 case SIM_D10V_A0_REGNUM
:
1246 case SIM_D10V_A1_REGNUM
:
1247 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1250 case SIM_D10V_SPI_REGNUM
:
1251 /* PSW_SM indicates that the current SP is the USER
1253 WRITE_16 (memory
, spi_register ());
1256 case SIM_D10V_SPU_REGNUM
:
1257 /* PSW_SM indicates that the current SP is the USER
1259 WRITE_16 (memory
, spu_register ());
1262 case SIM_D10V_IMAP0_REGNUM
:
1263 case SIM_D10V_IMAP1_REGNUM
:
1264 WRITE_16 (memory
, imap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1267 case SIM_D10V_DMAP0_REGNUM
:
1268 case SIM_D10V_DMAP1_REGNUM
:
1269 case SIM_D10V_DMAP2_REGNUM
:
1270 case SIM_D10V_DMAP3_REGNUM
:
1271 WRITE_16 (memory
, dmap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1274 case SIM_D10V_TS2_DMAP_REGNUM
:
1285 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1287 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1289 switch ((enum sim_d10v_regs
) rn
)
1291 case SIM_D10V_R0_REGNUM
:
1292 case SIM_D10V_R1_REGNUM
:
1293 case SIM_D10V_R2_REGNUM
:
1294 case SIM_D10V_R3_REGNUM
:
1295 case SIM_D10V_R4_REGNUM
:
1296 case SIM_D10V_R5_REGNUM
:
1297 case SIM_D10V_R6_REGNUM
:
1298 case SIM_D10V_R7_REGNUM
:
1299 case SIM_D10V_R8_REGNUM
:
1300 case SIM_D10V_R9_REGNUM
:
1301 case SIM_D10V_R10_REGNUM
:
1302 case SIM_D10V_R11_REGNUM
:
1303 case SIM_D10V_R12_REGNUM
:
1304 case SIM_D10V_R13_REGNUM
:
1305 case SIM_D10V_R14_REGNUM
:
1306 case SIM_D10V_R15_REGNUM
:
1307 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1310 case SIM_D10V_CR0_REGNUM
:
1311 case SIM_D10V_CR1_REGNUM
:
1312 case SIM_D10V_CR2_REGNUM
:
1313 case SIM_D10V_CR3_REGNUM
:
1314 case SIM_D10V_CR4_REGNUM
:
1315 case SIM_D10V_CR5_REGNUM
:
1316 case SIM_D10V_CR6_REGNUM
:
1317 case SIM_D10V_CR7_REGNUM
:
1318 case SIM_D10V_CR8_REGNUM
:
1319 case SIM_D10V_CR9_REGNUM
:
1320 case SIM_D10V_CR10_REGNUM
:
1321 case SIM_D10V_CR11_REGNUM
:
1322 case SIM_D10V_CR12_REGNUM
:
1323 case SIM_D10V_CR13_REGNUM
:
1324 case SIM_D10V_CR14_REGNUM
:
1325 case SIM_D10V_CR15_REGNUM
:
1326 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1329 case SIM_D10V_A0_REGNUM
:
1330 case SIM_D10V_A1_REGNUM
:
1331 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1334 case SIM_D10V_SPI_REGNUM
:
1335 /* PSW_SM indicates that the current SP is the USER
1337 set_spi_register (READ_16 (memory
));
1340 case SIM_D10V_SPU_REGNUM
:
1341 set_spu_register (READ_16 (memory
));
1344 case SIM_D10V_IMAP0_REGNUM
:
1345 case SIM_D10V_IMAP1_REGNUM
:
1346 set_imap_register (sd
, rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1349 case SIM_D10V_DMAP0_REGNUM
:
1350 case SIM_D10V_DMAP1_REGNUM
:
1351 case SIM_D10V_DMAP2_REGNUM
:
1352 case SIM_D10V_DMAP3_REGNUM
:
1353 set_dmap_register (sd
, rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1356 case SIM_D10V_TS2_DMAP_REGNUM
: