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Rework sim/common/sim-alu.h to differentiate between direcct
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10
11 #include "d10v_sim.h"
12 #include "simops.h"
13 #include "sys/syscall.h"
14
15 extern char *strrchr ();
16
17 enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
39 OP_PREDEC,
40 OP_R2,
41 OP_R3,
42 OP_R4,
43 OP_R2R3
44 };
45
46 #ifdef DEBUG
47 static void trace_input_func PARAMS ((char *name,
48 enum op_types in1,
49 enum op_types in2,
50 enum op_types in3));
51
52 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
53
54 static void trace_output_func PARAMS ((enum op_types result));
55
56 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
57
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 8
60 #endif
61
62 #ifndef SIZE_OPERANDS
63 #define SIZE_OPERANDS 18
64 #endif
65
66 #ifndef SIZE_VALUES
67 #define SIZE_VALUES 13
68 #endif
69
70 #ifndef SIZE_LOCATION
71 #define SIZE_LOCATION 20
72 #endif
73
74 #ifndef SIZE_PC
75 #define SIZE_PC 6
76 #endif
77
78 #ifndef SIZE_LINE_NUMBER
79 #define SIZE_LINE_NUMBER 4
80 #endif
81
82 static void
83 trace_input_func (name, in1, in2, in3)
84 char *name;
85 enum op_types in1;
86 enum op_types in2;
87 enum op_types in3;
88 {
89 char *comma;
90 enum op_types in[3];
91 int i;
92 char buf[1024];
93 char *p;
94 long tmp;
95 char *type;
96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
100
101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
116 case INS_LONG: type = " B"; break;
117 }
118
119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
121 "0x%.*x %s: %-*s ",
122 SIZE_PC, (unsigned)PC,
123 type,
124 SIZE_INSTRUCTION, name);
125
126 else
127 {
128 buf[0] = '\0';
129 byte_pc = decode_pc ();
130 if (text && byte_pc >= text_start && byte_pc < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
135 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
142 p += strlen (p);
143 }
144 else
145 {
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
148 }
149
150 if (functionname)
151 {
152 sprintf (p, "%s ", functionname);
153 p += strlen (p);
154 }
155 else if (filename)
156 {
157 char *q = strrchr (filename, '/');
158 sprintf (p, "%s ", (q) ? q+1 : filename);
159 p += strlen (p);
160 }
161
162 if (*p == ' ')
163 *p = '\0';
164 }
165 }
166
167 (*d10v_callback->printf_filtered) (d10v_callback,
168 "0x%.*x %s: %-*.*s %-*s ",
169 SIZE_PC, (unsigned)PC,
170 type,
171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
173 }
174
175 in[0] = in1;
176 in[1] = in2;
177 in[2] = in3;
178 comma = "";
179 p = buf;
180 for (i = 0; i < 3; i++)
181 {
182 switch (in[i])
183 {
184 case OP_VOID:
185 case OP_R2:
186 case OP_R3:
187 case OP_R4:
188 case OP_R2R3:
189 break;
190
191 case OP_REG:
192 case OP_REG_OUTPUT:
193 case OP_DREG:
194 case OP_DREG_OUTPUT:
195 sprintf (p, "%sr%d", comma, OP[i]);
196 p += strlen (p);
197 comma = ",";
198 break;
199
200 case OP_CR:
201 case OP_CR_OUTPUT:
202 case OP_CR_REVERSE:
203 sprintf (p, "%scr%d", comma, OP[i]);
204 p += strlen (p);
205 comma = ",";
206 break;
207
208 case OP_ACCUM:
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
212 p += strlen (p);
213 comma = ",";
214 break;
215
216 case OP_CONSTANT16:
217 sprintf (p, "%s%d", comma, OP[i]);
218 p += strlen (p);
219 comma = ",";
220 break;
221
222 case OP_CONSTANT8:
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
224 p += strlen (p);
225 comma = ",";
226 break;
227
228 case OP_CONSTANT4:
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
230 p += strlen (p);
231 comma = ",";
232 break;
233
234 case OP_CONSTANT3:
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
236 p += strlen (p);
237 comma = ",";
238 break;
239
240 case OP_MEMREF:
241 sprintf (p, "%s@r%d", comma, OP[i]);
242 p += strlen (p);
243 comma = ",";
244 break;
245
246 case OP_MEMREF2:
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
248 p += strlen (p);
249 comma = ",";
250 break;
251
252 case OP_POSTINC:
253 sprintf (p, "%s@r%d+", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_POSTDEC:
259 sprintf (p, "%s@r%d-", comma, OP[i]);
260 p += strlen (p);
261 comma = ",";
262 break;
263
264 case OP_PREDEC:
265 sprintf (p, "%s@-r%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_FLAG:
271 case OP_FLAG_OUTPUT:
272 if (OP[i] == 0)
273 sprintf (p, "%sf0", comma);
274
275 else if (OP[i] == 1)
276 sprintf (p, "%sf1", comma);
277
278 else
279 sprintf (p, "%sc", comma);
280
281 p += strlen (p);
282 comma = ",";
283 break;
284 }
285 }
286
287 if ((d10v_debug & DEBUG_VALUES) == 0)
288 {
289 *p++ = '\n';
290 *p = '\0';
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
292 }
293 else
294 {
295 *p = '\0';
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
297
298 p = buf;
299 for (i = 0; i < 3; i++)
300 {
301 buf[0] = '\0';
302 switch (in[i])
303 {
304 case OP_VOID:
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
306 break;
307
308 case OP_REG_OUTPUT:
309 case OP_DREG_OUTPUT:
310 case OP_CR_OUTPUT:
311 case OP_ACCUM_OUTPUT:
312 case OP_FLAG_OUTPUT:
313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
314 break;
315
316 case OP_REG:
317 case OP_MEMREF:
318 case OP_POSTDEC:
319 case OP_POSTINC:
320 case OP_PREDEC:
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
323 break;
324
325 case OP_DREG:
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
328 break;
329
330 case OP_CR:
331 case OP_CR_REVERSE:
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
334 break;
335
336 case OP_ACCUM:
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
341 break;
342
343 case OP_CONSTANT16:
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
345 (uint16)OP[i]);
346 break;
347
348 case OP_CONSTANT4:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
351 break;
352
353 case OP_CONSTANT8:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
356 break;
357
358 case OP_CONSTANT3:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
361 break;
362
363 case OP_FLAG:
364 if (OP[i] == 0)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
366 State.F0 != 0);
367
368 else if (OP[i] == 1)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
370 State.F1 != 0);
371
372 else
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
374 State.C != 0);
375
376 break;
377
378 case OP_MEMREF2:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16)OP[i]);
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
383 break;
384
385 case OP_R2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
388 break;
389
390 case OP_R3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
393 break;
394
395 case OP_R4:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
398 break;
399
400 case OP_R2R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
405 i++;
406 break;
407 }
408 }
409 }
410
411 (*d10v_callback->flush_stdout) (d10v_callback);
412 }
413
414 static void
415 trace_output_func (result)
416 enum op_types result;
417 {
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
419 {
420 long tmp;
421
422 switch (result)
423 {
424 default:
425 putchar ('\n');
426 break;
427
428 case OP_REG:
429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
433 break;
434
435 case OP_DREG:
436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
440 break;
441
442 case OP_CR:
443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
447 break;
448
449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
453 break;
454
455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
461 break;
462
463 case OP_ACCUM_REVERSE:
464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
468 break;
469
470 case OP_FLAG:
471 case OP_FLAG_OUTPUT:
472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
474 break;
475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
487 }
488 }
489
490 (*d10v_callback->flush_stdout) (d10v_callback);
491 }
492
493 #else
494 #define trace_input(NAME, IN1, IN2, IN3)
495 #define trace_output(RESULT)
496 #endif
497
498 /* abs */
499 void
500 OP_4607 ()
501 {
502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
503 State.F1 = State.F0;
504 if ((int16)(State.regs[OP[0]]) < 0)
505 {
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
507 State.F0 = 1;
508 }
509 else
510 State.F0 = 0;
511 trace_output (OP_REG);
512 }
513
514 /* abs */
515 void
516 OP_5607 ()
517 {
518 int64 tmp;
519
520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
521 State.F1 = State.F0;
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
523
524 if (State.a[OP[0]] < 0 )
525 {
526 tmp = -State.a[OP[0]];
527 if (State.ST)
528 {
529 if (tmp > MAX32)
530 State.a[OP[0]] = MAX32;
531 else if (tmp < MIN32)
532 State.a[OP[0]] = MIN32;
533 else
534 State.a[OP[0]] = tmp & MASK40;
535 }
536 else
537 State.a[OP[0]] = tmp & MASK40;
538 State.F0 = 1;
539 }
540 else
541 State.F0 = 0;
542 trace_output (OP_ACCUM);
543 }
544
545 /* add */
546 void
547 OP_200 ()
548 {
549 uint16 tmp = State.regs[OP[0]];
550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
553 State.C = 1;
554 else
555 State.C = 0;
556 trace_output (OP_REG);
557 }
558
559 /* add */
560 void
561 OP_1201 ()
562 {
563 int64 tmp;
564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
565
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
567 if (State.ST)
568 {
569 if ( tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
574 State.a[OP[0]] = tmp & MASK40;
575 }
576 else
577 State.a[OP[0]] = tmp & MASK40;
578 trace_output (OP_ACCUM);
579 }
580
581 /* add */
582 void
583 OP_1203 ()
584 {
585 int64 tmp;
586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
587
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
589 if (State.ST)
590 {
591 if (tmp > MAX32)
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
595 else
596 State.a[OP[0]] = tmp & MASK40;
597 }
598 else
599 State.a[OP[0]] = tmp & MASK40;
600 trace_output (OP_ACCUM);
601 }
602
603 /* add2w */
604 void
605 OP_1200 ()
606 {
607 uint32 tmp;
608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
610
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
612 tmp = a + b;
613 State.C = (tmp < a);
614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
616 trace_output (OP_DREG);
617 }
618
619 /* add3 */
620 void
621 OP_1000000 ()
622 {
623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
625
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
627 State.C = (State.regs[OP[0]] < tmp);
628 trace_output (OP_REG);
629 }
630
631 /* addac3 */
632 void
633 OP_17000200 ()
634 {
635 int64 tmp;
636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
637
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
641 trace_output (OP_DREG);
642 }
643
644 /* addac3 */
645 void
646 OP_17000202 ()
647 {
648 int64 tmp;
649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
650
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
654 trace_output (OP_DREG);
655 }
656
657 /* addac3s */
658 void
659 OP_17001200 ()
660 {
661 int64 tmp;
662 State.F1 = State.F0;
663
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
666 if ( tmp > MAX32)
667 {
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
670 State.F0 = 1;
671 }
672 else if (tmp < MIN32)
673 {
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
676 State.F0 = 1;
677 }
678 else
679 {
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
682 State.F0 = 0;
683 }
684 trace_output (OP_DREG);
685 }
686
687 /* addac3s */
688 void
689 OP_17001202 ()
690 {
691 int64 tmp;
692 State.F1 = State.F0;
693
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
696 if ( tmp > MAX32)
697 {
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
700 State.F0 = 1;
701 }
702 else if (tmp < MIN32)
703 {
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
706 State.F0 = 1;
707 }
708 else
709 {
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
712 State.F0 = 0;
713 }
714 trace_output (OP_DREG);
715 }
716
717 /* addi */
718 void
719 OP_201 ()
720 {
721 uint tmp = State.regs[OP[0]];
722 if (OP[1] == 0)
723 OP[1] = 16;
724
725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
726 State.regs[OP[0]] += OP[1];
727 State.C = (State.regs[OP[0]] < tmp);
728 trace_output (OP_REG);
729 }
730
731 /* and */
732 void
733 OP_C00 ()
734 {
735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
736 State.regs[OP[0]] &= State.regs[OP[1]];
737 trace_output (OP_REG);
738 }
739
740 /* and3 */
741 void
742 OP_6000000 ()
743 {
744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
746 trace_output (OP_REG);
747 }
748
749 /* bclri */
750 void
751 OP_C01 ()
752 {
753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
755 trace_output (OP_REG);
756 }
757
758 /* bl.s */
759 void
760 OP_4900 ()
761 {
762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
763 State.regs[13] = PC+1;
764 JMP( PC + SEXT8 (OP[0]));
765 trace_output (OP_VOID);
766 }
767
768 /* bl.l */
769 void
770 OP_24800000 ()
771 {
772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
773 State.regs[13] = PC+1;
774 JMP (PC + OP[0]);
775 trace_output (OP_VOID);
776 }
777
778 /* bnoti */
779 void
780 OP_A01 ()
781 {
782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
784 trace_output (OP_REG);
785 }
786
787 /* bra.s */
788 void
789 OP_4800 ()
790 {
791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
792 JMP (PC + SEXT8 (OP[0]));
793 trace_output (OP_VOID);
794 }
795
796 /* bra.l */
797 void
798 OP_24000000 ()
799 {
800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
801 JMP (PC + OP[0]);
802 trace_output (OP_VOID);
803 }
804
805 /* brf0f.s */
806 void
807 OP_4A00 ()
808 {
809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
810 if (State.F0 == 0)
811 JMP (PC + SEXT8 (OP[0]));
812 trace_output (OP_FLAG);
813 }
814
815 /* brf0f.l */
816 void
817 OP_25000000 ()
818 {
819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
820 if (State.F0 == 0)
821 JMP (PC + OP[0]);
822 trace_output (OP_FLAG);
823 }
824
825 /* brf0t.s */
826 void
827 OP_4B00 ()
828 {
829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
830 if (State.F0)
831 JMP (PC + SEXT8 (OP[0]));
832 trace_output (OP_FLAG);
833 }
834
835 /* brf0t.l */
836 void
837 OP_25800000 ()
838 {
839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
840 if (State.F0)
841 JMP (PC + OP[0]);
842 trace_output (OP_FLAG);
843 }
844
845 /* bseti */
846 void
847 OP_801 ()
848 {
849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
850 State.regs[OP[0]] |= 0x8000 >> OP[1];
851 trace_output (OP_REG);
852 }
853
854 /* btsti */
855 void
856 OP_E01 ()
857 {
858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
861 trace_output (OP_FLAG);
862 }
863
864 /* clrac */
865 void
866 OP_5601 ()
867 {
868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
869 State.a[OP[0]] = 0;
870 trace_output (OP_ACCUM);
871 }
872
873 /* cmp */
874 void
875 OP_600 ()
876 {
877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
880 trace_output (OP_FLAG);
881 }
882
883 /* cmp */
884 void
885 OP_1603 ()
886 {
887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
888 State.F1 = State.F0;
889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
890 trace_output (OP_FLAG);
891 }
892
893 /* cmpeq */
894 void
895 OP_400 ()
896 {
897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
900 trace_output (OP_FLAG);
901 }
902
903 /* cmpeq */
904 void
905 OP_1403 ()
906 {
907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
908 State.F1 = State.F0;
909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
910 trace_output (OP_FLAG);
911 }
912
913 /* cmpeqi.s */
914 void
915 OP_401 ()
916 {
917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
918 State.F1 = State.F0;
919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
920 trace_output (OP_FLAG);
921 }
922
923 /* cmpeqi.l */
924 void
925 OP_2000000 ()
926 {
927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
928 State.F1 = State.F0;
929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
930 trace_output (OP_FLAG);
931 }
932
933 /* cmpi.s */
934 void
935 OP_601 ()
936 {
937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
938 State.F1 = State.F0;
939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
940 trace_output (OP_FLAG);
941 }
942
943 /* cmpi.l */
944 void
945 OP_3000000 ()
946 {
947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
950 trace_output (OP_FLAG);
951 }
952
953 /* cmpu */
954 void
955 OP_4600 ()
956 {
957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
960 trace_output (OP_FLAG);
961 }
962
963 /* cmpui */
964 void
965 OP_23000000 ()
966 {
967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
968 State.F1 = State.F0;
969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
970 trace_output (OP_FLAG);
971 }
972
973 /* cpfg */
974 void
975 OP_4E09 ()
976 {
977 uint8 *src, *dst;
978
979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
993 trace_output (OP_FLAG);
994 }
995
996 /* dbt */
997 void
998 OP_5F20 ()
999 {
1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1001 State.exception = SIGTRAP;
1002 }
1003
1004 /* divs */
1005 void
1006 OP_14002800 ()
1007 {
1008 uint16 foo, tmp, tmpf;
1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
1016 trace_output (OP_DREG);
1017 }
1018
1019 /* exef0f */
1020 void
1021 OP_4E04 ()
1022 {
1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1024 State.exe = (State.F0 == 0);
1025 trace_output (OP_FLAG);
1026 }
1027
1028 /* exef0t */
1029 void
1030 OP_4E24 ()
1031 {
1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1033 State.exe = (State.F0 != 0);
1034 trace_output (OP_FLAG);
1035 }
1036
1037 /* exef1f */
1038 void
1039 OP_4E40 ()
1040 {
1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1042 State.exe = (State.F1 == 0);
1043 trace_output (OP_FLAG);
1044 }
1045
1046 /* exef1t */
1047 void
1048 OP_4E42 ()
1049 {
1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1051 State.exe = (State.F1 != 0);
1052 trace_output (OP_FLAG);
1053 }
1054
1055 /* exefaf */
1056 void
1057 OP_4E00 ()
1058 {
1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
1061 trace_output (OP_FLAG);
1062 }
1063
1064 /* exefat */
1065 void
1066 OP_4E02 ()
1067 {
1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
1070 trace_output (OP_FLAG);
1071 }
1072
1073 /* exetaf */
1074 void
1075 OP_4E20 ()
1076 {
1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
1079 trace_output (OP_FLAG);
1080 }
1081
1082 /* exetat */
1083 void
1084 OP_4E22 ()
1085 {
1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
1088 trace_output (OP_FLAG);
1089 }
1090
1091 /* exp */
1092 void
1093 OP_15002A00 ()
1094 {
1095 uint32 tmp, foo;
1096 int i;
1097
1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1101 else
1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1103
1104 foo = 0x40000000;
1105 for (i=1;i<17;i++)
1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
1110 trace_output (OP_REG);
1111 return;
1112 }
1113 foo >>= 1;
1114 }
1115 State.regs[OP[0]] = 16;
1116 trace_output (OP_REG);
1117 }
1118
1119 /* exp */
1120 void
1121 OP_15002A02 ()
1122 {
1123 int64 tmp, foo;
1124 int i;
1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1127 tmp = SEXT40(State.a[OP[1]]);
1128 if (tmp < 0)
1129 tmp = ~tmp & MASK40;
1130
1131 foo = 0x4000000000LL;
1132 for (i=1;i<25;i++)
1133 {
1134 if (tmp & foo)
1135 {
1136 State.regs[OP[0]] = i-9;
1137 trace_output (OP_REG);
1138 return;
1139 }
1140 foo >>= 1;
1141 }
1142 State.regs[OP[0]] = 16;
1143 trace_output (OP_REG);
1144 }
1145
1146 /* jl */
1147 void
1148 OP_4D00 ()
1149 {
1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
1151 State.regs[13] = PC+1;
1152 JMP (State.regs[OP[0]]);
1153 trace_output (OP_VOID);
1154 }
1155
1156 /* jmp */
1157 void
1158 OP_4C00 ()
1159 {
1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1163
1164 JMP (State.regs[OP[0]]);
1165 trace_output (OP_VOID);
1166 }
1167
1168 /* ld */
1169 void
1170 OP_30000000 ()
1171 {
1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1174 trace_output (OP_REG);
1175 }
1176
1177 /* ld */
1178 void
1179 OP_6401 ()
1180 {
1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1182 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1183 INC_ADDR(State.regs[OP[1]],-2);
1184 trace_output (OP_REG);
1185 }
1186
1187 /* ld */
1188 void
1189 OP_6001 ()
1190 {
1191 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1192 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1193 INC_ADDR(State.regs[OP[1]],2);
1194 trace_output (OP_REG);
1195 }
1196
1197 /* ld */
1198 void
1199 OP_6000 ()
1200 {
1201 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1202 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1203 trace_output (OP_REG);
1204 }
1205
1206 /* ld2w */
1207 void
1208 OP_31000000 ()
1209 {
1210 uint16 addr = State.regs[OP[2]];
1211 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1212 State.regs[OP[0]] = RW (OP[1] + addr);
1213 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
1214 trace_output (OP_DREG);
1215 }
1216
1217 /* ld2w */
1218 void
1219 OP_6601 ()
1220 {
1221 uint16 addr = State.regs[OP[1]];
1222 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1223 State.regs[OP[0]] = RW (addr);
1224 State.regs[OP[0]+1] = RW (addr+2);
1225 INC_ADDR(State.regs[OP[1]],-4);
1226 trace_output (OP_DREG);
1227 }
1228
1229 /* ld2w */
1230 void
1231 OP_6201 ()
1232 {
1233 uint16 addr = State.regs[OP[1]];
1234 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
1237 INC_ADDR(State.regs[OP[1]],4);
1238 trace_output (OP_DREG);
1239 }
1240
1241 /* ld2w */
1242 void
1243 OP_6200 ()
1244 {
1245 uint16 addr = State.regs[OP[1]];
1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
1249 trace_output (OP_DREG);
1250 }
1251
1252 /* ldb */
1253 void
1254 OP_38000000 ()
1255 {
1256 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1257 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
1258 trace_output (OP_REG);
1259 }
1260
1261 /* ldb */
1262 void
1263 OP_7000 ()
1264 {
1265 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1266 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
1267 trace_output (OP_REG);
1268 }
1269
1270 /* ldi.s */
1271 void
1272 OP_4001 ()
1273 {
1274 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1275 State.regs[OP[0]] = SEXT4(OP[1]);
1276 trace_output (OP_REG);
1277 }
1278
1279 /* ldi.l */
1280 void
1281 OP_20000000 ()
1282 {
1283 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1284 State.regs[OP[0]] = OP[1];
1285 trace_output (OP_REG);
1286 }
1287
1288 /* ldub */
1289 void
1290 OP_39000000 ()
1291 {
1292 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1293 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1294 trace_output (OP_REG);
1295 }
1296
1297 /* ldub */
1298 void
1299 OP_7200 ()
1300 {
1301 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1302 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1303 trace_output (OP_REG);
1304 }
1305
1306 /* mac */
1307 void
1308 OP_2A00 ()
1309 {
1310 int64 tmp;
1311
1312 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1313 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1314
1315 if (State.FX)
1316 tmp = SEXT40( (tmp << 1) & MASK40);
1317
1318 if (State.ST && tmp > MAX32)
1319 tmp = MAX32;
1320
1321 tmp += SEXT40(State.a[OP[0]]);
1322 if (State.ST)
1323 {
1324 if (tmp > MAX32)
1325 State.a[OP[0]] = MAX32;
1326 else if (tmp < MIN32)
1327 State.a[OP[0]] = MIN32;
1328 else
1329 State.a[OP[0]] = tmp & MASK40;
1330 }
1331 else
1332 State.a[OP[0]] = tmp & MASK40;
1333 trace_output (OP_ACCUM);
1334 }
1335
1336 /* macsu */
1337 void
1338 OP_1A00 ()
1339 {
1340 int64 tmp;
1341
1342 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1343 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1344 if (State.FX)
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1346
1347 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1348 trace_output (OP_ACCUM);
1349 }
1350
1351 /* macu */
1352 void
1353 OP_3A00 ()
1354 {
1355 int64 tmp;
1356
1357 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1358 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1359 if (State.FX)
1360 tmp = SEXT40( (tmp << 1) & MASK40);
1361 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1362 trace_output (OP_ACCUM);
1363 }
1364
1365 /* max */
1366 void
1367 OP_2600 ()
1368 {
1369 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1370 State.F1 = State.F0;
1371 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1372 {
1373 State.regs[OP[0]] = State.regs[OP[1]];
1374 State.F0 = 1;
1375 }
1376 else
1377 State.F0 = 0;
1378 trace_output (OP_REG);
1379 }
1380
1381 /* max */
1382 void
1383 OP_3600 ()
1384 {
1385 int64 tmp;
1386
1387 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1388 State.F1 = State.F0;
1389 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1390 if (tmp > SEXT40(State.a[OP[0]]))
1391 {
1392 State.a[OP[0]] = tmp & MASK40;
1393 State.F0 = 1;
1394 }
1395 else
1396 State.F0 = 0;
1397 trace_output (OP_ACCUM);
1398 }
1399
1400 /* max */
1401 void
1402 OP_3602 ()
1403 {
1404 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1405 State.F1 = State.F0;
1406 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1407 {
1408 State.a[OP[0]] = State.a[OP[1]];
1409 State.F0 = 1;
1410 }
1411 else
1412 State.F0 = 0;
1413 trace_output (OP_ACCUM);
1414 }
1415
1416
1417 /* min */
1418 void
1419 OP_2601 ()
1420 {
1421 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1422 State.F1 = State.F0;
1423 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1424 {
1425 State.regs[OP[0]] = State.regs[OP[1]];
1426 State.F0 = 1;
1427 }
1428 else
1429 State.F0 = 0;
1430 trace_output (OP_REG);
1431 }
1432
1433 /* min */
1434 void
1435 OP_3601 ()
1436 {
1437 int64 tmp;
1438
1439 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1440 State.F1 = State.F0;
1441 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1442 if (tmp < SEXT40(State.a[OP[0]]))
1443 {
1444 State.a[OP[0]] = tmp & MASK40;
1445 State.F0 = 1;
1446 }
1447 else
1448 State.F0 = 0;
1449 trace_output (OP_ACCUM);
1450 }
1451
1452 /* min */
1453 void
1454 OP_3603 ()
1455 {
1456 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1457 State.F1 = State.F0;
1458 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1459 {
1460 State.a[OP[0]] = State.a[OP[1]];
1461 State.F0 = 1;
1462 }
1463 else
1464 State.F0 = 0;
1465 trace_output (OP_ACCUM);
1466 }
1467
1468 /* msb */
1469 void
1470 OP_2800 ()
1471 {
1472 int64 tmp;
1473
1474 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1475 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1476
1477 if (State.FX)
1478 tmp = SEXT40 ((tmp << 1) & MASK40);
1479
1480 if (State.ST && tmp > MAX32)
1481 tmp = MAX32;
1482
1483 tmp = SEXT40(State.a[OP[0]]) - tmp;
1484 if (State.ST)
1485 {
1486 if (tmp > MAX32)
1487 State.a[OP[0]] = MAX32;
1488 else if (tmp < MIN32)
1489 State.a[OP[0]] = MIN32;
1490 else
1491 State.a[OP[0]] = tmp & MASK40;
1492 }
1493 else
1494 State.a[OP[0]] = tmp & MASK40;
1495 trace_output (OP_ACCUM);
1496 }
1497
1498 /* msbsu */
1499 void
1500 OP_1800 ()
1501 {
1502 int64 tmp;
1503
1504 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1505 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1506 if (State.FX)
1507 tmp = SEXT40( (tmp << 1) & MASK40);
1508
1509 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1510 trace_output (OP_ACCUM);
1511 }
1512
1513 /* msbu */
1514 void
1515 OP_3800 ()
1516 {
1517 int64 tmp;
1518
1519 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1520 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1521 if (State.FX)
1522 tmp = SEXT40( (tmp << 1) & MASK40);
1523
1524 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1525 trace_output (OP_ACCUM);
1526 }
1527
1528 /* mul */
1529 void
1530 OP_2E00 ()
1531 {
1532 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1533 State.regs[OP[0]] *= State.regs[OP[1]];
1534 trace_output (OP_REG);
1535 }
1536
1537 /* mulx */
1538 void
1539 OP_2C00 ()
1540 {
1541 int64 tmp;
1542
1543 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1544 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1545
1546 if (State.FX)
1547 tmp = SEXT40 ((tmp << 1) & MASK40);
1548
1549 if (State.ST && tmp > MAX32)
1550 State.a[OP[0]] = MAX32;
1551 else
1552 State.a[OP[0]] = tmp & MASK40;
1553 trace_output (OP_ACCUM);
1554 }
1555
1556 /* mulxsu */
1557 void
1558 OP_1C00 ()
1559 {
1560 int64 tmp;
1561
1562 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1563 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1564
1565 if (State.FX)
1566 tmp <<= 1;
1567
1568 State.a[OP[0]] = tmp & MASK40;
1569 trace_output (OP_ACCUM);
1570 }
1571
1572 /* mulxu */
1573 void
1574 OP_3C00 ()
1575 {
1576 int64 tmp;
1577
1578 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1579 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1580
1581 if (State.FX)
1582 tmp <<= 1;
1583
1584 State.a[OP[0]] = tmp & MASK40;
1585 trace_output (OP_ACCUM);
1586 }
1587
1588 /* mv */
1589 void
1590 OP_4000 ()
1591 {
1592 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1593 State.regs[OP[0]] = State.regs[OP[1]];
1594 trace_output (OP_REG);
1595 }
1596
1597 /* mv2w */
1598 void
1599 OP_5000 ()
1600 {
1601 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1602 State.regs[OP[0]] = State.regs[OP[1]];
1603 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1604 trace_output (OP_DREG);
1605 }
1606
1607 /* mv2wfac */
1608 void
1609 OP_3E00 ()
1610 {
1611 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1612 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1613 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1614 trace_output (OP_DREG);
1615 }
1616
1617 /* mv2wtac */
1618 void
1619 OP_3E01 ()
1620 {
1621 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1622 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1623 trace_output (OP_ACCUM_REVERSE);
1624 }
1625
1626 /* mvac */
1627 void
1628 OP_3E03 ()
1629 {
1630 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1631 State.a[OP[0]] = State.a[OP[1]];
1632 trace_output (OP_ACCUM);
1633 }
1634
1635 /* mvb */
1636 void
1637 OP_5400 ()
1638 {
1639 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1640 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1641 trace_output (OP_REG);
1642 }
1643
1644 /* mvf0f */
1645 void
1646 OP_4400 ()
1647 {
1648 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1649 if (State.F0 == 0)
1650 State.regs[OP[0]] = State.regs[OP[1]];
1651 trace_output (OP_REG);
1652 }
1653
1654 /* mvf0t */
1655 void
1656 OP_4401 ()
1657 {
1658 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1659 if (State.F0)
1660 State.regs[OP[0]] = State.regs[OP[1]];
1661 trace_output (OP_REG);
1662 }
1663
1664 /* mvfacg */
1665 void
1666 OP_1E04 ()
1667 {
1668 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1669 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1670 trace_output (OP_ACCUM);
1671 }
1672
1673 /* mvfachi */
1674 void
1675 OP_1E00 ()
1676 {
1677 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1678 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1679 trace_output (OP_REG);
1680 }
1681
1682 /* mvfaclo */
1683 void
1684 OP_1E02 ()
1685 {
1686 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1687 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1688 trace_output (OP_REG);
1689 }
1690
1691 /* mvfc */
1692 void
1693 OP_5200 ()
1694 {
1695 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1696 if (OP[1] == 0)
1697 {
1698 /* PSW is treated specially */
1699 PSW = 0;
1700 if (State.SM) PSW |= 0x8000;
1701 if (State.EA) PSW |= 0x2000;
1702 if (State.DB) PSW |= 0x1000;
1703 if (State.IE) PSW |= 0x400;
1704 if (State.RP) PSW |= 0x200;
1705 if (State.MD) PSW |= 0x100;
1706 if (State.FX) PSW |= 0x80;
1707 if (State.ST) PSW |= 0x40;
1708 if (State.F0) PSW |= 8;
1709 if (State.F1) PSW |= 4;
1710 if (State.C) PSW |= 1;
1711 }
1712 State.regs[OP[0]] = State.cregs[OP[1]];
1713 trace_output (OP_REG);
1714 }
1715
1716 /* mvtacg */
1717 void
1718 OP_1E41 ()
1719 {
1720 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1721 State.a[OP[1]] &= MASK32;
1722 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1723 trace_output (OP_ACCUM_REVERSE);
1724 }
1725
1726 /* mvtachi */
1727 void
1728 OP_1E01 ()
1729 {
1730 uint16 tmp;
1731
1732 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1733 tmp = State.a[OP[1]] & 0xffff;
1734 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1735 trace_output (OP_ACCUM_REVERSE);
1736 }
1737
1738 /* mvtaclo */
1739 void
1740 OP_1E21 ()
1741 {
1742 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1743 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1744 trace_output (OP_ACCUM_REVERSE);
1745 }
1746
1747 /* mvtc */
1748 void
1749 OP_5600 ()
1750 {
1751 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1752 State.cregs[OP[1]] = State.regs[OP[0]];
1753 if (OP[1] == 0)
1754 {
1755 /* PSW is treated specially */
1756 State.SM = (PSW & 0x8000) ? 1 : 0;
1757 State.EA = (PSW & 0x2000) ? 1 : 0;
1758 State.DB = (PSW & 0x1000) ? 1 : 0;
1759 State.IE = (PSW & 0x400) ? 1 : 0;
1760 State.RP = (PSW & 0x200) ? 1 : 0;
1761 State.MD = (PSW & 0x100) ? 1 : 0;
1762 State.FX = (PSW & 0x80) ? 1 : 0;
1763 State.ST = (PSW & 0x40) ? 1 : 0;
1764 State.F0 = (PSW & 8) ? 1 : 0;
1765 State.F1 = (PSW & 4) ? 1 : 0;
1766 State.C = PSW & 1;
1767 if (State.ST && !State.FX)
1768 {
1769 (*d10v_callback->printf_filtered) (d10v_callback,
1770 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1771 PC<<2);
1772 State.exception = SIGILL;
1773 }
1774 }
1775 trace_output (OP_CR_REVERSE);
1776 }
1777
1778 /* mvub */
1779 void
1780 OP_5401 ()
1781 {
1782 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1783 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1784 trace_output (OP_REG);
1785 }
1786
1787 /* neg */
1788 void
1789 OP_4605 ()
1790 {
1791 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1792 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1793 trace_output (OP_REG);
1794 }
1795
1796 /* neg */
1797 void
1798 OP_5605 ()
1799 {
1800 int64 tmp;
1801
1802 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1803 tmp = -SEXT40(State.a[OP[0]]);
1804 if (State.ST)
1805 {
1806 if ( tmp > MAX32)
1807 State.a[OP[0]] = MAX32;
1808 else if (tmp < MIN32)
1809 State.a[OP[0]] = MIN32;
1810 else
1811 State.a[OP[0]] = tmp & MASK40;
1812 }
1813 else
1814 State.a[OP[0]] = tmp & MASK40;
1815 trace_output (OP_ACCUM);
1816 }
1817
1818
1819 /* nop */
1820 void
1821 OP_5E00 ()
1822 {
1823 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1824
1825 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1826 switch (State.ins_type)
1827 {
1828 default:
1829 ins_type_counters[ (int)INS_UNKNOWN ]++;
1830 break;
1831
1832 case INS_LEFT_PARALLEL:
1833 /* Don't count a parallel op that includes a NOP as a true parallel op */
1834 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1835 ins_type_counters[ (int)INS_RIGHT ]++;
1836 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1837 break;
1838
1839 case INS_LEFT:
1840 case INS_LEFT_COND_EXE:
1841 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1842 break;
1843
1844 case INS_RIGHT_PARALLEL:
1845 /* Don't count a parallel op that includes a NOP as a true parallel op */
1846 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1847 ins_type_counters[ (int)INS_LEFT ]++;
1848 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1849 break;
1850
1851 case INS_RIGHT:
1852 case INS_RIGHT_COND_EXE:
1853 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1854 break;
1855 }
1856
1857 trace_output (OP_VOID);
1858 }
1859
1860 /* not */
1861 void
1862 OP_4603 ()
1863 {
1864 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1865 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1866 trace_output (OP_REG);
1867 }
1868
1869 /* or */
1870 void
1871 OP_800 ()
1872 {
1873 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1874 State.regs[OP[0]] |= State.regs[OP[1]];
1875 trace_output (OP_REG);
1876 }
1877
1878 /* or3 */
1879 void
1880 OP_4000000 ()
1881 {
1882 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1883 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1884 trace_output (OP_REG);
1885 }
1886
1887 /* rac */
1888 void
1889 OP_5201 ()
1890 {
1891 int64 tmp;
1892 int shift = SEXT3 (OP[2]);
1893
1894 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1895 if (OP[1] != 0)
1896 {
1897 (*d10v_callback->printf_filtered) (d10v_callback,
1898 "ERROR at PC 0x%x: instruction only valid for A0\n",
1899 PC<<2);
1900 State.exception = SIGILL;
1901 }
1902
1903 State.F1 = State.F0;
1904 if (shift >=0)
1905 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1906 else
1907 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1908 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1909 if (tmp > MAX32)
1910 {
1911 State.regs[OP[0]] = 0x7fff;
1912 State.regs[OP[0]+1] = 0xffff;
1913 State.F0 = 1;
1914 }
1915 else if (tmp < MIN32)
1916 {
1917 State.regs[OP[0]] = 0x8000;
1918 State.regs[OP[0]+1] = 0;
1919 State.F0 = 1;
1920 }
1921 else
1922 {
1923 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1924 State.regs[OP[0]+1] = tmp & 0xffff;
1925 State.F0 = 0;
1926 }
1927 trace_output (OP_DREG);
1928 }
1929
1930 /* rachi */
1931 void
1932 OP_4201 ()
1933 {
1934 signed64 tmp;
1935 int shift = SEXT3 (OP[2]);
1936
1937 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1938 State.F1 = State.F0;
1939 if (shift >=0)
1940 tmp = SEXT40 (State.a[OP[1]]) << shift;
1941 else
1942 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
1943 tmp += 0x8000;
1944
1945 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
1946 {
1947 State.regs[OP[0]] = 0x7fff;
1948 State.F0 = 1;
1949 }
1950 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
1951 {
1952 State.regs[OP[0]] = 0x8000;
1953 State.F0 = 1;
1954 }
1955 else
1956 {
1957 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1958 State.F0 = 0;
1959 }
1960 trace_output (OP_REG);
1961 }
1962
1963 /* rep */
1964 void
1965 OP_27000000 ()
1966 {
1967 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1968 RPT_S = PC + 1;
1969 RPT_E = PC + OP[1];
1970 RPT_C = State.regs[OP[0]];
1971 State.RP = 1;
1972 if (RPT_C == 0)
1973 {
1974 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1975 State.exception = SIGILL;
1976 }
1977 if (OP[1] < 4)
1978 {
1979 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1980 State.exception = SIGILL;
1981 }
1982 trace_output (OP_VOID);
1983 }
1984
1985 /* repi */
1986 void
1987 OP_2F000000 ()
1988 {
1989 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1990 RPT_S = PC + 1;
1991 RPT_E = PC + OP[1];
1992 RPT_C = OP[0];
1993 State.RP = 1;
1994 if (RPT_C == 0)
1995 {
1996 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
1997 State.exception = SIGILL;
1998 }
1999 if (OP[1] < 4)
2000 {
2001 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2002 State.exception = SIGILL;
2003 }
2004 trace_output (OP_VOID);
2005 }
2006
2007 /* rtd */
2008 void
2009 OP_5F60 ()
2010 {
2011 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
2012 State.exception = SIGILL;
2013 }
2014
2015 /* rte */
2016 void
2017 OP_5F40 ()
2018 {
2019 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2020 PC = BPC;
2021 PSW = BPSW;
2022 trace_output (OP_VOID);
2023 }
2024
2025 /* sadd */
2026 void
2027 OP_1223 ()
2028 {
2029 int64 tmp;
2030
2031 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2032 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
2033 if (State.ST)
2034 {
2035 if (tmp > MAX32)
2036 State.a[OP[0]] = MAX32;
2037 else if (tmp < MIN32)
2038 State.a[OP[0]] = MIN32;
2039 else
2040 State.a[OP[0]] = tmp & MASK40;
2041 }
2042 else
2043 State.a[OP[0]] = tmp & MASK40;
2044 trace_output (OP_ACCUM);
2045 }
2046
2047 /* setf0f */
2048 void
2049 OP_4611 ()
2050 {
2051 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2052 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2053 trace_output (OP_REG);
2054 }
2055
2056 /* setf0t */
2057 void
2058 OP_4613 ()
2059 {
2060 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2061 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2062 trace_output (OP_REG);
2063 }
2064
2065 /* sleep */
2066 void
2067 OP_5FC0 ()
2068 {
2069 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2070 State.IE = 1;
2071 trace_output (OP_VOID);
2072 }
2073
2074 /* sll */
2075 void
2076 OP_2200 ()
2077 {
2078 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2079 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2080 trace_output (OP_REG);
2081 }
2082
2083 /* sll */
2084 void
2085 OP_3200 ()
2086 {
2087 int64 tmp;
2088 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2089 if ((State.regs[OP[1]] & 31) <= 16)
2090 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2091 else
2092 {
2093 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2094 State.exception = SIGILL;
2095 return;
2096 }
2097
2098 if (State.ST)
2099 {
2100 if (tmp > MAX32)
2101 State.a[OP[0]] = MAX32;
2102 else if (tmp < 0xffffff80000000LL)
2103 State.a[OP[0]] = MIN32;
2104 else
2105 State.a[OP[0]] = tmp & MASK40;
2106 }
2107 else
2108 State.a[OP[0]] = tmp & MASK40;
2109 trace_output (OP_ACCUM);
2110 }
2111
2112 /* slli */
2113 void
2114 OP_2201 ()
2115 {
2116 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2117 State.regs[OP[0]] <<= OP[1];
2118 trace_output (OP_REG);
2119 }
2120
2121 /* slli */
2122 void
2123 OP_3201 ()
2124 {
2125 int64 tmp;
2126
2127 if (OP[1] == 0)
2128 OP[1] = 16;
2129
2130 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2131 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2132
2133 if (State.ST)
2134 {
2135 if (tmp > MAX32)
2136 State.a[OP[0]] = MAX32;
2137 else if (tmp < 0xffffff80000000LL)
2138 State.a[OP[0]] = MIN32;
2139 else
2140 State.a[OP[0]] = tmp & MASK40;
2141 }
2142 else
2143 State.a[OP[0]] = tmp & MASK40;
2144 trace_output (OP_ACCUM);
2145 }
2146
2147 /* slx */
2148 void
2149 OP_460B ()
2150 {
2151 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2152 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2153 trace_output (OP_REG);
2154 }
2155
2156 /* sra */
2157 void
2158 OP_2400 ()
2159 {
2160 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2161 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2162 trace_output (OP_REG);
2163 }
2164
2165 /* sra */
2166 void
2167 OP_3400 ()
2168 {
2169 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2170 if ((State.regs[OP[1]] & 31) <= 16)
2171 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
2172 else
2173 {
2174 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2175 State.exception = SIGILL;
2176 return;
2177 }
2178
2179 trace_output (OP_ACCUM);
2180 }
2181
2182 /* srai */
2183 void
2184 OP_2401 ()
2185 {
2186 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2187 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2188 trace_output (OP_REG);
2189 }
2190
2191 /* srai */
2192 void
2193 OP_3401 ()
2194 {
2195 if (OP[1] == 0)
2196 OP[1] = 16;
2197
2198 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2199 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
2200 trace_output (OP_ACCUM);
2201 }
2202
2203 /* srl */
2204 void
2205 OP_2000 ()
2206 {
2207 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2208 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2209 trace_output (OP_REG);
2210 }
2211
2212 /* srl */
2213 void
2214 OP_3000 ()
2215 {
2216 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2217 if ((State.regs[OP[1]] & 31) <= 16)
2218 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
2219 else
2220 {
2221 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2222 State.exception = SIGILL;
2223 return;
2224 }
2225
2226 trace_output (OP_ACCUM);
2227 }
2228
2229 /* srli */
2230 void
2231 OP_2001 ()
2232 {
2233 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2234 State.regs[OP[0]] >>= OP[1];
2235 trace_output (OP_REG);
2236 }
2237
2238 /* srli */
2239 void
2240 OP_3001 ()
2241 {
2242 if (OP[1] == 0)
2243 OP[1] = 16;
2244
2245 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2246 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
2247 trace_output (OP_ACCUM);
2248 }
2249
2250 /* srx */
2251 void
2252 OP_4609 ()
2253 {
2254 uint16 tmp;
2255
2256 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2257 tmp = State.F0 << 15;
2258 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2259 trace_output (OP_REG);
2260 }
2261
2262 /* st */
2263 void
2264 OP_34000000 ()
2265 {
2266 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2267 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2268 trace_output (OP_VOID);
2269 }
2270
2271 /* st */
2272 void
2273 OP_6800 ()
2274 {
2275 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2276 SW (State.regs[OP[1]], State.regs[OP[0]]);
2277 trace_output (OP_VOID);
2278 }
2279
2280 /* st */
2281 void
2282 OP_6C1F ()
2283 {
2284 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2285 if ( OP[1] != 15 )
2286 {
2287 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2288 State.exception = SIGILL;
2289 return;
2290 }
2291 State.regs[OP[1]] -= 2;
2292 SW (State.regs[OP[1]], State.regs[OP[0]]);
2293 trace_output (OP_VOID);
2294 }
2295
2296 /* st */
2297 void
2298 OP_6801 ()
2299 {
2300 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2301 SW (State.regs[OP[1]], State.regs[OP[0]]);
2302 INC_ADDR (State.regs[OP[1]],2);
2303 trace_output (OP_VOID);
2304 }
2305
2306 /* st */
2307 void
2308 OP_6C01 ()
2309 {
2310 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2311 if ( OP[1] == 15 )
2312 {
2313 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2314 State.exception = SIGILL;
2315 return;
2316 }
2317 SW (State.regs[OP[1]], State.regs[OP[0]]);
2318 INC_ADDR (State.regs[OP[1]],-2);
2319 trace_output (OP_VOID);
2320 }
2321
2322 /* st2w */
2323 void
2324 OP_35000000 ()
2325 {
2326 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2327 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2328 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2329 trace_output (OP_VOID);
2330 }
2331
2332 /* st2w */
2333 void
2334 OP_6A00 ()
2335 {
2336 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2337 SW (State.regs[OP[1]], State.regs[OP[0]]);
2338 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2339 trace_output (OP_VOID);
2340 }
2341
2342 /* st2w */
2343 void
2344 OP_6E1F ()
2345 {
2346 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2347 if ( OP[1] != 15 )
2348 {
2349 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2350 State.exception = SIGILL;
2351 return;
2352 }
2353 State.regs[OP[1]] -= 4;
2354 SW (State.regs[OP[1]], State.regs[OP[0]]);
2355 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2356 trace_output (OP_VOID);
2357 }
2358
2359 /* st2w */
2360 void
2361 OP_6A01 ()
2362 {
2363 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2364 SW (State.regs[OP[1]], State.regs[OP[0]]);
2365 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2366 INC_ADDR (State.regs[OP[1]],4);
2367 trace_output (OP_VOID);
2368 }
2369
2370 /* st2w */
2371 void
2372 OP_6E01 ()
2373 {
2374 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2375 if ( OP[1] == 15 )
2376 {
2377 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2378 State.exception = SIGILL;
2379 return;
2380 }
2381 SW (State.regs[OP[1]], State.regs[OP[0]]);
2382 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2383 INC_ADDR (State.regs[OP[1]],-4);
2384 trace_output (OP_VOID);
2385 }
2386
2387 /* stb */
2388 void
2389 OP_3C000000 ()
2390 {
2391 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2392 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2393 trace_output (OP_VOID);
2394 }
2395
2396 /* stb */
2397 void
2398 OP_7800 ()
2399 {
2400 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2401 SB (State.regs[OP[1]], State.regs[OP[0]]);
2402 trace_output (OP_VOID);
2403 }
2404
2405 /* stop */
2406 void
2407 OP_5FE0 ()
2408 {
2409 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2410 State.exception = SIG_D10V_STOP;
2411 trace_output (OP_VOID);
2412 }
2413
2414 /* sub */
2415 void
2416 OP_0 ()
2417 {
2418 uint16 tmp;
2419
2420 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2421 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2422 State.C = (tmp > State.regs[OP[0]]);
2423 State.regs[OP[0]] = tmp;
2424 trace_output (OP_REG);
2425 }
2426
2427 /* sub */
2428 void
2429 OP_1001 ()
2430 {
2431 int64 tmp;
2432
2433 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2434 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2435 if (State.ST)
2436 {
2437 if ( tmp > MAX32)
2438 State.a[OP[0]] = MAX32;
2439 else if ( tmp < MIN32)
2440 State.a[OP[0]] = MIN32;
2441 else
2442 State.a[OP[0]] = tmp & MASK40;
2443 }
2444 else
2445 State.a[OP[0]] = tmp & MASK40;
2446
2447 trace_output (OP_ACCUM);
2448 }
2449
2450 /* sub */
2451
2452 void
2453 OP_1003 ()
2454 {
2455 int64 tmp;
2456
2457 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2458 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2459 if (State.ST)
2460 {
2461 if (tmp > MAX32)
2462 State.a[OP[0]] = MAX32;
2463 else if ( tmp < MIN32)
2464 State.a[OP[0]] = MIN32;
2465 else
2466 State.a[OP[0]] = tmp & MASK40;
2467 }
2468 else
2469 State.a[OP[0]] = tmp & MASK40;
2470
2471 trace_output (OP_ACCUM);
2472 }
2473
2474 /* sub2w */
2475 void
2476 OP_1000 ()
2477 {
2478 uint32 tmp,a,b;
2479
2480 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2481 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2482 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2483 /* see ../common/sim-alu.h for a more extensive discussion on how to
2484 compute the carry/overflow bits */
2485 tmp = a - b;
2486 State.C = (a < b);
2487 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2488 State.regs[OP[0]+1] = tmp & 0xffff;
2489 trace_output (OP_DREG);
2490 }
2491
2492 /* subac3 */
2493 void
2494 OP_17000000 ()
2495 {
2496 int64 tmp;
2497
2498 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2499 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2500 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2501 State.regs[OP[0]+1] = tmp & 0xffff;
2502 trace_output (OP_DREG);
2503 }
2504
2505 /* subac3 */
2506 void
2507 OP_17000002 ()
2508 {
2509 int64 tmp;
2510
2511 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2512 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2513 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2514 State.regs[OP[0]+1] = tmp & 0xffff;
2515 trace_output (OP_DREG);
2516 }
2517
2518 /* subac3s */
2519 void
2520 OP_17001000 ()
2521 {
2522 int64 tmp;
2523
2524 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2525 State.F1 = State.F0;
2526 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2527 if ( tmp > MAX32)
2528 {
2529 State.regs[OP[0]] = 0x7fff;
2530 State.regs[OP[0]+1] = 0xffff;
2531 State.F0 = 1;
2532 }
2533 else if (tmp < MIN32)
2534 {
2535 State.regs[OP[0]] = 0x8000;
2536 State.regs[OP[0]+1] = 0;
2537 State.F0 = 1;
2538 }
2539 else
2540 {
2541 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2542 State.regs[OP[0]+1] = tmp & 0xffff;
2543 State.F0 = 0;
2544 }
2545 trace_output (OP_DREG);
2546 }
2547
2548 /* subac3s */
2549 void
2550 OP_17001002 ()
2551 {
2552 int64 tmp;
2553
2554 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2555 State.F1 = State.F0;
2556 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2557 if ( tmp > MAX32)
2558 {
2559 State.regs[OP[0]] = 0x7fff;
2560 State.regs[OP[0]+1] = 0xffff;
2561 State.F0 = 1;
2562 }
2563 else if (tmp < MIN32)
2564 {
2565 State.regs[OP[0]] = 0x8000;
2566 State.regs[OP[0]+1] = 0;
2567 State.F0 = 1;
2568 }
2569 else
2570 {
2571 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2572 State.regs[OP[0]+1] = tmp & 0xffff;
2573 State.F0 = 0;
2574 }
2575 trace_output (OP_DREG);
2576 }
2577
2578 /* subi */
2579 void
2580 OP_1 ()
2581 {
2582 unsigned tmp;
2583 if (OP[1] == 0)
2584 OP[1] = 16;
2585
2586 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2587 /* see ../common/sim-alu.h for a more extensive discussion on how to
2588 compute the carry/overflow bits */
2589 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2590 + (unsigned)(unsigned16) ( - OP[1]));
2591 State.C = (tmp >= (1 << 16));
2592 State.regs[OP[0]] = tmp;
2593 trace_output (OP_REG);
2594 }
2595
2596 /* trap */
2597 void
2598 OP_5F00 ()
2599 {
2600 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2601 trace_output (OP_VOID);
2602
2603 switch (OP[0])
2604 {
2605 default:
2606 #if 0
2607 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2608 State.exception = SIGILL;
2609 #else
2610 /* Use any other traps for batch debugging. */
2611 {
2612 int i;
2613 static int first_time = 1;
2614
2615 if (first_time)
2616 {
2617 first_time = 0;
2618 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2619 for (i = 0; i < 16; i++)
2620 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2621 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2622 }
2623
2624 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2625
2626 for (i = 0; i < 16; i++)
2627 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2628
2629 for (i = 0; i < 2; i++)
2630 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2631 ((int)(State.a[i] >> 32) & 0xff),
2632 ((unsigned long)State.a[i]) & 0xffffffff);
2633
2634 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2635 State.F0 != 0, State.F1 != 0, State.C != 0);
2636 (*d10v_callback->flush_stdout) (d10v_callback);
2637 break;
2638 }
2639 #endif
2640
2641 case 0: /* old system call trap, to be deleted */
2642 case 15: /* new system call trap */
2643 /* Trap 15 is used for simulating low-level I/O */
2644 {
2645 errno = 0;
2646
2647 /* Registers passed to trap 0 */
2648
2649 #define FUNC State.regs[6] /* function number */
2650 #define PARM1 State.regs[2] /* optional parm 1 */
2651 #define PARM2 State.regs[3] /* optional parm 2 */
2652 #define PARM3 State.regs[4] /* optional parm 3 */
2653 #define PARM4 State.regs[5] /* optional parm 3 */
2654
2655 /* Registers set by trap 0 */
2656
2657 #define RETVAL State.regs[2] /* return value */
2658 #define RETVAL_HIGH State.regs[2] /* return value */
2659 #define RETVAL_LOW State.regs[3] /* return value */
2660 #define RETERR State.regs[4] /* return error code */
2661
2662 /* Turn a pointer in a register into a pointer into real memory. */
2663
2664 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2665
2666 switch (FUNC)
2667 {
2668 #if !defined(__GO32__) && !defined(_WIN32)
2669 case SYS_fork:
2670 RETVAL = fork ();
2671 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2672 trace_output (OP_R2);
2673 break;
2674
2675 case SYS_getpid:
2676 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2677 RETVAL = getpid ();
2678 trace_output (OP_R2);
2679 break;
2680
2681 case SYS_kill:
2682 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2683 if (PARM1 == getpid ())
2684 {
2685 trace_output (OP_VOID);
2686 State.exception = PARM2;
2687 }
2688 else
2689 {
2690 int os_sig = -1;
2691 switch (PARM2)
2692 {
2693 #ifdef SIGHUP
2694 case 1: os_sig = SIGHUP; break;
2695 #endif
2696 #ifdef SIGINT
2697 case 2: os_sig = SIGINT; break;
2698 #endif
2699 #ifdef SIGQUIT
2700 case 3: os_sig = SIGQUIT; break;
2701 #endif
2702 #ifdef SIGILL
2703 case 4: os_sig = SIGILL; break;
2704 #endif
2705 #ifdef SIGTRAP
2706 case 5: os_sig = SIGTRAP; break;
2707 #endif
2708 #ifdef SIGABRT
2709 case 6: os_sig = SIGABRT; break;
2710 #elif defined(SIGIOT)
2711 case 6: os_sig = SIGIOT; break;
2712 #endif
2713 #ifdef SIGEMT
2714 case 7: os_sig = SIGEMT; break;
2715 #endif
2716 #ifdef SIGFPE
2717 case 8: os_sig = SIGFPE; break;
2718 #endif
2719 #ifdef SIGKILL
2720 case 9: os_sig = SIGKILL; break;
2721 #endif
2722 #ifdef SIGBUS
2723 case 10: os_sig = SIGBUS; break;
2724 #endif
2725 #ifdef SIGSEGV
2726 case 11: os_sig = SIGSEGV; break;
2727 #endif
2728 #ifdef SIGSYS
2729 case 12: os_sig = SIGSYS; break;
2730 #endif
2731 #ifdef SIGPIPE
2732 case 13: os_sig = SIGPIPE; break;
2733 #endif
2734 #ifdef SIGALRM
2735 case 14: os_sig = SIGALRM; break;
2736 #endif
2737 #ifdef SIGTERM
2738 case 15: os_sig = SIGTERM; break;
2739 #endif
2740 #ifdef SIGURG
2741 case 16: os_sig = SIGURG; break;
2742 #endif
2743 #ifdef SIGSTOP
2744 case 17: os_sig = SIGSTOP; break;
2745 #endif
2746 #ifdef SIGTSTP
2747 case 18: os_sig = SIGTSTP; break;
2748 #endif
2749 #ifdef SIGCONT
2750 case 19: os_sig = SIGCONT; break;
2751 #endif
2752 #ifdef SIGCHLD
2753 case 20: os_sig = SIGCHLD; break;
2754 #elif defined(SIGCLD)
2755 case 20: os_sig = SIGCLD; break;
2756 #endif
2757 #ifdef SIGTTIN
2758 case 21: os_sig = SIGTTIN; break;
2759 #endif
2760 #ifdef SIGTTOU
2761 case 22: os_sig = SIGTTOU; break;
2762 #endif
2763 #ifdef SIGIO
2764 case 23: os_sig = SIGIO; break;
2765 #elif defined (SIGPOLL)
2766 case 23: os_sig = SIGPOLL; break;
2767 #endif
2768 #ifdef SIGXCPU
2769 case 24: os_sig = SIGXCPU; break;
2770 #endif
2771 #ifdef SIGXFSZ
2772 case 25: os_sig = SIGXFSZ; break;
2773 #endif
2774 #ifdef SIGVTALRM
2775 case 26: os_sig = SIGVTALRM; break;
2776 #endif
2777 #ifdef SIGPROF
2778 case 27: os_sig = SIGPROF; break;
2779 #endif
2780 #ifdef SIGWINCH
2781 case 28: os_sig = SIGWINCH; break;
2782 #endif
2783 #ifdef SIGLOST
2784 case 29: os_sig = SIGLOST; break;
2785 #endif
2786 #ifdef SIGUSR1
2787 case 30: os_sig = SIGUSR1; break;
2788 #endif
2789 #ifdef SIGUSR2
2790 case 31: os_sig = SIGUSR2; break;
2791 #endif
2792 }
2793
2794 if (os_sig == -1)
2795 {
2796 trace_output (OP_VOID);
2797 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2798 (*d10v_callback->flush_stdout) (d10v_callback);
2799 State.exception = SIGILL;
2800 }
2801 else
2802 {
2803 RETVAL = kill (PARM1, PARM2);
2804 trace_output (OP_R2);
2805 }
2806 }
2807 break;
2808
2809 case SYS_execve:
2810 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2811 (char **)MEMPTR (PARM3));
2812 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2813 trace_output (OP_R2);
2814 break;
2815
2816 #ifdef SYS_execv
2817 case SYS_execv:
2818 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2819 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2820 trace_output (OP_R2);
2821 break;
2822 #endif
2823
2824 case SYS_pipe:
2825 {
2826 reg_t buf;
2827 int host_fd[2];
2828
2829 buf = PARM1;
2830 RETVAL = pipe (host_fd);
2831 SW (buf, host_fd[0]);
2832 buf += sizeof(uint16);
2833 SW (buf, host_fd[1]);
2834 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2835 trace_output (OP_R2);
2836 }
2837 break;
2838
2839 #ifdef SYS_wait
2840 case SYS_wait:
2841 {
2842 int status;
2843
2844 RETVAL = wait (&status);
2845 if (PARM1)
2846 SW (PARM1, status);
2847 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2848 trace_output (OP_R2);
2849 }
2850 break;
2851 #endif
2852 #else
2853 case SYS_getpid:
2854 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2855 RETVAL = 1;
2856 trace_output (OP_R2);
2857 break;
2858
2859 case SYS_kill:
2860 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2861 trace_output (OP_VOID);
2862 State.exception = PARM2;
2863 break;
2864 #endif
2865
2866 case SYS_read:
2867 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2868 PARM3);
2869 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2870 trace_output (OP_R2);
2871 break;
2872
2873 case SYS_write:
2874 if (PARM1 == 1)
2875 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2876 MEMPTR (PARM2), PARM3);
2877 else
2878 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2879 MEMPTR (PARM2), PARM3);
2880 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2881 trace_output (OP_R2);
2882 break;
2883
2884 case SYS_lseek:
2885 {
2886 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2887 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2888 PARM4);
2889 RETVAL_HIGH = ret >> 16;
2890 RETVAL_LOW = ret & 0xffff;
2891 }
2892 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2893 trace_output (OP_R2R3);
2894 break;
2895
2896 case SYS_close:
2897 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2898 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2899 trace_output (OP_R2);
2900 break;
2901
2902 case SYS_open:
2903 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2904 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2905 trace_output (OP_R2);
2906 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2907 trace_output (OP_R2);
2908 break;
2909
2910 case SYS_exit:
2911 State.exception = SIG_D10V_EXIT;
2912 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2913 trace_output (OP_VOID);
2914 break;
2915
2916 case SYS_stat:
2917 /* stat system call */
2918 {
2919 struct stat host_stat;
2920 reg_t buf;
2921
2922 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2923
2924 buf = PARM2;
2925
2926 /* The hard-coded offsets and sizes were determined by using
2927 * the D10V compiler on a test program that used struct stat.
2928 */
2929 SW (buf, host_stat.st_dev);
2930 SW (buf+2, host_stat.st_ino);
2931 SW (buf+4, host_stat.st_mode);
2932 SW (buf+6, host_stat.st_nlink);
2933 SW (buf+8, host_stat.st_uid);
2934 SW (buf+10, host_stat.st_gid);
2935 SW (buf+12, host_stat.st_rdev);
2936 SLW (buf+16, host_stat.st_size);
2937 SLW (buf+20, host_stat.st_atime);
2938 SLW (buf+28, host_stat.st_mtime);
2939 SLW (buf+36, host_stat.st_ctime);
2940 }
2941 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2942 trace_output (OP_R2);
2943 break;
2944
2945 case SYS_chown:
2946 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2947 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2948 trace_output (OP_R2);
2949 break;
2950
2951 case SYS_chmod:
2952 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2953 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2954 trace_output (OP_R2);
2955 break;
2956
2957 #ifdef SYS_utime
2958 case SYS_utime:
2959 /* Cast the second argument to void *, to avoid type mismatch
2960 if a prototype is present. */
2961 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2962 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2963 trace_output (OP_R2);
2964 break;
2965 #endif
2966
2967 #ifdef SYS_time
2968 case SYS_time:
2969 {
2970 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2971 RETVAL_HIGH = ret >> 16;
2972 RETVAL_LOW = ret & 0xffff;
2973 }
2974 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2975 trace_output (OP_R2R3);
2976 break;
2977 #endif
2978
2979 default:
2980 abort ();
2981 }
2982 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
2983 break;
2984 }
2985 }
2986 }
2987
2988 /* tst0i */
2989 void
2990 OP_7000000 ()
2991 {
2992 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2993 State.F1 = State.F0;
2994 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2995 trace_output (OP_FLAG);
2996 }
2997
2998 /* tst1i */
2999 void
3000 OP_F000000 ()
3001 {
3002 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3003 State.F1 = State.F0;
3004 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
3005 trace_output (OP_FLAG);
3006 }
3007
3008 /* wait */
3009 void
3010 OP_5F80 ()
3011 {
3012 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3013 State.IE = 1;
3014 trace_output (OP_VOID);
3015 }
3016
3017 /* xor */
3018 void
3019 OP_A00 ()
3020 {
3021 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3022 State.regs[OP[0]] ^= State.regs[OP[1]];
3023 trace_output (OP_REG);
3024 }
3025
3026 /* xor3 */
3027 void
3028 OP_5000000 ()
3029 {
3030 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3031 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
3032 trace_output (OP_REG);
3033 }
3034
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