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import gdb-1999-09-13 snapshot
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10
11 #include "d10v_sim.h"
12 #include "simops.h"
13 #include "targ-vals.h"
14
15 extern char *strrchr ();
16
17 enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_MEMREF3,
38 OP_POSTDEC,
39 OP_POSTINC,
40 OP_PREDEC,
41 OP_R0,
42 OP_R1,
43 OP_R2,
44 };
45
46
47 enum {
48 PSW_MASK = (PSW_SM_BIT
49 | PSW_EA_BIT
50 | PSW_DB_BIT
51 | PSW_DM_BIT
52 | PSW_IE_BIT
53 | PSW_RP_BIT
54 | PSW_MD_BIT
55 | PSW_FX_BIT
56 | PSW_ST_BIT
57 | PSW_F0_BIT
58 | PSW_F1_BIT
59 | PSW_C_BIT),
60 };
61
62 reg_t
63 move_to_cr (int cr, reg_t mask, reg_t val)
64 {
65 /* A MASK bit is set when the corresponding bit in the CR should
66 be left alone */
67 /* This assumes that (VAL & MASK) == 0 */
68 switch (cr)
69 {
70 case PSW_CR:
71 val &= PSW_MASK;
72 if ((mask & PSW_SM_BIT) == 0)
73 {
74 int new_sm = (val & PSW_SM_BIT) != 0;
75 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
76 if (PSW_SM != new_sm)
77 SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
78 }
79 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
80 {
81 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
82 {
83 (*d10v_callback->printf_filtered)
84 (d10v_callback,
85 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
86 PC<<2);
87 State.exception = SIGILL;
88 }
89 }
90 /* keep an up-to-date psw around for tracing */
91 State.trace.psw = (State.trace.psw & mask) | val;
92 break;
93 case BPSW_CR:
94 case DPSW_CR:
95 val &= PSW_MASK;
96 break;
97 case MOD_S_CR:
98 case MOD_E_CR:
99 val &= ~1;
100 break;
101 default:
102 break;
103 }
104 /* only issue an update if the register is being changed */
105 if ((State.cregs[cr] & ~mask) != val)
106 SLOT_PEND_MASK (State.cregs[cr], mask, val);
107 return val;
108 }
109
110 #ifdef DEBUG
111 static void trace_input_func PARAMS ((char *name,
112 enum op_types in1,
113 enum op_types in2,
114 enum op_types in3));
115
116 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
117
118 #ifndef SIZE_INSTRUCTION
119 #define SIZE_INSTRUCTION 8
120 #endif
121
122 #ifndef SIZE_OPERANDS
123 #define SIZE_OPERANDS 18
124 #endif
125
126 #ifndef SIZE_VALUES
127 #define SIZE_VALUES 13
128 #endif
129
130 #ifndef SIZE_LOCATION
131 #define SIZE_LOCATION 20
132 #endif
133
134 #ifndef SIZE_PC
135 #define SIZE_PC 6
136 #endif
137
138 #ifndef SIZE_LINE_NUMBER
139 #define SIZE_LINE_NUMBER 4
140 #endif
141
142 static void
143 trace_input_func (name, in1, in2, in3)
144 char *name;
145 enum op_types in1;
146 enum op_types in2;
147 enum op_types in3;
148 {
149 char *comma;
150 enum op_types in[3];
151 int i;
152 char buf[1024];
153 char *p;
154 long tmp;
155 char *type;
156 const char *filename;
157 const char *functionname;
158 unsigned int linenumber;
159 bfd_vma byte_pc;
160
161 if ((d10v_debug & DEBUG_TRACE) == 0)
162 return;
163
164 switch (State.ins_type)
165 {
166 default:
167 case INS_UNKNOWN: type = " ?"; break;
168 case INS_LEFT: type = " L"; break;
169 case INS_RIGHT: type = " R"; break;
170 case INS_LEFT_PARALLEL: type = "*L"; break;
171 case INS_RIGHT_PARALLEL: type = "*R"; break;
172 case INS_LEFT_COND_TEST: type = "?L"; break;
173 case INS_RIGHT_COND_TEST: type = "?R"; break;
174 case INS_LEFT_COND_EXE: type = "&L"; break;
175 case INS_RIGHT_COND_EXE: type = "&R"; break;
176 case INS_LONG: type = " B"; break;
177 }
178
179 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
180 (*d10v_callback->printf_filtered) (d10v_callback,
181 "0x%.*x %s: %-*s ",
182 SIZE_PC, (unsigned)PC,
183 type,
184 SIZE_INSTRUCTION, name);
185
186 else
187 {
188 buf[0] = '\0';
189 byte_pc = decode_pc ();
190 if (text && byte_pc >= text_start && byte_pc < text_end)
191 {
192 filename = (const char *)0;
193 functionname = (const char *)0;
194 linenumber = 0;
195 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
196 &filename, &functionname, &linenumber))
197 {
198 p = buf;
199 if (linenumber)
200 {
201 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
202 p += strlen (p);
203 }
204 else
205 {
206 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
207 p += SIZE_LINE_NUMBER+2;
208 }
209
210 if (functionname)
211 {
212 sprintf (p, "%s ", functionname);
213 p += strlen (p);
214 }
215 else if (filename)
216 {
217 char *q = strrchr (filename, '/');
218 sprintf (p, "%s ", (q) ? q+1 : filename);
219 p += strlen (p);
220 }
221
222 if (*p == ' ')
223 *p = '\0';
224 }
225 }
226
227 (*d10v_callback->printf_filtered) (d10v_callback,
228 "0x%.*x %s: %-*.*s %-*s ",
229 SIZE_PC, (unsigned)PC,
230 type,
231 SIZE_LOCATION, SIZE_LOCATION, buf,
232 SIZE_INSTRUCTION, name);
233 }
234
235 in[0] = in1;
236 in[1] = in2;
237 in[2] = in3;
238 comma = "";
239 p = buf;
240 for (i = 0; i < 3; i++)
241 {
242 switch (in[i])
243 {
244 case OP_VOID:
245 case OP_R0:
246 case OP_R1:
247 case OP_R2:
248 break;
249
250 case OP_REG:
251 case OP_REG_OUTPUT:
252 case OP_DREG:
253 case OP_DREG_OUTPUT:
254 sprintf (p, "%sr%d", comma, OP[i]);
255 p += strlen (p);
256 comma = ",";
257 break;
258
259 case OP_CR:
260 case OP_CR_OUTPUT:
261 case OP_CR_REVERSE:
262 sprintf (p, "%scr%d", comma, OP[i]);
263 p += strlen (p);
264 comma = ",";
265 break;
266
267 case OP_ACCUM:
268 case OP_ACCUM_OUTPUT:
269 case OP_ACCUM_REVERSE:
270 sprintf (p, "%sa%d", comma, OP[i]);
271 p += strlen (p);
272 comma = ",";
273 break;
274
275 case OP_CONSTANT16:
276 sprintf (p, "%s%d", comma, OP[i]);
277 p += strlen (p);
278 comma = ",";
279 break;
280
281 case OP_CONSTANT8:
282 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
283 p += strlen (p);
284 comma = ",";
285 break;
286
287 case OP_CONSTANT4:
288 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
289 p += strlen (p);
290 comma = ",";
291 break;
292
293 case OP_CONSTANT3:
294 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
295 p += strlen (p);
296 comma = ",";
297 break;
298
299 case OP_MEMREF:
300 sprintf (p, "%s@r%d", comma, OP[i]);
301 p += strlen (p);
302 comma = ",";
303 break;
304
305 case OP_MEMREF2:
306 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
307 p += strlen (p);
308 comma = ",";
309 break;
310
311 case OP_MEMREF3:
312 sprintf (p, "%s@%d", comma, OP[i]);
313 p += strlen (p);
314 comma = ",";
315 break;
316
317 case OP_POSTINC:
318 sprintf (p, "%s@r%d+", comma, OP[i]);
319 p += strlen (p);
320 comma = ",";
321 break;
322
323 case OP_POSTDEC:
324 sprintf (p, "%s@r%d-", comma, OP[i]);
325 p += strlen (p);
326 comma = ",";
327 break;
328
329 case OP_PREDEC:
330 sprintf (p, "%s@-r%d", comma, OP[i]);
331 p += strlen (p);
332 comma = ",";
333 break;
334
335 case OP_FLAG:
336 case OP_FLAG_OUTPUT:
337 if (OP[i] == 0)
338 sprintf (p, "%sf0", comma);
339
340 else if (OP[i] == 1)
341 sprintf (p, "%sf1", comma);
342
343 else
344 sprintf (p, "%sc", comma);
345
346 p += strlen (p);
347 comma = ",";
348 break;
349 }
350 }
351
352 if ((d10v_debug & DEBUG_VALUES) == 0)
353 {
354 *p++ = '\n';
355 *p = '\0';
356 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
357 }
358 else
359 {
360 *p = '\0';
361 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
362
363 p = buf;
364 for (i = 0; i < 3; i++)
365 {
366 buf[0] = '\0';
367 switch (in[i])
368 {
369 case OP_VOID:
370 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
371 break;
372
373 case OP_REG_OUTPUT:
374 case OP_DREG_OUTPUT:
375 case OP_CR_OUTPUT:
376 case OP_ACCUM_OUTPUT:
377 case OP_FLAG_OUTPUT:
378 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
379 break;
380
381 case OP_REG:
382 case OP_MEMREF:
383 case OP_POSTDEC:
384 case OP_POSTINC:
385 case OP_PREDEC:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16) GPR (OP[i]));
388 break;
389
390 case OP_MEMREF3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
392 break;
393
394 case OP_DREG:
395 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
397 break;
398
399 case OP_CR:
400 case OP_CR_REVERSE:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16) CREG (OP[i]));
403 break;
404
405 case OP_ACCUM:
406 case OP_ACCUM_REVERSE:
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
408 ((int)(ACC (OP[i]) >> 32) & 0xff),
409 ((unsigned long) ACC (OP[i])) & 0xffffffff);
410 break;
411
412 case OP_CONSTANT16:
413 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
414 (uint16)OP[i]);
415 break;
416
417 case OP_CONSTANT4:
418 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
419 (uint16)SEXT4(OP[i]));
420 break;
421
422 case OP_CONSTANT8:
423 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
424 (uint16)SEXT8(OP[i]));
425 break;
426
427 case OP_CONSTANT3:
428 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
429 (uint16)SEXT3(OP[i]));
430 break;
431
432 case OP_FLAG:
433 if (OP[i] == 0)
434 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
435 PSW_F0 != 0);
436
437 else if (OP[i] == 1)
438 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
439 PSW_F1 != 0);
440
441 else
442 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
443 PSW_C != 0);
444
445 break;
446
447 case OP_MEMREF2:
448 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
449 (uint16)OP[i]);
450 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
451 (uint16)GPR (OP[i + 1]));
452 i++;
453 break;
454
455 case OP_R0:
456 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
457 (uint16) GPR (0));
458 break;
459
460 case OP_R1:
461 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
462 (uint16) GPR (1));
463 break;
464
465 case OP_R2:
466 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
467 (uint16) GPR (2));
468 break;
469
470 }
471 }
472 }
473
474 (*d10v_callback->flush_stdout) (d10v_callback);
475 }
476
477 static void
478 do_trace_output_flush (void)
479 {
480 (*d10v_callback->flush_stdout) (d10v_callback);
481 }
482
483 static void
484 do_trace_output_finish (void)
485 {
486 (*d10v_callback->printf_filtered) (d10v_callback,
487 " F0=%d F1=%d C=%d\n",
488 (State.trace.psw & PSW_F0_BIT) != 0,
489 (State.trace.psw & PSW_F1_BIT) != 0,
490 (State.trace.psw & PSW_C_BIT) != 0);
491 (*d10v_callback->flush_stdout) (d10v_callback);
492 }
493
494 static void
495 trace_output_40 (uint64 val)
496 {
497 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
498 {
499 (*d10v_callback->printf_filtered) (d10v_callback,
500 " :: %*s0x%.2x%.8lx",
501 SIZE_VALUES - 12,
502 "",
503 ((int)(val >> 32) & 0xff),
504 ((unsigned long) val) & 0xffffffff);
505 do_trace_output_finish ();
506 }
507 }
508
509 static void
510 trace_output_32 (uint32 val)
511 {
512 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
513 {
514 (*d10v_callback->printf_filtered) (d10v_callback,
515 " :: %*s0x%.8x",
516 SIZE_VALUES - 10,
517 "",
518 (int) val);
519 do_trace_output_finish ();
520 }
521 }
522
523 static void
524 trace_output_16 (uint16 val)
525 {
526 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
527 {
528 (*d10v_callback->printf_filtered) (d10v_callback,
529 " :: %*s0x%.4x",
530 SIZE_VALUES - 6,
531 "",
532 (int) val);
533 do_trace_output_finish ();
534 }
535 }
536
537 static void
538 trace_output_void ()
539 {
540 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
541 {
542 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
543 do_trace_output_flush ();
544 }
545 }
546
547 static void
548 trace_output_flag ()
549 {
550 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
551 {
552 (*d10v_callback->printf_filtered) (d10v_callback,
553 " :: %*s",
554 SIZE_VALUES,
555 "");
556 do_trace_output_finish ();
557 }
558 }
559
560
561
562
563 #else
564 #define trace_input(NAME, IN1, IN2, IN3)
565 #define trace_output(RESULT)
566 #endif
567
568 /* abs */
569 void
570 OP_4607 ()
571 {
572 int16 tmp;
573 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
574 SET_PSW_F1 (PSW_F0);
575 tmp = GPR(OP[0]);
576 if (tmp < 0)
577 {
578 tmp = - tmp;
579 SET_PSW_F0 (1);
580 }
581 else
582 SET_PSW_F0 (0);
583 SET_GPR (OP[0], tmp);
584 trace_output_16 (tmp);
585 }
586
587 /* abs */
588 void
589 OP_5607 ()
590 {
591 int64 tmp;
592 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
593 SET_PSW_F1 (PSW_F0);
594
595 tmp = SEXT40 (ACC (OP[0]));
596 if (tmp < 0 )
597 {
598 tmp = - tmp;
599 if (PSW_ST)
600 {
601 if (tmp > SEXT40(MAX32))
602 tmp = (MAX32);
603 else if (tmp < SEXT40(MIN32))
604 tmp = (MIN32);
605 else
606 tmp = (tmp & MASK40);
607 }
608 else
609 tmp = (tmp & MASK40);
610 SET_PSW_F0 (1);
611 }
612 else
613 {
614 tmp = (tmp & MASK40);
615 SET_PSW_F0 (0);
616 }
617 SET_ACC (OP[0], tmp);
618 trace_output_40 (tmp);
619 }
620
621 /* add */
622 void
623 OP_200 ()
624 {
625 uint16 a = GPR (OP[0]);
626 uint16 b = GPR (OP[1]);
627 uint16 tmp = (a + b);
628 trace_input ("add", OP_REG, OP_REG, OP_VOID);
629 SET_PSW_C (a > tmp);
630 SET_GPR (OP[0], tmp);
631 trace_output_16 (tmp);
632 }
633
634 /* add */
635 void
636 OP_1201 ()
637 {
638 int64 tmp;
639 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
640
641 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
642 if (PSW_ST)
643 {
644 if (tmp > SEXT40(MAX32))
645 tmp = (MAX32);
646 else if (tmp < SEXT40(MIN32))
647 tmp = (MIN32);
648 else
649 tmp = (tmp & MASK40);
650 }
651 else
652 tmp = (tmp & MASK40);
653 SET_ACC (OP[0], tmp);
654 trace_output_40 (tmp);
655 }
656
657 /* add */
658 void
659 OP_1203 ()
660 {
661 int64 tmp;
662 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
663
664 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
665 if (PSW_ST)
666 {
667 if (tmp > SEXT40(MAX32))
668 tmp = (MAX32);
669 else if (tmp < SEXT40(MIN32))
670 tmp = (MIN32);
671 else
672 tmp = (tmp & MASK40);
673 }
674 else
675 tmp = (tmp & MASK40);
676 SET_ACC (OP[0], tmp);
677 trace_output_40 (tmp);
678 }
679
680 /* add2w */
681 void
682 OP_1200 ()
683 {
684 uint32 tmp;
685 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
686 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
687 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
688 tmp = a + b;
689 SET_PSW_C (tmp < a);
690 SET_GPR (OP[0] + 0, (tmp >> 16));
691 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
692 trace_output_32 (tmp);
693 }
694
695 /* add3 */
696 void
697 OP_1000000 ()
698 {
699 uint16 a = GPR (OP[1]);
700 uint16 b = OP[2];
701 uint16 tmp = (a + b);
702 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
703 SET_PSW_C (tmp < a);
704 SET_GPR (OP[0], tmp);
705 trace_output_16 (tmp);
706 }
707
708 /* addac3 */
709 void
710 OP_17000200 ()
711 {
712 int64 tmp;
713 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
714
715 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
716 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
717 SET_GPR (OP[0] + 1, (tmp & 0xffff));
718 trace_output_32 (tmp);
719 }
720
721 /* addac3 */
722 void
723 OP_17000202 ()
724 {
725 int64 tmp;
726 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
727
728 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
729 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
730 SET_GPR (OP[0] + 1, tmp & 0xffff);
731 trace_output_32 (tmp);
732 }
733
734 /* addac3s */
735 void
736 OP_17001200 ()
737 {
738 int64 tmp;
739 SET_PSW_F1 (PSW_F0);
740
741 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
742 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
743 if (tmp > SEXT40(MAX32))
744 {
745 tmp = (MAX32);
746 SET_PSW_F0 (1);
747 }
748 else if (tmp < SEXT40(MIN32))
749 {
750 tmp = (MIN32);
751 SET_PSW_F0 (1);
752 }
753 else
754 {
755 SET_PSW_F0 (0);
756 }
757 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
758 SET_GPR (OP[0] + 1, (tmp & 0xffff));
759 trace_output_32 (tmp);
760 }
761
762 /* addac3s */
763 void
764 OP_17001202 ()
765 {
766 int64 tmp;
767 SET_PSW_F1 (PSW_F0);
768
769 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
770 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
771 if (tmp > SEXT40(MAX32))
772 {
773 tmp = (MAX32);
774 SET_PSW_F0 (1);
775 }
776 else if (tmp < SEXT40(MIN32))
777 {
778 tmp = (MIN32);
779 SET_PSW_F0 (1);
780 }
781 else
782 {
783 SET_PSW_F0 (0);
784 }
785 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
786 SET_GPR (OP[0] + 1, (tmp & 0xffff));
787 trace_output_32 (tmp);
788 }
789
790 /* addi */
791 void
792 OP_201 ()
793 {
794 uint16 a = GPR (OP[0]);
795 uint16 b;
796 uint16 tmp;
797 if (OP[1] == 0)
798 OP[1] = 16;
799 b = OP[1];
800 tmp = (a + b);
801 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
802 SET_PSW_C (tmp < a);
803 SET_GPR (OP[0], tmp);
804 trace_output_16 (tmp);
805 }
806
807 /* and */
808 void
809 OP_C00 ()
810 {
811 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
812 trace_input ("and", OP_REG, OP_REG, OP_VOID);
813 SET_GPR (OP[0], tmp);
814 trace_output_16 (tmp);
815 }
816
817 /* and3 */
818 void
819 OP_6000000 ()
820 {
821 uint16 tmp = GPR (OP[1]) & OP[2];
822 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
823 SET_GPR (OP[0], tmp);
824 trace_output_16 (tmp);
825 }
826
827 /* bclri */
828 void
829 OP_C01 ()
830 {
831 int16 tmp;
832 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
833 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
834 SET_GPR (OP[0], tmp);
835 trace_output_16 (tmp);
836 }
837
838 /* bl.s */
839 void
840 OP_4900 ()
841 {
842 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
843 SET_GPR (13, PC + 1);
844 JMP( PC + SEXT8 (OP[0]));
845 trace_output_void ();
846 }
847
848 /* bl.l */
849 void
850 OP_24800000 ()
851 {
852 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
853 SET_GPR (13, (PC + 1));
854 JMP (PC + OP[0]);
855 trace_output_void ();
856 }
857
858 /* bnoti */
859 void
860 OP_A01 ()
861 {
862 int16 tmp;
863 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
864 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
865 SET_GPR (OP[0], tmp);
866 trace_output_16 (tmp);
867 }
868
869 /* bra.s */
870 void
871 OP_4800 ()
872 {
873 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
874 JMP (PC + SEXT8 (OP[0]));
875 trace_output_void ();
876 }
877
878 /* bra.l */
879 void
880 OP_24000000 ()
881 {
882 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
883 JMP (PC + OP[0]);
884 trace_output_void ();
885 }
886
887 /* brf0f.s */
888 void
889 OP_4A00 ()
890 {
891 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
892 if (!PSW_F0)
893 JMP (PC + SEXT8 (OP[0]));
894 trace_output_flag ();
895 }
896
897 /* brf0f.l */
898 void
899 OP_25000000 ()
900 {
901 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
902 if (!PSW_F0)
903 JMP (PC + OP[0]);
904 trace_output_flag ();
905 }
906
907 /* brf0t.s */
908 void
909 OP_4B00 ()
910 {
911 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
912 if (PSW_F0)
913 JMP (PC + SEXT8 (OP[0]));
914 trace_output_flag ();
915 }
916
917 /* brf0t.l */
918 void
919 OP_25800000 ()
920 {
921 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
922 if (PSW_F0)
923 JMP (PC + OP[0]);
924 trace_output_flag ();
925 }
926
927 /* bseti */
928 void
929 OP_801 ()
930 {
931 int16 tmp;
932 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
933 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
934 SET_GPR (OP[0], tmp);
935 trace_output_16 (tmp);
936 }
937
938 /* btsti */
939 void
940 OP_E01 ()
941 {
942 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
943 SET_PSW_F1 (PSW_F0);
944 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
945 trace_output_flag ();
946 }
947
948 /* clrac */
949 void
950 OP_5601 ()
951 {
952 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
953 SET_ACC (OP[0], 0);
954 trace_output_40 (0);
955 }
956
957 /* cmp */
958 void
959 OP_600 ()
960 {
961 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
962 SET_PSW_F1 (PSW_F0);
963 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
964 trace_output_flag ();
965 }
966
967 /* cmp */
968 void
969 OP_1603 ()
970 {
971 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
972 SET_PSW_F1 (PSW_F0);
973 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
974 trace_output_flag ();
975 }
976
977 /* cmpeq */
978 void
979 OP_400 ()
980 {
981 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
982 SET_PSW_F1 (PSW_F0);
983 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
984 trace_output_flag ();
985 }
986
987 /* cmpeq */
988 void
989 OP_1403 ()
990 {
991 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
992 SET_PSW_F1 (PSW_F0);
993 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
994 trace_output_flag ();
995 }
996
997 /* cmpeqi.s */
998 void
999 OP_401 ()
1000 {
1001 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1002 SET_PSW_F1 (PSW_F0);
1003 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1004 trace_output_flag ();
1005 }
1006
1007 /* cmpeqi.l */
1008 void
1009 OP_2000000 ()
1010 {
1011 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1012 SET_PSW_F1 (PSW_F0);
1013 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1014 trace_output_flag ();
1015 }
1016
1017 /* cmpi.s */
1018 void
1019 OP_601 ()
1020 {
1021 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1022 SET_PSW_F1 (PSW_F0);
1023 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1024 trace_output_flag ();
1025 }
1026
1027 /* cmpi.l */
1028 void
1029 OP_3000000 ()
1030 {
1031 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1032 SET_PSW_F1 (PSW_F0);
1033 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1034 trace_output_flag ();
1035 }
1036
1037 /* cmpu */
1038 void
1039 OP_4600 ()
1040 {
1041 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1042 SET_PSW_F1 (PSW_F0);
1043 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1044 trace_output_flag ();
1045 }
1046
1047 /* cmpui */
1048 void
1049 OP_23000000 ()
1050 {
1051 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1052 SET_PSW_F1 (PSW_F0);
1053 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1054 trace_output_flag ();
1055 }
1056
1057 /* cpfg */
1058 void
1059 OP_4E09 ()
1060 {
1061 uint8 val;
1062
1063 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1064
1065 if (OP[1] == 0)
1066 val = PSW_F0;
1067 else if (OP[1] == 1)
1068 val = PSW_F1;
1069 else
1070 val = PSW_C;
1071 if (OP[0] == 0)
1072 SET_PSW_F0 (val);
1073 else
1074 SET_PSW_F1 (val);
1075
1076 trace_output_flag ();
1077 }
1078
1079 /* dbt */
1080 void
1081 OP_5F20 ()
1082 {
1083 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1084
1085 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1086 The conditional below is for either of the instruction pairs
1087 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1088 where the dbt instruction should be interpreted.
1089
1090 The module `sim-break' provides a more effective mechanism for
1091 detecting GDB planted breakpoints. The code below may,
1092 eventually, be changed to use that mechanism. */
1093
1094 if (State.ins_type == INS_LEFT
1095 || State.ins_type == INS_RIGHT)
1096 {
1097 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1098 SET_DPC (PC + 1);
1099 SET_DPSW (PSW);
1100 SET_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1101 JMP (DBT_VECTOR_START);
1102 trace_output_void ();
1103 }
1104 else
1105 {
1106 State.exception = SIGTRAP;
1107 }
1108 }
1109
1110 /* divs */
1111 void
1112 OP_14002800 ()
1113 {
1114 uint16 foo, tmp, tmpf;
1115 uint16 hi;
1116 uint16 lo;
1117
1118 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1119 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1120 tmp = (int16)foo - (int16)(GPR (OP[1]));
1121 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1122 hi = ((tmpf == 1) ? tmp : foo);
1123 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1124 SET_GPR (OP[0] + 0, hi);
1125 SET_GPR (OP[0] + 1, lo);
1126 trace_output_32 (((uint32) hi << 16) | lo);
1127 }
1128
1129 /* exef0f */
1130 void
1131 OP_4E04 ()
1132 {
1133 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1134 State.exe = (PSW_F0 == 0);
1135 trace_output_flag ();
1136 }
1137
1138 /* exef0t */
1139 void
1140 OP_4E24 ()
1141 {
1142 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1143 State.exe = (PSW_F0 != 0);
1144 trace_output_flag ();
1145 }
1146
1147 /* exef1f */
1148 void
1149 OP_4E40 ()
1150 {
1151 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1152 State.exe = (PSW_F1 == 0);
1153 trace_output_flag ();
1154 }
1155
1156 /* exef1t */
1157 void
1158 OP_4E42 ()
1159 {
1160 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1161 State.exe = (PSW_F1 != 0);
1162 trace_output_flag ();
1163 }
1164
1165 /* exefaf */
1166 void
1167 OP_4E00 ()
1168 {
1169 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1170 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1171 trace_output_flag ();
1172 }
1173
1174 /* exefat */
1175 void
1176 OP_4E02 ()
1177 {
1178 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1179 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1180 trace_output_flag ();
1181 }
1182
1183 /* exetaf */
1184 void
1185 OP_4E20 ()
1186 {
1187 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1188 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1189 trace_output_flag ();
1190 }
1191
1192 /* exetat */
1193 void
1194 OP_4E22 ()
1195 {
1196 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1197 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1198 trace_output_flag ();
1199 }
1200
1201 /* exp */
1202 void
1203 OP_15002A00 ()
1204 {
1205 uint32 tmp, foo;
1206 int i;
1207
1208 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1209 if (((int16)GPR (OP[1])) >= 0)
1210 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1211 else
1212 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1213
1214 foo = 0x40000000;
1215 for (i=1;i<17;i++)
1216 {
1217 if (tmp & foo)
1218 {
1219 SET_GPR (OP[0], (i - 1));
1220 trace_output_16 (i - 1);
1221 return;
1222 }
1223 foo >>= 1;
1224 }
1225 SET_GPR (OP[0], 16);
1226 trace_output_16 (16);
1227 }
1228
1229 /* exp */
1230 void
1231 OP_15002A02 ()
1232 {
1233 int64 tmp, foo;
1234 int i;
1235
1236 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1237 tmp = SEXT40(ACC (OP[1]));
1238 if (tmp < 0)
1239 tmp = ~tmp & MASK40;
1240
1241 foo = 0x4000000000LL;
1242 for (i=1;i<25;i++)
1243 {
1244 if (tmp & foo)
1245 {
1246 SET_GPR (OP[0], i - 9);
1247 trace_output_16 (i - 9);
1248 return;
1249 }
1250 foo >>= 1;
1251 }
1252 SET_GPR (OP[0], 16);
1253 trace_output_16 (16);
1254 }
1255
1256 /* jl */
1257 void
1258 OP_4D00 ()
1259 {
1260 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1261 SET_GPR (13, PC + 1);
1262 JMP (GPR (OP[0]));
1263 trace_output_void ();
1264 }
1265
1266 /* jmp */
1267 void
1268 OP_4C00 ()
1269 {
1270 trace_input ("jmp", OP_REG,
1271 (OP[0] == 13) ? OP_R0 : OP_VOID,
1272 (OP[0] == 13) ? OP_R1 : OP_VOID);
1273
1274 JMP (GPR (OP[0]));
1275 trace_output_void ();
1276 }
1277
1278 /* ld */
1279 void
1280 OP_30000000 ()
1281 {
1282 uint16 tmp;
1283 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1284 tmp = RW (OP[1] + GPR (OP[2]));
1285 SET_GPR (OP[0], tmp);
1286 trace_output_16 (tmp);
1287 }
1288
1289 /* ld */
1290 void
1291 OP_6401 ()
1292 {
1293 uint16 tmp;
1294 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1295 tmp = RW (GPR (OP[1]));
1296 SET_GPR (OP[0], tmp);
1297 if (OP[0] != OP[1])
1298 INC_ADDR (OP[1], -2);
1299 trace_output_16 (tmp);
1300 }
1301
1302 /* ld */
1303 void
1304 OP_6001 ()
1305 {
1306 uint16 tmp;
1307 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1308 tmp = RW (GPR (OP[1]));
1309 SET_GPR (OP[0], tmp);
1310 if (OP[0] != OP[1])
1311 INC_ADDR (OP[1], 2);
1312 trace_output_16 (tmp);
1313 }
1314
1315 /* ld */
1316 void
1317 OP_6000 ()
1318 {
1319 uint16 tmp;
1320 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1321 tmp = RW (GPR (OP[1]));
1322 SET_GPR (OP[0], tmp);
1323 trace_output_16 (tmp);
1324 }
1325
1326 /* ld */
1327 void
1328 OP_32010000 ()
1329 {
1330 uint16 tmp;
1331
1332 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1333 tmp = RW (OP[1]);
1334 SET_GPR (OP[0], tmp);
1335 trace_output_16 (tmp);
1336 }
1337
1338 /* ld2w */
1339 void
1340 OP_31000000 ()
1341 {
1342 int32 tmp;
1343 uint16 addr = GPR (OP[2]);
1344 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1345 tmp = RLW (OP[1] + addr);
1346 SET_GPR32 (OP[0], tmp);
1347 trace_output_32 (tmp);
1348 }
1349
1350 /* ld2w */
1351 void
1352 OP_6601 ()
1353 {
1354 uint16 addr = GPR (OP[1]);
1355 int32 tmp;
1356 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1357 tmp = RLW (addr);
1358 SET_GPR32 (OP[0], tmp);
1359 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1360 INC_ADDR (OP[1], -4);
1361 trace_output_32 (tmp);
1362 }
1363
1364 /* ld2w */
1365 void
1366 OP_6201 ()
1367 {
1368 int32 tmp;
1369 uint16 addr = GPR (OP[1]);
1370 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1371 tmp = RLW (addr);
1372 SET_GPR32 (OP[0], tmp);
1373 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1374 INC_ADDR (OP[1], 4);
1375 trace_output_32 (tmp);
1376 }
1377
1378 /* ld2w */
1379 void
1380 OP_6200 ()
1381 {
1382 uint16 addr = GPR (OP[1]);
1383 int32 tmp;
1384 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1385 tmp = RLW (addr + 0);
1386 SET_GPR32 (OP[0], tmp);
1387 trace_output_32 (tmp);
1388 }
1389
1390 /* ld2w */
1391 void
1392 OP_33010000 ()
1393 {
1394 int32 tmp;
1395
1396 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1397 tmp = RLW (OP[1]);
1398 SET_GPR32 (OP[0], tmp);
1399 trace_output_32 (tmp);
1400 }
1401
1402 /* ldb */
1403 void
1404 OP_38000000 ()
1405 {
1406 int16 tmp;
1407 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1408 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1409 SET_GPR (OP[0], tmp);
1410 trace_output_16 (tmp);
1411 }
1412
1413 /* ldb */
1414 void
1415 OP_7000 ()
1416 {
1417 int16 tmp;
1418 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1419 tmp = SEXT8 (RB (GPR (OP[1])));
1420 SET_GPR (OP[0], tmp);
1421 trace_output_16 (tmp);
1422 }
1423
1424 /* ldi.s */
1425 void
1426 OP_4001 ()
1427 {
1428 int16 tmp;
1429 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1430 tmp = SEXT4 (OP[1]);
1431 SET_GPR (OP[0], tmp);
1432 trace_output_16 (tmp);
1433 }
1434
1435 /* ldi.l */
1436 void
1437 OP_20000000 ()
1438 {
1439 int16 tmp;
1440 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1441 tmp = OP[1];
1442 SET_GPR (OP[0], tmp);
1443 trace_output_16 (tmp);
1444 }
1445
1446 /* ldub */
1447 void
1448 OP_39000000 ()
1449 {
1450 int16 tmp;
1451 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1452 tmp = RB (OP[1] + GPR (OP[2]));
1453 SET_GPR (OP[0], tmp);
1454 trace_output_16 (tmp);
1455 }
1456
1457 /* ldub */
1458 void
1459 OP_7200 ()
1460 {
1461 int16 tmp;
1462 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1463 tmp = RB (GPR (OP[1]));
1464 SET_GPR (OP[0], tmp);
1465 trace_output_16 (tmp);
1466 }
1467
1468 /* mac */
1469 void
1470 OP_2A00 ()
1471 {
1472 int64 tmp;
1473
1474 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1475 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1476
1477 if (PSW_FX)
1478 tmp = SEXT40( (tmp << 1) & MASK40);
1479
1480 if (PSW_ST && tmp > SEXT40(MAX32))
1481 tmp = (MAX32);
1482
1483 tmp += SEXT40 (ACC (OP[0]));
1484 if (PSW_ST)
1485 {
1486 if (tmp > SEXT40(MAX32))
1487 tmp = (MAX32);
1488 else if (tmp < SEXT40(MIN32))
1489 tmp = (MIN32);
1490 else
1491 tmp = (tmp & MASK40);
1492 }
1493 else
1494 tmp = (tmp & MASK40);
1495 SET_ACC (OP[0], tmp);
1496 trace_output_40 (tmp);
1497 }
1498
1499 /* macsu */
1500 void
1501 OP_1A00 ()
1502 {
1503 int64 tmp;
1504
1505 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1506 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1507 if (PSW_FX)
1508 tmp = SEXT40 ((tmp << 1) & MASK40);
1509 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1510 SET_ACC (OP[0], tmp);
1511 trace_output_40 (tmp);
1512 }
1513
1514 /* macu */
1515 void
1516 OP_3A00 ()
1517 {
1518 uint64 tmp;
1519 uint32 src1;
1520 uint32 src2;
1521
1522 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1523 src1 = (uint16) GPR (OP[1]);
1524 src2 = (uint16) GPR (OP[2]);
1525 tmp = src1 * src2;
1526 if (PSW_FX)
1527 tmp = (tmp << 1);
1528 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1529 SET_ACC (OP[0], tmp);
1530 trace_output_40 (tmp);
1531 }
1532
1533 /* max */
1534 void
1535 OP_2600 ()
1536 {
1537 int16 tmp;
1538 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1539 SET_PSW_F1 (PSW_F0);
1540 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1541 {
1542 tmp = GPR (OP[1]);
1543 SET_PSW_F0 (1);
1544 }
1545 else
1546 {
1547 tmp = GPR (OP[0]);
1548 SET_PSW_F0 (0);
1549 }
1550 SET_GPR (OP[0], tmp);
1551 trace_output_16 (tmp);
1552 }
1553
1554 /* max */
1555 void
1556 OP_3600 ()
1557 {
1558 int64 tmp;
1559
1560 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1561 SET_PSW_F1 (PSW_F0);
1562 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1563 if (tmp > SEXT40 (ACC (OP[0])))
1564 {
1565 tmp = (tmp & MASK40);
1566 SET_PSW_F0 (1);
1567 }
1568 else
1569 {
1570 tmp = ACC (OP[0]);
1571 SET_PSW_F0 (0);
1572 }
1573 SET_ACC (OP[0], tmp);
1574 trace_output_40 (tmp);
1575 }
1576
1577 /* max */
1578 void
1579 OP_3602 ()
1580 {
1581 int64 tmp;
1582 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1583 SET_PSW_F1 (PSW_F0);
1584 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1585 {
1586 tmp = ACC (OP[1]);
1587 SET_PSW_F0 (1);
1588 }
1589 else
1590 {
1591 tmp = ACC (OP[0]);
1592 SET_PSW_F0 (0);
1593 }
1594 SET_ACC (OP[0], tmp);
1595 trace_output_40 (tmp);
1596 }
1597
1598
1599 /* min */
1600 void
1601 OP_2601 ()
1602 {
1603 int16 tmp;
1604 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1605 SET_PSW_F1 (PSW_F0);
1606 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1607 {
1608 tmp = GPR (OP[1]);
1609 SET_PSW_F0 (1);
1610 }
1611 else
1612 {
1613 tmp = GPR (OP[0]);
1614 SET_PSW_F0 (0);
1615 }
1616 SET_GPR (OP[0], tmp);
1617 trace_output_16 (tmp);
1618 }
1619
1620 /* min */
1621 void
1622 OP_3601 ()
1623 {
1624 int64 tmp;
1625
1626 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1627 SET_PSW_F1 (PSW_F0);
1628 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1629 if (tmp < SEXT40(ACC (OP[0])))
1630 {
1631 tmp = (tmp & MASK40);
1632 SET_PSW_F0 (1);
1633 }
1634 else
1635 {
1636 tmp = ACC (OP[0]);
1637 SET_PSW_F0 (0);
1638 }
1639 SET_ACC (OP[0], tmp);
1640 trace_output_40 (tmp);
1641 }
1642
1643 /* min */
1644 void
1645 OP_3603 ()
1646 {
1647 int64 tmp;
1648 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1649 SET_PSW_F1 (PSW_F0);
1650 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1651 {
1652 tmp = ACC (OP[1]);
1653 SET_PSW_F0 (1);
1654 }
1655 else
1656 {
1657 tmp = ACC (OP[0]);
1658 SET_PSW_F0 (0);
1659 }
1660 SET_ACC (OP[0], tmp);
1661 trace_output_40 (tmp);
1662 }
1663
1664 /* msb */
1665 void
1666 OP_2800 ()
1667 {
1668 int64 tmp;
1669
1670 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1671 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1672
1673 if (PSW_FX)
1674 tmp = SEXT40 ((tmp << 1) & MASK40);
1675
1676 if (PSW_ST && tmp > SEXT40(MAX32))
1677 tmp = (MAX32);
1678
1679 tmp = SEXT40(ACC (OP[0])) - tmp;
1680 if (PSW_ST)
1681 {
1682 if (tmp > SEXT40(MAX32))
1683 tmp = (MAX32);
1684 else if (tmp < SEXT40(MIN32))
1685 tmp = (MIN32);
1686 else
1687 tmp = (tmp & MASK40);
1688 }
1689 else
1690 {
1691 tmp = (tmp & MASK40);
1692 }
1693 SET_ACC (OP[0], tmp);
1694 trace_output_40 (tmp);
1695 }
1696
1697 /* msbsu */
1698 void
1699 OP_1800 ()
1700 {
1701 int64 tmp;
1702
1703 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1704 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1705 if (PSW_FX)
1706 tmp = SEXT40( (tmp << 1) & MASK40);
1707 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1708 SET_ACC (OP[0], tmp);
1709 trace_output_40 (tmp);
1710 }
1711
1712 /* msbu */
1713 void
1714 OP_3800 ()
1715 {
1716 uint64 tmp;
1717 uint32 src1;
1718 uint32 src2;
1719
1720 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1721 src1 = (uint16) GPR (OP[1]);
1722 src2 = (uint16) GPR (OP[2]);
1723 tmp = src1 * src2;
1724 if (PSW_FX)
1725 tmp = (tmp << 1);
1726 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1727 SET_ACC (OP[0], tmp);
1728 trace_output_40 (tmp);
1729 }
1730
1731 /* mul */
1732 void
1733 OP_2E00 ()
1734 {
1735 int16 tmp;
1736 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1737 tmp = GPR (OP[0]) * GPR (OP[1]);
1738 SET_GPR (OP[0], tmp);
1739 trace_output_16 (tmp);
1740 }
1741
1742 /* mulx */
1743 void
1744 OP_2C00 ()
1745 {
1746 int64 tmp;
1747
1748 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1749 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1750
1751 if (PSW_FX)
1752 tmp = SEXT40 ((tmp << 1) & MASK40);
1753
1754 if (PSW_ST && tmp > SEXT40(MAX32))
1755 tmp = (MAX32);
1756 else
1757 tmp = (tmp & MASK40);
1758 SET_ACC (OP[0], tmp);
1759 trace_output_40 (tmp);
1760 }
1761
1762 /* mulxsu */
1763 void
1764 OP_1C00 ()
1765 {
1766 int64 tmp;
1767
1768 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1769 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1770
1771 if (PSW_FX)
1772 tmp <<= 1;
1773 tmp = (tmp & MASK40);
1774 SET_ACC (OP[0], tmp);
1775 trace_output_40 (tmp);
1776 }
1777
1778 /* mulxu */
1779 void
1780 OP_3C00 ()
1781 {
1782 uint64 tmp;
1783 uint32 src1;
1784 uint32 src2;
1785
1786 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1787 src1 = (uint16) GPR (OP[1]);
1788 src2 = (uint16) GPR (OP[2]);
1789 tmp = src1 * src2;
1790 if (PSW_FX)
1791 tmp <<= 1;
1792 tmp = (tmp & MASK40);
1793 SET_ACC (OP[0], tmp);
1794 trace_output_40 (tmp);
1795 }
1796
1797 /* mv */
1798 void
1799 OP_4000 ()
1800 {
1801 int16 tmp;
1802 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1803 tmp = GPR (OP[1]);
1804 SET_GPR (OP[0], tmp);
1805 trace_output_16 (tmp);
1806 }
1807
1808 /* mv2w */
1809 void
1810 OP_5000 ()
1811 {
1812 int32 tmp;
1813 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1814 tmp = GPR32 (OP[1]);
1815 SET_GPR32 (OP[0], tmp);
1816 trace_output_32 (tmp);
1817 }
1818
1819 /* mv2wfac */
1820 void
1821 OP_3E00 ()
1822 {
1823 int32 tmp;
1824 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1825 tmp = ACC (OP[1]);
1826 SET_GPR32 (OP[0], tmp);
1827 trace_output_32 (tmp);
1828 }
1829
1830 /* mv2wtac */
1831 void
1832 OP_3E01 ()
1833 {
1834 int64 tmp;
1835 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1836 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1837 SET_ACC (OP[1], tmp);
1838 trace_output_40 (tmp);
1839 }
1840
1841 /* mvac */
1842 void
1843 OP_3E03 ()
1844 {
1845 int64 tmp;
1846 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1847 tmp = ACC (OP[1]);
1848 SET_ACC (OP[0], tmp);
1849 trace_output_40 (tmp);
1850 }
1851
1852 /* mvb */
1853 void
1854 OP_5400 ()
1855 {
1856 int16 tmp;
1857 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1858 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1859 SET_GPR (OP[0], tmp);
1860 trace_output_16 (tmp);
1861 }
1862
1863 /* mvf0f */
1864 void
1865 OP_4400 ()
1866 {
1867 int16 tmp;
1868 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1869 if (PSW_F0 == 0)
1870 {
1871 tmp = GPR (OP[1]);
1872 SET_GPR (OP[0], tmp);
1873 }
1874 else
1875 tmp = GPR (OP[0]);
1876 trace_output_16 (tmp);
1877 }
1878
1879 /* mvf0t */
1880 void
1881 OP_4401 ()
1882 {
1883 int16 tmp;
1884 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1885 if (PSW_F0)
1886 {
1887 tmp = GPR (OP[1]);
1888 SET_GPR (OP[0], tmp);
1889 }
1890 else
1891 tmp = GPR (OP[0]);
1892 trace_output_16 (tmp);
1893 }
1894
1895 /* mvfacg */
1896 void
1897 OP_1E04 ()
1898 {
1899 int16 tmp;
1900 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1901 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1902 SET_GPR (OP[0], tmp);
1903 trace_output_16 (tmp);
1904 }
1905
1906 /* mvfachi */
1907 void
1908 OP_1E00 ()
1909 {
1910 int16 tmp;
1911 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1912 tmp = (ACC (OP[1]) >> 16);
1913 SET_GPR (OP[0], tmp);
1914 trace_output_16 (tmp);
1915 }
1916
1917 /* mvfaclo */
1918 void
1919 OP_1E02 ()
1920 {
1921 int16 tmp;
1922 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1923 tmp = ACC (OP[1]);
1924 SET_GPR (OP[0], tmp);
1925 trace_output_16 (tmp);
1926 }
1927
1928 /* mvfc */
1929 void
1930 OP_5200 ()
1931 {
1932 int16 tmp;
1933 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1934 tmp = CREG (OP[1]);
1935 SET_GPR (OP[0], tmp);
1936 trace_output_16 (tmp);
1937 }
1938
1939 /* mvtacg */
1940 void
1941 OP_1E41 ()
1942 {
1943 int64 tmp;
1944 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1945 tmp = ((ACC (OP[1]) & MASK32)
1946 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1947 SET_ACC (OP[1], tmp);
1948 trace_output_40 (tmp);
1949 }
1950
1951 /* mvtachi */
1952 void
1953 OP_1E01 ()
1954 {
1955 uint64 tmp;
1956 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1957 tmp = ACC (OP[1]) & 0xffff;
1958 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1959 SET_ACC (OP[1], tmp);
1960 trace_output_40 (tmp);
1961 }
1962
1963 /* mvtaclo */
1964 void
1965 OP_1E21 ()
1966 {
1967 int64 tmp;
1968 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1969 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1970 SET_ACC (OP[1], tmp);
1971 trace_output_40 (tmp);
1972 }
1973
1974 /* mvtc */
1975 void
1976 OP_5600 ()
1977 {
1978 int16 tmp;
1979 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1980 tmp = GPR (OP[0]);
1981 tmp = SET_CREG (OP[1], tmp);
1982 trace_output_16 (tmp);
1983 }
1984
1985 /* mvub */
1986 void
1987 OP_5401 ()
1988 {
1989 int16 tmp;
1990 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1991 tmp = (GPR (OP[1]) & 0xff);
1992 SET_GPR (OP[0], tmp);
1993 trace_output_16 (tmp);
1994 }
1995
1996 /* neg */
1997 void
1998 OP_4605 ()
1999 {
2000 int16 tmp;
2001 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2002 tmp = - GPR (OP[0]);
2003 SET_GPR (OP[0], tmp);
2004 trace_output_16 (tmp);
2005 }
2006
2007 /* neg */
2008 void
2009 OP_5605 ()
2010 {
2011 int64 tmp;
2012
2013 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2014 tmp = -SEXT40(ACC (OP[0]));
2015 if (PSW_ST)
2016 {
2017 if (tmp > SEXT40(MAX32))
2018 tmp = (MAX32);
2019 else if (tmp < SEXT40(MIN32))
2020 tmp = (MIN32);
2021 else
2022 tmp = (tmp & MASK40);
2023 }
2024 else
2025 tmp = (tmp & MASK40);
2026 SET_ACC (OP[0], tmp);
2027 trace_output_40 (tmp);
2028 }
2029
2030
2031 /* nop */
2032 void
2033 OP_5E00 ()
2034 {
2035 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2036
2037 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2038 switch (State.ins_type)
2039 {
2040 default:
2041 ins_type_counters[ (int)INS_UNKNOWN ]++;
2042 break;
2043
2044 case INS_LEFT_PARALLEL:
2045 /* Don't count a parallel op that includes a NOP as a true parallel op */
2046 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2047 ins_type_counters[ (int)INS_RIGHT ]++;
2048 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2049 break;
2050
2051 case INS_LEFT:
2052 case INS_LEFT_COND_EXE:
2053 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2054 break;
2055
2056 case INS_RIGHT_PARALLEL:
2057 /* Don't count a parallel op that includes a NOP as a true parallel op */
2058 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2059 ins_type_counters[ (int)INS_LEFT ]++;
2060 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2061 break;
2062
2063 case INS_RIGHT:
2064 case INS_RIGHT_COND_EXE:
2065 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2066 break;
2067 }
2068
2069 trace_output_void ();
2070 }
2071
2072 /* not */
2073 void
2074 OP_4603 ()
2075 {
2076 int16 tmp;
2077 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2078 tmp = ~GPR (OP[0]);
2079 SET_GPR (OP[0], tmp);
2080 trace_output_16 (tmp);
2081 }
2082
2083 /* or */
2084 void
2085 OP_800 ()
2086 {
2087 int16 tmp;
2088 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2089 tmp = (GPR (OP[0]) | GPR (OP[1]));
2090 SET_GPR (OP[0], tmp);
2091 trace_output_16 (tmp);
2092 }
2093
2094 /* or3 */
2095 void
2096 OP_4000000 ()
2097 {
2098 int16 tmp;
2099 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2100 tmp = (GPR (OP[1]) | OP[2]);
2101 SET_GPR (OP[0], tmp);
2102 trace_output_16 (tmp);
2103 }
2104
2105 /* rac */
2106 void
2107 OP_5201 ()
2108 {
2109 int64 tmp;
2110 int shift = SEXT3 (OP[2]);
2111
2112 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2113 if (OP[1] != 0)
2114 {
2115 (*d10v_callback->printf_filtered) (d10v_callback,
2116 "ERROR at PC 0x%x: instruction only valid for A0\n",
2117 PC<<2);
2118 State.exception = SIGILL;
2119 }
2120
2121 SET_PSW_F1 (PSW_F0);
2122 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2123 if (shift >=0)
2124 tmp <<= shift;
2125 else
2126 tmp >>= -shift;
2127 tmp += 0x8000;
2128 tmp >>= 16; /* look at bits 0:43 */
2129 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2130 {
2131 tmp = 0x7fffffff;
2132 SET_PSW_F0 (1);
2133 }
2134 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2135 {
2136 tmp = 0x80000000;
2137 SET_PSW_F0 (1);
2138 }
2139 else
2140 {
2141 SET_PSW_F0 (0);
2142 }
2143 SET_GPR32 (OP[0], tmp);
2144 trace_output_32 (tmp);
2145 }
2146
2147 /* rachi */
2148 void
2149 OP_4201 ()
2150 {
2151 signed64 tmp;
2152 int shift = SEXT3 (OP[2]);
2153
2154 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2155 SET_PSW_F1 (PSW_F0);
2156 if (shift >=0)
2157 tmp = SEXT40 (ACC (OP[1])) << shift;
2158 else
2159 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2160 tmp += 0x8000;
2161
2162 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2163 {
2164 tmp = 0x7fff;
2165 SET_PSW_F0 (1);
2166 }
2167 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2168 {
2169 tmp = 0x8000;
2170 SET_PSW_F0 (1);
2171 }
2172 else
2173 {
2174 tmp = (tmp >> 16);
2175 SET_PSW_F0 (0);
2176 }
2177 SET_GPR (OP[0], tmp);
2178 trace_output_16 (tmp);
2179 }
2180
2181 /* rep */
2182 void
2183 OP_27000000 ()
2184 {
2185 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2186 SET_RPT_S (PC + 1);
2187 SET_RPT_E (PC + OP[1]);
2188 SET_RPT_C (GPR (OP[0]));
2189 SET_PSW_RP (1);
2190 if (GPR (OP[0]) == 0)
2191 {
2192 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2193 State.exception = SIGILL;
2194 }
2195 if (OP[1] < 4)
2196 {
2197 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2198 State.exception = SIGILL;
2199 }
2200 trace_output_void ();
2201 }
2202
2203 /* repi */
2204 void
2205 OP_2F000000 ()
2206 {
2207 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2208 SET_RPT_S (PC + 1);
2209 SET_RPT_E (PC + OP[1]);
2210 SET_RPT_C (OP[0]);
2211 SET_PSW_RP (1);
2212 if (OP[0] == 0)
2213 {
2214 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2215 State.exception = SIGILL;
2216 }
2217 if (OP[1] < 4)
2218 {
2219 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2220 State.exception = SIGILL;
2221 }
2222 trace_output_void ();
2223 }
2224
2225 /* rtd */
2226 void
2227 OP_5F60 ()
2228 {
2229 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2230 SET_CREG (PSW_CR, DPSW);
2231 JMP(DPC);
2232 trace_output_void ();
2233 }
2234
2235 /* rte */
2236 void
2237 OP_5F40 ()
2238 {
2239 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2240 SET_CREG (PSW_CR, BPSW);
2241 JMP(BPC);
2242 trace_output_void ();
2243 }
2244
2245
2246 /* sac */
2247 void OP_5209 ()
2248 {
2249 int64 tmp;
2250
2251 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2252
2253 tmp = SEXT40(ACC (OP[1]));
2254
2255 SET_PSW_F1 (PSW_F0);
2256
2257 if (tmp > SEXT40(MAX32))
2258 {
2259 tmp = (MAX32);
2260 SET_PSW_F0 (1);
2261 }
2262 else if (tmp < SEXT40(MIN32))
2263 {
2264 tmp = 0x80000000;
2265 SET_PSW_F0 (1);
2266 }
2267 else
2268 {
2269 tmp = (tmp & MASK32);
2270 SET_PSW_F0 (0);
2271 }
2272
2273 SET_GPR32 (OP[0], tmp);
2274
2275 trace_output_40 (tmp);
2276 }
2277
2278
2279 /* sachi */
2280 void
2281 OP_4209 ()
2282 {
2283 int64 tmp;
2284
2285 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2286
2287 tmp = SEXT40(ACC (OP[1]));
2288
2289 SET_PSW_F1 (PSW_F0);
2290
2291 if (tmp > SEXT40(MAX32))
2292 {
2293 tmp = 0x7fff;
2294 SET_PSW_F0 (1);
2295 }
2296 else if (tmp < SEXT40(MIN32))
2297 {
2298 tmp = 0x8000;
2299 SET_PSW_F0 (1);
2300 }
2301 else
2302 {
2303 tmp >>= 16;
2304 SET_PSW_F0 (0);
2305 }
2306
2307 SET_GPR (OP[0], tmp);
2308
2309 trace_output_16 (OP[0]);
2310 }
2311
2312
2313 /* sadd */
2314 void
2315 OP_1223 ()
2316 {
2317 int64 tmp;
2318
2319 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2320 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2321 if (PSW_ST)
2322 {
2323 if (tmp > SEXT40(MAX32))
2324 tmp = (MAX32);
2325 else if (tmp < SEXT40(MIN32))
2326 tmp = (MIN32);
2327 else
2328 tmp = (tmp & MASK40);
2329 }
2330 else
2331 tmp = (tmp & MASK40);
2332 SET_ACC (OP[0], tmp);
2333 trace_output_40 (tmp);
2334 }
2335
2336 /* setf0f */
2337 void
2338 OP_4611 ()
2339 {
2340 int16 tmp;
2341 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2342 tmp = ((PSW_F0 == 0) ? 1 : 0);
2343 SET_GPR (OP[0], tmp);
2344 trace_output_16 (tmp);
2345 }
2346
2347 /* setf0t */
2348 void
2349 OP_4613 ()
2350 {
2351 int16 tmp;
2352 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2353 tmp = ((PSW_F0 == 1) ? 1 : 0);
2354 SET_GPR (OP[0], tmp);
2355 trace_output_16 (tmp);
2356 }
2357
2358 /* slae */
2359 void
2360 OP_3220 ()
2361 {
2362 int64 tmp;
2363 int16 reg;
2364
2365 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2366
2367 reg = SEXT16( GPR (OP[1]));
2368
2369 if (reg >= 17 || reg <= -17)
2370 {
2371 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2372 State.exception = SIGILL;
2373 return;
2374 }
2375
2376 tmp = SEXT40 (ACC (OP[0]));
2377
2378 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2379 {
2380 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: value to shift 0x%x out of range.\n", tmp);
2381 State.exception = SIGILL;
2382 return;
2383 }
2384
2385 if (reg >= 0 && reg <= 16)
2386 {
2387 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2388 if (PSW_ST)
2389 {
2390 if (tmp > SEXT40(MAX32))
2391 tmp = (MAX32);
2392 else if (tmp < SEXT40(MIN32))
2393 tmp = (MIN32);
2394 else
2395 tmp = (tmp & MASK40);
2396 }
2397 else
2398 tmp = (tmp & MASK40);
2399 }
2400 else
2401 {
2402 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2403 }
2404
2405 SET_ACC(OP[0], tmp);
2406
2407 trace_output_40(tmp);
2408 }
2409
2410
2411 /* sleep */
2412 void
2413 OP_5FC0 ()
2414 {
2415 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2416 SET_PSW_IE (1);
2417 trace_output_void ();
2418 }
2419
2420 /* sll */
2421 void
2422 OP_2200 ()
2423 {
2424 int16 tmp;
2425 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2426 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2427 SET_GPR (OP[0], tmp);
2428 trace_output_16 (tmp);
2429 }
2430
2431 /* sll */
2432 void
2433 OP_3200 ()
2434 {
2435 int64 tmp;
2436 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2437 if ((GPR (OP[1]) & 31) <= 16)
2438 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2439 else
2440 {
2441 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2442 State.exception = SIGILL;
2443 return;
2444 }
2445
2446 if (PSW_ST)
2447 {
2448 if (tmp > SEXT40(MAX32))
2449 tmp = (MAX32);
2450 else if (tmp < SEXT40(MIN32))
2451 tmp = (MIN32);
2452 else
2453 tmp = (tmp & MASK40);
2454 }
2455 else
2456 tmp = (tmp & MASK40);
2457 SET_ACC (OP[0], tmp);
2458 trace_output_40 (tmp);
2459 }
2460
2461 /* slli */
2462 void
2463 OP_2201 ()
2464 {
2465 int16 tmp;
2466 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2467 tmp = (GPR (OP[0]) << OP[1]);
2468 SET_GPR (OP[0], tmp);
2469 trace_output_16 (tmp);
2470 }
2471
2472 /* slli */
2473 void
2474 OP_3201 ()
2475 {
2476 int64 tmp;
2477
2478 if (OP[1] == 0)
2479 OP[1] = 16;
2480
2481 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2482 tmp = SEXT40(ACC (OP[0])) << OP[1];
2483
2484 if (PSW_ST)
2485 {
2486 if (tmp > SEXT40(MAX32))
2487 tmp = (MAX32);
2488 else if (tmp < SEXT40(MIN32))
2489 tmp = (MIN32);
2490 else
2491 tmp = (tmp & MASK40);
2492 }
2493 else
2494 tmp = (tmp & MASK40);
2495 SET_ACC (OP[0], tmp);
2496 trace_output_40 (tmp);
2497 }
2498
2499 /* slx */
2500 void
2501 OP_460B ()
2502 {
2503 int16 tmp;
2504 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2505 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2506 SET_GPR (OP[0], tmp);
2507 trace_output_16 (tmp);
2508 }
2509
2510 /* sra */
2511 void
2512 OP_2400 ()
2513 {
2514 int16 tmp;
2515 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2516 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2517 SET_GPR (OP[0], tmp);
2518 trace_output_16 (tmp);
2519 }
2520
2521 /* sra */
2522 void
2523 OP_3400 ()
2524 {
2525 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2526 if ((GPR (OP[1]) & 31) <= 16)
2527 {
2528 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2529 SET_ACC (OP[0], tmp);
2530 trace_output_40 (tmp);
2531 }
2532 else
2533 {
2534 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2535 State.exception = SIGILL;
2536 return;
2537 }
2538 }
2539
2540 /* srai */
2541 void
2542 OP_2401 ()
2543 {
2544 int16 tmp;
2545 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2546 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2547 SET_GPR (OP[0], tmp);
2548 trace_output_16 (tmp);
2549 }
2550
2551 /* srai */
2552 void
2553 OP_3401 ()
2554 {
2555 int64 tmp;
2556 if (OP[1] == 0)
2557 OP[1] = 16;
2558
2559 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2560 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2561 SET_ACC (OP[0], tmp);
2562 trace_output_40 (tmp);
2563 }
2564
2565 /* srl */
2566 void
2567 OP_2000 ()
2568 {
2569 int16 tmp;
2570 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2571 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2572 SET_GPR (OP[0], tmp);
2573 trace_output_16 (tmp);
2574 }
2575
2576 /* srl */
2577 void
2578 OP_3000 ()
2579 {
2580 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2581 if ((GPR (OP[1]) & 31) <= 16)
2582 {
2583 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2584 SET_ACC (OP[0], tmp);
2585 trace_output_40 (tmp);
2586 }
2587 else
2588 {
2589 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2590 State.exception = SIGILL;
2591 return;
2592 }
2593
2594 }
2595
2596 /* srli */
2597 void
2598 OP_2001 ()
2599 {
2600 int16 tmp;
2601 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2602 tmp = (GPR (OP[0]) >> OP[1]);
2603 SET_GPR (OP[0], tmp);
2604 trace_output_16 (tmp);
2605 }
2606
2607 /* srli */
2608 void
2609 OP_3001 ()
2610 {
2611 int64 tmp;
2612 if (OP[1] == 0)
2613 OP[1] = 16;
2614
2615 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2616 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2617 SET_ACC (OP[0], tmp);
2618 trace_output_40 (tmp);
2619 }
2620
2621 /* srx */
2622 void
2623 OP_4609 ()
2624 {
2625 uint16 tmp;
2626 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2627 tmp = PSW_F0 << 15;
2628 tmp = ((GPR (OP[0]) >> 1) | tmp);
2629 SET_GPR (OP[0], tmp);
2630 trace_output_16 (tmp);
2631 }
2632
2633 /* st */
2634 void
2635 OP_34000000 ()
2636 {
2637 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2638 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2639 trace_output_void ();
2640 }
2641
2642 /* st */
2643 void
2644 OP_6800 ()
2645 {
2646 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2647 SW (GPR (OP[1]), GPR (OP[0]));
2648 trace_output_void ();
2649 }
2650
2651 /* st */
2652 void
2653 OP_6C1F ()
2654 {
2655 uint16 addr = GPR (OP[1]) - 2;
2656 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2657 if (OP[1] != 15)
2658 {
2659 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2660 State.exception = SIGILL;
2661 return;
2662 }
2663 SW (addr, GPR (OP[0]));
2664 SET_GPR (OP[1], addr);
2665 trace_output_void ();
2666 }
2667
2668 /* st */
2669 void
2670 OP_6801 ()
2671 {
2672 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2673 SW (GPR (OP[1]), GPR (OP[0]));
2674 INC_ADDR (OP[1], 2);
2675 trace_output_void ();
2676 }
2677
2678 /* st */
2679 void
2680 OP_6C01 ()
2681 {
2682 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2683 if ( OP[1] == 15 )
2684 {
2685 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2686 State.exception = SIGILL;
2687 return;
2688 }
2689 SW (GPR (OP[1]), GPR (OP[0]));
2690 INC_ADDR (OP[1], -2);
2691 trace_output_void ();
2692 }
2693
2694 /* st */
2695 void
2696 OP_36010000 ()
2697 {
2698 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2699 SW (OP[1], GPR (OP[0]));
2700 trace_output_void ();
2701 }
2702
2703 /* st2w */
2704 void
2705 OP_35000000 ()
2706 {
2707 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2708 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2709 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2710 trace_output_void ();
2711 }
2712
2713 /* st2w */
2714 void
2715 OP_6A00 ()
2716 {
2717 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2718 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2719 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2720 trace_output_void ();
2721 }
2722
2723 /* st2w */
2724 void
2725 OP_6E1F ()
2726 {
2727 uint16 addr = GPR (OP[1]) - 4;
2728 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2729 if ( OP[1] != 15 )
2730 {
2731 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2732 State.exception = SIGILL;
2733 return;
2734 }
2735 SW (addr + 0, GPR (OP[0] + 0));
2736 SW (addr + 2, GPR (OP[0] + 1));
2737 SET_GPR (OP[1], addr);
2738 trace_output_void ();
2739 }
2740
2741 /* st2w */
2742 void
2743 OP_6A01 ()
2744 {
2745 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2746 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2747 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2748 INC_ADDR (OP[1], 4);
2749 trace_output_void ();
2750 }
2751
2752 /* st2w */
2753 void
2754 OP_6E01 ()
2755 {
2756 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2757 if ( OP[1] == 15 )
2758 {
2759 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2760 State.exception = SIGILL;
2761 return;
2762 }
2763 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2764 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2765 INC_ADDR (OP[1], -4);
2766 trace_output_void ();
2767 }
2768
2769 /* st2w */
2770 void
2771 OP_37010000 ()
2772 {
2773 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2774 SW (OP [1] + 0, GPR (OP[0] + 0));
2775 SW (OP [1] + 2, GPR (OP[0] + 1));
2776 trace_output_void ();
2777 }
2778
2779 /* stb */
2780 void
2781 OP_3C000000 ()
2782 {
2783 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2784 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2785 trace_output_void ();
2786 }
2787
2788 /* stb */
2789 void
2790 OP_7800 ()
2791 {
2792 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2793 SB (GPR (OP[1]), GPR (OP[0]));
2794 trace_output_void ();
2795 }
2796
2797 /* stop */
2798 void
2799 OP_5FE0 ()
2800 {
2801 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2802 State.exception = SIG_D10V_STOP;
2803 trace_output_void ();
2804 }
2805
2806 /* sub */
2807 void
2808 OP_0 ()
2809 {
2810 uint16 a = GPR (OP[0]);
2811 uint16 b = GPR (OP[1]);
2812 uint16 tmp = (a - b);
2813 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2814 /* see ../common/sim-alu.h for a more extensive discussion on how to
2815 compute the carry/overflow bits. */
2816 SET_PSW_C (a >= b);
2817 SET_GPR (OP[0], tmp);
2818 trace_output_16 (tmp);
2819 }
2820
2821 /* sub */
2822 void
2823 OP_1001 ()
2824 {
2825 int64 tmp;
2826
2827 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2828 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2829 if (PSW_ST)
2830 {
2831 if (tmp > SEXT40(MAX32))
2832 tmp = (MAX32);
2833 else if (tmp < SEXT40(MIN32))
2834 tmp = (MIN32);
2835 else
2836 tmp = (tmp & MASK40);
2837 }
2838 else
2839 tmp = (tmp & MASK40);
2840 SET_ACC (OP[0], tmp);
2841
2842 trace_output_40 (tmp);
2843 }
2844
2845 /* sub */
2846
2847 void
2848 OP_1003 ()
2849 {
2850 int64 tmp;
2851
2852 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2853 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2854 if (PSW_ST)
2855 {
2856 if (tmp > SEXT40(MAX32))
2857 tmp = (MAX32);
2858 else if (tmp < SEXT40(MIN32))
2859 tmp = (MIN32);
2860 else
2861 tmp = (tmp & MASK40);
2862 }
2863 else
2864 tmp = (tmp & MASK40);
2865 SET_ACC (OP[0], tmp);
2866
2867 trace_output_40 (tmp);
2868 }
2869
2870 /* sub2w */
2871 void
2872 OP_1000 ()
2873 {
2874 uint32 tmp, a, b;
2875
2876 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2877 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2878 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2879 /* see ../common/sim-alu.h for a more extensive discussion on how to
2880 compute the carry/overflow bits */
2881 tmp = a - b;
2882 SET_PSW_C (a >= b);
2883 SET_GPR32 (OP[0], tmp);
2884 trace_output_32 (tmp);
2885 }
2886
2887 /* subac3 */
2888 void
2889 OP_17000000 ()
2890 {
2891 int64 tmp;
2892
2893 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2894 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2895 SET_GPR32 (OP[0], tmp);
2896 trace_output_32 (tmp);
2897 }
2898
2899 /* subac3 */
2900 void
2901 OP_17000002 ()
2902 {
2903 int64 tmp;
2904
2905 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2906 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2907 SET_GPR32 (OP[0], tmp);
2908 trace_output_32 (tmp);
2909 }
2910
2911 /* subac3s */
2912 void
2913 OP_17001000 ()
2914 {
2915 int64 tmp;
2916
2917 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2918 SET_PSW_F1 (PSW_F0);
2919 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2920 if (tmp > SEXT40(MAX32))
2921 {
2922 tmp = (MAX32);
2923 SET_PSW_F0 (1);
2924 }
2925 else if (tmp < SEXT40(MIN32))
2926 {
2927 tmp = (MIN32);
2928 SET_PSW_F0 (1);
2929 }
2930 else
2931 {
2932 SET_PSW_F0 (0);
2933 }
2934 SET_GPR32 (OP[0], tmp);
2935 trace_output_32 (tmp);
2936 }
2937
2938 /* subac3s */
2939 void
2940 OP_17001002 ()
2941 {
2942 int64 tmp;
2943
2944 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2945 SET_PSW_F1 (PSW_F0);
2946 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2947 if (tmp > SEXT40(MAX32))
2948 {
2949 tmp = (MAX32);
2950 SET_PSW_F0 (1);
2951 }
2952 else if (tmp < SEXT40(MIN32))
2953 {
2954 tmp = (MIN32);
2955 SET_PSW_F0 (1);
2956 }
2957 else
2958 {
2959 SET_PSW_F0 (0);
2960 }
2961 SET_GPR32 (OP[0], tmp);
2962 trace_output_32 (tmp);
2963 }
2964
2965 /* subi */
2966 void
2967 OP_1 ()
2968 {
2969 unsigned tmp;
2970 if (OP[1] == 0)
2971 OP[1] = 16;
2972
2973 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2974 /* see ../common/sim-alu.h for a more extensive discussion on how to
2975 compute the carry/overflow bits. */
2976 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2977 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2978 + (unsigned)(unsigned16) ( - OP[1]));
2979 SET_PSW_C (tmp >= (1 << 16));
2980 SET_GPR (OP[0], tmp);
2981 trace_output_16 (tmp);
2982 }
2983
2984 /* trap */
2985 void
2986 OP_5F00 ()
2987 {
2988 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2989 trace_output_void ();
2990
2991 switch (OP[0])
2992 {
2993 default:
2994 #if (DEBUG & DEBUG_TRAP) == 0
2995 {
2996 uint16 vec = OP[0] + TRAP_VECTOR_START;
2997 SET_BPC (PC + 1);
2998 SET_BPSW (PSW);
2999 SET_PSW (PSW & PSW_SM_BIT);
3000 JMP (vec);
3001 break;
3002 }
3003 #else /* if debugging use trap to print registers */
3004 {
3005 int i;
3006 static int first_time = 1;
3007
3008 if (first_time)
3009 {
3010 first_time = 0;
3011 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3012 for (i = 0; i < 16; i++)
3013 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3014 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3015 }
3016
3017 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3018
3019 for (i = 0; i < 16; i++)
3020 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3021
3022 for (i = 0; i < 2; i++)
3023 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3024 ((int)(ACC (i) >> 32) & 0xff),
3025 ((unsigned long) ACC (i)) & 0xffffffff);
3026
3027 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3028 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3029 (*d10v_callback->flush_stdout) (d10v_callback);
3030 break;
3031 }
3032 #endif
3033 case 15: /* new system call trap */
3034 /* Trap 15 is used for simulating low-level I/O */
3035 {
3036 unsigned32 result = 0;
3037 errno = 0;
3038
3039 /* Registers passed to trap 0 */
3040
3041 #define FUNC GPR (4) /* function number */
3042 #define PARM1 GPR (0) /* optional parm 1 */
3043 #define PARM2 GPR (1) /* optional parm 2 */
3044 #define PARM3 GPR (2) /* optional parm 3 */
3045 #define PARM4 GPR (3) /* optional parm 3 */
3046
3047 /* Registers set by trap 0 */
3048
3049 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3050 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3051 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3052
3053 /* Turn a pointer in a register into a pointer into real memory. */
3054
3055 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3056
3057 switch (FUNC)
3058 {
3059 #if !defined(__GO32__) && !defined(_WIN32)
3060 case TARGET_SYS_fork:
3061 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3062 RETVAL (fork ());
3063 trace_output_16 (result);
3064 break;
3065
3066 #define getpid() 47
3067 case TARGET_SYS_getpid:
3068 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3069 RETVAL (getpid ());
3070 trace_output_16 (result);
3071 break;
3072
3073 case TARGET_SYS_kill:
3074 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3075 if (PARM1 == getpid ())
3076 {
3077 trace_output_void ();
3078 State.exception = PARM2;
3079 }
3080 else
3081 {
3082 int os_sig = -1;
3083 switch (PARM2)
3084 {
3085 #ifdef SIGHUP
3086 case 1: os_sig = SIGHUP; break;
3087 #endif
3088 #ifdef SIGINT
3089 case 2: os_sig = SIGINT; break;
3090 #endif
3091 #ifdef SIGQUIT
3092 case 3: os_sig = SIGQUIT; break;
3093 #endif
3094 #ifdef SIGILL
3095 case 4: os_sig = SIGILL; break;
3096 #endif
3097 #ifdef SIGTRAP
3098 case 5: os_sig = SIGTRAP; break;
3099 #endif
3100 #ifdef SIGABRT
3101 case 6: os_sig = SIGABRT; break;
3102 #elif defined(SIGIOT)
3103 case 6: os_sig = SIGIOT; break;
3104 #endif
3105 #ifdef SIGEMT
3106 case 7: os_sig = SIGEMT; break;
3107 #endif
3108 #ifdef SIGFPE
3109 case 8: os_sig = SIGFPE; break;
3110 #endif
3111 #ifdef SIGKILL
3112 case 9: os_sig = SIGKILL; break;
3113 #endif
3114 #ifdef SIGBUS
3115 case 10: os_sig = SIGBUS; break;
3116 #endif
3117 #ifdef SIGSEGV
3118 case 11: os_sig = SIGSEGV; break;
3119 #endif
3120 #ifdef SIGSYS
3121 case 12: os_sig = SIGSYS; break;
3122 #endif
3123 #ifdef SIGPIPE
3124 case 13: os_sig = SIGPIPE; break;
3125 #endif
3126 #ifdef SIGALRM
3127 case 14: os_sig = SIGALRM; break;
3128 #endif
3129 #ifdef SIGTERM
3130 case 15: os_sig = SIGTERM; break;
3131 #endif
3132 #ifdef SIGURG
3133 case 16: os_sig = SIGURG; break;
3134 #endif
3135 #ifdef SIGSTOP
3136 case 17: os_sig = SIGSTOP; break;
3137 #endif
3138 #ifdef SIGTSTP
3139 case 18: os_sig = SIGTSTP; break;
3140 #endif
3141 #ifdef SIGCONT
3142 case 19: os_sig = SIGCONT; break;
3143 #endif
3144 #ifdef SIGCHLD
3145 case 20: os_sig = SIGCHLD; break;
3146 #elif defined(SIGCLD)
3147 case 20: os_sig = SIGCLD; break;
3148 #endif
3149 #ifdef SIGTTIN
3150 case 21: os_sig = SIGTTIN; break;
3151 #endif
3152 #ifdef SIGTTOU
3153 case 22: os_sig = SIGTTOU; break;
3154 #endif
3155 #ifdef SIGIO
3156 case 23: os_sig = SIGIO; break;
3157 #elif defined (SIGPOLL)
3158 case 23: os_sig = SIGPOLL; break;
3159 #endif
3160 #ifdef SIGXCPU
3161 case 24: os_sig = SIGXCPU; break;
3162 #endif
3163 #ifdef SIGXFSZ
3164 case 25: os_sig = SIGXFSZ; break;
3165 #endif
3166 #ifdef SIGVTALRM
3167 case 26: os_sig = SIGVTALRM; break;
3168 #endif
3169 #ifdef SIGPROF
3170 case 27: os_sig = SIGPROF; break;
3171 #endif
3172 #ifdef SIGWINCH
3173 case 28: os_sig = SIGWINCH; break;
3174 #endif
3175 #ifdef SIGLOST
3176 case 29: os_sig = SIGLOST; break;
3177 #endif
3178 #ifdef SIGUSR1
3179 case 30: os_sig = SIGUSR1; break;
3180 #endif
3181 #ifdef SIGUSR2
3182 case 31: os_sig = SIGUSR2; break;
3183 #endif
3184 }
3185
3186 if (os_sig == -1)
3187 {
3188 trace_output_void ();
3189 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3190 (*d10v_callback->flush_stdout) (d10v_callback);
3191 State.exception = SIGILL;
3192 }
3193 else
3194 {
3195 RETVAL (kill (PARM1, PARM2));
3196 trace_output_16 (result);
3197 }
3198 }
3199 break;
3200
3201 case TARGET_SYS_execve:
3202 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3203 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3204 (char **)MEMPTR (PARM3)));
3205 trace_output_16 (result);
3206 break;
3207
3208 #ifdef TARGET_SYS_execv
3209 case TARGET_SYS_execv:
3210 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3211 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3212 trace_output_16 (result);
3213 break;
3214 #endif
3215
3216 case TARGET_SYS_pipe:
3217 {
3218 reg_t buf;
3219 int host_fd[2];
3220
3221 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3222 buf = PARM1;
3223 RETVAL (pipe (host_fd));
3224 SW (buf, host_fd[0]);
3225 buf += sizeof(uint16);
3226 SW (buf, host_fd[1]);
3227 trace_output_16 (result);
3228 }
3229 break;
3230
3231 #if 0
3232 #ifdef TARGET_SYS_wait
3233 case TARGET_SYS_wait:
3234 {
3235 int status;
3236 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3237 RETVAL (wait (&status));
3238 if (PARM1)
3239 SW (PARM1, status);
3240 trace_output_16 (result);
3241 }
3242 break;
3243 #endif
3244 #endif
3245 #else
3246 case TARGET_SYS_getpid:
3247 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3248 RETVAL (1);
3249 trace_output_16 (result);
3250 break;
3251
3252 case TARGET_SYS_kill:
3253 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3254 trace_output_void ();
3255 State.exception = PARM2;
3256 break;
3257 #endif
3258
3259 case TARGET_SYS_read:
3260 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3261 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3262 PARM3));
3263 trace_output_16 (result);
3264 break;
3265
3266 case TARGET_SYS_write:
3267 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3268 if (PARM1 == 1)
3269 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3270 MEMPTR (PARM2), PARM3));
3271 else
3272 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3273 MEMPTR (PARM2), PARM3));
3274 trace_output_16 (result);
3275 break;
3276
3277 case TARGET_SYS_lseek:
3278 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3279 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3280 ((((unsigned long) PARM2) << 16)
3281 || (unsigned long) PARM3),
3282 PARM4));
3283 trace_output_32 (result);
3284 break;
3285
3286 case TARGET_SYS_close:
3287 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3288 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3289 trace_output_16 (result);
3290 break;
3291
3292 case TARGET_SYS_open:
3293 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3294 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3295 trace_output_16 (result);
3296 break;
3297
3298 case TARGET_SYS_exit:
3299 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3300 State.exception = SIG_D10V_EXIT;
3301 trace_output_void ();
3302 break;
3303
3304 #ifdef TARGET_SYS_stat
3305 case TARGET_SYS_stat:
3306 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3307 /* stat system call */
3308 {
3309 struct stat host_stat;
3310 reg_t buf;
3311
3312 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3313
3314 buf = PARM2;
3315
3316 /* The hard-coded offsets and sizes were determined by using
3317 * the D10V compiler on a test program that used struct stat.
3318 */
3319 SW (buf, host_stat.st_dev);
3320 SW (buf+2, host_stat.st_ino);
3321 SW (buf+4, host_stat.st_mode);
3322 SW (buf+6, host_stat.st_nlink);
3323 SW (buf+8, host_stat.st_uid);
3324 SW (buf+10, host_stat.st_gid);
3325 SW (buf+12, host_stat.st_rdev);
3326 SLW (buf+16, host_stat.st_size);
3327 SLW (buf+20, host_stat.st_atime);
3328 SLW (buf+28, host_stat.st_mtime);
3329 SLW (buf+36, host_stat.st_ctime);
3330 }
3331 trace_output_16 (result);
3332 break;
3333 #endif
3334
3335 case TARGET_SYS_chown:
3336 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3337 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3338 trace_output_16 (result);
3339 break;
3340
3341 case TARGET_SYS_chmod:
3342 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3343 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3344 trace_output_16 (result);
3345 break;
3346
3347 #if 0
3348 #ifdef TARGET_SYS_utime
3349 case TARGET_SYS_utime:
3350 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3351 /* Cast the second argument to void *, to avoid type mismatch
3352 if a prototype is present. */
3353 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3354 trace_output_16 (result);
3355 break;
3356 #endif
3357 #endif
3358
3359 #if 0
3360 #ifdef TARGET_SYS_time
3361 case TARGET_SYS_time:
3362 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3363 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3364 trace_output_32 (result);
3365 break;
3366 #endif
3367 #endif
3368
3369 default:
3370 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3371 }
3372 if ((uint16) result == (uint16) -1)
3373 RETERR (d10v_callback->get_errno(d10v_callback));
3374 else
3375 RETERR (0);
3376 break;
3377 }
3378 }
3379 }
3380
3381 /* tst0i */
3382 void
3383 OP_7000000 ()
3384 {
3385 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3386 SET_PSW_F1 (PSW_F0);;
3387 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3388 trace_output_flag ();
3389 }
3390
3391 /* tst1i */
3392 void
3393 OP_F000000 ()
3394 {
3395 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3396 SET_PSW_F1 (PSW_F0);
3397 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3398 trace_output_flag ();
3399 }
3400
3401 /* wait */
3402 void
3403 OP_5F80 ()
3404 {
3405 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3406 SET_PSW_IE (1);
3407 trace_output_void ();
3408 }
3409
3410 /* xor */
3411 void
3412 OP_A00 ()
3413 {
3414 int16 tmp;
3415 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3416 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3417 SET_GPR (OP[0], tmp);
3418 trace_output_16 (tmp);
3419 }
3420
3421 /* xor3 */
3422 void
3423 OP_5000000 ()
3424 {
3425 int16 tmp;
3426 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3427 tmp = (GPR (OP[1]) ^ OP[2]);
3428 SET_GPR (OP[0], tmp);
3429 trace_output_16 (tmp);
3430 }
3431
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