sim/d10v/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #include <errno.h>
   5 #include <sys/types.h>
   6 #include <sys/stat.h>
   7 #ifdef HAVE_UNISTD_H
   8 #include <unistd.h>
   9 #endif
  10
  11 #include "d10v_sim.h"
  12 #include "simops.h"
  13 #include "targ-vals.h"
  14
  15 extern char *strrchr ();
  16
  17 enum op_types {
  18   OP_VOID,
  19   OP_REG,
  20   OP_REG_OUTPUT,
  21   OP_DREG,
  22   OP_DREG_OUTPUT,
  23   OP_ACCUM,
  24   OP_ACCUM_OUTPUT,
  25   OP_ACCUM_REVERSE,
  26   OP_CR,
  27   OP_CR_OUTPUT,
  28   OP_CR_REVERSE,
  29   OP_FLAG,
  30   OP_FLAG_OUTPUT,
  31   OP_CONSTANT16,
  32   OP_CONSTANT8,
  33   OP_CONSTANT3,
  34   OP_CONSTANT4,
  35   OP_MEMREF,
  36   OP_MEMREF2,
  37   OP_MEMREF3,
  38   OP_POSTDEC,
  39   OP_POSTINC,
  40   OP_PREDEC,
  41   OP_R0,
  42   OP_R1,
  43   OP_R2,
  44 };
  45
  46
  47 enum {
  48   PSW_MASK = (PSW_SM_BIT
  49               | PSW_EA_BIT
  50               | PSW_DB_BIT
  51               | PSW_IE_BIT
  52               | PSW_RP_BIT
  53               | PSW_MD_BIT
  54               | PSW_FX_BIT
  55               | PSW_ST_BIT
  56               | PSW_F0_BIT
  57               | PSW_F1_BIT
  58               | PSW_C_BIT),
  59   /* The following bits in the PSW _can't_ be set by instructions such
  60      as mvtc. */
  61   PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
  62 };
  63
  64 reg_t
  65 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
  66 {
  67   /* A MASK bit is set when the corresponding bit in the CR should
  68      be left alone */
  69   /* This assumes that (VAL & MASK) == 0 */
  70   switch (cr)
  71     {
  72     case PSW_CR:
  73       if (psw_hw_p)
  74         val &= PSW_HW_MASK;
  75       else
  76         val &= PSW_MASK;
  77       if ((mask & PSW_SM_BIT) == 0)
  78         {
  79           int new_psw_sm = (val & PSW_SM_BIT) != 0;
  80           /* save old SP */
  81           SET_HELD_SP (PSW_SM, GPR (SP_IDX));
  82           if (PSW_SM != new_psw_sm)
  83             /* restore new SP */
  84             SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
  85         }
  86       if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
  87         {
  88           if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
  89             {
  90               (*d10v_callback->printf_filtered)
  91                 (d10v_callback,
  92                  "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
  93                  PC<<2);
  94               State.exception = SIGILL;
  95             }
  96         }
  97       /* keep an up-to-date psw around for tracing */
  98       State.trace.psw = (State.trace.psw & mask) | val;
  99       break;
 100     case BPSW_CR:
 101     case DPSW_CR:
 102       /* Just like PSW, mask things like DM out. */
 103       if (psw_hw_p)
 104         val &= PSW_HW_MASK;
 105       else
 106         val &= PSW_MASK;
 107       break;
 108     case MOD_S_CR:
 109     case MOD_E_CR:
 110       val &= ~1;
 111       break;
 112     default:
 113       break;
 114     }
 115   /* only issue an update if the register is being changed */
 116   if ((State.cregs[cr] & ~mask) != val)
 117     SLOT_PEND_MASK (State.cregs[cr], mask, val);
 118   return val;
 119 }
 120
 121 /* Modify registers according to an AE - address exception. */
 122 static void
 123 address_exception (void)
 124 {
 125   SET_BPC (PC);
 126   SET_BPSW (PSW);
 127   SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
 128   JMP (AE_VECTOR_START);
 129 }
 130
 131 #ifdef DEBUG
 132 static void trace_input_func PARAMS ((char *name,
 133                                       enum op_types in1,
 134                                       enum op_types in2,
 135                                       enum op_types in3));
 136
 137 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
 138
 139 #ifndef SIZE_INSTRUCTION
 140 #define SIZE_INSTRUCTION 8
 141 #endif
 142
 143 #ifndef SIZE_OPERANDS
 144 #define SIZE_OPERANDS 18
 145 #endif
 146
 147 #ifndef SIZE_VALUES
 148 #define SIZE_VALUES 13
 149 #endif
 150
 151 #ifndef SIZE_LOCATION
 152 #define SIZE_LOCATION 20
 153 #endif
 154
 155 #ifndef SIZE_PC
 156 #define SIZE_PC 6
 157 #endif
 158
 159 #ifndef SIZE_LINE_NUMBER
 160 #define SIZE_LINE_NUMBER 4
 161 #endif
 162
 163 static void
 164 trace_input_func (name, in1, in2, in3)
 165      char *name;
 166      enum op_types in1;
 167      enum op_types in2;
 168      enum op_types in3;
 169 {
 170   char *comma;
 171   enum op_types in[3];
 172   int i;
 173   char buf[1024];
 174   char *p;
 175   long tmp;
 176   char *type;
 177   const char *filename;
 178   const char *functionname;
 179   unsigned int linenumber;
 180   bfd_vma byte_pc;
 181
 182   if ((d10v_debug & DEBUG_TRACE) == 0)
 183     return;
 184
 185   switch (State.ins_type)
 186     {
 187     default:
 188     case INS_UNKNOWN:           type = " ?"; break;
 189     case INS_LEFT:              type = " L"; break;
 190     case INS_RIGHT:             type = " R"; break;
 191     case INS_LEFT_PARALLEL:     type = "*L"; break;
 192     case INS_RIGHT_PARALLEL:    type = "*R"; break;
 193     case INS_LEFT_COND_TEST:    type = "?L"; break;
 194     case INS_RIGHT_COND_TEST:   type = "?R"; break;
 195     case INS_LEFT_COND_EXE:     type = "&L"; break;
 196     case INS_RIGHT_COND_EXE:    type = "&R"; break;
 197     case INS_LONG:              type = " B"; break;
 198     }
 199
 200   if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
 201     (*d10v_callback->printf_filtered) (d10v_callback,
 202                                        "0x%.*x %s: %-*s ",
 203                                        SIZE_PC, (unsigned)PC,
 204                                        type,
 205                                        SIZE_INSTRUCTION, name);
 206
 207   else
 208     {
 209       buf[0] = '\0';
 210       byte_pc = decode_pc ();
 211       if (text && byte_pc >= text_start && byte_pc < text_end)
 212         {
 213           filename = (const char *)0;
 214           functionname = (const char *)0;
 215           linenumber = 0;
 216           if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
 217                                      &filename, &functionname, &linenumber))
 218             {
 219               p = buf;
 220               if (linenumber)
 221                 {
 222                   sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
 223                   p += strlen (p);
 224                 }
 225               else
 226                 {
 227                   sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
 228                   p += SIZE_LINE_NUMBER+2;
 229                 }
 230
 231               if (functionname)
 232                 {
 233                   sprintf (p, "%s ", functionname);
 234                   p += strlen (p);
 235                 }
 236               else if (filename)
 237                 {
 238                   char *q = strrchr (filename, '/');
 239                   sprintf (p, "%s ", (q) ? q+1 : filename);
 240                   p += strlen (p);
 241                 }
 242
 243               if (*p == ' ')
 244                 *p = '\0';
 245             }
 246         }
 247
 248       (*d10v_callback->printf_filtered) (d10v_callback,
 249                                          "0x%.*x %s: %-*.*s %-*s ",
 250                                          SIZE_PC, (unsigned)PC,
 251                                          type,
 252                                          SIZE_LOCATION, SIZE_LOCATION, buf,
 253                                          SIZE_INSTRUCTION, name);
 254     }
 255
 256   in[0] = in1;
 257   in[1] = in2;
 258   in[2] = in3;
 259   comma = "";
 260   p = buf;
 261   for (i = 0; i < 3; i++)
 262     {
 263       switch (in[i])
 264         {
 265         case OP_VOID:
 266         case OP_R0:
 267         case OP_R1:
 268         case OP_R2:
 269           break;
 270
 271         case OP_REG:
 272         case OP_REG_OUTPUT:
 273         case OP_DREG:
 274         case OP_DREG_OUTPUT:
 275           sprintf (p, "%sr%d", comma, OP[i]);
 276           p += strlen (p);
 277           comma = ",";
 278           break;
 279
 280         case OP_CR:
 281         case OP_CR_OUTPUT:
 282         case OP_CR_REVERSE:
 283           sprintf (p, "%scr%d", comma, OP[i]);
 284           p += strlen (p);
 285           comma = ",";
 286           break;
 287
 288         case OP_ACCUM:
 289         case OP_ACCUM_OUTPUT:
 290         case OP_ACCUM_REVERSE:
 291           sprintf (p, "%sa%d", comma, OP[i]);
 292           p += strlen (p);
 293           comma = ",";
 294           break;
 295
 296         case OP_CONSTANT16:
 297           sprintf (p, "%s%d", comma, OP[i]);
 298           p += strlen (p);
 299           comma = ",";
 300           break;
 301
 302         case OP_CONSTANT8:
 303           sprintf (p, "%s%d", comma, SEXT8(OP[i]));
 304           p += strlen (p);
 305           comma = ",";
 306           break;
 307
 308         case OP_CONSTANT4:
 309           sprintf (p, "%s%d", comma, SEXT4(OP[i]));
 310           p += strlen (p);
 311           comma = ",";
 312           break;
 313
 314         case OP_CONSTANT3:
 315           sprintf (p, "%s%d", comma, SEXT3(OP[i]));
 316           p += strlen (p);
 317           comma = ",";
 318           break;
 319
 320         case OP_MEMREF:
 321           sprintf (p, "%s@r%d", comma, OP[i]);
 322           p += strlen (p);
 323           comma = ",";
 324           break;
 325
 326         case OP_MEMREF2:
 327           sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
 328           p += strlen (p);
 329           comma = ",";
 330           break;
 331
 332         case OP_MEMREF3:
 333           sprintf (p, "%s@%d", comma, OP[i]);
 334           p += strlen (p);
 335           comma = ",";
 336           break;
 337
 338         case OP_POSTINC:
 339           sprintf (p, "%s@r%d+", comma, OP[i]);
 340           p += strlen (p);
 341           comma = ",";
 342           break;
 343
 344         case OP_POSTDEC:
 345           sprintf (p, "%s@r%d-", comma, OP[i]);
 346           p += strlen (p);
 347           comma = ",";
 348           break;
 349
 350         case OP_PREDEC:
 351           sprintf (p, "%s@-r%d", comma, OP[i]);
 352           p += strlen (p);
 353           comma = ",";
 354           break;
 355
 356         case OP_FLAG:
 357         case OP_FLAG_OUTPUT:
 358           if (OP[i] == 0)
 359             sprintf (p, "%sf0", comma);
 360
 361           else if (OP[i] == 1)
 362             sprintf (p, "%sf1", comma);
 363
 364           else
 365             sprintf (p, "%sc", comma);
 366
 367           p += strlen (p);
 368           comma = ",";
 369           break;
 370         }
 371     }
 372
 373   if ((d10v_debug & DEBUG_VALUES) == 0)
 374     {
 375       *p++ = '\n';
 376       *p = '\0';
 377       (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
 378     }
 379   else
 380     {
 381       *p = '\0';
 382       (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
 383
 384       p = buf;
 385       for (i = 0; i < 3; i++)
 386         {
 387           buf[0] = '\0';
 388           switch (in[i])
 389             {
 390             case OP_VOID:
 391               (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
 392               break;
 393
 394             case OP_REG_OUTPUT:
 395             case OP_DREG_OUTPUT:
 396             case OP_CR_OUTPUT:
 397             case OP_ACCUM_OUTPUT:
 398             case OP_FLAG_OUTPUT:
 399               (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
 400               break;
 401
 402             case OP_REG:
 403             case OP_MEMREF:
 404             case OP_POSTDEC:
 405             case OP_POSTINC:
 406             case OP_PREDEC:
 407               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 408                                                  (uint16) GPR (OP[i]));
 409               break;
 410
 411             case OP_MEMREF3:
 412               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
 413               break;
 414
 415             case OP_DREG:
 416               tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
 417               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
 418               break;
 419
 420             case OP_CR:
 421             case OP_CR_REVERSE:
 422               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 423                                                  (uint16) CREG (OP[i]));
 424               break;
 425
 426             case OP_ACCUM:
 427             case OP_ACCUM_REVERSE:
 428               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
 429                                                  ((int)(ACC (OP[i]) >> 32) & 0xff),
 430                                                  ((unsigned long) ACC (OP[i])) & 0xffffffff);
 431               break;
 432
 433             case OP_CONSTANT16:
 434               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 435                                                  (uint16)OP[i]);
 436               break;
 437
 438             case OP_CONSTANT4:
 439               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 440                                                  (uint16)SEXT4(OP[i]));
 441               break;
 442
 443             case OP_CONSTANT8:
 444               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 445                                                  (uint16)SEXT8(OP[i]));
 446               break;
 447
 448             case OP_CONSTANT3:
 449               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 450                                                  (uint16)SEXT3(OP[i]));
 451               break;
 452
 453             case OP_FLAG:
 454               if (OP[i] == 0)
 455                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
 456                                                    PSW_F0 != 0);
 457
 458               else if (OP[i] == 1)
 459                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
 460                                                    PSW_F1 != 0);
 461
 462               else
 463                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
 464                                                    PSW_C != 0);
 465
 466               break;
 467
 468             case OP_MEMREF2:
 469               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 470                                                  (uint16)OP[i]);
 471               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 472                                                  (uint16)GPR (OP[i + 1]));
 473               i++;
 474               break;
 475
 476             case OP_R0:
 477               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 478                                                  (uint16) GPR (0));
 479               break;
 480
 481             case OP_R1:
 482               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 483                                                  (uint16) GPR (1));
 484               break;
 485
 486             case OP_R2:
 487               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 488                                                  (uint16) GPR (2));
 489               break;
 490
 491             }
 492         }
 493     }
 494
 495   (*d10v_callback->flush_stdout) (d10v_callback);
 496 }
 497
 498 static void
 499 do_trace_output_flush (void)
 500 {
 501   (*d10v_callback->flush_stdout) (d10v_callback);
 502 }
 503
 504 static void
 505 do_trace_output_finish (void)
 506 {
 507   (*d10v_callback->printf_filtered) (d10v_callback,
 508                                      " F0=%d F1=%d C=%d\n",
 509                                      (State.trace.psw & PSW_F0_BIT) != 0,
 510                                      (State.trace.psw & PSW_F1_BIT) != 0,
 511                                      (State.trace.psw & PSW_C_BIT) != 0);
 512   (*d10v_callback->flush_stdout) (d10v_callback);
 513 }
 514
 515 static void
 516 trace_output_40 (uint64 val)
 517 {
 518   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 519     {
 520       (*d10v_callback->printf_filtered) (d10v_callback,
 521                                          " :: %*s0x%.2x%.8lx",
 522                                          SIZE_VALUES - 12,
 523                                          "",
 524                                          ((int)(val >> 32) & 0xff),
 525                                          ((unsigned long) val) & 0xffffffff);
 526       do_trace_output_finish ();
 527     }
 528 }
 529
 530 static void
 531 trace_output_32 (uint32 val)
 532 {
 533   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 534     {
 535       (*d10v_callback->printf_filtered) (d10v_callback,
 536                                          " :: %*s0x%.8x",
 537                                          SIZE_VALUES - 10,
 538                                          "",
 539                                          (int) val);
 540       do_trace_output_finish ();
 541     }
 542 }
 543
 544 static void
 545 trace_output_16 (uint16 val)
 546 {
 547   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 548     {
 549       (*d10v_callback->printf_filtered) (d10v_callback,
 550                                          " :: %*s0x%.4x",
 551                                          SIZE_VALUES - 6,
 552                                          "",
 553                                          (int) val);
 554       do_trace_output_finish ();
 555     }
 556 }
 557
 558 static void
 559 trace_output_void ()
 560 {
 561   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 562     {
 563       (*d10v_callback->printf_filtered) (d10v_callback, "\n");
 564       do_trace_output_flush ();
 565     }
 566 }
 567
 568 static void
 569 trace_output_flag ()
 570 {
 571   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 572     {
 573       (*d10v_callback->printf_filtered) (d10v_callback,
 574                                          " :: %*s",
 575                                          SIZE_VALUES,
 576                                          "");
 577       do_trace_output_finish ();
 578     }
 579 }
 580
 581
 582
 583
 584 #else
 585 #define trace_input(NAME, IN1, IN2, IN3)
 586 #define trace_output(RESULT)
 587 #endif
 588
 589 /* abs */
 590 void
 591 OP_4607 ()
 592 {
 593   int16 tmp;
 594   trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
 595   SET_PSW_F1 (PSW_F0);
 596   tmp = GPR(OP[0]);
 597   if (tmp < 0)
 598     {
 599       tmp = - tmp;
 600       SET_PSW_F0 (1);
 601     }
 602   else
 603     SET_PSW_F0 (0);
 604   SET_GPR (OP[0], tmp);
 605   trace_output_16 (tmp);
 606 }
 607
 608 /* abs */
 609 void
 610 OP_5607 ()
 611 {
 612   int64 tmp;
 613   trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
 614   SET_PSW_F1 (PSW_F0);
 615
 616   tmp = SEXT40 (ACC (OP[0]));
 617   if (tmp < 0 )
 618     {
 619       tmp = - tmp;
 620       if (PSW_ST)
 621         {
 622           if (tmp > SEXT40(MAX32))
 623             tmp = (MAX32);
 624           else if (tmp < SEXT40(MIN32))
 625             tmp = (MIN32);
 626           else
 627             tmp = (tmp & MASK40);
 628         }
 629       else
 630         tmp = (tmp & MASK40);
 631       SET_PSW_F0 (1);
 632     }
 633   else
 634     {
 635       tmp = (tmp & MASK40);
 636       SET_PSW_F0 (0);
 637     }
 638   SET_ACC (OP[0], tmp);
 639   trace_output_40 (tmp);
 640 }
 641
 642 /* add */
 643 void
 644 OP_200 ()
 645 {
 646   uint16 a = GPR (OP[0]);
 647   uint16 b = GPR (OP[1]);
 648   uint16 tmp = (a + b);
 649   trace_input ("add", OP_REG, OP_REG, OP_VOID);
 650   SET_PSW_C (a > tmp);
 651   SET_GPR (OP[0], tmp);
 652   trace_output_16 (tmp);
 653 }
 654
 655 /* add */
 656 void
 657 OP_1201 ()
 658 {
 659   int64 tmp;
 660   tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
 661
 662   trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
 663   if (PSW_ST)
 664     {
 665       if (tmp > SEXT40(MAX32))
 666         tmp = (MAX32);
 667       else if (tmp < SEXT40(MIN32))
 668         tmp = (MIN32);
 669       else
 670         tmp = (tmp & MASK40);
 671     }
 672   else
 673     tmp = (tmp & MASK40);
 674   SET_ACC (OP[0], tmp);
 675   trace_output_40 (tmp);
 676 }
 677
 678 /* add */
 679 void
 680 OP_1203 ()
 681 {
 682   int64 tmp;
 683   tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
 684
 685   trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
 686   if (PSW_ST)
 687     {
 688       if (tmp > SEXT40(MAX32))
 689         tmp = (MAX32);
 690       else if (tmp < SEXT40(MIN32))
 691         tmp = (MIN32);
 692       else
 693         tmp = (tmp & MASK40);
 694     }
 695   else
 696     tmp = (tmp & MASK40);
 697   SET_ACC (OP[0], tmp);
 698   trace_output_40 (tmp);
 699 }
 700
 701 /* add2w */
 702 void
 703 OP_1200 ()
 704 {
 705   uint32 tmp;
 706   uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
 707   uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
 708   trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
 709   tmp = a + b;
 710   SET_PSW_C (tmp < a);
 711   SET_GPR (OP[0] + 0, (tmp >> 16));
 712   SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
 713   trace_output_32 (tmp);
 714 }
 715
 716 /* add3 */
 717 void
 718 OP_1000000 ()
 719 {
 720   uint16 a = GPR (OP[1]);
 721   uint16 b = OP[2];
 722   uint16 tmp = (a + b);
 723   trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
 724   SET_PSW_C (tmp < a);
 725   SET_GPR (OP[0], tmp);
 726   trace_output_16 (tmp);
 727 }
 728
 729 /* addac3 */
 730 void
 731 OP_17000200 ()
 732 {
 733   int64 tmp;
 734   tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
 735
 736   trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
 737   SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
 738   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 739   trace_output_32 (tmp);
 740 }
 741
 742 /* addac3 */
 743 void
 744 OP_17000202 ()
 745 {
 746   int64 tmp;
 747   tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
 748
 749   trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
 750   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 751   SET_GPR (OP[0] + 1, tmp & 0xffff);
 752   trace_output_32 (tmp);
 753 }
 754
 755 /* addac3s */
 756 void
 757 OP_17001200 ()
 758 {
 759   int64 tmp;
 760   SET_PSW_F1 (PSW_F0);
 761
 762   trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
 763   tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
 764   if (tmp > SEXT40(MAX32))
 765     {
 766       tmp = (MAX32);
 767       SET_PSW_F0 (1);
 768     }
 769   else if (tmp < SEXT40(MIN32))
 770     {
 771       tmp = (MIN32);
 772       SET_PSW_F0 (1);
 773     }
 774   else
 775     {
 776       SET_PSW_F0 (0);
 777     }
 778   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 779   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 780   trace_output_32 (tmp);
 781 }
 782
 783 /* addac3s */
 784 void
 785 OP_17001202 ()
 786 {
 787   int64 tmp;
 788   SET_PSW_F1 (PSW_F0);
 789
 790   trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
 791   tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
 792   if (tmp > SEXT40(MAX32))
 793     {
 794       tmp = (MAX32);
 795       SET_PSW_F0 (1);
 796     }
 797   else if (tmp < SEXT40(MIN32))
 798     {
 799       tmp = (MIN32);
 800       SET_PSW_F0 (1);
 801     }
 802   else
 803     {
 804       SET_PSW_F0 (0);
 805     }
 806   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 807   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 808   trace_output_32 (tmp);
 809 }
 810
 811 /* addi */
 812 void
 813 OP_201 ()
 814 {
 815   uint16 a = GPR (OP[0]);
 816   uint16 b;
 817   uint16 tmp;
 818   if (OP[1] == 0)
 819     OP[1] = 16;
 820   b = OP[1];
 821   tmp = (a + b);
 822   trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
 823   SET_PSW_C (tmp < a);
 824   SET_GPR (OP[0], tmp);
 825   trace_output_16 (tmp);
 826 }
 827
 828 /* and */
 829 void
 830 OP_C00 ()
 831 {
 832   uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
 833   trace_input ("and", OP_REG, OP_REG, OP_VOID);
 834   SET_GPR (OP[0], tmp);
 835   trace_output_16 (tmp);
 836 }
 837
 838 /* and3 */
 839 void
 840 OP_6000000 ()
 841 {
 842   uint16 tmp = GPR (OP[1]) & OP[2];
 843   trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
 844   SET_GPR (OP[0], tmp);
 845   trace_output_16 (tmp);
 846 }
 847
 848 /* bclri */
 849 void
 850 OP_C01 ()
 851 {
 852   int16 tmp;
 853   trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
 854   tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
 855   SET_GPR (OP[0], tmp);
 856   trace_output_16 (tmp);
 857 }
 858
 859 /* bl.s */
 860 void
 861 OP_4900 ()
 862 {
 863   trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
 864   SET_GPR (13, PC + 1);
 865   JMP( PC + SEXT8 (OP[0]));
 866   trace_output_void ();
 867 }
 868
 869 /* bl.l */
 870 void
 871 OP_24800000 ()
 872 {
 873   trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
 874   SET_GPR (13, (PC + 1));
 875   JMP (PC + OP[0]);
 876   trace_output_void ();
 877 }
 878
 879 /* bnoti */
 880 void
 881 OP_A01 ()
 882 {
 883   int16 tmp;
 884   trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
 885   tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
 886   SET_GPR (OP[0], tmp);
 887   trace_output_16 (tmp);
 888 }
 889
 890 /* bra.s */
 891 void
 892 OP_4800 ()
 893 {
 894   trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 895   JMP (PC + SEXT8 (OP[0]));
 896   trace_output_void ();
 897 }
 898
 899 /* bra.l */
 900 void
 901 OP_24000000 ()
 902 {
 903   trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 904   JMP (PC + OP[0]);
 905   trace_output_void ();
 906 }
 907
 908 /* brf0f.s */
 909 void
 910 OP_4A00 ()
 911 {
 912   trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 913   if (!PSW_F0)
 914     JMP (PC + SEXT8 (OP[0]));
 915   trace_output_flag ();
 916 }
 917
 918 /* brf0f.l */
 919 void
 920 OP_25000000 ()
 921 {
 922   trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 923   if (!PSW_F0)
 924     JMP (PC + OP[0]);
 925   trace_output_flag ();
 926 }
 927
 928 /* brf0t.s */
 929 void
 930 OP_4B00 ()
 931 {
 932   trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 933   if (PSW_F0)
 934     JMP (PC + SEXT8 (OP[0]));
 935   trace_output_flag ();
 936 }
 937
 938 /* brf0t.l */
 939 void
 940 OP_25800000 ()
 941 {
 942   trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 943   if (PSW_F0)
 944     JMP (PC + OP[0]);
 945   trace_output_flag ();
 946 }
 947
 948 /* bseti */
 949 void
 950 OP_801 ()
 951 {
 952   int16 tmp;
 953   trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
 954   tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
 955   SET_GPR (OP[0], tmp);
 956   trace_output_16 (tmp);
 957 }
 958
 959 /* btsti */
 960 void
 961 OP_E01 ()
 962 {
 963   trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
 964   SET_PSW_F1 (PSW_F0);
 965   SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
 966   trace_output_flag ();
 967 }
 968
 969 /* clrac */
 970 void
 971 OP_5601 ()
 972 {
 973   trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
 974   SET_ACC (OP[0], 0);
 975   trace_output_40 (0);
 976 }
 977
 978 /* cmp */
 979 void
 980 OP_600 ()
 981 {
 982   trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
 983   SET_PSW_F1 (PSW_F0);
 984   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
 985   trace_output_flag ();
 986 }
 987
 988 /* cmp */
 989 void
 990 OP_1603 ()
 991 {
 992   trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
 993   SET_PSW_F1 (PSW_F0);
 994   SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
 995   trace_output_flag ();
 996 }
 997
 998 /* cmpeq */
 999 void
1000 OP_400 ()
1001 {
1002   trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
1003   SET_PSW_F1 (PSW_F0);
1004   SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
1005   trace_output_flag ();
1006 }
1007
1008 /* cmpeq */
1009 void
1010 OP_1403 ()
1011 {
1012   trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1013   SET_PSW_F1 (PSW_F0);
1014   SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1015   trace_output_flag ();
1016 }
1017
1018 /* cmpeqi.s */
1019 void
1020 OP_401 ()
1021 {
1022   trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1023   SET_PSW_F1 (PSW_F0);
1024   SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1025   trace_output_flag ();
1026 }
1027
1028 /* cmpeqi.l */
1029 void
1030 OP_2000000 ()
1031 {
1032   trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1033   SET_PSW_F1 (PSW_F0);
1034   SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1035   trace_output_flag ();
1036 }
1037
1038 /* cmpi.s */
1039 void
1040 OP_601 ()
1041 {
1042   trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1043   SET_PSW_F1 (PSW_F0);
1044   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1045   trace_output_flag ();
1046 }
1047
1048 /* cmpi.l */
1049 void
1050 OP_3000000 ()
1051 {
1052   trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1053   SET_PSW_F1 (PSW_F0);
1054   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1055   trace_output_flag ();
1056 }
1057
1058 /* cmpu */
1059 void
1060 OP_4600 ()
1061 {
1062   trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1063   SET_PSW_F1 (PSW_F0);
1064   SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1065   trace_output_flag ();
1066 }
1067
1068 /* cmpui */
1069 void
1070 OP_23000000 ()
1071 {
1072   trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1073   SET_PSW_F1 (PSW_F0);
1074   SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1075   trace_output_flag ();
1076 }
1077
1078 /* cpfg */
1079 void
1080 OP_4E09 ()
1081 {
1082   uint8 val;
1083
1084   trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1085
1086   if (OP[1] == 0)
1087     val = PSW_F0;
1088   else if (OP[1] == 1)
1089     val = PSW_F1;
1090   else
1091     val = PSW_C;
1092   if (OP[0] == 0)
1093     SET_PSW_F0 (val);
1094   else
1095     SET_PSW_F1 (val);
1096
1097   trace_output_flag ();
1098 }
1099
1100 /* cpfg */
1101 void
1102 OP_4E0F ()
1103 {
1104   uint8 val;
1105
1106   trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1107
1108   if (OP[1] == 0)
1109     val = PSW_F0;
1110   else if (OP[1] == 1)
1111     val = PSW_F1;
1112   else
1113     val = PSW_C;
1114   if (OP[0] == 0)
1115     SET_PSW_F0 (val);
1116   else
1117     SET_PSW_F1 (val);
1118
1119   trace_output_flag ();
1120 }
1121
1122 /* dbt */
1123 void
1124 OP_5F20 ()
1125 {
1126   /* d10v_callback->printf_filtered(d10v_callback, "***** DBT *****  PC=%x\n",PC); */
1127
1128   /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1129      The conditional below is for either of the instruction pairs
1130      ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1131      where the dbt instruction should be interpreted.
1132
1133      The module `sim-break' provides a more effective mechanism for
1134      detecting GDB planted breakpoints.  The code below may,
1135      eventually, be changed to use that mechanism. */
1136
1137   if (State.ins_type == INS_LEFT
1138       || State.ins_type == INS_RIGHT)
1139     {
1140       trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1141       SET_DPC (PC + 1);
1142       SET_DPSW (PSW);
1143       SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1144       JMP (DBT_VECTOR_START);
1145       trace_output_void ();
1146     }
1147   else
1148     {
1149       State.exception = SIGTRAP;
1150     }
1151 }
1152
1153 /* divs */
1154 void
1155 OP_14002800 ()
1156 {
1157   uint16 foo, tmp, tmpf;
1158   uint16 hi;
1159   uint16 lo;
1160
1161   trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1162   foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1163   tmp = (int16)foo - (int16)(GPR (OP[1]));
1164   tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1165   hi = ((tmpf == 1) ? tmp : foo);
1166   lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1167   SET_GPR (OP[0] + 0, hi);
1168   SET_GPR (OP[0] + 1, lo);
1169   trace_output_32 (((uint32) hi << 16) | lo);
1170 }
1171
1172 /* exef0f */
1173 void
1174 OP_4E04 ()
1175 {
1176   trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1177   State.exe = (PSW_F0 == 0);
1178   trace_output_flag ();
1179 }
1180
1181 /* exef0t */
1182 void
1183 OP_4E24 ()
1184 {
1185   trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1186   State.exe = (PSW_F0 != 0);
1187   trace_output_flag ();
1188 }
1189
1190 /* exef1f */
1191 void
1192 OP_4E40 ()
1193 {
1194   trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1195   State.exe = (PSW_F1 == 0);
1196   trace_output_flag ();
1197 }
1198
1199 /* exef1t */
1200 void
1201 OP_4E42 ()
1202 {
1203   trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1204   State.exe = (PSW_F1 != 0);
1205   trace_output_flag ();
1206 }
1207
1208 /* exefaf */
1209 void
1210 OP_4E00 ()
1211 {
1212   trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1213   State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1214   trace_output_flag ();
1215 }
1216
1217 /* exefat */
1218 void
1219 OP_4E02 ()
1220 {
1221   trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1222   State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1223   trace_output_flag ();
1224 }
1225
1226 /* exetaf */
1227 void
1228 OP_4E20 ()
1229 {
1230   trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1231   State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1232   trace_output_flag ();
1233 }
1234
1235 /* exetat */
1236 void
1237 OP_4E22 ()
1238 {
1239   trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1240   State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1241   trace_output_flag ();
1242 }
1243
1244 /* exp */
1245 void
1246 OP_15002A00 ()
1247 {
1248   uint32 tmp, foo;
1249   int i;
1250
1251   trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1252   if (((int16)GPR (OP[1])) >= 0)
1253     tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1254   else
1255     tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1256
1257   foo = 0x40000000;
1258   for (i=1;i<17;i++)
1259     {
1260       if (tmp & foo)
1261         {
1262           SET_GPR (OP[0], (i - 1));
1263           trace_output_16 (i - 1);
1264           return;
1265         }
1266       foo >>= 1;
1267     }
1268   SET_GPR (OP[0], 16);
1269   trace_output_16 (16);
1270 }
1271
1272 /* exp */
1273 void
1274 OP_15002A02 ()
1275 {
1276   int64 tmp, foo;
1277   int i;
1278
1279   trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1280   tmp = SEXT40(ACC (OP[1]));
1281   if (tmp < 0)
1282     tmp = ~tmp & MASK40;
1283
1284   foo = 0x4000000000LL;
1285   for (i=1;i<25;i++)
1286     {
1287       if (tmp & foo)
1288         {
1289           SET_GPR (OP[0], i - 9);
1290           trace_output_16 (i - 9);
1291           return;
1292         }
1293       foo >>= 1;
1294     }
1295   SET_GPR (OP[0], 16);
1296   trace_output_16 (16);
1297 }
1298
1299 /* jl */
1300 void
1301 OP_4D00 ()
1302 {
1303   trace_input ("jl", OP_REG, OP_R0, OP_R1);
1304   SET_GPR (13, PC + 1);
1305   JMP (GPR (OP[0]));
1306   trace_output_void ();
1307 }
1308
1309 /* jmp */
1310 void
1311 OP_4C00 ()
1312 {
1313   trace_input ("jmp", OP_REG,
1314                (OP[0] == 13) ? OP_R0 : OP_VOID,
1315                (OP[0] == 13) ? OP_R1 : OP_VOID);
1316
1317   JMP (GPR (OP[0]));
1318   trace_output_void ();
1319 }
1320
1321 /* ld */
1322 void
1323 OP_30000000 ()
1324 {
1325   uint16 tmp;
1326   uint16 addr = OP[1] + GPR (OP[2]);
1327   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1328   if ((addr & 1))
1329     {
1330       address_exception ();
1331       trace_output_void ();
1332       return;
1333     }
1334   tmp = RW (addr);
1335   SET_GPR (OP[0], tmp);
1336   trace_output_16 (tmp);
1337 }
1338
1339 /* ld */
1340 void
1341 OP_6401 ()
1342 {
1343   uint16 tmp;
1344   uint16 addr = GPR (OP[1]);
1345   trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1346   if ((addr & 1))
1347     {
1348       address_exception ();
1349       trace_output_void ();
1350       return;
1351     }
1352   tmp = RW (addr);
1353   SET_GPR (OP[0], tmp);
1354   if (OP[0] != OP[1])
1355     INC_ADDR (OP[1], -2);
1356   trace_output_16 (tmp);
1357 }
1358
1359 /* ld */
1360 void
1361 OP_6001 ()
1362 {
1363   uint16 tmp;
1364   uint16 addr = GPR (OP[1]);
1365   trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1366   if ((addr & 1))
1367     {
1368       address_exception ();
1369       trace_output_void ();
1370       return;
1371     }
1372   tmp = RW (addr);
1373   SET_GPR (OP[0], tmp);
1374   if (OP[0] != OP[1])
1375     INC_ADDR (OP[1], 2);
1376   trace_output_16 (tmp);
1377 }
1378
1379 /* ld */
1380 void
1381 OP_6000 ()
1382 {
1383   uint16 tmp;
1384   uint16 addr = GPR (OP[1]);
1385   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1386   if ((addr & 1))
1387     {
1388       address_exception ();
1389       trace_output_void ();
1390       return;
1391     }
1392   tmp = RW (addr);
1393   SET_GPR (OP[0], tmp);
1394   trace_output_16 (tmp);
1395 }
1396
1397 /* ld */
1398 void
1399 OP_32010000 ()
1400 {
1401   uint16 tmp;
1402   uint16 addr = OP[1];
1403   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1404   if ((addr & 1))
1405     {
1406       address_exception ();
1407       trace_output_void ();
1408       return;
1409     }
1410   tmp = RW (addr);
1411   SET_GPR (OP[0], tmp);
1412   trace_output_16 (tmp);
1413 }
1414
1415 /* ld2w */
1416 void
1417 OP_31000000 ()
1418 {
1419   int32 tmp;
1420   uint16 addr = OP[1] + GPR (OP[2]);
1421   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1422   if ((addr & 1))
1423     {
1424       address_exception ();
1425       trace_output_void ();
1426       return;
1427     }
1428   tmp = RLW (addr);
1429   SET_GPR32 (OP[0], tmp);
1430   trace_output_32 (tmp);
1431 }
1432
1433 /* ld2w */
1434 void
1435 OP_6601 ()
1436 {
1437   uint16 addr = GPR (OP[1]);
1438   int32 tmp;
1439   trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1440   if ((addr & 1))
1441     {
1442       address_exception ();
1443       trace_output_void ();
1444       return;
1445     }
1446   tmp = RLW (addr);
1447   SET_GPR32 (OP[0], tmp);
1448   if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1449     INC_ADDR (OP[1], -4);
1450   trace_output_32 (tmp);
1451 }
1452
1453 /* ld2w */
1454 void
1455 OP_6201 ()
1456 {
1457   int32 tmp;
1458   uint16 addr = GPR (OP[1]);
1459   trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1460   if ((addr & 1))
1461     {
1462       address_exception ();
1463       trace_output_void ();
1464       return;
1465     }
1466   tmp = RLW (addr);
1467   SET_GPR32 (OP[0], tmp);
1468   if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1469     INC_ADDR (OP[1], 4);
1470   trace_output_32 (tmp);
1471 }
1472
1473 /* ld2w */
1474 void
1475 OP_6200 ()
1476 {
1477   uint16 addr = GPR (OP[1]);
1478   int32 tmp;
1479   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1480   if ((addr & 1))
1481     {
1482       address_exception ();
1483       trace_output_void ();
1484       return;
1485     }
1486   tmp = RLW (addr);
1487   SET_GPR32 (OP[0], tmp);
1488   trace_output_32 (tmp);
1489 }
1490
1491 /* ld2w */
1492 void
1493 OP_33010000 ()
1494 {
1495   int32 tmp;
1496   uint16 addr = OP[1];
1497   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1498   if ((addr & 1))
1499     {
1500       address_exception ();
1501       trace_output_void ();
1502       return;
1503     }
1504   tmp = RLW (addr);
1505   SET_GPR32 (OP[0], tmp);
1506   trace_output_32 (tmp);
1507 }
1508
1509 /* ldb */
1510 void
1511 OP_38000000 ()
1512 {
1513   int16 tmp;
1514   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1515   tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1516   SET_GPR (OP[0], tmp);
1517   trace_output_16 (tmp);
1518 }
1519
1520 /* ldb */
1521 void
1522 OP_7000 ()
1523 {
1524   int16 tmp;
1525   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1526   tmp = SEXT8 (RB (GPR (OP[1])));
1527   SET_GPR (OP[0], tmp);
1528   trace_output_16 (tmp);
1529 }
1530
1531 /* ldi.s */
1532 void
1533 OP_4001 ()
1534 {
1535   int16 tmp;
1536   trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1537   tmp = SEXT4 (OP[1]);
1538   SET_GPR (OP[0], tmp);
1539   trace_output_16 (tmp);
1540 }
1541
1542 /* ldi.l */
1543 void
1544 OP_20000000 ()
1545 {
1546   int16 tmp;
1547   trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1548   tmp = OP[1];
1549   SET_GPR (OP[0], tmp);
1550   trace_output_16 (tmp);
1551 }
1552
1553 /* ldub */
1554 void
1555 OP_39000000 ()
1556 {
1557   int16 tmp;
1558   trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1559   tmp = RB (OP[1] + GPR (OP[2]));
1560   SET_GPR (OP[0], tmp);
1561   trace_output_16 (tmp);
1562 }
1563
1564 /* ldub */
1565 void
1566 OP_7200 ()
1567 {
1568   int16 tmp;
1569   trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1570   tmp = RB (GPR (OP[1]));
1571   SET_GPR (OP[0], tmp);
1572   trace_output_16 (tmp);
1573 }
1574
1575 /* mac */
1576 void
1577 OP_2A00 ()
1578 {
1579   int64 tmp;
1580
1581   trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1582   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1583
1584   if (PSW_FX)
1585     tmp = SEXT40( (tmp << 1) & MASK40);
1586
1587   if (PSW_ST && tmp > SEXT40(MAX32))
1588     tmp = (MAX32);
1589
1590   tmp += SEXT40 (ACC (OP[0]));
1591   if (PSW_ST)
1592     {
1593       if (tmp > SEXT40(MAX32))
1594         tmp = (MAX32);
1595       else if (tmp < SEXT40(MIN32))
1596         tmp = (MIN32);
1597       else
1598         tmp = (tmp & MASK40);
1599     }
1600   else
1601     tmp = (tmp & MASK40);
1602   SET_ACC (OP[0], tmp);
1603   trace_output_40 (tmp);
1604 }
1605
1606 /* macsu */
1607 void
1608 OP_1A00 ()
1609 {
1610   int64 tmp;
1611
1612   trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1613   tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1614   if (PSW_FX)
1615     tmp = SEXT40 ((tmp << 1) & MASK40);
1616   tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1617   SET_ACC (OP[0], tmp);
1618   trace_output_40 (tmp);
1619 }
1620
1621 /* macu */
1622 void
1623 OP_3A00 ()
1624 {
1625   uint64 tmp;
1626   uint32 src1;
1627   uint32 src2;
1628
1629   trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1630   src1 = (uint16) GPR (OP[1]);
1631   src2 = (uint16) GPR (OP[2]);
1632   tmp = src1 * src2;
1633   if (PSW_FX)
1634     tmp = (tmp << 1);
1635   tmp = ((ACC (OP[0]) + tmp) & MASK40);
1636   SET_ACC (OP[0], tmp);
1637   trace_output_40 (tmp);
1638 }
1639
1640 /* max */
1641 void
1642 OP_2600 ()
1643 {
1644   int16 tmp;
1645   trace_input ("max", OP_REG, OP_REG, OP_VOID);
1646   SET_PSW_F1 (PSW_F0);
1647   if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1648     {
1649       tmp = GPR (OP[1]);
1650       SET_PSW_F0 (1);
1651     }
1652   else
1653     {
1654       tmp = GPR (OP[0]);
1655       SET_PSW_F0 (0);
1656     }
1657   SET_GPR (OP[0], tmp);
1658   trace_output_16 (tmp);
1659 }
1660
1661 /* max */
1662 void
1663 OP_3600 ()
1664 {
1665   int64 tmp;
1666
1667   trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1668   SET_PSW_F1 (PSW_F0);
1669   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1670   if (tmp > SEXT40 (ACC (OP[0])))
1671     {
1672       tmp = (tmp & MASK40);
1673       SET_PSW_F0 (1);
1674     }
1675   else
1676     {
1677       tmp = ACC (OP[0]);
1678       SET_PSW_F0 (0);
1679     }
1680   SET_ACC (OP[0], tmp);
1681   trace_output_40 (tmp);
1682 }
1683
1684 /* max */
1685 void
1686 OP_3602 ()
1687 {
1688   int64 tmp;
1689   trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1690   SET_PSW_F1 (PSW_F0);
1691   if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1692     {
1693       tmp = ACC (OP[1]);
1694       SET_PSW_F0 (1);
1695     }
1696   else
1697     {
1698       tmp = ACC (OP[0]);
1699       SET_PSW_F0 (0);
1700     }
1701   SET_ACC (OP[0], tmp);
1702   trace_output_40 (tmp);
1703 }
1704
1705
1706 /* min */
1707 void
1708 OP_2601 ()
1709 {
1710   int16 tmp;
1711   trace_input ("min", OP_REG, OP_REG, OP_VOID);
1712   SET_PSW_F1 (PSW_F0);
1713   if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1714     {
1715       tmp = GPR (OP[1]);
1716       SET_PSW_F0 (1);
1717     }
1718   else
1719     {
1720       tmp = GPR (OP[0]);
1721       SET_PSW_F0 (0);
1722     }
1723   SET_GPR (OP[0], tmp);
1724   trace_output_16 (tmp);
1725 }
1726
1727 /* min */
1728 void
1729 OP_3601 ()
1730 {
1731   int64 tmp;
1732
1733   trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1734   SET_PSW_F1 (PSW_F0);
1735   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1736   if (tmp < SEXT40(ACC (OP[0])))
1737     {
1738       tmp = (tmp & MASK40);
1739       SET_PSW_F0 (1);
1740     }
1741   else
1742     {
1743       tmp = ACC (OP[0]);
1744       SET_PSW_F0 (0);
1745     }
1746   SET_ACC (OP[0], tmp);
1747   trace_output_40 (tmp);
1748 }
1749
1750 /* min */
1751 void
1752 OP_3603 ()
1753 {
1754   int64 tmp;
1755   trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1756   SET_PSW_F1 (PSW_F0);
1757   if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1758     {
1759       tmp = ACC (OP[1]);
1760       SET_PSW_F0 (1);
1761     }
1762   else
1763     {
1764       tmp = ACC (OP[0]);
1765       SET_PSW_F0 (0);
1766     }
1767   SET_ACC (OP[0], tmp);
1768   trace_output_40 (tmp);
1769 }
1770
1771 /* msb */
1772 void
1773 OP_2800 ()
1774 {
1775   int64 tmp;
1776
1777   trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1778   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1779
1780   if (PSW_FX)
1781     tmp = SEXT40 ((tmp << 1) & MASK40);
1782
1783   if (PSW_ST && tmp > SEXT40(MAX32))
1784     tmp = (MAX32);
1785
1786   tmp = SEXT40(ACC (OP[0])) - tmp;
1787   if (PSW_ST)
1788     {
1789       if (tmp > SEXT40(MAX32))
1790         tmp = (MAX32);
1791       else if (tmp < SEXT40(MIN32))
1792         tmp = (MIN32);
1793       else
1794         tmp = (tmp & MASK40);
1795     }
1796   else
1797     {
1798       tmp = (tmp & MASK40);
1799     }
1800   SET_ACC (OP[0], tmp);
1801   trace_output_40 (tmp);
1802 }
1803
1804 /* msbsu */
1805 void
1806 OP_1800 ()
1807 {
1808   int64 tmp;
1809
1810   trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1811   tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1812   if (PSW_FX)
1813     tmp = SEXT40( (tmp << 1) & MASK40);
1814   tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1815   SET_ACC (OP[0], tmp);
1816   trace_output_40 (tmp);
1817 }
1818
1819 /* msbu */
1820 void
1821 OP_3800 ()
1822 {
1823   uint64 tmp;
1824   uint32 src1;
1825   uint32 src2;
1826
1827   trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1828   src1 = (uint16) GPR (OP[1]);
1829   src2 = (uint16) GPR (OP[2]);
1830   tmp = src1 * src2;
1831   if (PSW_FX)
1832     tmp = (tmp << 1);
1833   tmp = ((ACC (OP[0]) - tmp) & MASK40);
1834   SET_ACC (OP[0], tmp);
1835   trace_output_40 (tmp);
1836 }
1837
1838 /* mul */
1839 void
1840 OP_2E00 ()
1841 {
1842   int16 tmp;
1843   trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1844   tmp = GPR (OP[0]) * GPR (OP[1]);
1845   SET_GPR (OP[0], tmp);
1846   trace_output_16 (tmp);
1847 }
1848
1849 /* mulx */
1850 void
1851 OP_2C00 ()
1852 {
1853   int64 tmp;
1854
1855   trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1856   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1857
1858   if (PSW_FX)
1859     tmp = SEXT40 ((tmp << 1) & MASK40);
1860
1861   if (PSW_ST && tmp > SEXT40(MAX32))
1862     tmp = (MAX32);
1863   else
1864     tmp = (tmp & MASK40);
1865   SET_ACC (OP[0], tmp);
1866   trace_output_40 (tmp);
1867 }
1868
1869 /* mulxsu */
1870 void
1871 OP_1C00 ()
1872 {
1873   int64 tmp;
1874
1875   trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1876   tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1877
1878   if (PSW_FX)
1879     tmp <<= 1;
1880   tmp = (tmp & MASK40);
1881   SET_ACC (OP[0], tmp);
1882   trace_output_40 (tmp);
1883 }
1884
1885 /* mulxu */
1886 void
1887 OP_3C00 ()
1888 {
1889   uint64 tmp;
1890   uint32 src1;
1891   uint32 src2;
1892
1893   trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1894   src1 = (uint16) GPR (OP[1]);
1895   src2 = (uint16) GPR (OP[2]);
1896   tmp = src1 * src2;
1897   if (PSW_FX)
1898     tmp <<= 1;
1899   tmp = (tmp & MASK40);
1900   SET_ACC (OP[0], tmp);
1901   trace_output_40 (tmp);
1902 }
1903
1904 /* mv */
1905 void
1906 OP_4000 ()
1907 {
1908   int16 tmp;
1909   trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1910   tmp = GPR (OP[1]);
1911   SET_GPR (OP[0], tmp);
1912   trace_output_16 (tmp);
1913 }
1914
1915 /* mv2w */
1916 void
1917 OP_5000 ()
1918 {
1919   int32 tmp;
1920   trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1921   tmp = GPR32 (OP[1]);
1922   SET_GPR32 (OP[0], tmp);
1923   trace_output_32 (tmp);
1924 }
1925
1926 /* mv2wfac */
1927 void
1928 OP_3E00 ()
1929 {
1930   int32 tmp;
1931   trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1932   tmp = ACC (OP[1]);
1933   SET_GPR32 (OP[0], tmp);
1934   trace_output_32 (tmp);
1935 }
1936
1937 /* mv2wtac */
1938 void
1939 OP_3E01 ()
1940 {
1941   int64 tmp;
1942   trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1943   tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1944   SET_ACC (OP[1], tmp);
1945   trace_output_40 (tmp);
1946 }
1947
1948 /* mvac */
1949 void
1950 OP_3E03 ()
1951 {
1952   int64 tmp;
1953   trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1954   tmp = ACC (OP[1]);
1955   SET_ACC (OP[0], tmp);
1956   trace_output_40 (tmp);
1957 }
1958
1959 /* mvb */
1960 void
1961 OP_5400 ()
1962 {
1963   int16 tmp;
1964   trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1965   tmp = SEXT8 (GPR (OP[1]) & 0xff);
1966   SET_GPR (OP[0], tmp);
1967   trace_output_16 (tmp);
1968 }
1969
1970 /* mvf0f */
1971 void
1972 OP_4400 ()
1973 {
1974   int16 tmp;
1975   trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1976   if (PSW_F0 == 0)
1977     {
1978       tmp = GPR (OP[1]);
1979       SET_GPR (OP[0], tmp);
1980     }
1981   else
1982     tmp = GPR (OP[0]);
1983   trace_output_16 (tmp);
1984 }
1985
1986 /* mvf0t */
1987 void
1988 OP_4401 ()
1989 {
1990   int16 tmp;
1991   trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1992   if (PSW_F0)
1993     {
1994       tmp = GPR (OP[1]);
1995       SET_GPR (OP[0], tmp);
1996     }
1997   else
1998     tmp = GPR (OP[0]);
1999   trace_output_16 (tmp);
2000 }
2001
2002 /* mvfacg */
2003 void
2004 OP_1E04 ()
2005 {
2006   int16 tmp;
2007   trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2008   tmp = ((ACC (OP[1]) >> 32) & 0xff);
2009   SET_GPR (OP[0], tmp);
2010   trace_output_16 (tmp);
2011 }
2012
2013 /* mvfachi */
2014 void
2015 OP_1E00 ()
2016 {
2017   int16 tmp;
2018   trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2019   tmp = (ACC (OP[1]) >> 16);
2020   SET_GPR (OP[0], tmp);
2021   trace_output_16 (tmp);
2022 }
2023
2024 /* mvfaclo */
2025 void
2026 OP_1E02 ()
2027 {
2028   int16 tmp;
2029   trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2030   tmp = ACC (OP[1]);
2031   SET_GPR (OP[0], tmp);
2032   trace_output_16 (tmp);
2033 }
2034
2035 /* mvfc */
2036 void
2037 OP_5200 ()
2038 {
2039   int16 tmp;
2040   trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2041   tmp = CREG (OP[1]);
2042   SET_GPR (OP[0], tmp);
2043   trace_output_16 (tmp);
2044 }
2045
2046 /* mvtacg */
2047 void
2048 OP_1E41 ()
2049 {
2050   int64 tmp;
2051   trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2052   tmp = ((ACC (OP[1]) & MASK32)
2053          | ((int64)(GPR (OP[0]) & 0xff) << 32));
2054   SET_ACC (OP[1], tmp);
2055   trace_output_40 (tmp);
2056 }
2057
2058 /* mvtachi */
2059 void
2060 OP_1E01 ()
2061 {
2062   uint64 tmp;
2063   trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2064   tmp = ACC (OP[1]) & 0xffff;
2065   tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2066   SET_ACC (OP[1], tmp);
2067   trace_output_40 (tmp);
2068 }
2069
2070 /* mvtaclo */
2071 void
2072 OP_1E21 ()
2073 {
2074   int64 tmp;
2075   trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2076   tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2077   SET_ACC (OP[1], tmp);
2078   trace_output_40 (tmp);
2079 }
2080
2081 /* mvtc */
2082 void
2083 OP_5600 ()
2084 {
2085   int16 tmp;
2086   trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2087   tmp = GPR (OP[0]);
2088   tmp = SET_CREG (OP[1], tmp);
2089   trace_output_16 (tmp);
2090 }
2091
2092 /* mvub */
2093 void
2094 OP_5401 ()
2095 {
2096   int16 tmp;
2097   trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2098   tmp = (GPR (OP[1]) & 0xff);
2099   SET_GPR (OP[0], tmp);
2100   trace_output_16 (tmp);
2101 }
2102
2103 /* neg */
2104 void
2105 OP_4605 ()
2106 {
2107   int16 tmp;
2108   trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2109   tmp = - GPR (OP[0]);
2110   SET_GPR (OP[0], tmp);
2111   trace_output_16 (tmp);
2112 }
2113
2114 /* neg */
2115 void
2116 OP_5605 ()
2117 {
2118   int64 tmp;
2119
2120   trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2121   tmp = -SEXT40(ACC (OP[0]));
2122   if (PSW_ST)
2123     {
2124       if (tmp > SEXT40(MAX32))
2125         tmp = (MAX32);
2126       else if (tmp < SEXT40(MIN32))
2127         tmp = (MIN32);
2128       else
2129         tmp = (tmp & MASK40);
2130     }
2131   else
2132     tmp = (tmp & MASK40);
2133   SET_ACC (OP[0], tmp);
2134   trace_output_40 (tmp);
2135 }
2136
2137
2138 /* nop */
2139 void
2140 OP_5E00 ()
2141 {
2142   trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2143
2144   ins_type_counters[ (int)State.ins_type ]--;   /* don't count nops as normal instructions */
2145   switch (State.ins_type)
2146     {
2147     default:
2148       ins_type_counters[ (int)INS_UNKNOWN ]++;
2149       break;
2150
2151     case INS_LEFT_PARALLEL:
2152       /* Don't count a parallel op that includes a NOP as a true parallel op */
2153       ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2154       ins_type_counters[ (int)INS_RIGHT ]++;
2155       ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2156       break;
2157
2158     case INS_LEFT:
2159     case INS_LEFT_COND_EXE:
2160       ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2161       break;
2162
2163     case INS_RIGHT_PARALLEL:
2164       /* Don't count a parallel op that includes a NOP as a true parallel op */
2165       ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2166       ins_type_counters[ (int)INS_LEFT ]++;
2167       ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2168       break;
2169
2170     case INS_RIGHT:
2171     case INS_RIGHT_COND_EXE:
2172       ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2173       break;
2174     }
2175
2176   trace_output_void ();
2177 }
2178
2179 /* not */
2180 void
2181 OP_4603 ()
2182 {
2183   int16 tmp;
2184   trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2185   tmp = ~GPR (OP[0]);
2186   SET_GPR (OP[0], tmp);
2187   trace_output_16 (tmp);
2188 }
2189
2190 /* or */
2191 void
2192 OP_800 ()
2193 {
2194   int16 tmp;
2195   trace_input ("or", OP_REG, OP_REG, OP_VOID);
2196   tmp = (GPR (OP[0]) | GPR (OP[1]));
2197   SET_GPR (OP[0], tmp);
2198   trace_output_16 (tmp);
2199 }
2200
2201 /* or3 */
2202 void
2203 OP_4000000 ()
2204 {
2205   int16 tmp;
2206   trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2207   tmp = (GPR (OP[1]) | OP[2]);
2208   SET_GPR (OP[0], tmp);
2209   trace_output_16 (tmp);
2210 }
2211
2212 /* rac */
2213 void
2214 OP_5201 ()
2215 {
2216   int64 tmp;
2217   int shift = SEXT3 (OP[2]);
2218
2219   trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2220   if (OP[1] != 0)
2221     {
2222       (*d10v_callback->printf_filtered) (d10v_callback,
2223                                          "ERROR at PC 0x%x: instruction only valid for A0\n",
2224                                          PC<<2);
2225       State.exception = SIGILL;
2226     }
2227
2228   SET_PSW_F1 (PSW_F0);
2229   tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2230   if (shift >=0)
2231     tmp <<= shift;
2232   else
2233     tmp >>= -shift;
2234   tmp += 0x8000;
2235   tmp >>= 16; /* look at bits 0:43 */
2236   if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2237     {
2238       tmp = 0x7fffffff;
2239       SET_PSW_F0 (1);
2240     }
2241   else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2242     {
2243       tmp = 0x80000000;
2244       SET_PSW_F0 (1);
2245     }
2246   else
2247     {
2248       SET_PSW_F0 (0);
2249     }
2250   SET_GPR32 (OP[0], tmp);
2251   trace_output_32 (tmp);
2252 }
2253
2254 /* rachi */
2255 void
2256 OP_4201 ()
2257 {
2258   signed64 tmp;
2259   int shift = SEXT3 (OP[2]);
2260
2261   trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2262   SET_PSW_F1 (PSW_F0);
2263   if (shift >=0)
2264     tmp = SEXT40 (ACC (OP[1])) << shift;
2265   else
2266     tmp = SEXT40 (ACC (OP[1])) >> -shift;
2267   tmp += 0x8000;
2268
2269   if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2270     {
2271       tmp = 0x7fff;
2272       SET_PSW_F0 (1);
2273     }
2274   else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2275     {
2276       tmp = 0x8000;
2277       SET_PSW_F0 (1);
2278     }
2279   else
2280     {
2281       tmp = (tmp >> 16);
2282       SET_PSW_F0 (0);
2283     }
2284   SET_GPR (OP[0], tmp);
2285   trace_output_16 (tmp);
2286 }
2287
2288 /* rep */
2289 void
2290 OP_27000000 ()
2291 {
2292   trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2293   SET_RPT_S (PC + 1);
2294   SET_RPT_E (PC + OP[1]);
2295   SET_RPT_C (GPR (OP[0]));
2296   SET_PSW_RP (1);
2297   if (GPR (OP[0]) == 0)
2298     {
2299       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2300       State.exception = SIGILL;
2301     }
2302   if (OP[1] < 4)
2303     {
2304       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2305       State.exception = SIGILL;
2306     }
2307   trace_output_void ();
2308 }
2309
2310 /* repi */
2311 void
2312 OP_2F000000 ()
2313 {
2314   trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2315   SET_RPT_S (PC + 1);
2316   SET_RPT_E (PC + OP[1]);
2317   SET_RPT_C (OP[0]);
2318   SET_PSW_RP (1);
2319   if (OP[0] == 0)
2320     {
2321       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2322       State.exception = SIGILL;
2323     }
2324   if (OP[1] < 4)
2325     {
2326       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2327       State.exception = SIGILL;
2328     }
2329   trace_output_void ();
2330 }
2331
2332 /* rtd */
2333 void
2334 OP_5F60 ()
2335 {
2336   trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2337   SET_CREG (PSW_CR, DPSW);
2338   JMP(DPC);
2339   trace_output_void ();
2340 }
2341
2342 /* rte */
2343 void
2344 OP_5F40 ()
2345 {
2346   trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2347   SET_CREG (PSW_CR, BPSW);
2348   JMP(BPC);
2349   trace_output_void ();
2350 }
2351
2352 /* sac */
2353 void OP_5209 ()
2354 {
2355   int64 tmp;
2356
2357   trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2358
2359   tmp = SEXT40(ACC (OP[1]));
2360
2361   SET_PSW_F1 (PSW_F0);
2362
2363   if (tmp > SEXT40(MAX32))
2364     {
2365       tmp = (MAX32);
2366       SET_PSW_F0 (1);
2367     }
2368   else if (tmp < SEXT40(MIN32))
2369     {
2370       tmp = 0x80000000;
2371       SET_PSW_F0 (1);
2372     }
2373   else
2374     {
2375       tmp = (tmp & MASK32);
2376       SET_PSW_F0 (0);
2377     }
2378
2379   SET_GPR32 (OP[0], tmp);
2380
2381   trace_output_40 (tmp);
2382 }
2383
2384 /* sachi */
2385 void
2386 OP_4209 ()
2387 {
2388   int64 tmp;
2389
2390   trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2391
2392   tmp = SEXT40(ACC (OP[1]));
2393
2394   SET_PSW_F1 (PSW_F0);
2395
2396   if (tmp > SEXT40(MAX32))
2397     {
2398       tmp = 0x7fff;
2399       SET_PSW_F0 (1);
2400     }
2401   else if (tmp < SEXT40(MIN32))
2402     {
2403       tmp = 0x8000;
2404       SET_PSW_F0 (1);
2405     }
2406   else
2407     {
2408       tmp >>= 16;
2409       SET_PSW_F0 (0);
2410     }
2411
2412   SET_GPR (OP[0], tmp);
2413
2414   trace_output_16 (OP[0]);
2415 }
2416
2417 /* sadd */
2418 void
2419 OP_1223 ()
2420 {
2421   int64 tmp;
2422
2423   trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2424   tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2425   if (PSW_ST)
2426     {
2427       if (tmp > SEXT40(MAX32))
2428         tmp = (MAX32);
2429       else if (tmp < SEXT40(MIN32))
2430         tmp = (MIN32);
2431       else
2432         tmp = (tmp & MASK40);
2433     }
2434   else
2435     tmp = (tmp & MASK40);
2436   SET_ACC (OP[0], tmp);
2437   trace_output_40 (tmp);
2438 }
2439
2440 /* setf0f */
2441 void
2442 OP_4611 ()
2443 {
2444   int16 tmp;
2445   trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2446   tmp = ((PSW_F0 == 0) ? 1 : 0);
2447   SET_GPR (OP[0], tmp);
2448   trace_output_16 (tmp);
2449 }
2450
2451 /* setf0t */
2452 void
2453 OP_4613 ()
2454 {
2455   int16 tmp;
2456   trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2457   tmp = ((PSW_F0 == 1) ? 1 : 0);
2458   SET_GPR (OP[0], tmp);
2459   trace_output_16 (tmp);
2460 }
2461
2462 /* slae */
2463 void
2464 OP_3220 ()
2465 {
2466   int64 tmp;
2467   int16 reg;
2468
2469   trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2470
2471   reg = SEXT16 (GPR (OP[1]));
2472
2473   if (reg >= 17 || reg <= -17)
2474     {
2475       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2476       State.exception = SIGILL;
2477       return;
2478     }
2479
2480   tmp = SEXT40 (ACC (OP[0]));
2481
2482   if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2483     {
2484       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2485       State.exception = SIGILL;
2486       return;
2487     }
2488
2489   if (reg >= 0 && reg <= 16)
2490     {
2491       tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2492       if (PSW_ST)
2493         {
2494           if (tmp > SEXT40(MAX32))
2495             tmp = (MAX32);
2496           else if (tmp < SEXT40(MIN32))
2497             tmp = (MIN32);
2498           else
2499             tmp = (tmp & MASK40);
2500         }
2501       else
2502         tmp = (tmp & MASK40);
2503     }
2504   else
2505     {
2506       tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2507     }
2508
2509   SET_ACC(OP[0], tmp);
2510
2511   trace_output_40(tmp);
2512 }
2513
2514 /* sleep */
2515 void
2516 OP_5FC0 ()
2517 {
2518   trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2519   SET_PSW_IE (1);
2520   trace_output_void ();
2521 }
2522
2523 /* sll */
2524 void
2525 OP_2200 ()
2526 {
2527   int16 tmp;
2528   trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2529   tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2530   SET_GPR (OP[0], tmp);
2531   trace_output_16 (tmp);
2532 }
2533
2534 /* sll */
2535 void
2536 OP_3200 ()
2537 {
2538   int64 tmp;
2539   trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2540   if ((GPR (OP[1]) & 31) <= 16)
2541     tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2542   else
2543     {
2544       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2545       State.exception = SIGILL;
2546       return;
2547     }
2548
2549   if (PSW_ST)
2550     {
2551       if (tmp > SEXT40(MAX32))
2552         tmp = (MAX32);
2553       else if (tmp < SEXT40(MIN32))
2554         tmp = (MIN32);
2555       else
2556         tmp = (tmp & MASK40);
2557     }
2558   else
2559     tmp = (tmp & MASK40);
2560   SET_ACC (OP[0], tmp);
2561   trace_output_40 (tmp);
2562 }
2563
2564 /* slli */
2565 void
2566 OP_2201 ()
2567 {
2568   int16 tmp;
2569   trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2570   tmp = (GPR (OP[0]) << OP[1]);
2571   SET_GPR (OP[0], tmp);
2572   trace_output_16 (tmp);
2573 }
2574
2575 /* slli */
2576 void
2577 OP_3201 ()
2578 {
2579   int64 tmp;
2580
2581   if (OP[1] == 0)
2582     OP[1] = 16;
2583
2584   trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2585   tmp = SEXT40(ACC (OP[0])) << OP[1];
2586
2587   if (PSW_ST)
2588     {
2589       if (tmp > SEXT40(MAX32))
2590         tmp = (MAX32);
2591       else if (tmp < SEXT40(MIN32))
2592         tmp = (MIN32);
2593       else
2594         tmp = (tmp & MASK40);
2595     }
2596   else
2597     tmp = (tmp & MASK40);
2598   SET_ACC (OP[0], tmp);
2599   trace_output_40 (tmp);
2600 }
2601
2602 /* slx */
2603 void
2604 OP_460B ()
2605 {
2606   int16 tmp;
2607   trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2608   tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2609   SET_GPR (OP[0], tmp);
2610   trace_output_16 (tmp);
2611 }
2612
2613 /* sra */
2614 void
2615 OP_2400 ()
2616 {
2617   int16 tmp;
2618   trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2619   tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2620   SET_GPR (OP[0], tmp);
2621   trace_output_16 (tmp);
2622 }
2623
2624 /* sra */
2625 void
2626 OP_3400 ()
2627 {
2628   trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2629   if ((GPR (OP[1]) & 31) <= 16)
2630     {
2631       int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2632       SET_ACC (OP[0], tmp);
2633       trace_output_40 (tmp);
2634     }
2635   else
2636     {
2637       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2638       State.exception = SIGILL;
2639       return;
2640     }
2641 }
2642
2643 /* srai */
2644 void
2645 OP_2401 ()
2646 {
2647   int16 tmp;
2648   trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2649   tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2650   SET_GPR (OP[0], tmp);
2651   trace_output_16 (tmp);
2652 }
2653
2654 /* srai */
2655 void
2656 OP_3401 ()
2657 {
2658   int64 tmp;
2659   if (OP[1] == 0)
2660     OP[1] = 16;
2661
2662   trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2663   tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2664   SET_ACC (OP[0], tmp);
2665   trace_output_40 (tmp);
2666 }
2667
2668 /* srl */
2669 void
2670 OP_2000 ()
2671 {
2672   int16 tmp;
2673   trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2674   tmp = (GPR (OP[0]) >>  (GPR (OP[1]) & 0xf));
2675   SET_GPR (OP[0], tmp);
2676   trace_output_16 (tmp);
2677 }
2678
2679 /* srl */
2680 void
2681 OP_3000 ()
2682 {
2683   trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2684   if ((GPR (OP[1]) & 31) <= 16)
2685     {
2686       int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2687       SET_ACC (OP[0], tmp);
2688       trace_output_40 (tmp);
2689     }
2690   else
2691     {
2692       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2693       State.exception = SIGILL;
2694       return;
2695     }
2696
2697 }
2698
2699 /* srli */
2700 void
2701 OP_2001 ()
2702 {
2703   int16 tmp;
2704   trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2705   tmp = (GPR (OP[0]) >> OP[1]);
2706   SET_GPR (OP[0], tmp);
2707   trace_output_16 (tmp);
2708 }
2709
2710 /* srli */
2711 void
2712 OP_3001 ()
2713 {
2714   int64 tmp;
2715   if (OP[1] == 0)
2716     OP[1] = 16;
2717
2718   trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2719   tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2720   SET_ACC (OP[0], tmp);
2721   trace_output_40 (tmp);
2722 }
2723
2724 /* srx */
2725 void
2726 OP_4609 ()
2727 {
2728   uint16 tmp;
2729   trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2730   tmp = PSW_F0 << 15;
2731   tmp = ((GPR (OP[0]) >> 1) | tmp);
2732   SET_GPR (OP[0], tmp);
2733   trace_output_16 (tmp);
2734 }
2735
2736 /* st */
2737 void
2738 OP_34000000 ()
2739 {
2740   uint16 addr = OP[1] + GPR (OP[2]);
2741   trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2742   if ((addr & 1))
2743     {
2744       address_exception ();
2745       trace_output_void ();
2746       return;
2747     }
2748   SW (addr, GPR (OP[0]));
2749   trace_output_void ();
2750 }
2751
2752 /* st */
2753 void
2754 OP_6800 ()
2755 {
2756   uint16 addr = GPR (OP[1]);
2757   trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2758   if ((addr & 1))
2759     {
2760       address_exception ();
2761       trace_output_void ();
2762       return;
2763     }
2764   SW (addr, GPR (OP[0]));
2765   trace_output_void ();
2766 }
2767
2768 /* st */
2769 /* st Rsrc1,@-SP */
2770 void
2771 OP_6C1F ()
2772 {
2773   uint16 addr = GPR (OP[1]) - 2;
2774   trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2775   if (OP[1] != 15)
2776     {
2777       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2778       State.exception = SIGILL;
2779       return;
2780     }
2781   if ((addr & 1))
2782     {
2783       address_exception ();
2784       trace_output_void ();
2785       return;
2786     }
2787   SW (addr, GPR (OP[0]));
2788   SET_GPR (OP[1], addr);
2789   trace_output_void ();
2790 }
2791
2792 /* st */
2793 void
2794 OP_6801 ()
2795 {
2796   uint16 addr = GPR (OP[1]);
2797   trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2798   if ((addr & 1))
2799     {
2800       address_exception ();
2801       trace_output_void ();
2802       return;
2803     }
2804   SW (addr, GPR (OP[0]));
2805   INC_ADDR (OP[1], 2);
2806   trace_output_void ();
2807 }
2808
2809 /* st */
2810 void
2811 OP_6C01 ()
2812 {
2813   uint16 addr = GPR (OP[1]);
2814   trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2815   if ( OP[1] == 15 )
2816     {
2817       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2818       State.exception = SIGILL;
2819       return;
2820     }
2821   if ((addr & 1))
2822     {
2823       address_exception ();
2824       trace_output_void ();
2825       return;
2826     }
2827   SW (addr, GPR (OP[0]));
2828   INC_ADDR (OP[1], -2);
2829   trace_output_void ();
2830 }
2831
2832 /* st */
2833 void
2834 OP_36010000 ()
2835 {
2836   uint16 addr = OP[1];
2837   trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2838   if ((addr & 1))
2839     {
2840       address_exception ();
2841       trace_output_void ();
2842       return;
2843     }
2844   SW (addr, GPR (OP[0]));
2845   trace_output_void ();
2846 }
2847
2848 /* st2w */
2849 void
2850 OP_35000000 ()
2851 {
2852   uint16 addr = GPR (OP[2])+ OP[1];
2853   trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2854   if ((addr & 1))
2855     {
2856       address_exception ();
2857       trace_output_void ();
2858       return;
2859     }
2860   SW (addr + 0, GPR (OP[0] + 0));
2861   SW (addr + 2, GPR (OP[0] + 1));
2862   trace_output_void ();
2863 }
2864
2865 /* st2w */
2866 void
2867 OP_6A00 ()
2868 {
2869   uint16 addr = GPR (OP[1]);
2870   trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2871   if ((addr & 1))
2872     {
2873       address_exception ();
2874       trace_output_void ();
2875       return;
2876     }
2877   SW (addr + 0, GPR (OP[0] + 0));
2878   SW (addr + 2, GPR (OP[0] + 1));
2879   trace_output_void ();
2880 }
2881
2882 /* st2w */
2883 void
2884 OP_6E1F ()
2885 {
2886   uint16 addr = GPR (OP[1]) - 4;
2887   trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2888   if ( OP[1] != 15 )
2889     {
2890       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2891       State.exception = SIGILL;
2892       return;
2893     }
2894   if ((addr & 1))
2895     {
2896       address_exception ();
2897       trace_output_void ();
2898       return;
2899     }
2900   SW (addr + 0, GPR (OP[0] + 0));
2901   SW (addr + 2, GPR (OP[0] + 1));
2902   SET_GPR (OP[1], addr);
2903   trace_output_void ();
2904 }
2905
2906 /* st2w */
2907 void
2908 OP_6A01 ()
2909 {
2910   uint16 addr = GPR (OP[1]);
2911   trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2912   if ((addr & 1))
2913     {
2914       address_exception ();
2915       trace_output_void ();
2916       return;
2917     }
2918   SW (addr + 0, GPR (OP[0] + 0));
2919   SW (addr + 2, GPR (OP[0] + 1));
2920   INC_ADDR (OP[1], 4);
2921   trace_output_void ();
2922 }
2923
2924 /* st2w */
2925 void
2926 OP_6E01 ()
2927 {
2928   uint16 addr = GPR (OP[1]);
2929   trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2930   if ( OP[1] == 15 )
2931     {
2932       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2933       State.exception = SIGILL;
2934       return;
2935     }
2936   if ((addr & 1))
2937     {
2938       address_exception ();
2939       trace_output_void ();
2940       return;
2941     }
2942   SW (addr + 0, GPR (OP[0] + 0));
2943   SW (addr + 2, GPR (OP[0] + 1));
2944   INC_ADDR (OP[1], -4);
2945   trace_output_void ();
2946 }
2947
2948 /* st2w */
2949 void
2950 OP_37010000 ()
2951 {
2952   uint16 addr = OP[1];
2953   trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2954   if ((addr & 1))
2955     {
2956       address_exception ();
2957       trace_output_void ();
2958       return;
2959     }
2960   SW (addr + 0, GPR (OP[0] + 0));
2961   SW (addr + 2, GPR (OP[0] + 1));
2962   trace_output_void ();
2963 }
2964
2965 /* stb */
2966 void
2967 OP_3C000000 ()
2968 {
2969   trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2970   SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2971   trace_output_void ();
2972 }
2973
2974 /* stb */
2975 void
2976 OP_7800 ()
2977 {
2978   trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2979   SB (GPR (OP[1]), GPR (OP[0]));
2980   trace_output_void ();
2981 }
2982
2983 /* stop */
2984 void
2985 OP_5FE0 ()
2986 {
2987   trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2988   State.exception = SIG_D10V_STOP;
2989   trace_output_void ();
2990 }
2991
2992 /* sub */
2993 void
2994 OP_0 ()
2995 {
2996   uint16 a = GPR (OP[0]);
2997   uint16 b = GPR (OP[1]);
2998   uint16 tmp = (a - b);
2999   trace_input ("sub", OP_REG, OP_REG, OP_VOID);
3000   /* see ../common/sim-alu.h for a more extensive discussion on how to
3001      compute the carry/overflow bits. */
3002   SET_PSW_C (a >= b);
3003   SET_GPR (OP[0], tmp);
3004   trace_output_16 (tmp);
3005 }
3006
3007 /* sub */
3008 void
3009 OP_1001 ()
3010 {
3011   int64 tmp;
3012
3013   trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
3014   tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
3015   if (PSW_ST)
3016     {
3017       if (tmp > SEXT40(MAX32))
3018         tmp = (MAX32);
3019       else if (tmp < SEXT40(MIN32))
3020         tmp = (MIN32);
3021       else
3022         tmp = (tmp & MASK40);
3023     }
3024   else
3025     tmp = (tmp & MASK40);
3026   SET_ACC (OP[0], tmp);
3027
3028   trace_output_40 (tmp);
3029 }
3030
3031 /* sub */
3032
3033 void
3034 OP_1003 ()
3035 {
3036   int64 tmp;
3037
3038   trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
3039   tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
3040   if (PSW_ST)
3041     {
3042       if (tmp > SEXT40(MAX32))
3043         tmp = (MAX32);
3044       else if (tmp < SEXT40(MIN32))
3045         tmp = (MIN32);
3046       else
3047         tmp = (tmp & MASK40);
3048     }
3049   else
3050     tmp = (tmp & MASK40);
3051   SET_ACC (OP[0], tmp);
3052
3053   trace_output_40 (tmp);
3054 }
3055
3056 /* sub2w */
3057 void
3058 OP_1000 ()
3059 {
3060   uint32 tmp, a, b;
3061
3062   trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
3063   a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3064   b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3065   /* see ../common/sim-alu.h for a more extensive discussion on how to
3066      compute the carry/overflow bits */
3067   tmp = a - b;
3068   SET_PSW_C (a >= b);
3069   SET_GPR32 (OP[0], tmp);
3070   trace_output_32 (tmp);
3071 }
3072
3073 /* subac3 */
3074 void
3075 OP_17000000 ()
3076 {
3077   int64 tmp;
3078
3079   trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3080   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3081   SET_GPR32 (OP[0], tmp);
3082   trace_output_32 (tmp);
3083 }
3084
3085 /* subac3 */
3086 void
3087 OP_17000002 ()
3088 {
3089   int64 tmp;
3090
3091   trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3092   tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
3093   SET_GPR32 (OP[0], tmp);
3094   trace_output_32 (tmp);
3095 }
3096
3097 /* subac3s */
3098 void
3099 OP_17001000 ()
3100 {
3101   int64 tmp;
3102
3103   trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3104   SET_PSW_F1 (PSW_F0);
3105   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3106   if (tmp > SEXT40(MAX32))
3107     {
3108       tmp = (MAX32);
3109       SET_PSW_F0 (1);
3110     }
3111   else if (tmp < SEXT40(MIN32))
3112     {
3113       tmp = (MIN32);
3114       SET_PSW_F0 (1);
3115     }
3116   else
3117     {
3118       SET_PSW_F0 (0);
3119     }
3120   SET_GPR32 (OP[0], tmp);
3121   trace_output_32 (tmp);
3122 }
3123
3124 /* subac3s */
3125 void
3126 OP_17001002 ()
3127 {
3128   int64 tmp;
3129
3130   trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3131   SET_PSW_F1 (PSW_F0);
3132   tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
3133   if (tmp > SEXT40(MAX32))
3134     {
3135       tmp = (MAX32);
3136       SET_PSW_F0 (1);
3137     }
3138   else if (tmp < SEXT40(MIN32))
3139     {
3140       tmp = (MIN32);
3141       SET_PSW_F0 (1);
3142     }
3143   else
3144     {
3145       SET_PSW_F0 (0);
3146     }
3147   SET_GPR32 (OP[0], tmp);
3148   trace_output_32 (tmp);
3149 }
3150
3151 /* subi */
3152 void
3153 OP_1 ()
3154 {
3155   unsigned tmp;
3156   if (OP[1] == 0)
3157     OP[1] = 16;
3158
3159   trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3160   /* see ../common/sim-alu.h for a more extensive discussion on how to
3161      compute the carry/overflow bits. */
3162   /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3163   tmp = ((unsigned)(unsigned16) GPR (OP[0])
3164          + (unsigned)(unsigned16) ( - OP[1]));
3165   SET_PSW_C (tmp >= (1 << 16));
3166   SET_GPR (OP[0], tmp);
3167   trace_output_16 (tmp);
3168 }
3169
3170 /* trap */
3171 void
3172 OP_5F00 ()
3173 {
3174   trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3175   trace_output_void ();
3176
3177   switch (OP[0])
3178     {
3179     default:
3180 #if (DEBUG & DEBUG_TRAP) == 0
3181       {
3182         uint16 vec = OP[0] + TRAP_VECTOR_START;
3183         SET_BPC (PC + 1);
3184         SET_BPSW (PSW);
3185         SET_PSW (PSW & PSW_SM_BIT);
3186         JMP (vec);
3187         break;
3188       }
3189 #else                   /* if debugging use trap to print registers */
3190       {
3191         int i;
3192         static int first_time = 1;
3193
3194         if (first_time)
3195           {
3196             first_time = 0;
3197             (*d10v_callback->printf_filtered) (d10v_callback, "Trap  #     PC ");
3198             for (i = 0; i < 16; i++)
3199               (*d10v_callback->printf_filtered) (d10v_callback, "  %sr%d", (i > 9) ? "" : " ", i);
3200             (*d10v_callback->printf_filtered) (d10v_callback, "         a0         a1 f0 f1 c\n");
3201           }
3202
3203         (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3204
3205         for (i = 0; i < 16; i++)
3206           (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3207
3208         for (i = 0; i < 2; i++)
3209           (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3210                                              ((int)(ACC (i) >> 32) & 0xff),
3211                                              ((unsigned long) ACC (i)) & 0xffffffff);
3212
3213         (*d10v_callback->printf_filtered) (d10v_callback, "  %d  %d %d\n",
3214                                            PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3215         (*d10v_callback->flush_stdout) (d10v_callback);
3216         break;
3217       }
3218 #endif
3219     case 15:                    /* new system call trap */
3220       /* Trap 15 is used for simulating low-level I/O */
3221       {
3222         unsigned32 result = 0;
3223         errno = 0;
3224
3225 /* Registers passed to trap 0 */
3226
3227 #define FUNC   GPR (4)  /* function number */
3228 #define PARM1  GPR (0)  /* optional parm 1 */
3229 #define PARM2  GPR (1)  /* optional parm 2 */
3230 #define PARM3  GPR (2)  /* optional parm 3 */
3231 #define PARM4  GPR (3)  /* optional parm 3 */
3232
3233 /* Registers set by trap 0 */
3234
3235 #define RETVAL(X)   do { result = (X); SET_GPR (0, result); } while (0)
3236 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3237 #define RETERR(X) SET_GPR (4, (X))              /* return error code */
3238
3239 /* Turn a pointer in a register into a pointer into real memory. */
3240
3241 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3242
3243         switch (FUNC)
3244           {
3245 #if !defined(__GO32__) && !defined(_WIN32)
3246           case TARGET_SYS_fork:
3247             trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3248             RETVAL (fork ());
3249             trace_output_16 (result);
3250             break;
3251
3252 #define getpid() 47
3253           case TARGET_SYS_getpid:
3254             trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3255             RETVAL (getpid ());
3256             trace_output_16 (result);
3257             break;
3258
3259           case TARGET_SYS_kill:
3260             trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3261             if (PARM1 == getpid ())
3262               {
3263                 trace_output_void ();
3264                 State.exception = PARM2;
3265               }
3266             else
3267               {
3268                 int os_sig = -1;
3269                 switch (PARM2)
3270                   {
3271 #ifdef SIGHUP
3272                   case 1: os_sig = SIGHUP;      break;
3273 #endif
3274 #ifdef SIGINT
3275                   case 2: os_sig = SIGINT;      break;
3276 #endif
3277 #ifdef SIGQUIT
3278                   case 3: os_sig = SIGQUIT;     break;
3279 #endif
3280 #ifdef SIGILL
3281                   case 4: os_sig = SIGILL;      break;
3282 #endif
3283 #ifdef SIGTRAP
3284                   case 5: os_sig = SIGTRAP;     break;
3285 #endif
3286 #ifdef SIGABRT
3287                   case 6: os_sig = SIGABRT;     break;
3288 #elif defined(SIGIOT)
3289                   case 6: os_sig = SIGIOT;      break;
3290 #endif
3291 #ifdef SIGEMT
3292                   case 7: os_sig = SIGEMT;      break;
3293 #endif
3294 #ifdef SIGFPE
3295                   case 8: os_sig = SIGFPE;      break;
3296 #endif
3297 #ifdef SIGKILL
3298                   case 9: os_sig = SIGKILL;     break;
3299 #endif
3300 #ifdef SIGBUS
3301                   case 10: os_sig = SIGBUS;     break;
3302 #endif
3303 #ifdef SIGSEGV
3304                   case 11: os_sig = SIGSEGV;    break;
3305 #endif
3306 #ifdef SIGSYS
3307                   case 12: os_sig = SIGSYS;     break;
3308 #endif
3309 #ifdef SIGPIPE
3310                   case 13: os_sig = SIGPIPE;    break;
3311 #endif
3312 #ifdef SIGALRM
3313                   case 14: os_sig = SIGALRM;    break;
3314 #endif
3315 #ifdef SIGTERM
3316                   case 15: os_sig = SIGTERM;    break;
3317 #endif
3318 #ifdef SIGURG
3319                   case 16: os_sig = SIGURG;     break;
3320 #endif
3321 #ifdef SIGSTOP
3322                   case 17: os_sig = SIGSTOP;    break;
3323 #endif
3324 #ifdef SIGTSTP
3325                   case 18: os_sig = SIGTSTP;    break;
3326 #endif
3327 #ifdef SIGCONT
3328                   case 19: os_sig = SIGCONT;    break;
3329 #endif
3330 #ifdef SIGCHLD
3331                   case 20: os_sig = SIGCHLD;    break;
3332 #elif defined(SIGCLD)
3333                   case 20: os_sig = SIGCLD;     break;
3334 #endif
3335 #ifdef SIGTTIN
3336                   case 21: os_sig = SIGTTIN;    break;
3337 #endif
3338 #ifdef SIGTTOU
3339                   case 22: os_sig = SIGTTOU;    break;
3340 #endif
3341 #ifdef SIGIO
3342                   case 23: os_sig = SIGIO;      break;
3343 #elif defined (SIGPOLL)
3344                   case 23: os_sig = SIGPOLL;    break;
3345 #endif
3346 #ifdef SIGXCPU
3347                   case 24: os_sig = SIGXCPU;    break;
3348 #endif
3349 #ifdef SIGXFSZ
3350                   case 25: os_sig = SIGXFSZ;    break;
3351 #endif
3352 #ifdef SIGVTALRM
3353                   case 26: os_sig = SIGVTALRM;  break;
3354 #endif
3355 #ifdef SIGPROF
3356                   case 27: os_sig = SIGPROF;    break;
3357 #endif
3358 #ifdef SIGWINCH
3359                   case 28: os_sig = SIGWINCH;   break;
3360 #endif
3361 #ifdef SIGLOST
3362                   case 29: os_sig = SIGLOST;    break;
3363 #endif
3364 #ifdef SIGUSR1
3365                   case 30: os_sig = SIGUSR1;    break;
3366 #endif
3367 #ifdef SIGUSR2
3368                   case 31: os_sig = SIGUSR2;    break;
3369 #endif
3370                   }
3371
3372                 if (os_sig == -1)
3373                   {
3374                     trace_output_void ();
3375                     (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3376                     (*d10v_callback->flush_stdout) (d10v_callback);
3377                     State.exception = SIGILL;
3378                   }
3379                 else
3380                   {
3381                     RETVAL (kill (PARM1, PARM2));
3382                     trace_output_16 (result);
3383                   }
3384               }
3385             break;
3386
3387           case TARGET_SYS_execve:
3388             trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3389             RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3390                              (char **)MEMPTR (PARM3)));
3391             trace_output_16 (result);
3392             break;
3393
3394 #ifdef TARGET_SYS_execv
3395           case TARGET_SYS_execv:
3396             trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3397             RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3398             trace_output_16 (result);
3399             break;
3400 #endif
3401
3402           case TARGET_SYS_pipe:
3403             {
3404               reg_t buf;
3405               int host_fd[2];
3406
3407               trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3408               buf = PARM1;
3409               RETVAL (pipe (host_fd));
3410               SW (buf, host_fd[0]);
3411               buf += sizeof(uint16);
3412               SW (buf, host_fd[1]);
3413               trace_output_16 (result);
3414             }
3415           break;
3416
3417 #if 0
3418 #ifdef TARGET_SYS_wait
3419           case TARGET_SYS_wait:
3420             {
3421               int status;
3422               trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3423               RETVAL (wait (&status));
3424               if (PARM1)
3425                 SW (PARM1, status);
3426               trace_output_16 (result);
3427             }
3428           break;
3429 #endif
3430 #endif
3431 #else
3432           case TARGET_SYS_getpid:
3433             trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3434             RETVAL (1);
3435             trace_output_16 (result);
3436             break;
3437
3438           case TARGET_SYS_kill:
3439             trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3440             trace_output_void ();
3441             State.exception = PARM2;
3442             break;
3443 #endif
3444
3445           case TARGET_SYS_read:
3446             trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3447             RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3448                                           PARM3));
3449             trace_output_16 (result);
3450             break;
3451
3452           case TARGET_SYS_write:
3453             trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3454             if (PARM1 == 1)
3455               RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3456                                                          MEMPTR (PARM2), PARM3));
3457             else
3458               RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3459                                                   MEMPTR (PARM2), PARM3));
3460             trace_output_16 (result);
3461             break;
3462
3463           case TARGET_SYS_lseek:
3464             trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3465             RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3466                                             ((((unsigned long) PARM2) << 16)
3467                                              || (unsigned long) PARM3),
3468                                             PARM4));
3469             trace_output_32 (result);
3470             break;
3471
3472           case TARGET_SYS_close:
3473             trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3474             RETVAL (d10v_callback->close (d10v_callback, PARM1));
3475             trace_output_16 (result);
3476             break;
3477
3478           case TARGET_SYS_open:
3479             trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3480             RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3481             trace_output_16 (result);
3482             break;
3483
3484           case TARGET_SYS_exit:
3485             trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3486             State.exception = SIG_D10V_EXIT;
3487             trace_output_void ();
3488             break;
3489
3490 #ifdef TARGET_SYS_stat
3491           case TARGET_SYS_stat:
3492             trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3493             /* stat system call */
3494             {
3495               struct stat host_stat;
3496               reg_t buf;
3497
3498               RETVAL (stat (MEMPTR (PARM1), &host_stat));
3499
3500               buf = PARM2;
3501
3502               /* The hard-coded offsets and sizes were determined by using
3503                * the D10V compiler on a test program that used struct stat.
3504                */
3505               SW  (buf,    host_stat.st_dev);
3506               SW  (buf+2,  host_stat.st_ino);
3507               SW  (buf+4,  host_stat.st_mode);
3508               SW  (buf+6,  host_stat.st_nlink);
3509               SW  (buf+8,  host_stat.st_uid);
3510               SW  (buf+10, host_stat.st_gid);
3511               SW  (buf+12, host_stat.st_rdev);
3512               SLW (buf+16, host_stat.st_size);
3513               SLW (buf+20, host_stat.st_atime);
3514               SLW (buf+28, host_stat.st_mtime);
3515               SLW (buf+36, host_stat.st_ctime);
3516             }
3517             trace_output_16 (result);
3518             break;
3519 #endif
3520
3521           case TARGET_SYS_chown:
3522             trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3523             RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3524             trace_output_16 (result);
3525             break;
3526
3527           case TARGET_SYS_chmod:
3528             trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3529             RETVAL (chmod (MEMPTR (PARM1), PARM2));
3530             trace_output_16 (result);
3531             break;
3532
3533 #if 0
3534 #ifdef TARGET_SYS_utime
3535           case TARGET_SYS_utime:
3536             trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3537             /* Cast the second argument to void *, to avoid type mismatch
3538                if a prototype is present.  */
3539             RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3540             trace_output_16 (result);
3541             break;
3542 #endif
3543 #endif
3544
3545 #if 0
3546 #ifdef TARGET_SYS_time
3547           case TARGET_SYS_time:
3548             trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3549             RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3550             trace_output_32 (result);
3551             break;
3552 #endif
3553 #endif
3554
3555           default:
3556             d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3557           }
3558         if ((uint16) result == (uint16) -1)
3559           RETERR (d10v_callback->get_errno(d10v_callback));
3560         else
3561           RETERR (0);
3562         break;
3563       }
3564     }
3565 }
3566
3567 /* tst0i */
3568 void
3569 OP_7000000 ()
3570 {
3571   trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3572   SET_PSW_F1 (PSW_F0);;
3573   SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3574   trace_output_flag ();
3575 }
3576
3577 /* tst1i */
3578 void
3579 OP_F000000 ()
3580 {
3581   trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3582   SET_PSW_F1 (PSW_F0);
3583   SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3584   trace_output_flag ();
3585 }
3586
3587 /* wait */
3588 void
3589 OP_5F80 ()
3590 {
3591   trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3592   SET_PSW_IE (1);
3593   trace_output_void ();
3594 }
3595
3596 /* xor */
3597 void
3598 OP_A00 ()
3599 {
3600   int16 tmp;
3601   trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3602   tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3603   SET_GPR (OP[0], tmp);
3604   trace_output_16 (tmp);
3605 }
3606
3607 /* xor3 */
3608 void
3609 OP_5000000 ()
3610 {
3611   int16 tmp;
3612   trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3613   tmp = (GPR (OP[1]) ^ OP[2]);
3614   SET_GPR (OP[0], tmp);
3615   trace_output_16 (tmp);
3616 }