sim/d10v/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #include <errno.h>
   5 #include <sys/types.h>
   6 #include <sys/stat.h>
   7 #ifdef HAVE_UNISTD_H
   8 #include <unistd.h>
   9 #endif
  10 #ifdef HAVE_STRING_H
  11 #include <string.h>
  12 #endif
  13
  14 #include "sim-main.h"
  15 #include "simops.h"
  16 #include "targ-vals.h"
  17
  18 enum op_types {
  19   OP_VOID,
  20   OP_REG,
  21   OP_REG_OUTPUT,
  22   OP_DREG,
  23   OP_DREG_OUTPUT,
  24   OP_ACCUM,
  25   OP_ACCUM_OUTPUT,
  26   OP_ACCUM_REVERSE,
  27   OP_CR,
  28   OP_CR_OUTPUT,
  29   OP_CR_REVERSE,
  30   OP_FLAG,
  31   OP_FLAG_OUTPUT,
  32   OP_CONSTANT16,
  33   OP_CONSTANT8,
  34   OP_CONSTANT3,
  35   OP_CONSTANT4,
  36   OP_MEMREF,
  37   OP_MEMREF2,
  38   OP_MEMREF3,
  39   OP_POSTDEC,
  40   OP_POSTINC,
  41   OP_PREDEC,
  42   OP_R0,
  43   OP_R1,
  44   OP_R2,
  45 };
  46
  47
  48 enum {
  49   PSW_MASK = (PSW_SM_BIT
  50               | PSW_EA_BIT
  51               | PSW_DB_BIT
  52               | PSW_IE_BIT
  53               | PSW_RP_BIT
  54               | PSW_MD_BIT
  55               | PSW_FX_BIT
  56               | PSW_ST_BIT
  57               | PSW_F0_BIT
  58               | PSW_F1_BIT
  59               | PSW_C_BIT),
  60   /* The following bits in the PSW _can't_ be set by instructions such
  61      as mvtc. */
  62   PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
  63 };
  64
  65 reg_t
  66 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
  67 {
  68   /* A MASK bit is set when the corresponding bit in the CR should
  69      be left alone */
  70   /* This assumes that (VAL & MASK) == 0 */
  71   switch (cr)
  72     {
  73     case PSW_CR:
  74       if (psw_hw_p)
  75         val &= PSW_HW_MASK;
  76       else
  77         val &= PSW_MASK;
  78       if ((mask & PSW_SM_BIT) == 0)
  79         {
  80           int new_psw_sm = (val & PSW_SM_BIT) != 0;
  81           /* save old SP */
  82           SET_HELD_SP (PSW_SM, GPR (SP_IDX));
  83           if (PSW_SM != new_psw_sm)
  84             /* restore new SP */
  85             SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
  86         }
  87       if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
  88         {
  89           if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
  90             {
  91               (*d10v_callback->printf_filtered)
  92                 (d10v_callback,
  93                  "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
  94                  PC<<2);
  95               State.exception = SIGILL;
  96             }
  97         }
  98       /* keep an up-to-date psw around for tracing */
  99       State.trace.psw = (State.trace.psw & mask) | val;
 100       break;
 101     case BPSW_CR:
 102     case DPSW_CR:
 103       /* Just like PSW, mask things like DM out. */
 104       if (psw_hw_p)
 105         val &= PSW_HW_MASK;
 106       else
 107         val &= PSW_MASK;
 108       break;
 109     case MOD_S_CR:
 110     case MOD_E_CR:
 111       val &= ~1;
 112       break;
 113     default:
 114       break;
 115     }
 116   /* only issue an update if the register is being changed */
 117   if ((State.cregs[cr] & ~mask) != val)
 118     SLOT_PEND_MASK (State.cregs[cr], mask, val);
 119   return val;
 120 }
 121
 122 #ifdef DEBUG
 123 static void trace_input_func (const char *name,
 124                               enum op_types in1,
 125                               enum op_types in2,
 126                               enum op_types in3);
 127
 128 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
 129
 130 #ifndef SIZE_INSTRUCTION
 131 #define SIZE_INSTRUCTION 8
 132 #endif
 133
 134 #ifndef SIZE_OPERANDS
 135 #define SIZE_OPERANDS 18
 136 #endif
 137
 138 #ifndef SIZE_VALUES
 139 #define SIZE_VALUES 13
 140 #endif
 141
 142 #ifndef SIZE_LOCATION
 143 #define SIZE_LOCATION 20
 144 #endif
 145
 146 #ifndef SIZE_PC
 147 #define SIZE_PC 6
 148 #endif
 149
 150 #ifndef SIZE_LINE_NUMBER
 151 #define SIZE_LINE_NUMBER 4
 152 #endif
 153
 154 static void
 155 trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
 156 {
 157   char *comma;
 158   enum op_types in[3];
 159   int i;
 160   char buf[1024];
 161   char *p;
 162   long tmp;
 163   char *type;
 164   const char *filename;
 165   const char *functionname;
 166   unsigned int linenumber;
 167   bfd_vma byte_pc;
 168
 169   if ((d10v_debug & DEBUG_TRACE) == 0)
 170     return;
 171
 172   switch (State.ins_type)
 173     {
 174     default:
 175     case INS_UNKNOWN:           type = " ?"; break;
 176     case INS_LEFT:              type = " L"; break;
 177     case INS_RIGHT:             type = " R"; break;
 178     case INS_LEFT_PARALLEL:     type = "*L"; break;
 179     case INS_RIGHT_PARALLEL:    type = "*R"; break;
 180     case INS_LEFT_COND_TEST:    type = "?L"; break;
 181     case INS_RIGHT_COND_TEST:   type = "?R"; break;
 182     case INS_LEFT_COND_EXE:     type = "&L"; break;
 183     case INS_RIGHT_COND_EXE:    type = "&R"; break;
 184     case INS_LONG:              type = " B"; break;
 185     }
 186
 187   if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
 188     (*d10v_callback->printf_filtered) (d10v_callback,
 189                                        "0x%.*x %s: %-*s ",
 190                                        SIZE_PC, (unsigned)PC,
 191                                        type,
 192                                        SIZE_INSTRUCTION, name);
 193
 194   else
 195     {
 196       extern SIM_DESC trace_sd;
 197
 198       buf[0] = '\0';
 199       byte_pc = PC;
 200       if (STATE_TEXT_SECTION (trace_sd)
 201           && byte_pc >= STATE_TEXT_START (trace_sd)
 202           && byte_pc < STATE_TEXT_END (trace_sd))
 203         {
 204           filename = (const char *)0;
 205           functionname = (const char *)0;
 206           linenumber = 0;
 207           if (bfd_find_nearest_line (STATE_PROG_BFD (trace_sd),
 208                                      STATE_TEXT_SECTION (trace_sd),
 209                                      (struct bfd_symbol **)0,
 210                                      byte_pc - STATE_TEXT_START (trace_sd),
 211                                      &filename, &functionname, &linenumber))
 212             {
 213               p = buf;
 214               if (linenumber)
 215                 {
 216                   sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
 217                   p += strlen (p);
 218                 }
 219               else
 220                 {
 221                   sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
 222                   p += SIZE_LINE_NUMBER+2;
 223                 }
 224
 225               if (functionname)
 226                 {
 227                   sprintf (p, "%s ", functionname);
 228                   p += strlen (p);
 229                 }
 230               else if (filename)
 231                 {
 232                   char *q = strrchr (filename, '/');
 233                   sprintf (p, "%s ", (q) ? q+1 : filename);
 234                   p += strlen (p);
 235                 }
 236
 237               if (*p == ' ')
 238                 *p = '\0';
 239             }
 240         }
 241
 242       (*d10v_callback->printf_filtered) (d10v_callback,
 243                                          "0x%.*x %s: %-*.*s %-*s ",
 244                                          SIZE_PC, (unsigned)PC,
 245                                          type,
 246                                          SIZE_LOCATION, SIZE_LOCATION, buf,
 247                                          SIZE_INSTRUCTION, name);
 248     }
 249
 250   in[0] = in1;
 251   in[1] = in2;
 252   in[2] = in3;
 253   comma = "";
 254   p = buf;
 255   for (i = 0; i < 3; i++)
 256     {
 257       switch (in[i])
 258         {
 259         case OP_VOID:
 260         case OP_R0:
 261         case OP_R1:
 262         case OP_R2:
 263           break;
 264
 265         case OP_REG:
 266         case OP_REG_OUTPUT:
 267         case OP_DREG:
 268         case OP_DREG_OUTPUT:
 269           sprintf (p, "%sr%d", comma, OP[i]);
 270           p += strlen (p);
 271           comma = ",";
 272           break;
 273
 274         case OP_CR:
 275         case OP_CR_OUTPUT:
 276         case OP_CR_REVERSE:
 277           sprintf (p, "%scr%d", comma, OP[i]);
 278           p += strlen (p);
 279           comma = ",";
 280           break;
 281
 282         case OP_ACCUM:
 283         case OP_ACCUM_OUTPUT:
 284         case OP_ACCUM_REVERSE:
 285           sprintf (p, "%sa%d", comma, OP[i]);
 286           p += strlen (p);
 287           comma = ",";
 288           break;
 289
 290         case OP_CONSTANT16:
 291           sprintf (p, "%s%d", comma, OP[i]);
 292           p += strlen (p);
 293           comma = ",";
 294           break;
 295
 296         case OP_CONSTANT8:
 297           sprintf (p, "%s%d", comma, SEXT8(OP[i]));
 298           p += strlen (p);
 299           comma = ",";
 300           break;
 301
 302         case OP_CONSTANT4:
 303           sprintf (p, "%s%d", comma, SEXT4(OP[i]));
 304           p += strlen (p);
 305           comma = ",";
 306           break;
 307
 308         case OP_CONSTANT3:
 309           sprintf (p, "%s%d", comma, SEXT3(OP[i]));
 310           p += strlen (p);
 311           comma = ",";
 312           break;
 313
 314         case OP_MEMREF:
 315           sprintf (p, "%s@r%d", comma, OP[i]);
 316           p += strlen (p);
 317           comma = ",";
 318           break;
 319
 320         case OP_MEMREF2:
 321           sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
 322           p += strlen (p);
 323           comma = ",";
 324           break;
 325
 326         case OP_MEMREF3:
 327           sprintf (p, "%s@%d", comma, OP[i]);
 328           p += strlen (p);
 329           comma = ",";
 330           break;
 331
 332         case OP_POSTINC:
 333           sprintf (p, "%s@r%d+", comma, OP[i]);
 334           p += strlen (p);
 335           comma = ",";
 336           break;
 337
 338         case OP_POSTDEC:
 339           sprintf (p, "%s@r%d-", comma, OP[i]);
 340           p += strlen (p);
 341           comma = ",";
 342           break;
 343
 344         case OP_PREDEC:
 345           sprintf (p, "%s@-r%d", comma, OP[i]);
 346           p += strlen (p);
 347           comma = ",";
 348           break;
 349
 350         case OP_FLAG:
 351         case OP_FLAG_OUTPUT:
 352           if (OP[i] == 0)
 353             sprintf (p, "%sf0", comma);
 354
 355           else if (OP[i] == 1)
 356             sprintf (p, "%sf1", comma);
 357
 358           else
 359             sprintf (p, "%sc", comma);
 360
 361           p += strlen (p);
 362           comma = ",";
 363           break;
 364         }
 365     }
 366
 367   if ((d10v_debug & DEBUG_VALUES) == 0)
 368     {
 369       *p++ = '\n';
 370       *p = '\0';
 371       (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
 372     }
 373   else
 374     {
 375       *p = '\0';
 376       (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
 377
 378       p = buf;
 379       for (i = 0; i < 3; i++)
 380         {
 381           buf[0] = '\0';
 382           switch (in[i])
 383             {
 384             case OP_VOID:
 385               (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
 386               break;
 387
 388             case OP_REG_OUTPUT:
 389             case OP_DREG_OUTPUT:
 390             case OP_CR_OUTPUT:
 391             case OP_ACCUM_OUTPUT:
 392             case OP_FLAG_OUTPUT:
 393               (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
 394               break;
 395
 396             case OP_REG:
 397             case OP_MEMREF:
 398             case OP_POSTDEC:
 399             case OP_POSTINC:
 400             case OP_PREDEC:
 401               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 402                                                  (uint16) GPR (OP[i]));
 403               break;
 404
 405             case OP_MEMREF3:
 406               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
 407               break;
 408
 409             case OP_DREG:
 410               tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
 411               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
 412               break;
 413
 414             case OP_CR:
 415             case OP_CR_REVERSE:
 416               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 417                                                  (uint16) CREG (OP[i]));
 418               break;
 419
 420             case OP_ACCUM:
 421             case OP_ACCUM_REVERSE:
 422               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
 423                                                  ((int)(ACC (OP[i]) >> 32) & 0xff),
 424                                                  ((unsigned long) ACC (OP[i])) & 0xffffffff);
 425               break;
 426
 427             case OP_CONSTANT16:
 428               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 429                                                  (uint16)OP[i]);
 430               break;
 431
 432             case OP_CONSTANT4:
 433               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 434                                                  (uint16)SEXT4(OP[i]));
 435               break;
 436
 437             case OP_CONSTANT8:
 438               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 439                                                  (uint16)SEXT8(OP[i]));
 440               break;
 441
 442             case OP_CONSTANT3:
 443               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 444                                                  (uint16)SEXT3(OP[i]));
 445               break;
 446
 447             case OP_FLAG:
 448               if (OP[i] == 0)
 449                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
 450                                                    PSW_F0 != 0);
 451
 452               else if (OP[i] == 1)
 453                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
 454                                                    PSW_F1 != 0);
 455
 456               else
 457                 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
 458                                                    PSW_C != 0);
 459
 460               break;
 461
 462             case OP_MEMREF2:
 463               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 464                                                  (uint16)OP[i]);
 465               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 466                                                  (uint16)GPR (OP[i + 1]));
 467               i++;
 468               break;
 469
 470             case OP_R0:
 471               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 472                                                  (uint16) GPR (0));
 473               break;
 474
 475             case OP_R1:
 476               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 477                                                  (uint16) GPR (1));
 478               break;
 479
 480             case OP_R2:
 481               (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
 482                                                  (uint16) GPR (2));
 483               break;
 484
 485             }
 486         }
 487     }
 488
 489   (*d10v_callback->flush_stdout) (d10v_callback);
 490 }
 491
 492 static void
 493 do_trace_output_flush (void)
 494 {
 495   (*d10v_callback->flush_stdout) (d10v_callback);
 496 }
 497
 498 static void
 499 do_trace_output_finish (void)
 500 {
 501   (*d10v_callback->printf_filtered) (d10v_callback,
 502                                      " F0=%d F1=%d C=%d\n",
 503                                      (State.trace.psw & PSW_F0_BIT) != 0,
 504                                      (State.trace.psw & PSW_F1_BIT) != 0,
 505                                      (State.trace.psw & PSW_C_BIT) != 0);
 506   (*d10v_callback->flush_stdout) (d10v_callback);
 507 }
 508
 509 static void
 510 trace_output_40 (uint64 val)
 511 {
 512   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 513     {
 514       (*d10v_callback->printf_filtered) (d10v_callback,
 515                                          " :: %*s0x%.2x%.8lx",
 516                                          SIZE_VALUES - 12,
 517                                          "",
 518                                          ((int)(val >> 32) & 0xff),
 519                                          ((unsigned long) val) & 0xffffffff);
 520       do_trace_output_finish ();
 521     }
 522 }
 523
 524 static void
 525 trace_output_32 (uint32 val)
 526 {
 527   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 528     {
 529       (*d10v_callback->printf_filtered) (d10v_callback,
 530                                          " :: %*s0x%.8x",
 531                                          SIZE_VALUES - 10,
 532                                          "",
 533                                          (int) val);
 534       do_trace_output_finish ();
 535     }
 536 }
 537
 538 static void
 539 trace_output_16 (uint16 val)
 540 {
 541   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 542     {
 543       (*d10v_callback->printf_filtered) (d10v_callback,
 544                                          " :: %*s0x%.4x",
 545                                          SIZE_VALUES - 6,
 546                                          "",
 547                                          (int) val);
 548       do_trace_output_finish ();
 549     }
 550 }
 551
 552 static void
 553 trace_output_void (void)
 554 {
 555   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 556     {
 557       (*d10v_callback->printf_filtered) (d10v_callback, "\n");
 558       do_trace_output_flush ();
 559     }
 560 }
 561
 562 static void
 563 trace_output_flag (void)
 564 {
 565   if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
 566     {
 567       (*d10v_callback->printf_filtered) (d10v_callback,
 568                                          " :: %*s",
 569                                          SIZE_VALUES,
 570                                          "");
 571       do_trace_output_finish ();
 572     }
 573 }
 574
 575
 576
 577
 578 #else
 579 #define trace_input(NAME, IN1, IN2, IN3)
 580 #define trace_output(RESULT)
 581 #endif
 582
 583 /* abs */
 584 void
 585 OP_4607 (void)
 586 {
 587   int16 tmp;
 588   trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
 589   SET_PSW_F1 (PSW_F0);
 590   tmp = GPR(OP[0]);
 591   if (tmp < 0)
 592     {
 593       tmp = - tmp;
 594       SET_PSW_F0 (1);
 595     }
 596   else
 597     SET_PSW_F0 (0);
 598   SET_GPR (OP[0], tmp);
 599   trace_output_16 (tmp);
 600 }
 601
 602 /* abs */
 603 void
 604 OP_5607 (void)
 605 {
 606   int64 tmp;
 607   trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
 608   SET_PSW_F1 (PSW_F0);
 609
 610   tmp = SEXT40 (ACC (OP[0]));
 611   if (tmp < 0 )
 612     {
 613       tmp = - tmp;
 614       if (PSW_ST)
 615         {
 616           if (tmp > SEXT40(MAX32))
 617             tmp = (MAX32);
 618           else if (tmp < SEXT40(MIN32))
 619             tmp = (MIN32);
 620           else
 621             tmp = (tmp & MASK40);
 622         }
 623       else
 624         tmp = (tmp & MASK40);
 625       SET_PSW_F0 (1);
 626     }
 627   else
 628     {
 629       tmp = (tmp & MASK40);
 630       SET_PSW_F0 (0);
 631     }
 632   SET_ACC (OP[0], tmp);
 633   trace_output_40 (tmp);
 634 }
 635
 636 /* add */
 637 void
 638 OP_200 (void)
 639 {
 640   uint16 a = GPR (OP[0]);
 641   uint16 b = GPR (OP[1]);
 642   uint16 tmp = (a + b);
 643   trace_input ("add", OP_REG, OP_REG, OP_VOID);
 644   SET_PSW_C (a > tmp);
 645   SET_GPR (OP[0], tmp);
 646   trace_output_16 (tmp);
 647 }
 648
 649 /* add */
 650 void
 651 OP_1201 (void)
 652 {
 653   int64 tmp;
 654   tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
 655
 656   trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
 657   if (PSW_ST)
 658     {
 659       if (tmp > SEXT40(MAX32))
 660         tmp = (MAX32);
 661       else if (tmp < SEXT40(MIN32))
 662         tmp = (MIN32);
 663       else
 664         tmp = (tmp & MASK40);
 665     }
 666   else
 667     tmp = (tmp & MASK40);
 668   SET_ACC (OP[0], tmp);
 669   trace_output_40 (tmp);
 670 }
 671
 672 /* add */
 673 void
 674 OP_1203 (void)
 675 {
 676   int64 tmp;
 677   tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
 678
 679   trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
 680   if (PSW_ST)
 681     {
 682       if (tmp > SEXT40(MAX32))
 683         tmp = (MAX32);
 684       else if (tmp < SEXT40(MIN32))
 685         tmp = (MIN32);
 686       else
 687         tmp = (tmp & MASK40);
 688     }
 689   else
 690     tmp = (tmp & MASK40);
 691   SET_ACC (OP[0], tmp);
 692   trace_output_40 (tmp);
 693 }
 694
 695 /* add2w */
 696 void
 697 OP_1200 (void)
 698 {
 699   uint32 tmp;
 700   uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
 701   uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
 702   trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
 703   tmp = a + b;
 704   SET_PSW_C (tmp < a);
 705   SET_GPR (OP[0] + 0, (tmp >> 16));
 706   SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
 707   trace_output_32 (tmp);
 708 }
 709
 710 /* add3 */
 711 void
 712 OP_1000000 (void)
 713 {
 714   uint16 a = GPR (OP[1]);
 715   uint16 b = OP[2];
 716   uint16 tmp = (a + b);
 717   trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
 718   SET_PSW_C (tmp < a);
 719   SET_GPR (OP[0], tmp);
 720   trace_output_16 (tmp);
 721 }
 722
 723 /* addac3 */
 724 void
 725 OP_17000200 (void)
 726 {
 727   int64 tmp;
 728   tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
 729
 730   trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
 731   SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
 732   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 733   trace_output_32 (tmp);
 734 }
 735
 736 /* addac3 */
 737 void
 738 OP_17000202 (void)
 739 {
 740   int64 tmp;
 741   tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
 742
 743   trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
 744   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 745   SET_GPR (OP[0] + 1, tmp & 0xffff);
 746   trace_output_32 (tmp);
 747 }
 748
 749 /* addac3s */
 750 void
 751 OP_17001200 (void)
 752 {
 753   int64 tmp;
 754   SET_PSW_F1 (PSW_F0);
 755
 756   trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
 757   tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
 758   if (tmp > SEXT40(MAX32))
 759     {
 760       tmp = (MAX32);
 761       SET_PSW_F0 (1);
 762     }
 763   else if (tmp < SEXT40(MIN32))
 764     {
 765       tmp = (MIN32);
 766       SET_PSW_F0 (1);
 767     }
 768   else
 769     {
 770       SET_PSW_F0 (0);
 771     }
 772   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 773   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 774   trace_output_32 (tmp);
 775 }
 776
 777 /* addac3s */
 778 void
 779 OP_17001202 (void)
 780 {
 781   int64 tmp;
 782   SET_PSW_F1 (PSW_F0);
 783
 784   trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
 785   tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
 786   if (tmp > SEXT40(MAX32))
 787     {
 788       tmp = (MAX32);
 789       SET_PSW_F0 (1);
 790     }
 791   else if (tmp < SEXT40(MIN32))
 792     {
 793       tmp = (MIN32);
 794       SET_PSW_F0 (1);
 795     }
 796   else
 797     {
 798       SET_PSW_F0 (0);
 799     }
 800   SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
 801   SET_GPR (OP[0] + 1, (tmp & 0xffff));
 802   trace_output_32 (tmp);
 803 }
 804
 805 /* addi */
 806 void
 807 OP_201 (void)
 808 {
 809   uint16 a = GPR (OP[0]);
 810   uint16 b;
 811   uint16 tmp;
 812   if (OP[1] == 0)
 813     OP[1] = 16;
 814   b = OP[1];
 815   tmp = (a + b);
 816   trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
 817   SET_PSW_C (tmp < a);
 818   SET_GPR (OP[0], tmp);
 819   trace_output_16 (tmp);
 820 }
 821
 822 /* and */
 823 void
 824 OP_C00 (void)
 825 {
 826   uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
 827   trace_input ("and", OP_REG, OP_REG, OP_VOID);
 828   SET_GPR (OP[0], tmp);
 829   trace_output_16 (tmp);
 830 }
 831
 832 /* and3 */
 833 void
 834 OP_6000000 (void)
 835 {
 836   uint16 tmp = GPR (OP[1]) & OP[2];
 837   trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
 838   SET_GPR (OP[0], tmp);
 839   trace_output_16 (tmp);
 840 }
 841
 842 /* bclri */
 843 void
 844 OP_C01 (void)
 845 {
 846   int16 tmp;
 847   trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
 848   tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
 849   SET_GPR (OP[0], tmp);
 850   trace_output_16 (tmp);
 851 }
 852
 853 /* bl.s */
 854 void
 855 OP_4900 (void)
 856 {
 857   trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
 858   SET_GPR (13, PC + 1);
 859   JMP( PC + SEXT8 (OP[0]));
 860   trace_output_void ();
 861 }
 862
 863 /* bl.l */
 864 void
 865 OP_24800000 (void)
 866 {
 867   trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
 868   SET_GPR (13, (PC + 1));
 869   JMP (PC + OP[0]);
 870   trace_output_void ();
 871 }
 872
 873 /* bnoti */
 874 void
 875 OP_A01 (void)
 876 {
 877   int16 tmp;
 878   trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
 879   tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
 880   SET_GPR (OP[0], tmp);
 881   trace_output_16 (tmp);
 882 }
 883
 884 /* bra.s */
 885 void
 886 OP_4800 (void)
 887 {
 888   trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 889   JMP (PC + SEXT8 (OP[0]));
 890   trace_output_void ();
 891 }
 892
 893 /* bra.l */
 894 void
 895 OP_24000000 (void)
 896 {
 897   trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 898   JMP (PC + OP[0]);
 899   trace_output_void ();
 900 }
 901
 902 /* brf0f.s */
 903 void
 904 OP_4A00 (void)
 905 {
 906   trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 907   if (!PSW_F0)
 908     JMP (PC + SEXT8 (OP[0]));
 909   trace_output_flag ();
 910 }
 911
 912 /* brf0f.l */
 913 void
 914 OP_25000000 (void)
 915 {
 916   trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 917   if (!PSW_F0)
 918     JMP (PC + OP[0]);
 919   trace_output_flag ();
 920 }
 921
 922 /* brf0t.s */
 923 void
 924 OP_4B00 (void)
 925 {
 926   trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
 927   if (PSW_F0)
 928     JMP (PC + SEXT8 (OP[0]));
 929   trace_output_flag ();
 930 }
 931
 932 /* brf0t.l */
 933 void
 934 OP_25800000 (void)
 935 {
 936   trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
 937   if (PSW_F0)
 938     JMP (PC + OP[0]);
 939   trace_output_flag ();
 940 }
 941
 942 /* bseti */
 943 void
 944 OP_801 (void)
 945 {
 946   int16 tmp;
 947   trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
 948   tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
 949   SET_GPR (OP[0], tmp);
 950   trace_output_16 (tmp);
 951 }
 952
 953 /* btsti */
 954 void
 955 OP_E01 (void)
 956 {
 957   trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
 958   SET_PSW_F1 (PSW_F0);
 959   SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
 960   trace_output_flag ();
 961 }
 962
 963 /* clrac */
 964 void
 965 OP_5601 (void)
 966 {
 967   trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
 968   SET_ACC (OP[0], 0);
 969   trace_output_40 (0);
 970 }
 971
 972 /* cmp */
 973 void
 974 OP_600 (void)
 975 {
 976   trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
 977   SET_PSW_F1 (PSW_F0);
 978   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
 979   trace_output_flag ();
 980 }
 981
 982 /* cmp */
 983 void
 984 OP_1603 (void)
 985 {
 986   trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
 987   SET_PSW_F1 (PSW_F0);
 988   SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
 989   trace_output_flag ();
 990 }
 991
 992 /* cmpeq */
 993 void
 994 OP_400 (void)
 995 {
 996   trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
 997   SET_PSW_F1 (PSW_F0);
 998   SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
 999   trace_output_flag ();
1000 }
1001
1002 /* cmpeq */
1003 void
1004 OP_1403 (void)
1005 {
1006   trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1007   SET_PSW_F1 (PSW_F0);
1008   SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1009   trace_output_flag ();
1010 }
1011
1012 /* cmpeqi.s */
1013 void
1014 OP_401 (void)
1015 {
1016   trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1017   SET_PSW_F1 (PSW_F0);
1018   SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1019   trace_output_flag ();
1020 }
1021
1022 /* cmpeqi.l */
1023 void
1024 OP_2000000 (void)
1025 {
1026   trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1027   SET_PSW_F1 (PSW_F0);
1028   SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1029   trace_output_flag ();
1030 }
1031
1032 /* cmpi.s */
1033 void
1034 OP_601 (void)
1035 {
1036   trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1037   SET_PSW_F1 (PSW_F0);
1038   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1039   trace_output_flag ();
1040 }
1041
1042 /* cmpi.l */
1043 void
1044 OP_3000000 (void)
1045 {
1046   trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1047   SET_PSW_F1 (PSW_F0);
1048   SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1049   trace_output_flag ();
1050 }
1051
1052 /* cmpu */
1053 void
1054 OP_4600 (void)
1055 {
1056   trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1057   SET_PSW_F1 (PSW_F0);
1058   SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1059   trace_output_flag ();
1060 }
1061
1062 /* cmpui */
1063 void
1064 OP_23000000 (void)
1065 {
1066   trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1067   SET_PSW_F1 (PSW_F0);
1068   SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1069   trace_output_flag ();
1070 }
1071
1072 /* cpfg */
1073 void
1074 OP_4E09 (void)
1075 {
1076   uint8 val;
1077
1078   trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1079
1080   if (OP[1] == 0)
1081     val = PSW_F0;
1082   else if (OP[1] == 1)
1083     val = PSW_F1;
1084   else
1085     val = PSW_C;
1086   if (OP[0] == 0)
1087     SET_PSW_F0 (val);
1088   else
1089     SET_PSW_F1 (val);
1090
1091   trace_output_flag ();
1092 }
1093
1094 /* cpfg */
1095 void
1096 OP_4E0F (void)
1097 {
1098   uint8 val;
1099
1100   trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1101
1102   if (OP[1] == 0)
1103     val = PSW_F0;
1104   else if (OP[1] == 1)
1105     val = PSW_F1;
1106   else
1107     val = PSW_C;
1108   if (OP[0] == 0)
1109     SET_PSW_F0 (val);
1110   else
1111     SET_PSW_F1 (val);
1112
1113   trace_output_flag ();
1114 }
1115
1116 /* dbt */
1117 void
1118 OP_5F20 (void)
1119 {
1120   /* d10v_callback->printf_filtered(d10v_callback, "***** DBT *****  PC=%x\n",PC); */
1121
1122   /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1123      The conditional below is for either of the instruction pairs
1124      ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1125      where the dbt instruction should be interpreted.
1126
1127      The module `sim-break' provides a more effective mechanism for
1128      detecting GDB planted breakpoints.  The code below may,
1129      eventually, be changed to use that mechanism. */
1130
1131   if (State.ins_type == INS_LEFT
1132       || State.ins_type == INS_RIGHT)
1133     {
1134       trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1135       SET_DPC (PC + 1);
1136       SET_DPSW (PSW);
1137       SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1138       JMP (DBT_VECTOR_START);
1139       trace_output_void ();
1140     }
1141   else
1142     {
1143       State.exception = SIGTRAP;
1144     }
1145 }
1146
1147 /* divs */
1148 void
1149 OP_14002800 (void)
1150 {
1151   uint16 foo, tmp, tmpf;
1152   uint16 hi;
1153   uint16 lo;
1154
1155   trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1156   foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1157   tmp = (int16)foo - (int16)(GPR (OP[1]));
1158   tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1159   hi = ((tmpf == 1) ? tmp : foo);
1160   lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1161   SET_GPR (OP[0] + 0, hi);
1162   SET_GPR (OP[0] + 1, lo);
1163   trace_output_32 (((uint32) hi << 16) | lo);
1164 }
1165
1166 /* exef0f */
1167 void
1168 OP_4E04 (void)
1169 {
1170   trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1171   State.exe = (PSW_F0 == 0);
1172   trace_output_flag ();
1173 }
1174
1175 /* exef0t */
1176 void
1177 OP_4E24 (void)
1178 {
1179   trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1180   State.exe = (PSW_F0 != 0);
1181   trace_output_flag ();
1182 }
1183
1184 /* exef1f */
1185 void
1186 OP_4E40 (void)
1187 {
1188   trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1189   State.exe = (PSW_F1 == 0);
1190   trace_output_flag ();
1191 }
1192
1193 /* exef1t */
1194 void
1195 OP_4E42 (void)
1196 {
1197   trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1198   State.exe = (PSW_F1 != 0);
1199   trace_output_flag ();
1200 }
1201
1202 /* exefaf */
1203 void
1204 OP_4E00 (void)
1205 {
1206   trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1207   State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1208   trace_output_flag ();
1209 }
1210
1211 /* exefat */
1212 void
1213 OP_4E02 (void)
1214 {
1215   trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1216   State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1217   trace_output_flag ();
1218 }
1219
1220 /* exetaf */
1221 void
1222 OP_4E20 (void)
1223 {
1224   trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1225   State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1226   trace_output_flag ();
1227 }
1228
1229 /* exetat */
1230 void
1231 OP_4E22 (void)
1232 {
1233   trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1234   State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1235   trace_output_flag ();
1236 }
1237
1238 /* exp */
1239 void
1240 OP_15002A00 (void)
1241 {
1242   uint32 tmp, foo;
1243   int i;
1244
1245   trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1246   if (((int16)GPR (OP[1])) >= 0)
1247     tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1248   else
1249     tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1250
1251   foo = 0x40000000;
1252   for (i=1;i<17;i++)
1253     {
1254       if (tmp & foo)
1255         {
1256           SET_GPR (OP[0], (i - 1));
1257           trace_output_16 (i - 1);
1258           return;
1259         }
1260       foo >>= 1;
1261     }
1262   SET_GPR (OP[0], 16);
1263   trace_output_16 (16);
1264 }
1265
1266 /* exp */
1267 void
1268 OP_15002A02 (void)
1269 {
1270   int64 tmp, foo;
1271   int i;
1272
1273   trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1274   tmp = SEXT40(ACC (OP[1]));
1275   if (tmp < 0)
1276     tmp = ~tmp & MASK40;
1277
1278   foo = 0x4000000000LL;
1279   for (i=1;i<25;i++)
1280     {
1281       if (tmp & foo)
1282         {
1283           SET_GPR (OP[0], i - 9);
1284           trace_output_16 (i - 9);
1285           return;
1286         }
1287       foo >>= 1;
1288     }
1289   SET_GPR (OP[0], 16);
1290   trace_output_16 (16);
1291 }
1292
1293 /* jl */
1294 void
1295 OP_4D00 (void)
1296 {
1297   trace_input ("jl", OP_REG, OP_R0, OP_R1);
1298   SET_GPR (13, PC + 1);
1299   JMP (GPR (OP[0]));
1300   trace_output_void ();
1301 }
1302
1303 /* jmp */
1304 void
1305 OP_4C00 (void)
1306 {
1307   trace_input ("jmp", OP_REG,
1308                (OP[0] == 13) ? OP_R0 : OP_VOID,
1309                (OP[0] == 13) ? OP_R1 : OP_VOID);
1310
1311   JMP (GPR (OP[0]));
1312   trace_output_void ();
1313 }
1314
1315 /* ld */
1316 void
1317 OP_30000000 (void)
1318 {
1319   uint16 tmp;
1320   uint16 addr = OP[1] + GPR (OP[2]);
1321   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1322   if ((addr & 1))
1323     {
1324       State.exception = SIG_D10V_BUS;
1325       State.pc_changed = 1; /* Don't increment the PC. */
1326       trace_output_void ();
1327       return;
1328     }
1329   tmp = RW (addr);
1330   SET_GPR (OP[0], tmp);
1331   trace_output_16 (tmp);
1332 }
1333
1334 /* ld */
1335 void
1336 OP_6401 (void)
1337 {
1338   uint16 tmp;
1339   uint16 addr = GPR (OP[1]);
1340   trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1341   if ((addr & 1))
1342     {
1343       State.exception = SIG_D10V_BUS;
1344       State.pc_changed = 1; /* Don't increment the PC. */
1345       trace_output_void ();
1346       return;
1347     }
1348   tmp = RW (addr);
1349   SET_GPR (OP[0], tmp);
1350   if (OP[0] != OP[1])
1351     INC_ADDR (OP[1], -2);
1352   trace_output_16 (tmp);
1353 }
1354
1355 /* ld */
1356 void
1357 OP_6001 (void)
1358 {
1359   uint16 tmp;
1360   uint16 addr = GPR (OP[1]);
1361   trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1362   if ((addr & 1))
1363     {
1364       State.exception = SIG_D10V_BUS;
1365       State.pc_changed = 1; /* Don't increment the PC. */
1366       trace_output_void ();
1367       return;
1368     }
1369   tmp = RW (addr);
1370   SET_GPR (OP[0], tmp);
1371   if (OP[0] != OP[1])
1372     INC_ADDR (OP[1], 2);
1373   trace_output_16 (tmp);
1374 }
1375
1376 /* ld */
1377 void
1378 OP_6000 (void)
1379 {
1380   uint16 tmp;
1381   uint16 addr = GPR (OP[1]);
1382   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1383   if ((addr & 1))
1384     {
1385       State.exception = SIG_D10V_BUS;
1386       State.pc_changed = 1; /* Don't increment the PC. */
1387       trace_output_void ();
1388       return;
1389     }
1390   tmp = RW (addr);
1391   SET_GPR (OP[0], tmp);
1392   trace_output_16 (tmp);
1393 }
1394
1395 /* ld */
1396 void
1397 OP_32010000 (void)
1398 {
1399   uint16 tmp;
1400   uint16 addr = OP[1];
1401   trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1402   if ((addr & 1))
1403     {
1404       State.exception = SIG_D10V_BUS;
1405       State.pc_changed = 1; /* Don't increment the PC. */
1406       trace_output_void ();
1407       return;
1408     }
1409   tmp = RW (addr);
1410   SET_GPR (OP[0], tmp);
1411   trace_output_16 (tmp);
1412 }
1413
1414 /* ld2w */
1415 void
1416 OP_31000000 (void)
1417 {
1418   int32 tmp;
1419   uint16 addr = OP[1] + GPR (OP[2]);
1420   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1421   if ((addr & 1))
1422     {
1423       State.exception = SIG_D10V_BUS;
1424       State.pc_changed = 1; /* Don't increment the PC. */
1425       trace_output_void ();
1426       return;
1427     }
1428   tmp = RLW (addr);
1429   SET_GPR32 (OP[0], tmp);
1430   trace_output_32 (tmp);
1431 }
1432
1433 /* ld2w */
1434 void
1435 OP_6601 (void)
1436 {
1437   uint16 addr = GPR (OP[1]);
1438   int32 tmp;
1439   trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1440   if ((addr & 1))
1441     {
1442       State.exception = SIG_D10V_BUS;
1443       State.pc_changed = 1; /* Don't increment the PC. */
1444       trace_output_void ();
1445       return;
1446     }
1447   tmp = RLW (addr);
1448   SET_GPR32 (OP[0], tmp);
1449   if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1450     INC_ADDR (OP[1], -4);
1451   trace_output_32 (tmp);
1452 }
1453
1454 /* ld2w */
1455 void
1456 OP_6201 (void)
1457 {
1458   int32 tmp;
1459   uint16 addr = GPR (OP[1]);
1460   trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1461   if ((addr & 1))
1462     {
1463       State.exception = SIG_D10V_BUS;
1464       State.pc_changed = 1; /* Don't increment the PC. */
1465       trace_output_void ();
1466       return;
1467     }
1468   tmp = RLW (addr);
1469   SET_GPR32 (OP[0], tmp);
1470   if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1471     INC_ADDR (OP[1], 4);
1472   trace_output_32 (tmp);
1473 }
1474
1475 /* ld2w */
1476 void
1477 OP_6200 (void)
1478 {
1479   uint16 addr = GPR (OP[1]);
1480   int32 tmp;
1481   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1482   if ((addr & 1))
1483     {
1484       State.exception = SIG_D10V_BUS;
1485       State.pc_changed = 1; /* Don't increment the PC. */
1486       trace_output_void ();
1487       return;
1488     }
1489   tmp = RLW (addr);
1490   SET_GPR32 (OP[0], tmp);
1491   trace_output_32 (tmp);
1492 }
1493
1494 /* ld2w */
1495 void
1496 OP_33010000 (void)
1497 {
1498   int32 tmp;
1499   uint16 addr = OP[1];
1500   trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1501   if ((addr & 1))
1502     {
1503       State.exception = SIG_D10V_BUS;
1504       State.pc_changed = 1; /* Don't increment the PC. */
1505       trace_output_void ();
1506       return;
1507     }
1508   tmp = RLW (addr);
1509   SET_GPR32 (OP[0], tmp);
1510   trace_output_32 (tmp);
1511 }
1512
1513 /* ldb */
1514 void
1515 OP_38000000 (void)
1516 {
1517   int16 tmp;
1518   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1519   tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1520   SET_GPR (OP[0], tmp);
1521   trace_output_16 (tmp);
1522 }
1523
1524 /* ldb */
1525 void
1526 OP_7000 (void)
1527 {
1528   int16 tmp;
1529   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1530   tmp = SEXT8 (RB (GPR (OP[1])));
1531   SET_GPR (OP[0], tmp);
1532   trace_output_16 (tmp);
1533 }
1534
1535 /* ldi.s */
1536 void
1537 OP_4001 (void)
1538 {
1539   int16 tmp;
1540   trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1541   tmp = SEXT4 (OP[1]);
1542   SET_GPR (OP[0], tmp);
1543   trace_output_16 (tmp);
1544 }
1545
1546 /* ldi.l */
1547 void
1548 OP_20000000 (void)
1549 {
1550   int16 tmp;
1551   trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1552   tmp = OP[1];
1553   SET_GPR (OP[0], tmp);
1554   trace_output_16 (tmp);
1555 }
1556
1557 /* ldub */
1558 void
1559 OP_39000000 (void)
1560 {
1561   int16 tmp;
1562   trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1563   tmp = RB (OP[1] + GPR (OP[2]));
1564   SET_GPR (OP[0], tmp);
1565   trace_output_16 (tmp);
1566 }
1567
1568 /* ldub */
1569 void
1570 OP_7200 (void)
1571 {
1572   int16 tmp;
1573   trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1574   tmp = RB (GPR (OP[1]));
1575   SET_GPR (OP[0], tmp);
1576   trace_output_16 (tmp);
1577 }
1578
1579 /* mac */
1580 void
1581 OP_2A00 (void)
1582 {
1583   int64 tmp;
1584
1585   trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1586   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1587
1588   if (PSW_FX)
1589     tmp = SEXT40( (tmp << 1) & MASK40);
1590
1591   if (PSW_ST && tmp > SEXT40(MAX32))
1592     tmp = (MAX32);
1593
1594   tmp += SEXT40 (ACC (OP[0]));
1595   if (PSW_ST)
1596     {
1597       if (tmp > SEXT40(MAX32))
1598         tmp = (MAX32);
1599       else if (tmp < SEXT40(MIN32))
1600         tmp = (MIN32);
1601       else
1602         tmp = (tmp & MASK40);
1603     }
1604   else
1605     tmp = (tmp & MASK40);
1606   SET_ACC (OP[0], tmp);
1607   trace_output_40 (tmp);
1608 }
1609
1610 /* macsu */
1611 void
1612 OP_1A00 (void)
1613 {
1614   int64 tmp;
1615
1616   trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1617   tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1618   if (PSW_FX)
1619     tmp = SEXT40 ((tmp << 1) & MASK40);
1620   tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1621   SET_ACC (OP[0], tmp);
1622   trace_output_40 (tmp);
1623 }
1624
1625 /* macu */
1626 void
1627 OP_3A00 (void)
1628 {
1629   uint64 tmp;
1630   uint32 src1;
1631   uint32 src2;
1632
1633   trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1634   src1 = (uint16) GPR (OP[1]);
1635   src2 = (uint16) GPR (OP[2]);
1636   tmp = src1 * src2;
1637   if (PSW_FX)
1638     tmp = (tmp << 1);
1639   tmp = ((ACC (OP[0]) + tmp) & MASK40);
1640   SET_ACC (OP[0], tmp);
1641   trace_output_40 (tmp);
1642 }
1643
1644 /* max */
1645 void
1646 OP_2600 (void)
1647 {
1648   int16 tmp;
1649   trace_input ("max", OP_REG, OP_REG, OP_VOID);
1650   SET_PSW_F1 (PSW_F0);
1651   if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1652     {
1653       tmp = GPR (OP[1]);
1654       SET_PSW_F0 (1);
1655     }
1656   else
1657     {
1658       tmp = GPR (OP[0]);
1659       SET_PSW_F0 (0);
1660     }
1661   SET_GPR (OP[0], tmp);
1662   trace_output_16 (tmp);
1663 }
1664
1665 /* max */
1666 void
1667 OP_3600 (void)
1668 {
1669   int64 tmp;
1670
1671   trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1672   SET_PSW_F1 (PSW_F0);
1673   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1674   if (tmp > SEXT40 (ACC (OP[0])))
1675     {
1676       tmp = (tmp & MASK40);
1677       SET_PSW_F0 (1);
1678     }
1679   else
1680     {
1681       tmp = ACC (OP[0]);
1682       SET_PSW_F0 (0);
1683     }
1684   SET_ACC (OP[0], tmp);
1685   trace_output_40 (tmp);
1686 }
1687
1688 /* max */
1689 void
1690 OP_3602 (void)
1691 {
1692   int64 tmp;
1693   trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1694   SET_PSW_F1 (PSW_F0);
1695   if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1696     {
1697       tmp = ACC (OP[1]);
1698       SET_PSW_F0 (1);
1699     }
1700   else
1701     {
1702       tmp = ACC (OP[0]);
1703       SET_PSW_F0 (0);
1704     }
1705   SET_ACC (OP[0], tmp);
1706   trace_output_40 (tmp);
1707 }
1708
1709
1710 /* min */
1711 void
1712 OP_2601 (void)
1713 {
1714   int16 tmp;
1715   trace_input ("min", OP_REG, OP_REG, OP_VOID);
1716   SET_PSW_F1 (PSW_F0);
1717   if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1718     {
1719       tmp = GPR (OP[1]);
1720       SET_PSW_F0 (1);
1721     }
1722   else
1723     {
1724       tmp = GPR (OP[0]);
1725       SET_PSW_F0 (0);
1726     }
1727   SET_GPR (OP[0], tmp);
1728   trace_output_16 (tmp);
1729 }
1730
1731 /* min */
1732 void
1733 OP_3601 (void)
1734 {
1735   int64 tmp;
1736
1737   trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1738   SET_PSW_F1 (PSW_F0);
1739   tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1740   if (tmp < SEXT40(ACC (OP[0])))
1741     {
1742       tmp = (tmp & MASK40);
1743       SET_PSW_F0 (1);
1744     }
1745   else
1746     {
1747       tmp = ACC (OP[0]);
1748       SET_PSW_F0 (0);
1749     }
1750   SET_ACC (OP[0], tmp);
1751   trace_output_40 (tmp);
1752 }
1753
1754 /* min */
1755 void
1756 OP_3603 (void)
1757 {
1758   int64 tmp;
1759   trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1760   SET_PSW_F1 (PSW_F0);
1761   if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1762     {
1763       tmp = ACC (OP[1]);
1764       SET_PSW_F0 (1);
1765     }
1766   else
1767     {
1768       tmp = ACC (OP[0]);
1769       SET_PSW_F0 (0);
1770     }
1771   SET_ACC (OP[0], tmp);
1772   trace_output_40 (tmp);
1773 }
1774
1775 /* msb */
1776 void
1777 OP_2800 (void)
1778 {
1779   int64 tmp;
1780
1781   trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1782   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1783
1784   if (PSW_FX)
1785     tmp = SEXT40 ((tmp << 1) & MASK40);
1786
1787   if (PSW_ST && tmp > SEXT40(MAX32))
1788     tmp = (MAX32);
1789
1790   tmp = SEXT40(ACC (OP[0])) - tmp;
1791   if (PSW_ST)
1792     {
1793       if (tmp > SEXT40(MAX32))
1794         tmp = (MAX32);
1795       else if (tmp < SEXT40(MIN32))
1796         tmp = (MIN32);
1797       else
1798         tmp = (tmp & MASK40);
1799     }
1800   else
1801     {
1802       tmp = (tmp & MASK40);
1803     }
1804   SET_ACC (OP[0], tmp);
1805   trace_output_40 (tmp);
1806 }
1807
1808 /* msbsu */
1809 void
1810 OP_1800 (void)
1811 {
1812   int64 tmp;
1813
1814   trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1815   tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1816   if (PSW_FX)
1817     tmp = SEXT40( (tmp << 1) & MASK40);
1818   tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1819   SET_ACC (OP[0], tmp);
1820   trace_output_40 (tmp);
1821 }
1822
1823 /* msbu */
1824 void
1825 OP_3800 (void)
1826 {
1827   uint64 tmp;
1828   uint32 src1;
1829   uint32 src2;
1830
1831   trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1832   src1 = (uint16) GPR (OP[1]);
1833   src2 = (uint16) GPR (OP[2]);
1834   tmp = src1 * src2;
1835   if (PSW_FX)
1836     tmp = (tmp << 1);
1837   tmp = ((ACC (OP[0]) - tmp) & MASK40);
1838   SET_ACC (OP[0], tmp);
1839   trace_output_40 (tmp);
1840 }
1841
1842 /* mul */
1843 void
1844 OP_2E00 (void)
1845 {
1846   int16 tmp;
1847   trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1848   tmp = GPR (OP[0]) * GPR (OP[1]);
1849   SET_GPR (OP[0], tmp);
1850   trace_output_16 (tmp);
1851 }
1852
1853 /* mulx */
1854 void
1855 OP_2C00 (void)
1856 {
1857   int64 tmp;
1858
1859   trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1860   tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1861
1862   if (PSW_FX)
1863     tmp = SEXT40 ((tmp << 1) & MASK40);
1864
1865   if (PSW_ST && tmp > SEXT40(MAX32))
1866     tmp = (MAX32);
1867   else
1868     tmp = (tmp & MASK40);
1869   SET_ACC (OP[0], tmp);
1870   trace_output_40 (tmp);
1871 }
1872
1873 /* mulxsu */
1874 void
1875 OP_1C00 (void)
1876 {
1877   int64 tmp;
1878
1879   trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1880   tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1881
1882   if (PSW_FX)
1883     tmp <<= 1;
1884   tmp = (tmp & MASK40);
1885   SET_ACC (OP[0], tmp);
1886   trace_output_40 (tmp);
1887 }
1888
1889 /* mulxu */
1890 void
1891 OP_3C00 (void)
1892 {
1893   uint64 tmp;
1894   uint32 src1;
1895   uint32 src2;
1896
1897   trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1898   src1 = (uint16) GPR (OP[1]);
1899   src2 = (uint16) GPR (OP[2]);
1900   tmp = src1 * src2;
1901   if (PSW_FX)
1902     tmp <<= 1;
1903   tmp = (tmp & MASK40);
1904   SET_ACC (OP[0], tmp);
1905   trace_output_40 (tmp);
1906 }
1907
1908 /* mv */
1909 void
1910 OP_4000 (void)
1911 {
1912   int16 tmp;
1913   trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1914   tmp = GPR (OP[1]);
1915   SET_GPR (OP[0], tmp);
1916   trace_output_16 (tmp);
1917 }
1918
1919 /* mv2w */
1920 void
1921 OP_5000 (void)
1922 {
1923   int32 tmp;
1924   trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1925   tmp = GPR32 (OP[1]);
1926   SET_GPR32 (OP[0], tmp);
1927   trace_output_32 (tmp);
1928 }
1929
1930 /* mv2wfac */
1931 void
1932 OP_3E00 (void)
1933 {
1934   int32 tmp;
1935   trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1936   tmp = ACC (OP[1]);
1937   SET_GPR32 (OP[0], tmp);
1938   trace_output_32 (tmp);
1939 }
1940
1941 /* mv2wtac */
1942 void
1943 OP_3E01 (void)
1944 {
1945   int64 tmp;
1946   trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1947   tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1948   SET_ACC (OP[1], tmp);
1949   trace_output_40 (tmp);
1950 }
1951
1952 /* mvac */
1953 void
1954 OP_3E03 (void)
1955 {
1956   int64 tmp;
1957   trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1958   tmp = ACC (OP[1]);
1959   SET_ACC (OP[0], tmp);
1960   trace_output_40 (tmp);
1961 }
1962
1963 /* mvb */
1964 void
1965 OP_5400 (void)
1966 {
1967   int16 tmp;
1968   trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1969   tmp = SEXT8 (GPR (OP[1]) & 0xff);
1970   SET_GPR (OP[0], tmp);
1971   trace_output_16 (tmp);
1972 }
1973
1974 /* mvf0f */
1975 void
1976 OP_4400 (void)
1977 {
1978   int16 tmp;
1979   trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1980   if (PSW_F0 == 0)
1981     {
1982       tmp = GPR (OP[1]);
1983       SET_GPR (OP[0], tmp);
1984     }
1985   else
1986     tmp = GPR (OP[0]);
1987   trace_output_16 (tmp);
1988 }
1989
1990 /* mvf0t */
1991 void
1992 OP_4401 (void)
1993 {
1994   int16 tmp;
1995   trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1996   if (PSW_F0)
1997     {
1998       tmp = GPR (OP[1]);
1999       SET_GPR (OP[0], tmp);
2000     }
2001   else
2002     tmp = GPR (OP[0]);
2003   trace_output_16 (tmp);
2004 }
2005
2006 /* mvfacg */
2007 void
2008 OP_1E04 (void)
2009 {
2010   int16 tmp;
2011   trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2012   tmp = ((ACC (OP[1]) >> 32) & 0xff);
2013   SET_GPR (OP[0], tmp);
2014   trace_output_16 (tmp);
2015 }
2016
2017 /* mvfachi */
2018 void
2019 OP_1E00 (void)
2020 {
2021   int16 tmp;
2022   trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2023   tmp = (ACC (OP[1]) >> 16);
2024   SET_GPR (OP[0], tmp);
2025   trace_output_16 (tmp);
2026 }
2027
2028 /* mvfaclo */
2029 void
2030 OP_1E02 (void)
2031 {
2032   int16 tmp;
2033   trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2034   tmp = ACC (OP[1]);
2035   SET_GPR (OP[0], tmp);
2036   trace_output_16 (tmp);
2037 }
2038
2039 /* mvfc */
2040 void
2041 OP_5200 (void)
2042 {
2043   int16 tmp;
2044   trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2045   tmp = CREG (OP[1]);
2046   SET_GPR (OP[0], tmp);
2047   trace_output_16 (tmp);
2048 }
2049
2050 /* mvtacg */
2051 void
2052 OP_1E41 (void)
2053 {
2054   int64 tmp;
2055   trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2056   tmp = ((ACC (OP[1]) & MASK32)
2057          | ((int64)(GPR (OP[0]) & 0xff) << 32));
2058   SET_ACC (OP[1], tmp);
2059   trace_output_40 (tmp);
2060 }
2061
2062 /* mvtachi */
2063 void
2064 OP_1E01 (void)
2065 {
2066   uint64 tmp;
2067   trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2068   tmp = ACC (OP[1]) & 0xffff;
2069   tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2070   SET_ACC (OP[1], tmp);
2071   trace_output_40 (tmp);
2072 }
2073
2074 /* mvtaclo */
2075 void
2076 OP_1E21 (void)
2077 {
2078   int64 tmp;
2079   trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2080   tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2081   SET_ACC (OP[1], tmp);
2082   trace_output_40 (tmp);
2083 }
2084
2085 /* mvtc */
2086 void
2087 OP_5600 (void)
2088 {
2089   int16 tmp;
2090   trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2091   tmp = GPR (OP[0]);
2092   tmp = SET_CREG (OP[1], tmp);
2093   trace_output_16 (tmp);
2094 }
2095
2096 /* mvub */
2097 void
2098 OP_5401 (void)
2099 {
2100   int16 tmp;
2101   trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2102   tmp = (GPR (OP[1]) & 0xff);
2103   SET_GPR (OP[0], tmp);
2104   trace_output_16 (tmp);
2105 }
2106
2107 /* neg */
2108 void
2109 OP_4605 (void)
2110 {
2111   int16 tmp;
2112   trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2113   tmp = - GPR (OP[0]);
2114   SET_GPR (OP[0], tmp);
2115   trace_output_16 (tmp);
2116 }
2117
2118 /* neg */
2119 void
2120 OP_5605 (void)
2121 {
2122   int64 tmp;
2123
2124   trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2125   tmp = -SEXT40(ACC (OP[0]));
2126   if (PSW_ST)
2127     {
2128       if (tmp > SEXT40(MAX32))
2129         tmp = (MAX32);
2130       else if (tmp < SEXT40(MIN32))
2131         tmp = (MIN32);
2132       else
2133         tmp = (tmp & MASK40);
2134     }
2135   else
2136     tmp = (tmp & MASK40);
2137   SET_ACC (OP[0], tmp);
2138   trace_output_40 (tmp);
2139 }
2140
2141
2142 /* nop */
2143 void
2144 OP_5E00 (void)
2145 {
2146   trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2147
2148   ins_type_counters[ (int)State.ins_type ]--;   /* don't count nops as normal instructions */
2149   switch (State.ins_type)
2150     {
2151     default:
2152       ins_type_counters[ (int)INS_UNKNOWN ]++;
2153       break;
2154
2155     case INS_LEFT_PARALLEL:
2156       /* Don't count a parallel op that includes a NOP as a true parallel op */
2157       ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2158       ins_type_counters[ (int)INS_RIGHT ]++;
2159       ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2160       break;
2161
2162     case INS_LEFT:
2163     case INS_LEFT_COND_EXE:
2164       ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2165       break;
2166
2167     case INS_RIGHT_PARALLEL:
2168       /* Don't count a parallel op that includes a NOP as a true parallel op */
2169       ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2170       ins_type_counters[ (int)INS_LEFT ]++;
2171       ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2172       break;
2173
2174     case INS_RIGHT:
2175     case INS_RIGHT_COND_EXE:
2176       ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2177       break;
2178     }
2179
2180   trace_output_void ();
2181 }
2182
2183 /* not */
2184 void
2185 OP_4603 (void)
2186 {
2187   int16 tmp;
2188   trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2189   tmp = ~GPR (OP[0]);
2190   SET_GPR (OP[0], tmp);
2191   trace_output_16 (tmp);
2192 }
2193
2194 /* or */
2195 void
2196 OP_800 (void)
2197 {
2198   int16 tmp;
2199   trace_input ("or", OP_REG, OP_REG, OP_VOID);
2200   tmp = (GPR (OP[0]) | GPR (OP[1]));
2201   SET_GPR (OP[0], tmp);
2202   trace_output_16 (tmp);
2203 }
2204
2205 /* or3 */
2206 void
2207 OP_4000000 (void)
2208 {
2209   int16 tmp;
2210   trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2211   tmp = (GPR (OP[1]) | OP[2]);
2212   SET_GPR (OP[0], tmp);
2213   trace_output_16 (tmp);
2214 }
2215
2216 /* rac */
2217 void
2218 OP_5201 (void)
2219 {
2220   int64 tmp;
2221   int shift = SEXT3 (OP[2]);
2222
2223   trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2224   if (OP[1] != 0)
2225     {
2226       (*d10v_callback->printf_filtered) (d10v_callback,
2227                                          "ERROR at PC 0x%x: instruction only valid for A0\n",
2228                                          PC<<2);
2229       State.exception = SIGILL;
2230     }
2231
2232   SET_PSW_F1 (PSW_F0);
2233   tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2234   if (shift >=0)
2235     tmp <<= shift;
2236   else
2237     tmp >>= -shift;
2238   tmp += 0x8000;
2239   tmp >>= 16; /* look at bits 0:43 */
2240   if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2241     {
2242       tmp = 0x7fffffff;
2243       SET_PSW_F0 (1);
2244     }
2245   else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2246     {
2247       tmp = 0x80000000;
2248       SET_PSW_F0 (1);
2249     }
2250   else
2251     {
2252       SET_PSW_F0 (0);
2253     }
2254   SET_GPR32 (OP[0], tmp);
2255   trace_output_32 (tmp);
2256 }
2257
2258 /* rachi */
2259 void
2260 OP_4201 (void)
2261 {
2262   signed64 tmp;
2263   int shift = SEXT3 (OP[2]);
2264
2265   trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2266   SET_PSW_F1 (PSW_F0);
2267   if (shift >=0)
2268     tmp = SEXT40 (ACC (OP[1])) << shift;
2269   else
2270     tmp = SEXT40 (ACC (OP[1])) >> -shift;
2271   tmp += 0x8000;
2272
2273   if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2274     {
2275       tmp = 0x7fff;
2276       SET_PSW_F0 (1);
2277     }
2278   else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2279     {
2280       tmp = 0x8000;
2281       SET_PSW_F0 (1);
2282     }
2283   else
2284     {
2285       tmp = (tmp >> 16);
2286       SET_PSW_F0 (0);
2287     }
2288   SET_GPR (OP[0], tmp);
2289   trace_output_16 (tmp);
2290 }
2291
2292 /* rep */
2293 void
2294 OP_27000000 (void)
2295 {
2296   trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2297   SET_RPT_S (PC + 1);
2298   SET_RPT_E (PC + OP[1]);
2299   SET_RPT_C (GPR (OP[0]));
2300   SET_PSW_RP (1);
2301   if (GPR (OP[0]) == 0)
2302     {
2303       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2304       State.exception = SIGILL;
2305     }
2306   if (OP[1] < 4)
2307     {
2308       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2309       State.exception = SIGILL;
2310     }
2311   trace_output_void ();
2312 }
2313
2314 /* repi */
2315 void
2316 OP_2F000000 (void)
2317 {
2318   trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2319   SET_RPT_S (PC + 1);
2320   SET_RPT_E (PC + OP[1]);
2321   SET_RPT_C (OP[0]);
2322   SET_PSW_RP (1);
2323   if (OP[0] == 0)
2324     {
2325       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2326       State.exception = SIGILL;
2327     }
2328   if (OP[1] < 4)
2329     {
2330       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2331       State.exception = SIGILL;
2332     }
2333   trace_output_void ();
2334 }
2335
2336 /* rtd */
2337 void
2338 OP_5F60 (void)
2339 {
2340   trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2341   SET_CREG (PSW_CR, DPSW);
2342   JMP(DPC);
2343   trace_output_void ();
2344 }
2345
2346 /* rte */
2347 void
2348 OP_5F40 (void)
2349 {
2350   trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2351   SET_CREG (PSW_CR, BPSW);
2352   JMP(BPC);
2353   trace_output_void ();
2354 }
2355
2356 /* sac */
2357 void OP_5209 (void)
2358 {
2359   int64 tmp;
2360
2361   trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2362
2363   tmp = SEXT40(ACC (OP[1]));
2364
2365   SET_PSW_F1 (PSW_F0);
2366
2367   if (tmp > SEXT40(MAX32))
2368     {
2369       tmp = (MAX32);
2370       SET_PSW_F0 (1);
2371     }
2372   else if (tmp < SEXT40(MIN32))
2373     {
2374       tmp = 0x80000000;
2375       SET_PSW_F0 (1);
2376     }
2377   else
2378     {
2379       tmp = (tmp & MASK32);
2380       SET_PSW_F0 (0);
2381     }
2382
2383   SET_GPR32 (OP[0], tmp);
2384
2385   trace_output_40 (tmp);
2386 }
2387
2388 /* sachi */
2389 void
2390 OP_4209 (void)
2391 {
2392   int64 tmp;
2393
2394   trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2395
2396   tmp = SEXT40(ACC (OP[1]));
2397
2398   SET_PSW_F1 (PSW_F0);
2399
2400   if (tmp > SEXT40(MAX32))
2401     {
2402       tmp = 0x7fff;
2403       SET_PSW_F0 (1);
2404     }
2405   else if (tmp < SEXT40(MIN32))
2406     {
2407       tmp = 0x8000;
2408       SET_PSW_F0 (1);
2409     }
2410   else
2411     {
2412       tmp >>= 16;
2413       SET_PSW_F0 (0);
2414     }
2415
2416   SET_GPR (OP[0], tmp);
2417
2418   trace_output_16 (OP[0]);
2419 }
2420
2421 /* sadd */
2422 void
2423 OP_1223 (void)
2424 {
2425   int64 tmp;
2426
2427   trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2428   tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2429   if (PSW_ST)
2430     {
2431       if (tmp > SEXT40(MAX32))
2432         tmp = (MAX32);
2433       else if (tmp < SEXT40(MIN32))
2434         tmp = (MIN32);
2435       else
2436         tmp = (tmp & MASK40);
2437     }
2438   else
2439     tmp = (tmp & MASK40);
2440   SET_ACC (OP[0], tmp);
2441   trace_output_40 (tmp);
2442 }
2443
2444 /* setf0f */
2445 void
2446 OP_4611 (void)
2447 {
2448   int16 tmp;
2449   trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2450   tmp = ((PSW_F0 == 0) ? 1 : 0);
2451   SET_GPR (OP[0], tmp);
2452   trace_output_16 (tmp);
2453 }
2454
2455 /* setf0t */
2456 void
2457 OP_4613 (void)
2458 {
2459   int16 tmp;
2460   trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2461   tmp = ((PSW_F0 == 1) ? 1 : 0);
2462   SET_GPR (OP[0], tmp);
2463   trace_output_16 (tmp);
2464 }
2465
2466 /* slae */
2467 void
2468 OP_3220 (void)
2469 {
2470   int64 tmp;
2471   int16 reg;
2472
2473   trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2474
2475   reg = SEXT16 (GPR (OP[1]));
2476
2477   if (reg >= 17 || reg <= -17)
2478     {
2479       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2480       State.exception = SIGILL;
2481       return;
2482     }
2483
2484   tmp = SEXT40 (ACC (OP[0]));
2485
2486   if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2487     {
2488       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2489       State.exception = SIGILL;
2490       return;
2491     }
2492
2493   if (reg >= 0 && reg <= 16)
2494     {
2495       tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2496       if (PSW_ST)
2497         {
2498           if (tmp > SEXT40(MAX32))
2499             tmp = (MAX32);
2500           else if (tmp < SEXT40(MIN32))
2501             tmp = (MIN32);
2502           else
2503             tmp = (tmp & MASK40);
2504         }
2505       else
2506         tmp = (tmp & MASK40);
2507     }
2508   else
2509     {
2510       tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2511     }
2512
2513   SET_ACC(OP[0], tmp);
2514
2515   trace_output_40(tmp);
2516 }
2517
2518 /* sleep */
2519 void
2520 OP_5FC0 (void)
2521 {
2522   trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2523   SET_PSW_IE (1);
2524   trace_output_void ();
2525 }
2526
2527 /* sll */
2528 void
2529 OP_2200 (void)
2530 {
2531   int16 tmp;
2532   trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2533   tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2534   SET_GPR (OP[0], tmp);
2535   trace_output_16 (tmp);
2536 }
2537
2538 /* sll */
2539 void
2540 OP_3200 (void)
2541 {
2542   int64 tmp;
2543   trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2544   if ((GPR (OP[1]) & 31) <= 16)
2545     tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2546   else
2547     {
2548       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2549       State.exception = SIGILL;
2550       return;
2551     }
2552
2553   if (PSW_ST)
2554     {
2555       if (tmp > SEXT40(MAX32))
2556         tmp = (MAX32);
2557       else if (tmp < SEXT40(MIN32))
2558         tmp = (MIN32);
2559       else
2560         tmp = (tmp & MASK40);
2561     }
2562   else
2563     tmp = (tmp & MASK40);
2564   SET_ACC (OP[0], tmp);
2565   trace_output_40 (tmp);
2566 }
2567
2568 /* slli */
2569 void
2570 OP_2201 (void)
2571 {
2572   int16 tmp;
2573   trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2574   tmp = (GPR (OP[0]) << OP[1]);
2575   SET_GPR (OP[0], tmp);
2576   trace_output_16 (tmp);
2577 }
2578
2579 /* slli */
2580 void
2581 OP_3201 (void)
2582 {
2583   int64 tmp;
2584
2585   if (OP[1] == 0)
2586     OP[1] = 16;
2587
2588   trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2589   tmp = SEXT40(ACC (OP[0])) << OP[1];
2590
2591   if (PSW_ST)
2592     {
2593       if (tmp > SEXT40(MAX32))
2594         tmp = (MAX32);
2595       else if (tmp < SEXT40(MIN32))
2596         tmp = (MIN32);
2597       else
2598         tmp = (tmp & MASK40);
2599     }
2600   else
2601     tmp = (tmp & MASK40);
2602   SET_ACC (OP[0], tmp);
2603   trace_output_40 (tmp);
2604 }
2605
2606 /* slx */
2607 void
2608 OP_460B (void)
2609 {
2610   int16 tmp;
2611   trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
2612   tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2613   SET_GPR (OP[0], tmp);
2614   trace_output_16 (tmp);
2615 }
2616
2617 /* sra */
2618 void
2619 OP_2400 (void)
2620 {
2621   int16 tmp;
2622   trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2623   tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2624   SET_GPR (OP[0], tmp);
2625   trace_output_16 (tmp);
2626 }
2627
2628 /* sra */
2629 void
2630 OP_3400 (void)
2631 {
2632   trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2633   if ((GPR (OP[1]) & 31) <= 16)
2634     {
2635       int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2636       SET_ACC (OP[0], tmp);
2637       trace_output_40 (tmp);
2638     }
2639   else
2640     {
2641       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2642       State.exception = SIGILL;
2643       return;
2644     }
2645 }
2646
2647 /* srai */
2648 void
2649 OP_2401 (void)
2650 {
2651   int16 tmp;
2652   trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2653   tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2654   SET_GPR (OP[0], tmp);
2655   trace_output_16 (tmp);
2656 }
2657
2658 /* srai */
2659 void
2660 OP_3401 (void)
2661 {
2662   int64 tmp;
2663   if (OP[1] == 0)
2664     OP[1] = 16;
2665
2666   trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2667   tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2668   SET_ACC (OP[0], tmp);
2669   trace_output_40 (tmp);
2670 }
2671
2672 /* srl */
2673 void
2674 OP_2000 (void)
2675 {
2676   int16 tmp;
2677   trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2678   tmp = (GPR (OP[0]) >>  (GPR (OP[1]) & 0xf));
2679   SET_GPR (OP[0], tmp);
2680   trace_output_16 (tmp);
2681 }
2682
2683 /* srl */
2684 void
2685 OP_3000 (void)
2686 {
2687   trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2688   if ((GPR (OP[1]) & 31) <= 16)
2689     {
2690       int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2691       SET_ACC (OP[0], tmp);
2692       trace_output_40 (tmp);
2693     }
2694   else
2695     {
2696       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2697       State.exception = SIGILL;
2698       return;
2699     }
2700
2701 }
2702
2703 /* srli */
2704 void
2705 OP_2001 (void)
2706 {
2707   int16 tmp;
2708   trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2709   tmp = (GPR (OP[0]) >> OP[1]);
2710   SET_GPR (OP[0], tmp);
2711   trace_output_16 (tmp);
2712 }
2713
2714 /* srli */
2715 void
2716 OP_3001 (void)
2717 {
2718   int64 tmp;
2719   if (OP[1] == 0)
2720     OP[1] = 16;
2721
2722   trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2723   tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2724   SET_ACC (OP[0], tmp);
2725   trace_output_40 (tmp);
2726 }
2727
2728 /* srx */
2729 void
2730 OP_4609 (void)
2731 {
2732   uint16 tmp;
2733   trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
2734   tmp = PSW_F0 << 15;
2735   tmp = ((GPR (OP[0]) >> 1) | tmp);
2736   SET_GPR (OP[0], tmp);
2737   trace_output_16 (tmp);
2738 }
2739
2740 /* st */
2741 void
2742 OP_34000000 (void)
2743 {
2744   uint16 addr = OP[1] + GPR (OP[2]);
2745   trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2746   if ((addr & 1))
2747     {
2748       State.exception = SIG_D10V_BUS;
2749       State.pc_changed = 1; /* Don't increment the PC. */
2750       trace_output_void ();
2751       return;
2752     }
2753   SW (addr, GPR (OP[0]));
2754   trace_output_void ();
2755 }
2756
2757 /* st */
2758 void
2759 OP_6800 (void)
2760 {
2761   uint16 addr = GPR (OP[1]);
2762   trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2763   if ((addr & 1))
2764     {
2765       State.exception = SIG_D10V_BUS;
2766       State.pc_changed = 1; /* Don't increment the PC. */
2767       trace_output_void ();
2768       return;
2769     }
2770   SW (addr, GPR (OP[0]));
2771   trace_output_void ();
2772 }
2773
2774 /* st */
2775 /* st Rsrc1,@-SP */
2776 void
2777 OP_6C1F (void)
2778 {
2779   uint16 addr = GPR (OP[1]) - 2;
2780   trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2781   if (OP[1] != 15)
2782     {
2783       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2784       State.exception = SIGILL;
2785       return;
2786     }
2787   if ((addr & 1))
2788     {
2789       State.exception = SIG_D10V_BUS;
2790       State.pc_changed = 1; /* Don't increment the PC. */
2791       trace_output_void ();
2792       return;
2793     }
2794   SW (addr, GPR (OP[0]));
2795   SET_GPR (OP[1], addr);
2796   trace_output_void ();
2797 }
2798
2799 /* st */
2800 void
2801 OP_6801 (void)
2802 {
2803   uint16 addr = GPR (OP[1]);
2804   trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2805   if ((addr & 1))
2806     {
2807       State.exception = SIG_D10V_BUS;
2808       State.pc_changed = 1; /* Don't increment the PC. */
2809       trace_output_void ();
2810       return;
2811     }
2812   SW (addr, GPR (OP[0]));
2813   INC_ADDR (OP[1], 2);
2814   trace_output_void ();
2815 }
2816
2817 /* st */
2818 void
2819 OP_6C01 (void)
2820 {
2821   uint16 addr = GPR (OP[1]);
2822   trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2823   if ( OP[1] == 15 )
2824     {
2825       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2826       State.exception = SIGILL;
2827       return;
2828     }
2829   if ((addr & 1))
2830     {
2831       State.exception = SIG_D10V_BUS;
2832       State.pc_changed = 1; /* Don't increment the PC. */
2833       trace_output_void ();
2834       return;
2835     }
2836   SW (addr, GPR (OP[0]));
2837   INC_ADDR (OP[1], -2);
2838   trace_output_void ();
2839 }
2840
2841 /* st */
2842 void
2843 OP_36010000 (void)
2844 {
2845   uint16 addr = OP[1];
2846   trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2847   if ((addr & 1))
2848     {
2849       State.exception = SIG_D10V_BUS;
2850       State.pc_changed = 1; /* Don't increment the PC. */
2851       trace_output_void ();
2852       return;
2853     }
2854   SW (addr, GPR (OP[0]));
2855   trace_output_void ();
2856 }
2857
2858 /* st2w */
2859 void
2860 OP_35000000 (void)
2861 {
2862   uint16 addr = GPR (OP[2])+ OP[1];
2863   trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2864   if ((addr & 1))
2865     {
2866       State.exception = SIG_D10V_BUS;
2867       State.pc_changed = 1; /* Don't increment the PC. */
2868       trace_output_void ();
2869       return;
2870     }
2871   SW (addr + 0, GPR (OP[0] + 0));
2872   SW (addr + 2, GPR (OP[0] + 1));
2873   trace_output_void ();
2874 }
2875
2876 /* st2w */
2877 void
2878 OP_6A00 (void)
2879 {
2880   uint16 addr = GPR (OP[1]);
2881   trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2882   if ((addr & 1))
2883     {
2884       State.exception = SIG_D10V_BUS;
2885       State.pc_changed = 1; /* Don't increment the PC. */
2886       trace_output_void ();
2887       return;
2888     }
2889   SW (addr + 0, GPR (OP[0] + 0));
2890   SW (addr + 2, GPR (OP[0] + 1));
2891   trace_output_void ();
2892 }
2893
2894 /* st2w */
2895 void
2896 OP_6E1F (void)
2897 {
2898   uint16 addr = GPR (OP[1]) - 4;
2899   trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2900   if ( OP[1] != 15 )
2901     {
2902       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2903       State.exception = SIGILL;
2904       return;
2905     }
2906   if ((addr & 1))
2907     {
2908       State.exception = SIG_D10V_BUS;
2909       State.pc_changed = 1; /* Don't increment the PC. */
2910       trace_output_void ();
2911       return;
2912     }
2913   SW (addr + 0, GPR (OP[0] + 0));
2914   SW (addr + 2, GPR (OP[0] + 1));
2915   SET_GPR (OP[1], addr);
2916   trace_output_void ();
2917 }
2918
2919 /* st2w */
2920 void
2921 OP_6A01 (void)
2922 {
2923   uint16 addr = GPR (OP[1]);
2924   trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2925   if ((addr & 1))
2926     {
2927       State.exception = SIG_D10V_BUS;
2928       State.pc_changed = 1; /* Don't increment the PC. */
2929       trace_output_void ();
2930       return;
2931     }
2932   SW (addr + 0, GPR (OP[0] + 0));
2933   SW (addr + 2, GPR (OP[0] + 1));
2934   INC_ADDR (OP[1], 4);
2935   trace_output_void ();
2936 }
2937
2938 /* st2w */
2939 void
2940 OP_6E01 (void)
2941 {
2942   uint16 addr = GPR (OP[1]);
2943   trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2944   if ( OP[1] == 15 )
2945     {
2946       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2947       State.exception = SIGILL;
2948       return;
2949     }
2950   if ((addr & 1))
2951     {
2952       State.exception = SIG_D10V_BUS;
2953       State.pc_changed = 1; /* Don't increment the PC. */
2954       trace_output_void ();
2955       return;
2956     }
2957   SW (addr + 0, GPR (OP[0] + 0));
2958   SW (addr + 2, GPR (OP[0] + 1));
2959   INC_ADDR (OP[1], -4);
2960   trace_output_void ();
2961 }
2962
2963 /* st2w */
2964 void
2965 OP_37010000 (void)
2966 {
2967   uint16 addr = OP[1];
2968   trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2969   if ((addr & 1))
2970     {
2971       State.exception = SIG_D10V_BUS;
2972       State.pc_changed = 1; /* Don't increment the PC. */
2973       trace_output_void ();
2974       return;
2975     }
2976   SW (addr + 0, GPR (OP[0] + 0));
2977   SW (addr + 2, GPR (OP[0] + 1));
2978   trace_output_void ();
2979 }
2980
2981 /* stb */
2982 void
2983 OP_3C000000 (void)
2984 {
2985   trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2986   SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2987   trace_output_void ();
2988 }
2989
2990 /* stb */
2991 void
2992 OP_7800 (void)
2993 {
2994   trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2995   SB (GPR (OP[1]), GPR (OP[0]));
2996   trace_output_void ();
2997 }
2998
2999 /* stop */
3000 void
3001 OP_5FE0 (void)
3002 {
3003   trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
3004   State.exception = SIG_D10V_STOP;
3005   trace_output_void ();
3006 }
3007
3008 /* sub */
3009 void
3010 OP_0 (void)
3011 {
3012   uint16 a = GPR (OP[0]);
3013   uint16 b = GPR (OP[1]);
3014   uint16 tmp = (a - b);
3015   trace_input ("sub", OP_REG, OP_REG, OP_VOID);
3016   /* see ../common/sim-alu.h for a more extensive discussion on how to
3017      compute the carry/overflow bits. */
3018   SET_PSW_C (a >= b);
3019   SET_GPR (OP[0], tmp);
3020   trace_output_16 (tmp);
3021 }
3022
3023 /* sub */
3024 void
3025 OP_1001 (void)
3026 {
3027   int64 tmp;
3028
3029   trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
3030   tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
3031   if (PSW_ST)
3032     {
3033       if (tmp > SEXT40(MAX32))
3034         tmp = (MAX32);
3035       else if (tmp < SEXT40(MIN32))
3036         tmp = (MIN32);
3037       else
3038         tmp = (tmp & MASK40);
3039     }
3040   else
3041     tmp = (tmp & MASK40);
3042   SET_ACC (OP[0], tmp);
3043
3044   trace_output_40 (tmp);
3045 }
3046
3047 /* sub */
3048
3049 void
3050 OP_1003 (void)
3051 {
3052   int64 tmp;
3053
3054   trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
3055   tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
3056   if (PSW_ST)
3057     {
3058       if (tmp > SEXT40(MAX32))
3059         tmp = (MAX32);
3060       else if (tmp < SEXT40(MIN32))
3061         tmp = (MIN32);
3062       else
3063         tmp = (tmp & MASK40);
3064     }
3065   else
3066     tmp = (tmp & MASK40);
3067   SET_ACC (OP[0], tmp);
3068
3069   trace_output_40 (tmp);
3070 }
3071
3072 /* sub2w */
3073 void
3074 OP_1000 (void)
3075 {
3076   uint32 tmp, a, b;
3077
3078   trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
3079   a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3080   b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3081   /* see ../common/sim-alu.h for a more extensive discussion on how to
3082      compute the carry/overflow bits */
3083   tmp = a - b;
3084   SET_PSW_C (a >= b);
3085   SET_GPR32 (OP[0], tmp);
3086   trace_output_32 (tmp);
3087 }
3088
3089 /* subac3 */
3090 void
3091 OP_17000000 (void)
3092 {
3093   int64 tmp;
3094
3095   trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3096   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3097   SET_GPR32 (OP[0], tmp);
3098   trace_output_32 (tmp);
3099 }
3100
3101 /* subac3 */
3102 void
3103 OP_17000002 (void)
3104 {
3105   int64 tmp;
3106
3107   trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3108   tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
3109   SET_GPR32 (OP[0], tmp);
3110   trace_output_32 (tmp);
3111 }
3112
3113 /* subac3s */
3114 void
3115 OP_17001000 (void)
3116 {
3117   int64 tmp;
3118
3119   trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3120   SET_PSW_F1 (PSW_F0);
3121   tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3122   if (tmp > SEXT40(MAX32))
3123     {
3124       tmp = (MAX32);
3125       SET_PSW_F0 (1);
3126     }
3127   else if (tmp < SEXT40(MIN32))
3128     {
3129       tmp = (MIN32);
3130       SET_PSW_F0 (1);
3131     }
3132   else
3133     {
3134       SET_PSW_F0 (0);
3135     }
3136   SET_GPR32 (OP[0], tmp);
3137   trace_output_32 (tmp);
3138 }
3139
3140 /* subac3s */
3141 void
3142 OP_17001002 (void)
3143 {
3144   int64 tmp;
3145
3146   trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3147   SET_PSW_F1 (PSW_F0);
3148   tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
3149   if (tmp > SEXT40(MAX32))
3150     {
3151       tmp = (MAX32);
3152       SET_PSW_F0 (1);
3153     }
3154   else if (tmp < SEXT40(MIN32))
3155     {
3156       tmp = (MIN32);
3157       SET_PSW_F0 (1);
3158     }
3159   else
3160     {
3161       SET_PSW_F0 (0);
3162     }
3163   SET_GPR32 (OP[0], tmp);
3164   trace_output_32 (tmp);
3165 }
3166
3167 /* subi */
3168 void
3169 OP_1 (void)
3170 {
3171   unsigned tmp;
3172   if (OP[1] == 0)
3173     OP[1] = 16;
3174
3175   trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3176   /* see ../common/sim-alu.h for a more extensive discussion on how to
3177      compute the carry/overflow bits. */
3178   /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3179   tmp = ((unsigned)(unsigned16) GPR (OP[0])
3180          + (unsigned)(unsigned16) ( - OP[1]));
3181   SET_PSW_C (tmp >= (1 << 16));
3182   SET_GPR (OP[0], tmp);
3183   trace_output_16 (tmp);
3184 }
3185
3186 /* trap */
3187 void
3188 OP_5F00 (void)
3189 {
3190   trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3191   trace_output_void ();
3192
3193   switch (OP[0])
3194     {
3195     default:
3196 #if (DEBUG & DEBUG_TRAP) == 0
3197       {
3198         uint16 vec = OP[0] + TRAP_VECTOR_START;
3199         SET_BPC (PC + 1);
3200         SET_BPSW (PSW);
3201         SET_PSW (PSW & PSW_SM_BIT);
3202         JMP (vec);
3203         break;
3204       }
3205 #else                   /* if debugging use trap to print registers */
3206       {
3207         int i;
3208         static int first_time = 1;
3209
3210         if (first_time)
3211           {
3212             first_time = 0;
3213             (*d10v_callback->printf_filtered) (d10v_callback, "Trap  #     PC ");
3214             for (i = 0; i < 16; i++)
3215               (*d10v_callback->printf_filtered) (d10v_callback, "  %sr%d", (i > 9) ? "" : " ", i);
3216             (*d10v_callback->printf_filtered) (d10v_callback, "         a0         a1 f0 f1 c\n");
3217           }
3218
3219         (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3220
3221         for (i = 0; i < 16; i++)
3222           (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3223
3224         for (i = 0; i < 2; i++)
3225           (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3226                                              ((int)(ACC (i) >> 32) & 0xff),
3227                                              ((unsigned long) ACC (i)) & 0xffffffff);
3228
3229         (*d10v_callback->printf_filtered) (d10v_callback, "  %d  %d %d\n",
3230                                            PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3231         (*d10v_callback->flush_stdout) (d10v_callback);
3232         break;
3233       }
3234 #endif
3235     case 15:                    /* new system call trap */
3236       /* Trap 15 is used for simulating low-level I/O */
3237       {
3238         unsigned32 result = 0;
3239         errno = 0;
3240
3241 /* Registers passed to trap 0 */
3242
3243 #define FUNC   GPR (4)  /* function number */
3244 #define PARM1  GPR (0)  /* optional parm 1 */
3245 #define PARM2  GPR (1)  /* optional parm 2 */
3246 #define PARM3  GPR (2)  /* optional parm 3 */
3247 #define PARM4  GPR (3)  /* optional parm 3 */
3248
3249 /* Registers set by trap 0 */
3250
3251 #define RETVAL(X)   do { result = (X); SET_GPR (0, result); } while (0)
3252 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3253 #define RETERR(X) SET_GPR (4, (X))              /* return error code */
3254
3255 /* Turn a pointer in a register into a pointer into real memory. */
3256
3257 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3258
3259         switch (FUNC)
3260           {
3261 #if !defined(__GO32__) && !defined(_WIN32)
3262           case TARGET_SYS_fork:
3263             trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3264             RETVAL (fork ());
3265             trace_output_16 (result);
3266             break;
3267
3268 #define getpid() 47
3269           case TARGET_SYS_getpid:
3270             trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3271             RETVAL (getpid ());
3272             trace_output_16 (result);
3273             break;
3274
3275           case TARGET_SYS_kill:
3276             trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3277             if (PARM1 == getpid ())
3278               {
3279                 trace_output_void ();
3280                 State.exception = PARM2;
3281               }
3282             else
3283               {
3284                 int os_sig = -1;
3285                 switch (PARM2)
3286                   {
3287 #ifdef SIGHUP
3288                   case 1: os_sig = SIGHUP;      break;
3289 #endif
3290 #ifdef SIGINT
3291                   case 2: os_sig = SIGINT;      break;
3292 #endif
3293 #ifdef SIGQUIT
3294                   case 3: os_sig = SIGQUIT;     break;
3295 #endif
3296 #ifdef SIGILL
3297                   case 4: os_sig = SIGILL;      break;
3298 #endif
3299 #ifdef SIGTRAP
3300                   case 5: os_sig = SIGTRAP;     break;
3301 #endif
3302 #ifdef SIGABRT
3303                   case 6: os_sig = SIGABRT;     break;
3304 #elif defined(SIGIOT)
3305                   case 6: os_sig = SIGIOT;      break;
3306 #endif
3307 #ifdef SIGEMT
3308                   case 7: os_sig = SIGEMT;      break;
3309 #endif
3310 #ifdef SIGFPE
3311                   case 8: os_sig = SIGFPE;      break;
3312 #endif
3313 #ifdef SIGKILL
3314                   case 9: os_sig = SIGKILL;     break;
3315 #endif
3316 #ifdef SIGBUS
3317                   case 10: os_sig = SIGBUS;     break;
3318 #endif
3319 #ifdef SIGSEGV
3320                   case 11: os_sig = SIGSEGV;    break;
3321 #endif
3322 #ifdef SIGSYS
3323                   case 12: os_sig = SIGSYS;     break;
3324 #endif
3325 #ifdef SIGPIPE
3326                   case 13: os_sig = SIGPIPE;    break;
3327 #endif
3328 #ifdef SIGALRM
3329                   case 14: os_sig = SIGALRM;    break;
3330 #endif
3331 #ifdef SIGTERM
3332                   case 15: os_sig = SIGTERM;    break;
3333 #endif
3334 #ifdef SIGURG
3335                   case 16: os_sig = SIGURG;     break;
3336 #endif
3337 #ifdef SIGSTOP
3338                   case 17: os_sig = SIGSTOP;    break;
3339 #endif
3340 #ifdef SIGTSTP
3341                   case 18: os_sig = SIGTSTP;    break;
3342 #endif
3343 #ifdef SIGCONT
3344                   case 19: os_sig = SIGCONT;    break;
3345 #endif
3346 #ifdef SIGCHLD
3347                   case 20: os_sig = SIGCHLD;    break;
3348 #elif defined(SIGCLD)
3349                   case 20: os_sig = SIGCLD;     break;
3350 #endif
3351 #ifdef SIGTTIN
3352                   case 21: os_sig = SIGTTIN;    break;
3353 #endif
3354 #ifdef SIGTTOU
3355                   case 22: os_sig = SIGTTOU;    break;
3356 #endif
3357 #ifdef SIGIO
3358                   case 23: os_sig = SIGIO;      break;
3359 #elif defined (SIGPOLL)
3360                   case 23: os_sig = SIGPOLL;    break;
3361 #endif
3362 #ifdef SIGXCPU
3363                   case 24: os_sig = SIGXCPU;    break;
3364 #endif
3365 #ifdef SIGXFSZ
3366                   case 25: os_sig = SIGXFSZ;    break;
3367 #endif
3368 #ifdef SIGVTALRM
3369                   case 26: os_sig = SIGVTALRM;  break;
3370 #endif
3371 #ifdef SIGPROF
3372                   case 27: os_sig = SIGPROF;    break;
3373 #endif
3374 #ifdef SIGWINCH
3375                   case 28: os_sig = SIGWINCH;   break;
3376 #endif
3377 #ifdef SIGLOST
3378                   case 29: os_sig = SIGLOST;    break;
3379 #endif
3380 #ifdef SIGUSR1
3381                   case 30: os_sig = SIGUSR1;    break;
3382 #endif
3383 #ifdef SIGUSR2
3384                   case 31: os_sig = SIGUSR2;    break;
3385 #endif
3386                   }
3387
3388                 if (os_sig == -1)
3389                   {
3390                     trace_output_void ();
3391                     (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3392                     (*d10v_callback->flush_stdout) (d10v_callback);
3393                     State.exception = SIGILL;
3394                   }
3395                 else
3396                   {
3397                     RETVAL (kill (PARM1, PARM2));
3398                     trace_output_16 (result);
3399                   }
3400               }
3401             break;
3402
3403           case TARGET_SYS_execve:
3404             trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3405             RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3406                              (char **)MEMPTR (PARM3)));
3407             trace_output_16 (result);
3408             break;
3409
3410 #ifdef TARGET_SYS_execv
3411           case TARGET_SYS_execv:
3412             trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3413             RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3414             trace_output_16 (result);
3415             break;
3416 #endif
3417
3418           case TARGET_SYS_pipe:
3419             {
3420               reg_t buf;
3421               int host_fd[2];
3422
3423               trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3424               buf = PARM1;
3425               RETVAL (pipe (host_fd));
3426               SW (buf, host_fd[0]);
3427               buf += sizeof(uint16);
3428               SW (buf, host_fd[1]);
3429               trace_output_16 (result);
3430             }
3431           break;
3432
3433 #if 0
3434 #ifdef TARGET_SYS_wait
3435           case TARGET_SYS_wait:
3436             {
3437               int status;
3438               trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3439               RETVAL (wait (&status));
3440               if (PARM1)
3441                 SW (PARM1, status);
3442               trace_output_16 (result);
3443             }
3444           break;
3445 #endif
3446 #endif
3447 #else
3448           case TARGET_SYS_getpid:
3449             trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3450             RETVAL (1);
3451             trace_output_16 (result);
3452             break;
3453
3454           case TARGET_SYS_kill:
3455             trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3456             trace_output_void ();
3457             State.exception = PARM2;
3458             break;
3459 #endif
3460
3461           case TARGET_SYS_read:
3462             trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3463             RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3464                                           PARM3));
3465             trace_output_16 (result);
3466             break;
3467
3468           case TARGET_SYS_write:
3469             trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3470             if (PARM1 == 1)
3471               RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3472                                                          MEMPTR (PARM2), PARM3));
3473             else
3474               RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3475                                                   MEMPTR (PARM2), PARM3));
3476             trace_output_16 (result);
3477             break;
3478
3479           case TARGET_SYS_lseek:
3480             trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3481             RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3482                                             ((((unsigned long) PARM2) << 16)
3483                                              || (unsigned long) PARM3),
3484                                             PARM4));
3485             trace_output_32 (result);
3486             break;
3487
3488           case TARGET_SYS_close:
3489             trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3490             RETVAL (d10v_callback->close (d10v_callback, PARM1));
3491             trace_output_16 (result);
3492             break;
3493
3494           case TARGET_SYS_open:
3495             trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3496             RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3497             trace_output_16 (result);
3498             break;
3499
3500           case TARGET_SYS_exit:
3501             trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3502             State.exception = SIG_D10V_EXIT;
3503             trace_output_void ();
3504             break;
3505
3506 #ifdef TARGET_SYS_stat
3507           case TARGET_SYS_stat:
3508             trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3509             /* stat system call */
3510             {
3511               struct stat host_stat;
3512               reg_t buf;
3513
3514               RETVAL (stat (MEMPTR (PARM1), &host_stat));
3515
3516               buf = PARM2;
3517
3518               /* The hard-coded offsets and sizes were determined by using
3519                * the D10V compiler on a test program that used struct stat.
3520                */
3521               SW  (buf,    host_stat.st_dev);
3522               SW  (buf+2,  host_stat.st_ino);
3523               SW  (buf+4,  host_stat.st_mode);
3524               SW  (buf+6,  host_stat.st_nlink);
3525               SW  (buf+8,  host_stat.st_uid);
3526               SW  (buf+10, host_stat.st_gid);
3527               SW  (buf+12, host_stat.st_rdev);
3528               SLW (buf+16, host_stat.st_size);
3529               SLW (buf+20, host_stat.st_atime);
3530               SLW (buf+28, host_stat.st_mtime);
3531               SLW (buf+36, host_stat.st_ctime);
3532             }
3533             trace_output_16 (result);
3534             break;
3535 #endif
3536
3537           case TARGET_SYS_chown:
3538             trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3539             RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3540             trace_output_16 (result);
3541             break;
3542
3543           case TARGET_SYS_chmod:
3544             trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3545             RETVAL (chmod (MEMPTR (PARM1), PARM2));
3546             trace_output_16 (result);
3547             break;
3548
3549 #if 0
3550 #ifdef TARGET_SYS_utime
3551           case TARGET_SYS_utime:
3552             trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3553             /* Cast the second argument to void *, to avoid type mismatch
3554                if a prototype is present.  */
3555             RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3556             trace_output_16 (result);
3557             break;
3558 #endif
3559 #endif
3560
3561 #if 0
3562 #ifdef TARGET_SYS_time
3563           case TARGET_SYS_time:
3564             trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3565             RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3566             trace_output_32 (result);
3567             break;
3568 #endif
3569 #endif
3570
3571           default:
3572             d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3573           }
3574         if ((uint16) result == (uint16) -1)
3575           RETERR (d10v_callback->get_errno(d10v_callback));
3576         else
3577           RETERR (0);
3578         break;
3579       }
3580     }
3581 }
3582
3583 /* tst0i */
3584 void
3585 OP_7000000 (void)
3586 {
3587   trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3588   SET_PSW_F1 (PSW_F0);;
3589   SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3590   trace_output_flag ();
3591 }
3592
3593 /* tst1i */
3594 void
3595 OP_F000000 (void)
3596 {
3597   trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3598   SET_PSW_F1 (PSW_F0);
3599   SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3600   trace_output_flag ();
3601 }
3602
3603 /* wait */
3604 void
3605 OP_5F80 (void)
3606 {
3607   trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3608   SET_PSW_IE (1);
3609   trace_output_void ();
3610 }
3611
3612 /* xor */
3613 void
3614 OP_A00 (void)
3615 {
3616   int16 tmp;
3617   trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3618   tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3619   SET_GPR (OP[0], tmp);
3620   trace_output_16 (tmp);
3621 }
3622
3623 /* xor3 */
3624 void
3625 OP_5000000 (void)
3626 {
3627   int16 tmp;
3628   trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3629   tmp = (GPR (OP[1]) ^ OP[2]);
3630   SET_GPR (OP[0], tmp);
3631   trace_output_16 (tmp);
3632 }