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[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10
11 #include "d10v_sim.h"
12 #include "simops.h"
13 #include "sys/syscall.h"
14
15 extern char *strrchr ();
16
17 enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
39 OP_PREDEC,
40 OP_R2,
41 OP_R3,
42 OP_R4,
43 OP_R2R3
44 };
45
46 #ifdef DEBUG
47 static void trace_input_func PARAMS ((char *name,
48 enum op_types in1,
49 enum op_types in2,
50 enum op_types in3));
51
52 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
53
54 static void trace_output_func PARAMS ((enum op_types result));
55
56 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
57
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 8
60 #endif
61
62 #ifndef SIZE_OPERANDS
63 #define SIZE_OPERANDS 18
64 #endif
65
66 #ifndef SIZE_VALUES
67 #define SIZE_VALUES 13
68 #endif
69
70 #ifndef SIZE_LOCATION
71 #define SIZE_LOCATION 20
72 #endif
73
74 #ifndef SIZE_PC
75 #define SIZE_PC 6
76 #endif
77
78 #ifndef SIZE_LINE_NUMBER
79 #define SIZE_LINE_NUMBER 4
80 #endif
81
82 static void
83 trace_input_func (name, in1, in2, in3)
84 char *name;
85 enum op_types in1;
86 enum op_types in2;
87 enum op_types in3;
88 {
89 char *comma;
90 enum op_types in[3];
91 int i;
92 char buf[1024];
93 char *p;
94 long tmp;
95 char *type;
96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
100
101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
116 case INS_LONG: type = " B"; break;
117 }
118
119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
121 "0x%.*x %s: %-*s ",
122 SIZE_PC, (unsigned)PC,
123 type,
124 SIZE_INSTRUCTION, name);
125
126 else
127 {
128 buf[0] = '\0';
129 byte_pc = decode_pc ();
130 if (text && byte_pc >= text_start && byte_pc < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
135 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
142 p += strlen (p);
143 }
144 else
145 {
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
148 }
149
150 if (functionname)
151 {
152 sprintf (p, "%s ", functionname);
153 p += strlen (p);
154 }
155 else if (filename)
156 {
157 char *q = strrchr (filename, '/');
158 sprintf (p, "%s ", (q) ? q+1 : filename);
159 p += strlen (p);
160 }
161
162 if (*p == ' ')
163 *p = '\0';
164 }
165 }
166
167 (*d10v_callback->printf_filtered) (d10v_callback,
168 "0x%.*x %s: %-*.*s %-*s ",
169 SIZE_PC, (unsigned)PC,
170 type,
171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
173 }
174
175 in[0] = in1;
176 in[1] = in2;
177 in[2] = in3;
178 comma = "";
179 p = buf;
180 for (i = 0; i < 3; i++)
181 {
182 switch (in[i])
183 {
184 case OP_VOID:
185 case OP_R2:
186 case OP_R3:
187 case OP_R4:
188 case OP_R2R3:
189 break;
190
191 case OP_REG:
192 case OP_REG_OUTPUT:
193 case OP_DREG:
194 case OP_DREG_OUTPUT:
195 sprintf (p, "%sr%d", comma, OP[i]);
196 p += strlen (p);
197 comma = ",";
198 break;
199
200 case OP_CR:
201 case OP_CR_OUTPUT:
202 case OP_CR_REVERSE:
203 sprintf (p, "%scr%d", comma, OP[i]);
204 p += strlen (p);
205 comma = ",";
206 break;
207
208 case OP_ACCUM:
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
212 p += strlen (p);
213 comma = ",";
214 break;
215
216 case OP_CONSTANT16:
217 sprintf (p, "%s%d", comma, OP[i]);
218 p += strlen (p);
219 comma = ",";
220 break;
221
222 case OP_CONSTANT8:
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
224 p += strlen (p);
225 comma = ",";
226 break;
227
228 case OP_CONSTANT4:
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
230 p += strlen (p);
231 comma = ",";
232 break;
233
234 case OP_CONSTANT3:
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
236 p += strlen (p);
237 comma = ",";
238 break;
239
240 case OP_MEMREF:
241 sprintf (p, "%s@r%d", comma, OP[i]);
242 p += strlen (p);
243 comma = ",";
244 break;
245
246 case OP_MEMREF2:
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
248 p += strlen (p);
249 comma = ",";
250 break;
251
252 case OP_POSTINC:
253 sprintf (p, "%s@r%d+", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_POSTDEC:
259 sprintf (p, "%s@r%d-", comma, OP[i]);
260 p += strlen (p);
261 comma = ",";
262 break;
263
264 case OP_PREDEC:
265 sprintf (p, "%s@-r%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_FLAG:
271 case OP_FLAG_OUTPUT:
272 if (OP[i] == 0)
273 sprintf (p, "%sf0", comma);
274
275 else if (OP[i] == 1)
276 sprintf (p, "%sf1", comma);
277
278 else
279 sprintf (p, "%sc", comma);
280
281 p += strlen (p);
282 comma = ",";
283 break;
284 }
285 }
286
287 if ((d10v_debug & DEBUG_VALUES) == 0)
288 {
289 *p++ = '\n';
290 *p = '\0';
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
292 }
293 else
294 {
295 *p = '\0';
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
297
298 p = buf;
299 for (i = 0; i < 3; i++)
300 {
301 buf[0] = '\0';
302 switch (in[i])
303 {
304 case OP_VOID:
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
306 break;
307
308 case OP_REG_OUTPUT:
309 case OP_DREG_OUTPUT:
310 case OP_CR_OUTPUT:
311 case OP_ACCUM_OUTPUT:
312 case OP_FLAG_OUTPUT:
313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
314 break;
315
316 case OP_REG:
317 case OP_MEMREF:
318 case OP_POSTDEC:
319 case OP_POSTINC:
320 case OP_PREDEC:
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
323 break;
324
325 case OP_DREG:
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
328 break;
329
330 case OP_CR:
331 case OP_CR_REVERSE:
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
334 break;
335
336 case OP_ACCUM:
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
341 break;
342
343 case OP_CONSTANT16:
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
345 (uint16)OP[i]);
346 break;
347
348 case OP_CONSTANT4:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
351 break;
352
353 case OP_CONSTANT8:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
356 break;
357
358 case OP_CONSTANT3:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
361 break;
362
363 case OP_FLAG:
364 if (OP[i] == 0)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
366 State.F0 != 0);
367
368 else if (OP[i] == 1)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
370 State.F1 != 0);
371
372 else
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
374 State.C != 0);
375
376 break;
377
378 case OP_MEMREF2:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16)OP[i]);
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
383 break;
384
385 case OP_R2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
388 break;
389
390 case OP_R3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
393 break;
394
395 case OP_R4:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
398 break;
399
400 case OP_R2R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
405 i++;
406 break;
407 }
408 }
409 }
410
411 (*d10v_callback->flush_stdout) (d10v_callback);
412 }
413
414 static void
415 trace_output_func (result)
416 enum op_types result;
417 {
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
419 {
420 long tmp;
421
422 switch (result)
423 {
424 default:
425 putchar ('\n');
426 break;
427
428 case OP_REG:
429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
433 break;
434
435 case OP_DREG:
436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
440 break;
441
442 case OP_CR:
443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
447 break;
448
449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
453 break;
454
455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
461 break;
462
463 case OP_ACCUM_REVERSE:
464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
468 break;
469
470 case OP_FLAG:
471 case OP_FLAG_OUTPUT:
472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
474 break;
475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
487 }
488 }
489
490 (*d10v_callback->flush_stdout) (d10v_callback);
491 }
492
493 #else
494 #define trace_input(NAME, IN1, IN2, IN3)
495 #define trace_output(RESULT)
496 #endif
497
498 /* abs */
499 void
500 OP_4607 ()
501 {
502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
503 State.F1 = State.F0;
504 if ((int16)(State.regs[OP[0]]) < 0)
505 {
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
507 State.F0 = 1;
508 }
509 else
510 State.F0 = 0;
511 trace_output (OP_REG);
512 }
513
514 /* abs */
515 void
516 OP_5607 ()
517 {
518 int64 tmp;
519
520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
521 State.F1 = State.F0;
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
523
524 if (State.a[OP[0]] < 0 )
525 {
526 tmp = -State.a[OP[0]];
527 if (State.ST)
528 {
529 if (tmp > MAX32)
530 State.a[OP[0]] = MAX32;
531 else if (tmp < MIN32)
532 State.a[OP[0]] = MIN32;
533 else
534 State.a[OP[0]] = tmp & MASK40;
535 }
536 else
537 State.a[OP[0]] = tmp & MASK40;
538 State.F0 = 1;
539 }
540 else
541 State.F0 = 0;
542 trace_output (OP_ACCUM);
543 }
544
545 /* add */
546 void
547 OP_200 ()
548 {
549 uint16 tmp = State.regs[OP[0]];
550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
553 State.C = 1;
554 else
555 State.C = 0;
556 trace_output (OP_REG);
557 }
558
559 /* add */
560 void
561 OP_1201 ()
562 {
563 int64 tmp;
564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
565
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
567 if (State.ST)
568 {
569 if ( tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
574 State.a[OP[0]] = tmp & MASK40;
575 }
576 else
577 State.a[OP[0]] = tmp & MASK40;
578 trace_output (OP_ACCUM);
579 }
580
581 /* add */
582 void
583 OP_1203 ()
584 {
585 int64 tmp;
586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
587
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
589 if (State.ST)
590 {
591 if (tmp > MAX32)
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
595 else
596 State.a[OP[0]] = tmp & MASK40;
597 }
598 else
599 State.a[OP[0]] = tmp & MASK40;
600 trace_output (OP_ACCUM);
601 }
602
603 /* add2w */
604 void
605 OP_1200 ()
606 {
607 uint32 tmp;
608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
610
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
612 tmp = a + b;
613 State.C = (tmp < a);
614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
616 trace_output (OP_DREG);
617 }
618
619 /* add3 */
620 void
621 OP_1000000 ()
622 {
623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
625
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
627 State.C = (State.regs[OP[0]] < tmp);
628 trace_output (OP_REG);
629 }
630
631 /* addac3 */
632 void
633 OP_17000200 ()
634 {
635 int64 tmp;
636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
637
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
641 trace_output (OP_DREG);
642 }
643
644 /* addac3 */
645 void
646 OP_17000202 ()
647 {
648 int64 tmp;
649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
650
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
654 trace_output (OP_DREG);
655 }
656
657 /* addac3s */
658 void
659 OP_17001200 ()
660 {
661 int64 tmp;
662 State.F1 = State.F0;
663
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
666 if ( tmp > MAX32)
667 {
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
670 State.F0 = 1;
671 }
672 else if (tmp < MIN32)
673 {
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
676 State.F0 = 1;
677 }
678 else
679 {
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
682 State.F0 = 0;
683 }
684 trace_output (OP_DREG);
685 }
686
687 /* addac3s */
688 void
689 OP_17001202 ()
690 {
691 int64 tmp;
692 State.F1 = State.F0;
693
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
696 if ( tmp > MAX32)
697 {
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
700 State.F0 = 1;
701 }
702 else if (tmp < MIN32)
703 {
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
706 State.F0 = 1;
707 }
708 else
709 {
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
712 State.F0 = 0;
713 }
714 trace_output (OP_DREG);
715 }
716
717 /* addi */
718 void
719 OP_201 ()
720 {
721 uint tmp = State.regs[OP[0]];
722 if (OP[1] == 0)
723 OP[1] = 16;
724
725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
726 State.regs[OP[0]] += OP[1];
727 State.C = (State.regs[OP[0]] < tmp);
728 trace_output (OP_REG);
729 }
730
731 /* and */
732 void
733 OP_C00 ()
734 {
735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
736 State.regs[OP[0]] &= State.regs[OP[1]];
737 trace_output (OP_REG);
738 }
739
740 /* and3 */
741 void
742 OP_6000000 ()
743 {
744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
746 trace_output (OP_REG);
747 }
748
749 /* bclri */
750 void
751 OP_C01 ()
752 {
753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
755 trace_output (OP_REG);
756 }
757
758 /* bl.s */
759 void
760 OP_4900 ()
761 {
762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
763 State.regs[13] = PC+1;
764 JMP( PC + SEXT8 (OP[0]));
765 trace_output (OP_VOID);
766 }
767
768 /* bl.l */
769 void
770 OP_24800000 ()
771 {
772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
773 State.regs[13] = PC+1;
774 JMP (PC + OP[0]);
775 trace_output (OP_VOID);
776 }
777
778 /* bnoti */
779 void
780 OP_A01 ()
781 {
782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
784 trace_output (OP_REG);
785 }
786
787 /* bra.s */
788 void
789 OP_4800 ()
790 {
791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
792 JMP (PC + SEXT8 (OP[0]));
793 trace_output (OP_VOID);
794 }
795
796 /* bra.l */
797 void
798 OP_24000000 ()
799 {
800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
801 JMP (PC + OP[0]);
802 trace_output (OP_VOID);
803 }
804
805 /* brf0f.s */
806 void
807 OP_4A00 ()
808 {
809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
810 if (State.F0 == 0)
811 JMP (PC + SEXT8 (OP[0]));
812 trace_output (OP_FLAG);
813 }
814
815 /* brf0f.l */
816 void
817 OP_25000000 ()
818 {
819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
820 if (State.F0 == 0)
821 JMP (PC + OP[0]);
822 trace_output (OP_FLAG);
823 }
824
825 /* brf0t.s */
826 void
827 OP_4B00 ()
828 {
829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
830 if (State.F0)
831 JMP (PC + SEXT8 (OP[0]));
832 trace_output (OP_FLAG);
833 }
834
835 /* brf0t.l */
836 void
837 OP_25800000 ()
838 {
839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
840 if (State.F0)
841 JMP (PC + OP[0]);
842 trace_output (OP_FLAG);
843 }
844
845 /* bseti */
846 void
847 OP_801 ()
848 {
849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
850 State.regs[OP[0]] |= 0x8000 >> OP[1];
851 trace_output (OP_REG);
852 }
853
854 /* btsti */
855 void
856 OP_E01 ()
857 {
858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
861 trace_output (OP_FLAG);
862 }
863
864 /* clrac */
865 void
866 OP_5601 ()
867 {
868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
869 State.a[OP[0]] = 0;
870 trace_output (OP_ACCUM);
871 }
872
873 /* cmp */
874 void
875 OP_600 ()
876 {
877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
880 trace_output (OP_FLAG);
881 }
882
883 /* cmp */
884 void
885 OP_1603 ()
886 {
887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
888 State.F1 = State.F0;
889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
890 trace_output (OP_FLAG);
891 }
892
893 /* cmpeq */
894 void
895 OP_400 ()
896 {
897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
900 trace_output (OP_FLAG);
901 }
902
903 /* cmpeq */
904 void
905 OP_1403 ()
906 {
907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
908 State.F1 = State.F0;
909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
910 trace_output (OP_FLAG);
911 }
912
913 /* cmpeqi.s */
914 void
915 OP_401 ()
916 {
917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
918 State.F1 = State.F0;
919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
920 trace_output (OP_FLAG);
921 }
922
923 /* cmpeqi.l */
924 void
925 OP_2000000 ()
926 {
927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
928 State.F1 = State.F0;
929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
930 trace_output (OP_FLAG);
931 }
932
933 /* cmpi.s */
934 void
935 OP_601 ()
936 {
937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
938 State.F1 = State.F0;
939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
940 trace_output (OP_FLAG);
941 }
942
943 /* cmpi.l */
944 void
945 OP_3000000 ()
946 {
947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
950 trace_output (OP_FLAG);
951 }
952
953 /* cmpu */
954 void
955 OP_4600 ()
956 {
957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
960 trace_output (OP_FLAG);
961 }
962
963 /* cmpui */
964 void
965 OP_23000000 ()
966 {
967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
968 State.F1 = State.F0;
969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
970 trace_output (OP_FLAG);
971 }
972
973 /* cpfg */
974 void
975 OP_4E09 ()
976 {
977 uint8 *src, *dst;
978
979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
993 trace_output (OP_FLAG);
994 }
995
996 /* dbt */
997 void
998 OP_5F20 ()
999 {
1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1001 State.exception = SIGTRAP;
1002 }
1003
1004 /* divs */
1005 void
1006 OP_14002800 ()
1007 {
1008 uint16 foo, tmp, tmpf;
1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
1016 trace_output (OP_DREG);
1017 }
1018
1019 /* exef0f */
1020 void
1021 OP_4E04 ()
1022 {
1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1024 State.exe = (State.F0 == 0);
1025 trace_output (OP_FLAG);
1026 }
1027
1028 /* exef0t */
1029 void
1030 OP_4E24 ()
1031 {
1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1033 State.exe = (State.F0 != 0);
1034 trace_output (OP_FLAG);
1035 }
1036
1037 /* exef1f */
1038 void
1039 OP_4E40 ()
1040 {
1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1042 State.exe = (State.F1 == 0);
1043 trace_output (OP_FLAG);
1044 }
1045
1046 /* exef1t */
1047 void
1048 OP_4E42 ()
1049 {
1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1051 State.exe = (State.F1 != 0);
1052 trace_output (OP_FLAG);
1053 }
1054
1055 /* exefaf */
1056 void
1057 OP_4E00 ()
1058 {
1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
1061 trace_output (OP_FLAG);
1062 }
1063
1064 /* exefat */
1065 void
1066 OP_4E02 ()
1067 {
1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
1070 trace_output (OP_FLAG);
1071 }
1072
1073 /* exetaf */
1074 void
1075 OP_4E20 ()
1076 {
1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
1079 trace_output (OP_FLAG);
1080 }
1081
1082 /* exetat */
1083 void
1084 OP_4E22 ()
1085 {
1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
1088 trace_output (OP_FLAG);
1089 }
1090
1091 /* exp */
1092 void
1093 OP_15002A00 ()
1094 {
1095 uint32 tmp, foo;
1096 int i;
1097
1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1101 else
1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1103
1104 foo = 0x40000000;
1105 for (i=1;i<17;i++)
1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
1110 trace_output (OP_REG);
1111 return;
1112 }
1113 foo >>= 1;
1114 }
1115 State.regs[OP[0]] = 16;
1116 trace_output (OP_REG);
1117 }
1118
1119 /* exp */
1120 void
1121 OP_15002A02 ()
1122 {
1123 int64 tmp, foo;
1124 int i;
1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1127 tmp = SEXT40(State.a[OP[1]]);
1128 if (tmp < 0)
1129 tmp = ~tmp & MASK40;
1130
1131 foo = 0x4000000000LL;
1132 for (i=1;i<25;i++)
1133 {
1134 if (tmp & foo)
1135 {
1136 State.regs[OP[0]] = i-9;
1137 trace_output (OP_REG);
1138 return;
1139 }
1140 foo >>= 1;
1141 }
1142 State.regs[OP[0]] = 16;
1143 trace_output (OP_REG);
1144 }
1145
1146 /* jl */
1147 void
1148 OP_4D00 ()
1149 {
1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
1151 State.regs[13] = PC+1;
1152 JMP (State.regs[OP[0]]);
1153 trace_output (OP_VOID);
1154 }
1155
1156 /* jmp */
1157 void
1158 OP_4C00 ()
1159 {
1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1163
1164 JMP (State.regs[OP[0]]);
1165 trace_output (OP_VOID);
1166 }
1167
1168 /* ld */
1169 void
1170 OP_30000000 ()
1171 {
1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1174 trace_output (OP_REG);
1175 }
1176
1177 /* ld */
1178 void
1179 OP_6401 ()
1180 {
1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1182 if ( OP[1] == 15 )
1183 {
1184 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
1185 State.exception = SIGILL;
1186 return;
1187 }
1188 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1189 INC_ADDR(State.regs[OP[1]],-2);
1190 trace_output (OP_REG);
1191 }
1192
1193 /* ld */
1194 void
1195 OP_6001 ()
1196 {
1197 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1198 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1199 INC_ADDR(State.regs[OP[1]],2);
1200 trace_output (OP_REG);
1201 }
1202
1203 /* ld */
1204 void
1205 OP_6000 ()
1206 {
1207 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1208 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1209 trace_output (OP_REG);
1210 }
1211
1212 /* ld2w */
1213 void
1214 OP_31000000 ()
1215 {
1216 uint16 addr = State.regs[OP[2]];
1217 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1218 State.regs[OP[0]] = RW (OP[1] + addr);
1219 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
1220 trace_output (OP_DREG);
1221 }
1222
1223 /* ld2w */
1224 void
1225 OP_6601 ()
1226 {
1227 uint16 addr = State.regs[OP[1]];
1228 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1229 if ( OP[1] == 15 )
1230 {
1231 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
1232 State.exception = SIGILL;
1233 return;
1234 }
1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
1237 INC_ADDR(State.regs[OP[1]],-4);
1238 trace_output (OP_DREG);
1239 }
1240
1241 /* ld2w */
1242 void
1243 OP_6201 ()
1244 {
1245 uint16 addr = State.regs[OP[1]];
1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
1249 INC_ADDR(State.regs[OP[1]],4);
1250 trace_output (OP_DREG);
1251 }
1252
1253 /* ld2w */
1254 void
1255 OP_6200 ()
1256 {
1257 uint16 addr = State.regs[OP[1]];
1258 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1259 State.regs[OP[0]] = RW (addr);
1260 State.regs[OP[0]+1] = RW (addr+2);
1261 trace_output (OP_DREG);
1262 }
1263
1264 /* ldb */
1265 void
1266 OP_38000000 ()
1267 {
1268 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1269 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
1270 trace_output (OP_REG);
1271 }
1272
1273 /* ldb */
1274 void
1275 OP_7000 ()
1276 {
1277 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1278 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
1279 trace_output (OP_REG);
1280 }
1281
1282 /* ldi.s */
1283 void
1284 OP_4001 ()
1285 {
1286 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1287 State.regs[OP[0]] = SEXT4(OP[1]);
1288 trace_output (OP_REG);
1289 }
1290
1291 /* ldi.l */
1292 void
1293 OP_20000000 ()
1294 {
1295 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1296 State.regs[OP[0]] = OP[1];
1297 trace_output (OP_REG);
1298 }
1299
1300 /* ldub */
1301 void
1302 OP_39000000 ()
1303 {
1304 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1305 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1306 trace_output (OP_REG);
1307 }
1308
1309 /* ldub */
1310 void
1311 OP_7200 ()
1312 {
1313 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1314 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1315 trace_output (OP_REG);
1316 }
1317
1318 /* mac */
1319 void
1320 OP_2A00 ()
1321 {
1322 int64 tmp;
1323
1324 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1325 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1326
1327 if (State.FX)
1328 tmp = SEXT40( (tmp << 1) & MASK40);
1329
1330 if (State.ST && tmp > MAX32)
1331 tmp = MAX32;
1332
1333 tmp += SEXT40(State.a[OP[0]]);
1334 if (State.ST)
1335 {
1336 if (tmp > MAX32)
1337 State.a[OP[0]] = MAX32;
1338 else if (tmp < MIN32)
1339 State.a[OP[0]] = MIN32;
1340 else
1341 State.a[OP[0]] = tmp & MASK40;
1342 }
1343 else
1344 State.a[OP[0]] = tmp & MASK40;
1345 trace_output (OP_ACCUM);
1346 }
1347
1348 /* macsu */
1349 void
1350 OP_1A00 ()
1351 {
1352 int64 tmp;
1353
1354 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1355 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1356 if (State.FX)
1357 tmp = SEXT40( (tmp << 1) & MASK40);
1358
1359 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1360 trace_output (OP_ACCUM);
1361 }
1362
1363 /* macu */
1364 void
1365 OP_3A00 ()
1366 {
1367 int64 tmp;
1368
1369 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1370 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1371 if (State.FX)
1372 tmp = SEXT40( (tmp << 1) & MASK40);
1373 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1374 trace_output (OP_ACCUM);
1375 }
1376
1377 /* max */
1378 void
1379 OP_2600 ()
1380 {
1381 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1382 State.F1 = State.F0;
1383 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1384 {
1385 State.regs[OP[0]] = State.regs[OP[1]];
1386 State.F0 = 1;
1387 }
1388 else
1389 State.F0 = 0;
1390 trace_output (OP_REG);
1391 }
1392
1393 /* max */
1394 void
1395 OP_3600 ()
1396 {
1397 int64 tmp;
1398
1399 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1400 State.F1 = State.F0;
1401 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1402 if (tmp > SEXT40(State.a[OP[0]]))
1403 {
1404 State.a[OP[0]] = tmp & MASK40;
1405 State.F0 = 1;
1406 }
1407 else
1408 State.F0 = 0;
1409 trace_output (OP_ACCUM);
1410 }
1411
1412 /* max */
1413 void
1414 OP_3602 ()
1415 {
1416 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1417 State.F1 = State.F0;
1418 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1419 {
1420 State.a[OP[0]] = State.a[OP[1]];
1421 State.F0 = 1;
1422 }
1423 else
1424 State.F0 = 0;
1425 trace_output (OP_ACCUM);
1426 }
1427
1428
1429 /* min */
1430 void
1431 OP_2601 ()
1432 {
1433 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1434 State.F1 = State.F0;
1435 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1436 {
1437 State.regs[OP[0]] = State.regs[OP[1]];
1438 State.F0 = 1;
1439 }
1440 else
1441 State.F0 = 0;
1442 trace_output (OP_REG);
1443 }
1444
1445 /* min */
1446 void
1447 OP_3601 ()
1448 {
1449 int64 tmp;
1450
1451 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1452 State.F1 = State.F0;
1453 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1454 if (tmp < SEXT40(State.a[OP[0]]))
1455 {
1456 State.a[OP[0]] = tmp & MASK40;
1457 State.F0 = 1;
1458 }
1459 else
1460 State.F0 = 0;
1461 trace_output (OP_ACCUM);
1462 }
1463
1464 /* min */
1465 void
1466 OP_3603 ()
1467 {
1468 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1469 State.F1 = State.F0;
1470 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1471 {
1472 State.a[OP[0]] = State.a[OP[1]];
1473 State.F0 = 1;
1474 }
1475 else
1476 State.F0 = 0;
1477 trace_output (OP_ACCUM);
1478 }
1479
1480 /* msb */
1481 void
1482 OP_2800 ()
1483 {
1484 int64 tmp;
1485
1486 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1487 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1488
1489 if (State.FX)
1490 tmp = SEXT40 ((tmp << 1) & MASK40);
1491
1492 if (State.ST && tmp > MAX32)
1493 tmp = MAX32;
1494
1495 tmp = SEXT40(State.a[OP[0]]) - tmp;
1496 if (State.ST)
1497 {
1498 if (tmp > MAX32)
1499 State.a[OP[0]] = MAX32;
1500 else if (tmp < MIN32)
1501 State.a[OP[0]] = MIN32;
1502 else
1503 State.a[OP[0]] = tmp & MASK40;
1504 }
1505 else
1506 State.a[OP[0]] = tmp & MASK40;
1507 trace_output (OP_ACCUM);
1508 }
1509
1510 /* msbsu */
1511 void
1512 OP_1800 ()
1513 {
1514 int64 tmp;
1515
1516 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1517 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1518 if (State.FX)
1519 tmp = SEXT40( (tmp << 1) & MASK40);
1520
1521 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1522 trace_output (OP_ACCUM);
1523 }
1524
1525 /* msbu */
1526 void
1527 OP_3800 ()
1528 {
1529 int64 tmp;
1530
1531 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1532 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1533 if (State.FX)
1534 tmp = SEXT40( (tmp << 1) & MASK40);
1535
1536 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1537 trace_output (OP_ACCUM);
1538 }
1539
1540 /* mul */
1541 void
1542 OP_2E00 ()
1543 {
1544 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1545 State.regs[OP[0]] *= State.regs[OP[1]];
1546 trace_output (OP_REG);
1547 }
1548
1549 /* mulx */
1550 void
1551 OP_2C00 ()
1552 {
1553 int64 tmp;
1554
1555 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1556 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1557
1558 if (State.FX)
1559 tmp = SEXT40 ((tmp << 1) & MASK40);
1560
1561 if (State.ST && tmp > MAX32)
1562 State.a[OP[0]] = MAX32;
1563 else
1564 State.a[OP[0]] = tmp & MASK40;
1565 trace_output (OP_ACCUM);
1566 }
1567
1568 /* mulxsu */
1569 void
1570 OP_1C00 ()
1571 {
1572 int64 tmp;
1573
1574 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1575 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1576
1577 if (State.FX)
1578 tmp <<= 1;
1579
1580 State.a[OP[0]] = tmp & MASK40;
1581 trace_output (OP_ACCUM);
1582 }
1583
1584 /* mulxu */
1585 void
1586 OP_3C00 ()
1587 {
1588 int64 tmp;
1589
1590 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1591 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1592
1593 if (State.FX)
1594 tmp <<= 1;
1595
1596 State.a[OP[0]] = tmp & MASK40;
1597 trace_output (OP_ACCUM);
1598 }
1599
1600 /* mv */
1601 void
1602 OP_4000 ()
1603 {
1604 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1605 State.regs[OP[0]] = State.regs[OP[1]];
1606 trace_output (OP_REG);
1607 }
1608
1609 /* mv2w */
1610 void
1611 OP_5000 ()
1612 {
1613 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1614 State.regs[OP[0]] = State.regs[OP[1]];
1615 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1616 trace_output (OP_DREG);
1617 }
1618
1619 /* mv2wfac */
1620 void
1621 OP_3E00 ()
1622 {
1623 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1624 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1625 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1626 trace_output (OP_DREG);
1627 }
1628
1629 /* mv2wtac */
1630 void
1631 OP_3E01 ()
1632 {
1633 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1634 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1635 trace_output (OP_ACCUM_REVERSE);
1636 }
1637
1638 /* mvac */
1639 void
1640 OP_3E03 ()
1641 {
1642 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1643 State.a[OP[0]] = State.a[OP[1]];
1644 trace_output (OP_ACCUM);
1645 }
1646
1647 /* mvb */
1648 void
1649 OP_5400 ()
1650 {
1651 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1652 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1653 trace_output (OP_REG);
1654 }
1655
1656 /* mvf0f */
1657 void
1658 OP_4400 ()
1659 {
1660 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1661 if (State.F0 == 0)
1662 State.regs[OP[0]] = State.regs[OP[1]];
1663 trace_output (OP_REG);
1664 }
1665
1666 /* mvf0t */
1667 void
1668 OP_4401 ()
1669 {
1670 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1671 if (State.F0)
1672 State.regs[OP[0]] = State.regs[OP[1]];
1673 trace_output (OP_REG);
1674 }
1675
1676 /* mvfacg */
1677 void
1678 OP_1E04 ()
1679 {
1680 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1681 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1682 trace_output (OP_ACCUM);
1683 }
1684
1685 /* mvfachi */
1686 void
1687 OP_1E00 ()
1688 {
1689 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1690 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1691 trace_output (OP_REG);
1692 }
1693
1694 /* mvfaclo */
1695 void
1696 OP_1E02 ()
1697 {
1698 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1699 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1700 trace_output (OP_REG);
1701 }
1702
1703 /* mvfc */
1704 void
1705 OP_5200 ()
1706 {
1707 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1708 if (OP[1] == 0)
1709 {
1710 /* PSW is treated specially */
1711 PSW = 0;
1712 if (State.SM) PSW |= 0x8000;
1713 if (State.EA) PSW |= 0x2000;
1714 if (State.DB) PSW |= 0x1000;
1715 if (State.IE) PSW |= 0x400;
1716 if (State.RP) PSW |= 0x200;
1717 if (State.MD) PSW |= 0x100;
1718 if (State.FX) PSW |= 0x80;
1719 if (State.ST) PSW |= 0x40;
1720 if (State.F0) PSW |= 8;
1721 if (State.F1) PSW |= 4;
1722 if (State.C) PSW |= 1;
1723 }
1724 State.regs[OP[0]] = State.cregs[OP[1]];
1725 trace_output (OP_REG);
1726 }
1727
1728 /* mvtacg */
1729 void
1730 OP_1E41 ()
1731 {
1732 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1733 State.a[OP[1]] &= MASK32;
1734 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1735 trace_output (OP_ACCUM_REVERSE);
1736 }
1737
1738 /* mvtachi */
1739 void
1740 OP_1E01 ()
1741 {
1742 uint16 tmp;
1743
1744 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1745 tmp = State.a[OP[1]] & 0xffff;
1746 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1747 trace_output (OP_ACCUM_REVERSE);
1748 }
1749
1750 /* mvtaclo */
1751 void
1752 OP_1E21 ()
1753 {
1754 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1755 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1756 trace_output (OP_ACCUM_REVERSE);
1757 }
1758
1759 /* mvtc */
1760 void
1761 OP_5600 ()
1762 {
1763 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1764 State.cregs[OP[1]] = State.regs[OP[0]];
1765 if (OP[1] == 0)
1766 {
1767 /* PSW is treated specially */
1768 State.SM = (PSW & 0x8000) ? 1 : 0;
1769 State.EA = (PSW & 0x2000) ? 1 : 0;
1770 State.DB = (PSW & 0x1000) ? 1 : 0;
1771 State.IE = (PSW & 0x400) ? 1 : 0;
1772 State.RP = (PSW & 0x200) ? 1 : 0;
1773 State.MD = (PSW & 0x100) ? 1 : 0;
1774 State.FX = (PSW & 0x80) ? 1 : 0;
1775 State.ST = (PSW & 0x40) ? 1 : 0;
1776 State.F0 = (PSW & 8) ? 1 : 0;
1777 State.F1 = (PSW & 4) ? 1 : 0;
1778 State.C = PSW & 1;
1779 if (State.ST && !State.FX)
1780 {
1781 (*d10v_callback->printf_filtered) (d10v_callback,
1782 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1783 PC<<2);
1784 State.exception = SIGILL;
1785 }
1786 }
1787 trace_output (OP_CR_REVERSE);
1788 }
1789
1790 /* mvub */
1791 void
1792 OP_5401 ()
1793 {
1794 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1795 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1796 trace_output (OP_REG);
1797 }
1798
1799 /* neg */
1800 void
1801 OP_4605 ()
1802 {
1803 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1804 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1805 trace_output (OP_REG);
1806 }
1807
1808 /* neg */
1809 void
1810 OP_5605 ()
1811 {
1812 int64 tmp;
1813
1814 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1815 tmp = -SEXT40(State.a[OP[0]]);
1816 if (State.ST)
1817 {
1818 if ( tmp > MAX32)
1819 State.a[OP[0]] = MAX32;
1820 else if (tmp < MIN32)
1821 State.a[OP[0]] = MIN32;
1822 else
1823 State.a[OP[0]] = tmp & MASK40;
1824 }
1825 else
1826 State.a[OP[0]] = tmp & MASK40;
1827 trace_output (OP_ACCUM);
1828 }
1829
1830
1831 /* nop */
1832 void
1833 OP_5E00 ()
1834 {
1835 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1836
1837 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1838 switch (State.ins_type)
1839 {
1840 default:
1841 ins_type_counters[ (int)INS_UNKNOWN ]++;
1842 break;
1843
1844 case INS_LEFT_PARALLEL:
1845 /* Don't count a parallel op that includes a NOP as a true parallel op */
1846 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1847 ins_type_counters[ (int)INS_RIGHT ]++;
1848 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1849 break;
1850
1851 case INS_LEFT:
1852 case INS_LEFT_COND_EXE:
1853 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1854 break;
1855
1856 case INS_RIGHT_PARALLEL:
1857 /* Don't count a parallel op that includes a NOP as a true parallel op */
1858 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1859 ins_type_counters[ (int)INS_LEFT ]++;
1860 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1861 break;
1862
1863 case INS_RIGHT:
1864 case INS_RIGHT_COND_EXE:
1865 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1866 break;
1867 }
1868
1869 trace_output (OP_VOID);
1870 }
1871
1872 /* not */
1873 void
1874 OP_4603 ()
1875 {
1876 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1877 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1878 trace_output (OP_REG);
1879 }
1880
1881 /* or */
1882 void
1883 OP_800 ()
1884 {
1885 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1886 State.regs[OP[0]] |= State.regs[OP[1]];
1887 trace_output (OP_REG);
1888 }
1889
1890 /* or3 */
1891 void
1892 OP_4000000 ()
1893 {
1894 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1895 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1896 trace_output (OP_REG);
1897 }
1898
1899 /* rac */
1900 void
1901 OP_5201 ()
1902 {
1903 int64 tmp;
1904 int shift = SEXT3 (OP[2]);
1905
1906 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1907 if (OP[1] != 0)
1908 {
1909 (*d10v_callback->printf_filtered) (d10v_callback,
1910 "ERROR at PC 0x%x: instruction only valid for A0\n",
1911 PC<<2);
1912 State.exception = SIGILL;
1913 }
1914
1915 State.F1 = State.F0;
1916 if (shift >=0)
1917 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1918 else
1919 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1920 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1921 if (tmp > MAX32)
1922 {
1923 State.regs[OP[0]] = 0x7fff;
1924 State.regs[OP[0]+1] = 0xffff;
1925 State.F0 = 1;
1926 }
1927 else if (tmp < MIN32)
1928 {
1929 State.regs[OP[0]] = 0x8000;
1930 State.regs[OP[0]+1] = 0;
1931 State.F0 = 1;
1932 }
1933 else
1934 {
1935 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1936 State.regs[OP[0]+1] = tmp & 0xffff;
1937 State.F0 = 0;
1938 }
1939 trace_output (OP_DREG);
1940 }
1941
1942 /* rachi */
1943 void
1944 OP_4201 ()
1945 {
1946 int64 tmp;
1947 int shift = SEXT3 (OP[2]);
1948
1949 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1950 State.F1 = State.F0;
1951 if (shift >=0)
1952 tmp = SEXT44 (State.a[1]) << shift;
1953 else
1954 tmp = SEXT44 (State.a[1]) >> -shift;
1955 tmp += 0x8000;
1956
1957 if (tmp > MAX32)
1958 {
1959 State.regs[OP[0]] = 0x7fff;
1960 State.F0 = 1;
1961 }
1962 else if (tmp < 0xfff80000000LL)
1963 {
1964 State.regs[OP[0]] = 0x8000;
1965 State.F0 = 1;
1966 }
1967 else
1968 {
1969 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1970 State.F0 = 0;
1971 }
1972 trace_output (OP_REG);
1973 }
1974
1975 /* rep */
1976 void
1977 OP_27000000 ()
1978 {
1979 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1980 RPT_S = PC + 1;
1981 RPT_E = PC + OP[1];
1982 RPT_C = State.regs[OP[0]];
1983 State.RP = 1;
1984 if (RPT_C == 0)
1985 {
1986 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1987 State.exception = SIGILL;
1988 }
1989 if (OP[1] < 4)
1990 {
1991 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1992 State.exception = SIGILL;
1993 }
1994 trace_output (OP_VOID);
1995 }
1996
1997 /* repi */
1998 void
1999 OP_2F000000 ()
2000 {
2001 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2002 RPT_S = PC + 1;
2003 RPT_E = PC + OP[1];
2004 RPT_C = OP[0];
2005 State.RP = 1;
2006 if (RPT_C == 0)
2007 {
2008 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2009 State.exception = SIGILL;
2010 }
2011 if (OP[1] < 4)
2012 {
2013 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2014 State.exception = SIGILL;
2015 }
2016 trace_output (OP_VOID);
2017 }
2018
2019 /* rtd */
2020 void
2021 OP_5F60 ()
2022 {
2023 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
2024 State.exception = SIGILL;
2025 }
2026
2027 /* rte */
2028 void
2029 OP_5F40 ()
2030 {
2031 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2032 PC = BPC;
2033 PSW = BPSW;
2034 trace_output (OP_VOID);
2035 }
2036
2037 /* sadd */
2038 void
2039 OP_1223 ()
2040 {
2041 int64 tmp;
2042
2043 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2044 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
2045 if (State.ST)
2046 {
2047 if (tmp > MAX32)
2048 State.a[OP[0]] = MAX32;
2049 else if (tmp < MIN32)
2050 State.a[OP[0]] = MIN32;
2051 else
2052 State.a[OP[0]] = tmp & MASK40;
2053 }
2054 else
2055 State.a[OP[0]] = tmp & MASK40;
2056 trace_output (OP_ACCUM);
2057 }
2058
2059 /* setf0f */
2060 void
2061 OP_4611 ()
2062 {
2063 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2064 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2065 trace_output (OP_REG);
2066 }
2067
2068 /* setf0t */
2069 void
2070 OP_4613 ()
2071 {
2072 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2073 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2074 trace_output (OP_REG);
2075 }
2076
2077 /* sleep */
2078 void
2079 OP_5FC0 ()
2080 {
2081 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2082 State.IE = 1;
2083 trace_output (OP_VOID);
2084 }
2085
2086 /* sll */
2087 void
2088 OP_2200 ()
2089 {
2090 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2091 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2092 trace_output (OP_REG);
2093 }
2094
2095 /* sll */
2096 void
2097 OP_3200 ()
2098 {
2099 int64 tmp;
2100 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2101 if ((State.regs[OP[1]] & 31) <= 16)
2102 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2103 else
2104 {
2105 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2106 State.exception = SIGILL;
2107 return;
2108 }
2109
2110 if (State.ST)
2111 {
2112 if (tmp > MAX32)
2113 State.a[OP[0]] = MAX32;
2114 else if (tmp < 0xffffff80000000LL)
2115 State.a[OP[0]] = MIN32;
2116 else
2117 State.a[OP[0]] = tmp & MASK40;
2118 }
2119 else
2120 State.a[OP[0]] = tmp & MASK40;
2121 trace_output (OP_ACCUM);
2122 }
2123
2124 /* slli */
2125 void
2126 OP_2201 ()
2127 {
2128 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2129 State.regs[OP[0]] <<= OP[1];
2130 trace_output (OP_REG);
2131 }
2132
2133 /* slli */
2134 void
2135 OP_3201 ()
2136 {
2137 int64 tmp;
2138
2139 if (OP[1] == 0)
2140 OP[1] = 16;
2141
2142 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2143 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2144
2145 if (State.ST)
2146 {
2147 if (tmp > MAX32)
2148 State.a[OP[0]] = MAX32;
2149 else if (tmp < 0xffffff80000000LL)
2150 State.a[OP[0]] = MIN32;
2151 else
2152 State.a[OP[0]] = tmp & MASK40;
2153 }
2154 else
2155 State.a[OP[0]] = tmp & MASK40;
2156 trace_output (OP_ACCUM);
2157 }
2158
2159 /* slx */
2160 void
2161 OP_460B ()
2162 {
2163 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2164 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2165 trace_output (OP_REG);
2166 }
2167
2168 /* sra */
2169 void
2170 OP_2400 ()
2171 {
2172 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2173 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2174 trace_output (OP_REG);
2175 }
2176
2177 /* sra */
2178 void
2179 OP_3400 ()
2180 {
2181 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2182 if ((State.regs[OP[1]] & 31) <= 16)
2183 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
2184 else
2185 {
2186 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2187 State.exception = SIGILL;
2188 return;
2189 }
2190
2191 trace_output (OP_ACCUM);
2192 }
2193
2194 /* srai */
2195 void
2196 OP_2401 ()
2197 {
2198 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2199 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2200 trace_output (OP_REG);
2201 }
2202
2203 /* srai */
2204 void
2205 OP_3401 ()
2206 {
2207 if (OP[1] == 0)
2208 OP[1] = 16;
2209
2210 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2211 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
2212 trace_output (OP_ACCUM);
2213 }
2214
2215 /* srl */
2216 void
2217 OP_2000 ()
2218 {
2219 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2220 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2221 trace_output (OP_REG);
2222 }
2223
2224 /* srl */
2225 void
2226 OP_3000 ()
2227 {
2228 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2229 if ((State.regs[OP[1]] & 31) <= 16)
2230 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
2231 else
2232 {
2233 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2234 State.exception = SIGILL;
2235 return;
2236 }
2237
2238 trace_output (OP_ACCUM);
2239 }
2240
2241 /* srli */
2242 void
2243 OP_2001 ()
2244 {
2245 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2246 State.regs[OP[0]] >>= OP[1];
2247 trace_output (OP_REG);
2248 }
2249
2250 /* srli */
2251 void
2252 OP_3001 ()
2253 {
2254 if (OP[1] == 0)
2255 OP[1] = 16;
2256
2257 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2258 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
2259 trace_output (OP_ACCUM);
2260 }
2261
2262 /* srx */
2263 void
2264 OP_4609 ()
2265 {
2266 uint16 tmp;
2267
2268 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2269 tmp = State.F0 << 15;
2270 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2271 trace_output (OP_REG);
2272 }
2273
2274 /* st */
2275 void
2276 OP_34000000 ()
2277 {
2278 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2279 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2280 trace_output (OP_VOID);
2281 }
2282
2283 /* st */
2284 void
2285 OP_6800 ()
2286 {
2287 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2288 SW (State.regs[OP[1]], State.regs[OP[0]]);
2289 trace_output (OP_VOID);
2290 }
2291
2292 /* st */
2293 void
2294 OP_6C1F ()
2295 {
2296 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2297 if ( OP[1] != 15 )
2298 {
2299 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2300 State.exception = SIGILL;
2301 return;
2302 }
2303 State.regs[OP[1]] -= 2;
2304 SW (State.regs[OP[1]], State.regs[OP[0]]);
2305 trace_output (OP_VOID);
2306 }
2307
2308 /* st */
2309 void
2310 OP_6801 ()
2311 {
2312 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2313 SW (State.regs[OP[1]], State.regs[OP[0]]);
2314 INC_ADDR (State.regs[OP[1]],2);
2315 trace_output (OP_VOID);
2316 }
2317
2318 /* st */
2319 void
2320 OP_6C01 ()
2321 {
2322 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2323 if ( OP[1] == 15 )
2324 {
2325 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2326 State.exception = SIGILL;
2327 return;
2328 }
2329 SW (State.regs[OP[1]], State.regs[OP[0]]);
2330 INC_ADDR (State.regs[OP[1]],-2);
2331 trace_output (OP_VOID);
2332 }
2333
2334 /* st2w */
2335 void
2336 OP_35000000 ()
2337 {
2338 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2339 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2340 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2341 trace_output (OP_VOID);
2342 }
2343
2344 /* st2w */
2345 void
2346 OP_6A00 ()
2347 {
2348 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2349 SW (State.regs[OP[1]], State.regs[OP[0]]);
2350 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2351 trace_output (OP_VOID);
2352 }
2353
2354 /* st2w */
2355 void
2356 OP_6E1F ()
2357 {
2358 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2359 if ( OP[1] != 15 )
2360 {
2361 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2362 State.exception = SIGILL;
2363 return;
2364 }
2365 State.regs[OP[1]] -= 4;
2366 SW (State.regs[OP[1]], State.regs[OP[0]]);
2367 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2368 trace_output (OP_VOID);
2369 }
2370
2371 /* st2w */
2372 void
2373 OP_6A01 ()
2374 {
2375 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2376 if ( OP[1] == 15 )
2377 {
2378 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2379 State.exception = SIGILL;
2380 return;
2381 }
2382 SW (State.regs[OP[1]], State.regs[OP[0]]);
2383 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2384 INC_ADDR (State.regs[OP[1]],4);
2385 trace_output (OP_VOID);
2386 }
2387
2388 /* st2w */
2389 void
2390 OP_6E01 ()
2391 {
2392 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2393 SW (State.regs[OP[1]], State.regs[OP[0]]);
2394 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2395 INC_ADDR (State.regs[OP[1]],-4);
2396 trace_output (OP_VOID);
2397 }
2398
2399 /* stb */
2400 void
2401 OP_3C000000 ()
2402 {
2403 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2404 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2405 trace_output (OP_VOID);
2406 }
2407
2408 /* stb */
2409 void
2410 OP_7800 ()
2411 {
2412 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2413 SB (State.regs[OP[1]], State.regs[OP[0]]);
2414 trace_output (OP_VOID);
2415 }
2416
2417 /* stop */
2418 void
2419 OP_5FE0 ()
2420 {
2421 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2422 State.exception = SIG_D10V_STOP;
2423 trace_output (OP_VOID);
2424 }
2425
2426 /* sub */
2427 void
2428 OP_0 ()
2429 {
2430 uint16 tmp;
2431
2432 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2433 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2434 State.C = (tmp > State.regs[OP[0]]);
2435 State.regs[OP[0]] = tmp;
2436 trace_output (OP_REG);
2437 }
2438
2439 /* sub */
2440 void
2441 OP_1001 ()
2442 {
2443 int64 tmp;
2444
2445 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2446 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2447 if (State.ST)
2448 {
2449 if ( tmp > MAX32)
2450 State.a[OP[0]] = MAX32;
2451 else if ( tmp < MIN32)
2452 State.a[OP[0]] = MIN32;
2453 else
2454 State.a[OP[0]] = tmp & MASK40;
2455 }
2456 else
2457 State.a[OP[0]] = tmp & MASK40;
2458
2459 trace_output (OP_ACCUM);
2460 }
2461
2462 /* sub */
2463
2464 void
2465 OP_1003 ()
2466 {
2467 int64 tmp;
2468
2469 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2470 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2471 if (State.ST)
2472 {
2473 if (tmp > MAX32)
2474 State.a[OP[0]] = MAX32;
2475 else if ( tmp < MIN32)
2476 State.a[OP[0]] = MIN32;
2477 else
2478 State.a[OP[0]] = tmp & MASK40;
2479 }
2480 else
2481 State.a[OP[0]] = tmp & MASK40;
2482
2483 trace_output (OP_ACCUM);
2484 }
2485
2486 /* sub2w */
2487 void
2488 OP_1000 ()
2489 {
2490 uint32 tmp,a,b;
2491
2492 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2493 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2494 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2495 tmp = a-b;
2496 State.C = (tmp > a);
2497 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2498 State.regs[OP[0]+1] = tmp & 0xffff;
2499 trace_output (OP_DREG);
2500 }
2501
2502 /* subac3 */
2503 void
2504 OP_17000000 ()
2505 {
2506 int64 tmp;
2507
2508 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2509 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2510 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2511 State.regs[OP[0]+1] = tmp & 0xffff;
2512 trace_output (OP_DREG);
2513 }
2514
2515 /* subac3 */
2516 void
2517 OP_17000002 ()
2518 {
2519 int64 tmp;
2520
2521 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2522 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2523 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2524 State.regs[OP[0]+1] = tmp & 0xffff;
2525 trace_output (OP_DREG);
2526 }
2527
2528 /* subac3s */
2529 void
2530 OP_17001000 ()
2531 {
2532 int64 tmp;
2533
2534 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2535 State.F1 = State.F0;
2536 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2537 if ( tmp > MAX32)
2538 {
2539 State.regs[OP[0]] = 0x7fff;
2540 State.regs[OP[0]+1] = 0xffff;
2541 State.F0 = 1;
2542 }
2543 else if (tmp < MIN32)
2544 {
2545 State.regs[OP[0]] = 0x8000;
2546 State.regs[OP[0]+1] = 0;
2547 State.F0 = 1;
2548 }
2549 else
2550 {
2551 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2552 State.regs[OP[0]+1] = tmp & 0xffff;
2553 State.F0 = 0;
2554 }
2555 trace_output (OP_DREG);
2556 }
2557
2558 /* subac3s */
2559 void
2560 OP_17001002 ()
2561 {
2562 int64 tmp;
2563
2564 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2565 State.F1 = State.F0;
2566 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2567 if ( tmp > MAX32)
2568 {
2569 State.regs[OP[0]] = 0x7fff;
2570 State.regs[OP[0]+1] = 0xffff;
2571 State.F0 = 1;
2572 }
2573 else if (tmp < MIN32)
2574 {
2575 State.regs[OP[0]] = 0x8000;
2576 State.regs[OP[0]+1] = 0;
2577 State.F0 = 1;
2578 }
2579 else
2580 {
2581 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2582 State.regs[OP[0]+1] = tmp & 0xffff;
2583 State.F0 = 0;
2584 }
2585 trace_output (OP_DREG);
2586 }
2587
2588 /* subi */
2589 void
2590 OP_1 ()
2591 {
2592 uint16 tmp;
2593 if (OP[1] == 0)
2594 OP[1] = 16;
2595
2596 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2597 tmp = State.regs[OP[0]] - OP[1];
2598 State.C = (tmp > State.regs[OP[0]]);
2599 State.regs[OP[0]] = tmp;
2600 trace_output (OP_REG);
2601 }
2602
2603 /* trap */
2604 void
2605 OP_5F00 ()
2606 {
2607 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2608 trace_output (OP_VOID);
2609
2610 switch (OP[0])
2611 {
2612 default:
2613 #if 0
2614 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2615 State.exception = SIGILL;
2616 #else
2617 /* Use any other traps for batch debugging. */
2618 {
2619 int i;
2620 static int first_time = 1;
2621
2622 if (first_time)
2623 {
2624 first_time = 0;
2625 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2626 for (i = 0; i < 16; i++)
2627 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2628 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2629 }
2630
2631 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2632
2633 for (i = 0; i < 16; i++)
2634 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2635
2636 for (i = 0; i < 2; i++)
2637 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2638 ((int)(State.a[i] >> 32) & 0xff),
2639 ((unsigned long)State.a[i]) & 0xffffffff);
2640
2641 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2642 State.F0 != 0, State.F1 != 0, State.C != 0);
2643 (*d10v_callback->flush_stdout) (d10v_callback);
2644 break;
2645 #endif
2646
2647 case 0:
2648 /* Trap 0 is used for simulating low-level I/O */
2649 {
2650 errno = 0;
2651
2652 /* Registers passed to trap 0 */
2653
2654 #define FUNC State.regs[6] /* function number */
2655 #define PARM1 State.regs[2] /* optional parm 1 */
2656 #define PARM2 State.regs[3] /* optional parm 2 */
2657 #define PARM3 State.regs[4] /* optional parm 3 */
2658 #define PARM4 State.regs[5] /* optional parm 3 */
2659
2660 /* Registers set by trap 0 */
2661
2662 #define RETVAL State.regs[2] /* return value */
2663 #define RETVAL_HIGH State.regs[2] /* return value */
2664 #define RETVAL_LOW State.regs[3] /* return value */
2665 #define RETERR State.regs[4] /* return error code */
2666
2667 /* Turn a pointer in a register into a pointer into real memory. */
2668
2669 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2670
2671 switch (FUNC)
2672 {
2673 #if !defined(__GO32__) && !defined(_WIN32)
2674 case SYS_fork:
2675 RETVAL = fork ();
2676 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2677 trace_output (OP_R2);
2678 break;
2679
2680 case SYS_getpid:
2681 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2682 RETVAL = getpid ();
2683 trace_output (OP_R2);
2684 break;
2685
2686 case SYS_kill:
2687 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2688 if (PARM1 == getpid ())
2689 {
2690 trace_output (OP_VOID);
2691 State.exception = PARM2;
2692 }
2693 else
2694 {
2695 int os_sig = -1;
2696 switch (PARM2)
2697 {
2698 #ifdef SIGHUP
2699 case 1: os_sig = SIGHUP; break;
2700 #endif
2701 #ifdef SIGINT
2702 case 2: os_sig = SIGINT; break;
2703 #endif
2704 #ifdef SIGQUIT
2705 case 3: os_sig = SIGQUIT; break;
2706 #endif
2707 #ifdef SIGILL
2708 case 4: os_sig = SIGILL; break;
2709 #endif
2710 #ifdef SIGTRAP
2711 case 5: os_sig = SIGTRAP; break;
2712 #endif
2713 #ifdef SIGABRT
2714 case 6: os_sig = SIGABRT; break;
2715 #elif defined(SIGIOT)
2716 case 6: os_sig = SIGIOT; break;
2717 #endif
2718 #ifdef SIGEMT
2719 case 7: os_sig = SIGEMT; break;
2720 #endif
2721 #ifdef SIGFPE
2722 case 8: os_sig = SIGFPE; break;
2723 #endif
2724 #ifdef SIGKILL
2725 case 9: os_sig = SIGKILL; break;
2726 #endif
2727 #ifdef SIGBUS
2728 case 10: os_sig = SIGBUS; break;
2729 #endif
2730 #ifdef SIGSEGV
2731 case 11: os_sig = SIGSEGV; break;
2732 #endif
2733 #ifdef SIGSYS
2734 case 12: os_sig = SIGSYS; break;
2735 #endif
2736 #ifdef SIGPIPE
2737 case 13: os_sig = SIGPIPE; break;
2738 #endif
2739 #ifdef SIGALRM
2740 case 14: os_sig = SIGALRM; break;
2741 #endif
2742 #ifdef SIGTERM
2743 case 15: os_sig = SIGTERM; break;
2744 #endif
2745 #ifdef SIGURG
2746 case 16: os_sig = SIGURG; break;
2747 #endif
2748 #ifdef SIGSTOP
2749 case 17: os_sig = SIGSTOP; break;
2750 #endif
2751 #ifdef SIGTSTP
2752 case 18: os_sig = SIGTSTP; break;
2753 #endif
2754 #ifdef SIGCONT
2755 case 19: os_sig = SIGCONT; break;
2756 #endif
2757 #ifdef SIGCHLD
2758 case 20: os_sig = SIGCHLD; break;
2759 #elif defined(SIGCLD)
2760 case 20: os_sig = SIGCLD; break;
2761 #endif
2762 #ifdef SIGTTIN
2763 case 21: os_sig = SIGTTIN; break;
2764 #endif
2765 #ifdef SIGTTOU
2766 case 22: os_sig = SIGTTOU; break;
2767 #endif
2768 #ifdef SIGIO
2769 case 23: os_sig = SIGIO; break;
2770 #elif defined (SIGPOLL)
2771 case 23: os_sig = SIGPOLL; break;
2772 #endif
2773 #ifdef SIGXCPU
2774 case 24: os_sig = SIGXCPU; break;
2775 #endif
2776 #ifdef SIGXFSZ
2777 case 25: os_sig = SIGXFSZ; break;
2778 #endif
2779 #ifdef SIGVTALRM
2780 case 26: os_sig = SIGVTALRM; break;
2781 #endif
2782 #ifdef SIGPROF
2783 case 27: os_sig = SIGPROF; break;
2784 #endif
2785 #ifdef SIGWINCH
2786 case 28: os_sig = SIGWINCH; break;
2787 #endif
2788 #ifdef SIGLOST
2789 case 29: os_sig = SIGLOST; break;
2790 #endif
2791 #ifdef SIGUSR1
2792 case 30: os_sig = SIGUSR1; break;
2793 #endif
2794 #ifdef SIGUSR2
2795 case 31: os_sig = SIGUSR2; break;
2796 #endif
2797 }
2798
2799 if (os_sig == -1)
2800 {
2801 trace_output (OP_VOID);
2802 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2803 (*d10v_callback->flush_stdout) (d10v_callback);
2804 State.exception = SIGILL;
2805 }
2806 else
2807 {
2808 RETVAL = kill (PARM1, PARM2);
2809 trace_output (OP_R2);
2810 }
2811 }
2812 break;
2813
2814 case SYS_execve:
2815 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2816 (char **)MEMPTR (PARM3));
2817 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2818 trace_output (OP_R2);
2819 break;
2820
2821 case SYS_execv:
2822 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2823 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2824 trace_output (OP_R2);
2825 break;
2826
2827 case SYS_pipe:
2828 {
2829 reg_t buf;
2830 int host_fd[2];
2831
2832 buf = PARM1;
2833 RETVAL = pipe (host_fd);
2834 SW (buf, host_fd[0]);
2835 buf += sizeof(uint16);
2836 SW (buf, host_fd[1]);
2837 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2838 trace_output (OP_R2);
2839 }
2840 break;
2841
2842 case SYS_wait:
2843 {
2844 int status;
2845
2846 RETVAL = wait (&status);
2847 if (PARM1)
2848 SW (PARM1, status);
2849 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2850 trace_output (OP_R2);
2851 }
2852 break;
2853 #else
2854 case SYS_getpid:
2855 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2856 RETVAL = 1;
2857 trace_output (OP_R2);
2858 break;
2859
2860 case SYS_kill:
2861 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2862 trace_output (OP_VOID);
2863 State.exception = PARM2;
2864 break;
2865 #endif
2866
2867 case SYS_read:
2868 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2869 PARM3);
2870 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2871 trace_output (OP_R2);
2872 break;
2873
2874 case SYS_write:
2875 if (PARM1 == 1)
2876 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2877 MEMPTR (PARM2), PARM3);
2878 else
2879 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2880 MEMPTR (PARM2), PARM3);
2881 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2882 trace_output (OP_R2);
2883 break;
2884
2885 case SYS_lseek:
2886 {
2887 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2888 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2889 PARM4);
2890 RETVAL_HIGH = ret >> 16;
2891 RETVAL_LOW = ret & 0xffff;
2892 }
2893 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2894 trace_output (OP_R2R3);
2895 break;
2896
2897 case SYS_close:
2898 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2899 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2900 trace_output (OP_R2);
2901 break;
2902
2903 case SYS_open:
2904 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2905 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2906 trace_output (OP_R2);
2907 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2908 trace_output (OP_R2);
2909 break;
2910
2911 case SYS_exit:
2912 State.exception = SIG_D10V_EXIT;
2913 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2914 trace_output (OP_VOID);
2915 break;
2916
2917 case SYS_stat:
2918 /* stat system call */
2919 {
2920 struct stat host_stat;
2921 reg_t buf;
2922
2923 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2924
2925 buf = PARM2;
2926
2927 /* The hard-coded offsets and sizes were determined by using
2928 * the D10V compiler on a test program that used struct stat.
2929 */
2930 SW (buf, host_stat.st_dev);
2931 SW (buf+2, host_stat.st_ino);
2932 SW (buf+4, host_stat.st_mode);
2933 SW (buf+6, host_stat.st_nlink);
2934 SW (buf+8, host_stat.st_uid);
2935 SW (buf+10, host_stat.st_gid);
2936 SW (buf+12, host_stat.st_rdev);
2937 SLW (buf+16, host_stat.st_size);
2938 SLW (buf+20, host_stat.st_atime);
2939 SLW (buf+28, host_stat.st_mtime);
2940 SLW (buf+36, host_stat.st_ctime);
2941 }
2942 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2943 trace_output (OP_R2);
2944 break;
2945
2946 case SYS_chown:
2947 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2948 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2949 trace_output (OP_R2);
2950 break;
2951
2952 case SYS_chmod:
2953 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2954 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2955 trace_output (OP_R2);
2956 break;
2957
2958 case SYS_utime:
2959 /* Cast the second argument to void *, to avoid type mismatch
2960 if a prototype is present. */
2961 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2962 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2963 trace_output (OP_R2);
2964 break;
2965
2966 case SYS_time:
2967 {
2968 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2969 RETVAL_HIGH = ret >> 16;
2970 RETVAL_LOW = ret & 0xffff;
2971 }
2972 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2973 trace_output (OP_R2R3);
2974 break;
2975
2976 default:
2977 abort ();
2978 }
2979 RETERR = d10v_callback->get_errno(d10v_callback);
2980 break;
2981 }
2982
2983 case 1:
2984 /* Trap 1 prints a string */
2985 {
2986 char *fstr = dmem_addr(State.regs[2]);
2987 fputs (fstr, stdout);
2988 break;
2989 }
2990
2991 case 2:
2992 /* Trap 2 calls printf */
2993 {
2994 char *fstr = dmem_addr(State.regs[2]);
2995 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2996 (int16)State.regs[3],
2997 (int16)State.regs[4],
2998 (int16)State.regs[5]);
2999 (*d10v_callback->flush_stdout) (d10v_callback);
3000 break;
3001 }
3002
3003 case 3:
3004 /* Trap 3 writes a character */
3005 putchar (State.regs[2]);
3006 break;
3007 }
3008 }
3009 }
3010
3011 /* tst0i */
3012 void
3013 OP_7000000 ()
3014 {
3015 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3016 State.F1 = State.F0;
3017 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
3018 trace_output (OP_FLAG);
3019 }
3020
3021 /* tst1i */
3022 void
3023 OP_F000000 ()
3024 {
3025 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3026 State.F1 = State.F0;
3027 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
3028 trace_output (OP_FLAG);
3029 }
3030
3031 /* wait */
3032 void
3033 OP_5F80 ()
3034 {
3035 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3036 State.IE = 1;
3037 trace_output (OP_VOID);
3038 }
3039
3040 /* xor */
3041 void
3042 OP_A00 ()
3043 {
3044 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3045 State.regs[OP[0]] ^= State.regs[OP[1]];
3046 trace_output (OP_REG);
3047 }
3048
3049 /* xor3 */
3050 void
3051 OP_5000000 ()
3052 {
3053 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3054 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
3055 trace_output (OP_REG);
3056 }
3057
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