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Fix accumulator shifts
[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include <signal.h>
2 #include <errno.h>
3 #include <sys/types.h>
4 #include <sys/stat.h>
5 #include <unistd.h>
6
7 #include "d10v_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10
11 enum op_types {
12 OP_VOID,
13 OP_REG,
14 OP_REG_OUTPUT,
15 OP_DREG,
16 OP_DREG_OUTPUT,
17 OP_ACCUM,
18 OP_ACCUM_OUTPUT,
19 OP_ACCUM_REVERSE,
20 OP_CR,
21 OP_CR_OUTPUT,
22 OP_CR_REVERSE,
23 OP_FLAG,
24 OP_CONSTANT16,
25 OP_CONSTANT3,
26 OP_CONSTANT4,
27 OP_MEMREF,
28 OP_MEMREF2,
29 OP_POSTDEC,
30 OP_POSTINC,
31 OP_PREDEC
32 };
33
34 #ifdef DEBUG
35 static void trace_input PARAMS ((char *name,
36 enum op_types in1,
37 enum op_types in2,
38 enum op_types in3));
39
40 static void trace_output PARAMS ((enum op_types result));
41
42 #ifndef SIZE_INSTRUCTION
43 #define SIZE_INSTRUCTION 10
44 #endif
45
46 #ifndef SIZE_OPERANDS
47 #define SIZE_OPERANDS 24
48 #endif
49
50 #ifndef SIZE_VALUES
51 #define SIZE_VALUES 13
52 #endif
53
54 static void
55 trace_input (name, in1, in2, in3)
56 char *name;
57 enum op_types in1;
58 enum op_types in2;
59 enum op_types in3;
60 {
61 char *comma;
62 enum op_types in[3];
63 int i;
64 char buf[80];
65 char *p;
66 long tmp;
67 char *type;
68
69 if ((d10v_debug & DEBUG_TRACE) == 0)
70 return;
71
72 switch (State.ins_type)
73 {
74 default:
75 case INS_UNKNOWN: type = " ?"; break;
76 case INS_LEFT: type = " L"; break;
77 case INS_RIGHT: type = " R"; break;
78 case INS_LEFT_PARALLEL: type = "*L"; break;
79 case INS_RIGHT_PARALLEL: type = "*R"; break;
80 case INS_LONG: type = " B"; break;
81 }
82
83 (*d10v_callback->printf_filtered) (d10v_callback,
84 "0x%.6x %s: %-*s",
85 (unsigned)PC, type,
86 SIZE_INSTRUCTION, name);
87
88 in[0] = in1;
89 in[1] = in2;
90 in[2] = in3;
91 comma = "";
92 p = buf;
93 for (i = 0; i < 3; i++)
94 {
95 switch (in[i])
96 {
97 case OP_VOID:
98 break;
99
100 case OP_REG:
101 case OP_REG_OUTPUT:
102 case OP_DREG:
103 case OP_DREG_OUTPUT:
104 sprintf (p, "%sr%d", comma, OP[i]);
105 p += strlen (p);
106 comma = ",";
107 break;
108
109 case OP_CR:
110 case OP_CR_OUTPUT:
111 case OP_CR_REVERSE:
112 sprintf (p, "%scr%d", comma, OP[i]);
113 p += strlen (p);
114 comma = ",";
115 break;
116
117 case OP_ACCUM:
118 case OP_ACCUM_OUTPUT:
119 case OP_ACCUM_REVERSE:
120 sprintf (p, "%sa%d", comma, OP[i]);
121 p += strlen (p);
122 comma = ",";
123 break;
124
125 case OP_CONSTANT16:
126 sprintf (p, "%s%d", comma, OP[i]);
127 p += strlen (p);
128 comma = ",";
129 break;
130
131 case OP_CONSTANT4:
132 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
133 p += strlen (p);
134 comma = ",";
135 break;
136
137 case OP_CONSTANT3:
138 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
139 p += strlen (p);
140 comma = ",";
141 break;
142
143 case OP_MEMREF:
144 sprintf (p, "%s@r%d", comma, OP[i]);
145 p += strlen (p);
146 comma = ",";
147 break;
148
149 case OP_MEMREF2:
150 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
151 p += strlen (p);
152 comma = ",";
153 break;
154
155 case OP_POSTINC:
156 sprintf (p, "%s@r%d+", comma, OP[i]);
157 p += strlen (p);
158 comma = ",";
159 break;
160
161 case OP_POSTDEC:
162 sprintf (p, "%s@r%d-", comma, OP[i]);
163 p += strlen (p);
164 comma = ",";
165 break;
166
167 case OP_PREDEC:
168 sprintf (p, "%s@-r%d", comma, OP[i]);
169 p += strlen (p);
170 comma = ",";
171 break;
172
173 case OP_FLAG:
174 if (OP[i] == 0)
175 sprintf (p, "%sf0", comma);
176
177 else if (OP[i] == 1)
178 sprintf (p, "%sf1", comma);
179
180 else
181 sprintf (p, "%scarry", comma);
182
183 p += strlen (p);
184 comma = ",";
185 break;
186 }
187 }
188
189 if ((d10v_debug & DEBUG_VALUES) == 0)
190 {
191 *p++ = '\n';
192 *p = '\0';
193 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
194 }
195 else
196 {
197 *p = '\0';
198 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
199
200 p = buf;
201 for (i = 0; i < 3; i++)
202 {
203 buf[0] = '\0';
204 switch (in[i])
205 {
206 case OP_VOID:
207 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
208 break;
209
210 case OP_REG_OUTPUT:
211 case OP_DREG_OUTPUT:
212 case OP_CR_OUTPUT:
213 case OP_ACCUM_OUTPUT:
214 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
215 break;
216
217 case OP_REG:
218 case OP_MEMREF:
219 case OP_POSTDEC:
220 case OP_POSTINC:
221 case OP_PREDEC:
222 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
223 (uint16)State.regs[OP[i]]);
224 break;
225
226 case OP_DREG:
227 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
228 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
229 break;
230
231 case OP_CR:
232 case OP_CR_REVERSE:
233 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
234 (uint16)State.cregs[OP[i]]);
235 break;
236
237 case OP_ACCUM:
238 case OP_ACCUM_REVERSE:
239 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
240 ((int)(State.a[OP[i]] >> 32) & 0xff),
241 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
242 break;
243
244 case OP_CONSTANT16:
245 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
246 (uint16)OP[i]);
247 break;
248
249 case OP_CONSTANT4:
250 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
251 (uint16)SEXT4(OP[i]));
252 break;
253
254 case OP_CONSTANT3:
255 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
256 (uint16)SEXT3(OP[i]));
257 break;
258
259 case OP_FLAG:
260 if (OP[i] == 0)
261 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
262 State.F0 != 0);
263
264 else if (OP[i] == 1)
265 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
266 State.F1 != 0);
267
268 else
269 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
270 State.C != 0);
271
272 break;
273
274 case OP_MEMREF2:
275 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
276 (uint16)OP[i]);
277 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
278 (uint16)State.regs[OP[++i]]);
279 break;
280 }
281 }
282 }
283 }
284
285 static void
286 trace_output (result)
287 enum op_types result;
288 {
289 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
290 {
291 long tmp;
292
293 switch (result)
294 {
295 default:
296 putchar ('\n');
297 break;
298
299 case OP_REG:
300 case OP_REG_OUTPUT:
301 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
302 (uint16)State.regs[OP[0]],
303 State.F0 != 0, State.F1 != 0, State.C != 0);
304 break;
305
306 case OP_DREG:
307 case OP_DREG_OUTPUT:
308 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
309 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
310 State.F0 != 0, State.F1 != 0, State.C != 0);
311 break;
312
313 case OP_CR:
314 case OP_CR_OUTPUT:
315 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
316 (uint16)State.cregs[OP[0]],
317 State.F0 != 0, State.F1 != 0, State.C != 0);
318 break;
319
320 case OP_CR_REVERSE:
321 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
322 (uint16)State.cregs[OP[1]],
323 State.F0 != 0, State.F1 != 0, State.C != 0);
324 break;
325
326 case OP_ACCUM:
327 case OP_ACCUM_OUTPUT:
328 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
329 ((int)(State.a[OP[0]] >> 32) & 0xff),
330 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
331 State.F0 != 0, State.F1 != 0, State.C != 0);
332 break;
333
334 case OP_ACCUM_REVERSE:
335 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
336 ((int)(State.a[OP[1]] >> 32) & 0xff),
337 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
338 State.F0 != 0, State.F1 != 0, State.C != 0);
339 break;
340
341 case OP_FLAG:
342 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
343 State.F0 != 0, State.F1 != 0, State.C != 0);
344 break;
345 }
346 }
347 }
348
349 #else
350 #define trace_input(NAME, IN1, IN2, IN3)
351 #define trace_output(RESULT)
352 #endif
353
354 /* abs */
355 void
356 OP_4607 ()
357 {
358 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
359 State.F1 = State.F0;
360 if ((int16)(State.regs[OP[0]]) < 0)
361 {
362 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
363 State.F0 = 1;
364 }
365 else
366 State.F0 = 0;
367 trace_output (OP_REG);
368 }
369
370 /* abs */
371 void
372 OP_5607 ()
373 {
374 int64 tmp;
375
376 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
377 State.F1 = State.F0;
378 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
379
380 if (State.a[OP[0]] < 0 )
381 {
382 tmp = -State.a[OP[0]];
383 if (State.ST)
384 {
385 if (tmp > MAX32)
386 State.a[OP[0]] = MAX32;
387 else if (tmp < MIN32)
388 State.a[OP[0]] = MIN32;
389 else
390 State.a[OP[0]] = tmp & MASK40;
391 }
392 else
393 State.a[OP[0]] = tmp & MASK40;
394 State.F0 = 1;
395 }
396 else
397 State.F0 = 0;
398 trace_output (OP_ACCUM);
399 }
400
401 /* add */
402 void
403 OP_200 ()
404 {
405 uint16 tmp = State.regs[OP[0]];
406 trace_input ("add", OP_REG, OP_REG, OP_VOID);
407 State.regs[OP[0]] += State.regs[OP[1]];
408 if ( tmp > State.regs[OP[0]])
409 State.C = 1;
410 else
411 State.C = 0;
412 trace_output (OP_REG);
413 }
414
415 /* add */
416 void
417 OP_1201 ()
418 {
419 int64 tmp;
420 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
421
422 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
423 if (State.ST)
424 {
425 if ( tmp > MAX32)
426 State.a[OP[0]] = MAX32;
427 else if ( tmp < MIN32)
428 State.a[OP[0]] = MIN32;
429 else
430 State.a[OP[0]] = tmp & MASK40;
431 }
432 else
433 State.a[OP[0]] = tmp & MASK40;
434 trace_output (OP_ACCUM);
435 }
436
437 /* add */
438 void
439 OP_1203 ()
440 {
441 int64 tmp;
442 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
443
444 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
445 if (State.ST)
446 {
447 if (tmp > MAX32)
448 State.a[OP[0]] = MAX32;
449 else if ( tmp < MIN32)
450 State.a[OP[0]] = MIN32;
451 else
452 State.a[OP[0]] = tmp & MASK40;
453 }
454 else
455 State.a[OP[0]] = tmp & MASK40;
456 trace_output (OP_ACCUM);
457 }
458
459 /* add2w */
460 void
461 OP_1200 ()
462 {
463 uint32 tmp;
464 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
465 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
466
467 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
468 tmp = tmp1 + tmp2;
469 if ( (tmp < tmp1) || (tmp < tmp2) )
470 State.C = 1;
471 else
472 State.C = 0;
473 State.regs[OP[0]] = tmp >> 16;
474 State.regs[OP[0]+1] = tmp & 0xFFFF;
475 trace_output (OP_DREG);
476 }
477
478 /* add3 */
479 void
480 OP_1000000 ()
481 {
482 uint16 tmp = State.regs[OP[0]];
483 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
484
485 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
486 if ( tmp > State.regs[OP[0]])
487 State.C = 1;
488 else
489 State.C = 0;
490 trace_output (OP_REG);
491 }
492
493 /* addac3 */
494 void
495 OP_17000200 ()
496 {
497 int64 tmp;
498 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
499
500 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
501 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
502 State.regs[OP[0]+1] = tmp & 0xffff;
503 trace_output (OP_DREG);
504 }
505
506 /* addac3 */
507 void
508 OP_17000202 ()
509 {
510 int64 tmp;
511 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
512
513 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
514 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
515 State.regs[OP[0]+1] = tmp & 0xffff;
516 trace_output (OP_DREG);
517 }
518
519 /* addac3s */
520 void
521 OP_17001200 ()
522 {
523 int64 tmp;
524 State.F1 = State.F0;
525
526 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
527 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
528 if ( tmp > MAX32)
529 {
530 State.regs[OP[0]] = 0x7fff;
531 State.regs[OP[0]+1] = 0xffff;
532 State.F0 = 1;
533 }
534 else if (tmp < MIN32)
535 {
536 State.regs[OP[0]] = 0x8000;
537 State.regs[OP[0]+1] = 0;
538 State.F0 = 1;
539 }
540 else
541 {
542 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
543 State.regs[OP[0]+1] = tmp & 0xffff;
544 State.F0 = 0;
545 }
546 trace_output (OP_DREG);
547 }
548
549 /* addac3s */
550 void
551 OP_17001202 ()
552 {
553 int64 tmp;
554 State.F1 = State.F0;
555
556 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
557 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
558 if ( tmp > MAX32)
559 {
560 State.regs[OP[0]] = 0x7fff;
561 State.regs[OP[0]+1] = 0xffff;
562 State.F0 = 1;
563 }
564 else if (tmp < MIN32)
565 {
566 State.regs[OP[0]] = 0x8000;
567 State.regs[OP[0]+1] = 0;
568 State.F0 = 1;
569 }
570 else
571 {
572 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
573 State.regs[OP[0]+1] = tmp & 0xffff;
574 State.F0 = 0;
575 }
576 trace_output (OP_DREG);
577 }
578
579 /* addi */
580 void
581 OP_201 ()
582 {
583 if (OP[1] == 0)
584 OP[1] = 16;
585 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
586 State.regs[OP[0]] += OP[1];
587 trace_output (OP_REG);
588 }
589
590 /* and */
591 void
592 OP_C00 ()
593 {
594 trace_input ("and", OP_REG, OP_REG, OP_VOID);
595 State.regs[OP[0]] &= State.regs[OP[1]];
596 trace_output (OP_REG);
597 }
598
599 /* and3 */
600 void
601 OP_6000000 ()
602 {
603 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
604 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
605 trace_output (OP_REG);
606 }
607
608 /* bclri */
609 void
610 OP_C01 ()
611 {
612 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
613 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
614 trace_output (OP_REG);
615 }
616
617 /* bl.s */
618 void
619 OP_4900 ()
620 {
621 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
622 State.regs[13] = PC+1;
623 PC += SEXT8 (OP[0]);
624 trace_output (OP_VOID);
625 }
626
627 /* bl.l */
628 void
629 OP_24800000 ()
630 {
631 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
632 State.regs[13] = PC+1;
633 PC += OP[0];
634 trace_output (OP_VOID);
635 }
636
637 /* bnoti */
638 void
639 OP_A01 ()
640 {
641 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
642 State.regs[OP[0]] ^= 0x8000 >> OP[1];
643 trace_output (OP_REG);
644 }
645
646 /* bra.s */
647 void
648 OP_4800 ()
649 {
650 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
651 PC += SEXT8 (OP[0]);
652 trace_output (OP_VOID);
653 }
654
655 /* bra.l */
656 void
657 OP_24000000 ()
658 {
659 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
660 PC += OP[0];
661 trace_output (OP_VOID);
662 }
663
664 /* brf0f.s */
665 void
666 OP_4A00 ()
667 {
668 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
669 if (State.F0 == 0)
670 PC += SEXT8 (OP[0]);
671 trace_output (OP_FLAG);
672 }
673
674 /* brf0f.l */
675 void
676 OP_25000000 ()
677 {
678 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
679 if (State.F0 == 0)
680 PC += OP[0];
681 trace_output (OP_FLAG);
682 }
683
684 /* brf0t.s */
685 void
686 OP_4B00 ()
687 {
688 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
689 if (State.F0)
690 PC += SEXT8 (OP[0]);
691 trace_output (OP_FLAG);
692 }
693
694 /* brf0t.l */
695 void
696 OP_25800000 ()
697 {
698 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
699 if (State.F0)
700 PC += OP[0];
701 trace_output (OP_FLAG);
702 }
703
704 /* bseti */
705 void
706 OP_801 ()
707 {
708 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
709 State.regs[OP[0]] |= 0x8000 >> OP[1];
710 trace_output (OP_REG);
711 }
712
713 /* btsti */
714 void
715 OP_E01 ()
716 {
717 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
718 State.F1 = State.F0;
719 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
720 trace_output (OP_FLAG);
721 }
722
723 /* clrac */
724 void
725 OP_5601 ()
726 {
727 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
728 State.a[OP[0]] = 0;
729 trace_output (OP_ACCUM);
730 }
731
732 /* cmp */
733 void
734 OP_600 ()
735 {
736 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
737 State.F1 = State.F0;
738 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
739 trace_output (OP_FLAG);
740 }
741
742 /* cmp */
743 void
744 OP_1603 ()
745 {
746 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
747 State.F1 = State.F0;
748 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
749 trace_output (OP_FLAG);
750 }
751
752 /* cmpeq */
753 void
754 OP_400 ()
755 {
756 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
757 State.F1 = State.F0;
758 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
759 trace_output (OP_FLAG);
760 }
761
762 /* cmpeq */
763 void
764 OP_1403 ()
765 {
766 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
767 State.F1 = State.F0;
768 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
769 trace_output (OP_FLAG);
770 }
771
772 /* cmpeqi.s */
773 void
774 OP_401 ()
775 {
776 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
777 State.F1 = State.F0;
778 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
779 trace_output (OP_FLAG);
780 }
781
782 /* cmpeqi.l */
783 void
784 OP_2000000 ()
785 {
786 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
787 State.F1 = State.F0;
788 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
789 trace_output (OP_FLAG);
790 }
791
792 /* cmpi.s */
793 void
794 OP_601 ()
795 {
796 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
797 State.F1 = State.F0;
798 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
799 trace_output (OP_FLAG);
800 }
801
802 /* cmpi.l */
803 void
804 OP_3000000 ()
805 {
806 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
807 State.F1 = State.F0;
808 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
809 trace_output (OP_FLAG);
810 }
811
812 /* cmpu */
813 void
814 OP_4600 ()
815 {
816 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
817 State.F1 = State.F0;
818 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
819 trace_output (OP_FLAG);
820 }
821
822 /* cmpui */
823 void
824 OP_23000000 ()
825 {
826 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
827 State.F1 = State.F0;
828 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
829 trace_output (OP_FLAG);
830 }
831
832 /* cpfg */
833 void
834 OP_4E09 ()
835 {
836 uint8 *src, *dst;
837
838 trace_input ("cpfg", OP_FLAG, OP_VOID, OP_VOID);
839 if (OP[0] == 0)
840 dst = &State.F0;
841 else
842 dst = &State.F1;
843
844 if (OP[1] == 0)
845 src = &State.F0;
846 else if (OP[1] == 1)
847 src = &State.F1;
848 else
849 src = &State.C;
850
851 *dst = *src;
852 trace_output (OP_FLAG);
853 }
854
855 /* dbt */
856 void
857 OP_5F20 ()
858 {
859 d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC);
860 State.exception = SIGTRAP;
861 }
862
863 /* divs */
864 void
865 OP_14002800 ()
866 {
867 uint16 foo, tmp, tmpf;
868
869 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
870 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
871 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
872 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
873 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
874 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
875 trace_output (OP_DREG);
876 }
877
878 /* exef0f */
879 void
880 OP_4E04 ()
881 {
882 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
883 State.exe = (State.F0) ? 0 : 1;
884 trace_output (OP_FLAG);
885 }
886
887 /* exef0t */
888 void
889 OP_4E24 ()
890 {
891 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
892 State.exe = State.F0;
893 trace_output (OP_FLAG);
894 }
895
896 /* exef1f */
897 void
898 OP_4E40 ()
899 {
900 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
901 State.exe = (State.F1) ? 0 : 1;
902 trace_output (OP_FLAG);
903 }
904
905 /* exef1t */
906 void
907 OP_4E42 ()
908 {
909 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
910 State.exe = State.F1;
911 trace_output (OP_FLAG);
912 }
913
914 /* exefaf */
915 void
916 OP_4E00 ()
917 {
918 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
919 State.exe = (State.F0 | State.F1) ? 0 : 1;
920 trace_output (OP_FLAG);
921 }
922
923 /* exefat */
924 void
925 OP_4E02 ()
926 {
927 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
928 State.exe = (State.F0) ? 0 : (State.F1);
929 trace_output (OP_FLAG);
930 }
931
932 /* exetaf */
933 void
934 OP_4E20 ()
935 {
936 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
937 State.exe = (State.F1) ? 0 : (State.F0);
938 trace_output (OP_FLAG);
939 }
940
941 /* exetat */
942 void
943 OP_4E22 ()
944 {
945 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
946 State.exe = (State.F0) ? (State.F1) : 0;
947 trace_output (OP_FLAG);
948 }
949
950 /* exp */
951 void
952 OP_15002A00 ()
953 {
954 uint32 tmp, foo;
955 int i;
956
957 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
958 if (((int16)State.regs[OP[1]]) >= 0)
959 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
960 else
961 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
962
963 foo = 0x40000000;
964 for (i=1;i<17;i++)
965 {
966 if (tmp & foo)
967 {
968 State.regs[OP[0]] = i-1;
969 trace_output (OP_REG);
970 return;
971 }
972 foo >>= 1;
973 }
974 State.regs[OP[0]] = 16;
975 trace_output (OP_REG);
976 }
977
978 /* exp */
979 void
980 OP_15002A02 ()
981 {
982 int64 tmp, foo;
983 int i;
984
985 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
986 if (SEXT40(State.a[OP[1]]) >= 0)
987 tmp = State.a[OP[1]];
988 else
989 tmp = ~(State.a[OP[1]]);
990
991 foo = 0x4000000000LL;
992 for (i=1;i<25;i++)
993 {
994 if (tmp & foo)
995 {
996 State.regs[OP[0]] = i-9;
997 trace_output (OP_REG);
998 return;
999 }
1000 foo >>= 1;
1001 }
1002 State.regs[OP[0]] = 16;
1003 trace_output (OP_REG);
1004 }
1005
1006 /* jl */
1007 void
1008 OP_4D00 ()
1009 {
1010 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
1011 State.regs[13] = PC+1;
1012 PC = State.regs[OP[0]];
1013 trace_output (OP_VOID);
1014 }
1015
1016 /* jmp */
1017 void
1018 OP_4C00 ()
1019 {
1020 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
1021 PC = State.regs[OP[0]];
1022 trace_output (OP_VOID);
1023 }
1024
1025 /* ld */
1026 void
1027 OP_30000000 ()
1028 {
1029 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1030 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1031 trace_output (OP_REG);
1032 }
1033
1034 /* ld */
1035 void
1036 OP_6401 ()
1037 {
1038 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1039 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1040 INC_ADDR(State.regs[OP[1]],-2);
1041 trace_output (OP_REG);
1042 }
1043
1044 /* ld */
1045 void
1046 OP_6001 ()
1047 {
1048 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1049 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1050 INC_ADDR(State.regs[OP[1]],2);
1051 trace_output (OP_REG);
1052 }
1053
1054 /* ld */
1055 void
1056 OP_6000 ()
1057 {
1058 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1059 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1060 trace_output (OP_REG);
1061 }
1062
1063 /* ld2w */
1064 void
1065 OP_31000000 ()
1066 {
1067 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1068 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1069 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
1070 trace_output (OP_DREG);
1071 }
1072
1073 /* ld2w */
1074 void
1075 OP_6601 ()
1076 {
1077 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1078 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1079 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1080 INC_ADDR(State.regs[OP[1]],-4);
1081 trace_output (OP_DREG);
1082 }
1083
1084 /* ld2w */
1085 void
1086 OP_6201 ()
1087 {
1088 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1089 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1090 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1091 INC_ADDR(State.regs[OP[1]],4);
1092 trace_output (OP_REG);
1093 }
1094
1095 /* ld2w */
1096 void
1097 OP_6200 ()
1098 {
1099 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1100 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1101 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1102 trace_output (OP_REG);
1103 }
1104
1105 /* ldb */
1106 void
1107 OP_38000000 ()
1108 {
1109 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1110 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1111 SEXT8 (State.regs[OP[0]]);
1112 trace_output (OP_REG);
1113 }
1114
1115 /* ldb */
1116 void
1117 OP_7000 ()
1118 {
1119 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1120 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1121 SEXT8 (State.regs[OP[0]]);
1122 trace_output (OP_REG);
1123 }
1124
1125 /* ldi.s */
1126 void
1127 OP_4001 ()
1128 {
1129 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1130 State.regs[OP[0]] = SEXT4(OP[1]);
1131 trace_output (OP_REG);
1132 }
1133
1134 /* ldi.l */
1135 void
1136 OP_20000000 ()
1137 {
1138 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1139 State.regs[OP[0]] = OP[1];
1140 trace_output (OP_REG);
1141 }
1142
1143 /* ldub */
1144 void
1145 OP_39000000 ()
1146 {
1147 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1148 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1149 trace_output (OP_REG);
1150 }
1151
1152 /* ldub */
1153 void
1154 OP_7200 ()
1155 {
1156 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1157 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1158 trace_output (OP_REG);
1159 }
1160
1161 /* mac */
1162 void
1163 OP_2A00 ()
1164 {
1165 int64 tmp;
1166
1167 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1168 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1169
1170 if (State.FX)
1171 tmp = SEXT40( (tmp << 1) & MASK40);
1172
1173 if (State.ST && tmp > MAX32)
1174 tmp = MAX32;
1175
1176 tmp += SEXT40(State.a[OP[0]]);
1177 if (State.ST)
1178 {
1179 if (tmp > MAX32)
1180 State.a[OP[0]] = MAX32;
1181 else if (tmp < MIN32)
1182 State.a[OP[0]] = MIN32;
1183 else
1184 State.a[OP[0]] = tmp & MASK40;
1185 }
1186 else
1187 State.a[OP[0]] = tmp & MASK40;
1188 trace_output (OP_ACCUM);
1189 }
1190
1191 /* macsu */
1192 void
1193 OP_1A00 ()
1194 {
1195 int64 tmp;
1196
1197 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1198 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1199 if (State.FX)
1200 tmp = SEXT40( (tmp << 1) & MASK40);
1201
1202 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1203 trace_output (OP_ACCUM);
1204 }
1205
1206 /* macu */
1207 void
1208 OP_3A00 ()
1209 {
1210 int64 tmp;
1211
1212 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1213 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1214 if (State.FX)
1215 tmp = SEXT40( (tmp << 1) & MASK40);
1216 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1217 trace_output (OP_ACCUM);
1218 }
1219
1220 /* max */
1221 void
1222 OP_2600 ()
1223 {
1224 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1225 State.F1 = State.F0;
1226 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1227 {
1228 State.regs[OP[0]] = State.regs[OP[1]];
1229 State.F0 = 1;
1230 }
1231 else
1232 State.F0 = 0;
1233 trace_output (OP_REG);
1234 }
1235
1236 /* max */
1237 void
1238 OP_3600 ()
1239 {
1240 int64 tmp;
1241
1242 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1243 State.F1 = State.F0;
1244 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1245 if (tmp > SEXT40(State.a[OP[0]]))
1246 {
1247 State.a[OP[0]] = tmp & MASK40;
1248 State.F0 = 1;
1249 }
1250 else
1251 State.F0 = 0;
1252 trace_output (OP_ACCUM);
1253 }
1254
1255 /* max */
1256 void
1257 OP_3602 ()
1258 {
1259 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1260 State.F1 = State.F0;
1261 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1262 {
1263 State.a[OP[0]] = State.a[OP[1]];
1264 State.F0 = 1;
1265 }
1266 else
1267 State.F0 = 0;
1268 trace_output (OP_ACCUM);
1269 }
1270
1271
1272 /* min */
1273 void
1274 OP_2601 ()
1275 {
1276 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1277 State.F1 = State.F0;
1278 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1279 {
1280 State.regs[OP[0]] = State.regs[OP[1]];
1281 State.F0 = 1;
1282 }
1283 else
1284 State.F0 = 0;
1285 trace_output (OP_REG);
1286 }
1287
1288 /* min */
1289 void
1290 OP_3601 ()
1291 {
1292 int64 tmp;
1293
1294 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1295 State.F1 = State.F0;
1296 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1297 if (tmp < SEXT40(State.a[OP[0]]))
1298 {
1299 State.a[OP[0]] = tmp & MASK40;
1300 State.F0 = 1;
1301 }
1302 else
1303 State.F0 = 0;
1304 trace_output (OP_ACCUM);
1305 }
1306
1307 /* min */
1308 void
1309 OP_3603 ()
1310 {
1311 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1312 State.F1 = State.F0;
1313 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1314 {
1315 State.a[OP[0]] = State.a[OP[1]];
1316 State.F0 = 1;
1317 }
1318 else
1319 State.F0 = 0;
1320 trace_output (OP_ACCUM);
1321 }
1322
1323 /* msb */
1324 void
1325 OP_2800 ()
1326 {
1327 int64 tmp;
1328
1329 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1330 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1331
1332 if (State.FX)
1333 tmp = SEXT40 ((tmp << 1) & MASK40);
1334
1335 if (State.ST && tmp > MAX32)
1336 tmp = MAX32;
1337
1338 tmp = SEXT40(State.a[OP[0]]) - tmp;
1339 if (State.ST)
1340 {
1341 if (tmp > MAX32)
1342 State.a[OP[0]] = MAX32;
1343 else if (tmp < MIN32)
1344 State.a[OP[0]] = MIN32;
1345 else
1346 State.a[OP[0]] = tmp & MASK40;
1347 }
1348 else
1349 State.a[OP[0]] = tmp & MASK40;
1350 trace_output (OP_ACCUM);
1351 }
1352
1353 /* msbsu */
1354 void
1355 OP_1800 ()
1356 {
1357 int64 tmp;
1358
1359 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1360 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1361 if (State.FX)
1362 tmp = SEXT40( (tmp << 1) & MASK40);
1363
1364 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1365 trace_output (OP_ACCUM);
1366 }
1367
1368 /* msbu */
1369 void
1370 OP_3800 ()
1371 {
1372 int64 tmp;
1373
1374 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1375 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1376 if (State.FX)
1377 tmp = SEXT40( (tmp << 1) & MASK40);
1378
1379 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1380 trace_output (OP_ACCUM);
1381 }
1382
1383 /* mul */
1384 void
1385 OP_2E00 ()
1386 {
1387 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1388 State.regs[OP[0]] *= State.regs[OP[1]];
1389 trace_output (OP_REG);
1390 }
1391
1392 /* mulx */
1393 void
1394 OP_2C00 ()
1395 {
1396 int64 tmp;
1397
1398 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1399 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1400
1401 if (State.FX)
1402 tmp = SEXT40 ((tmp << 1) & MASK40);
1403
1404 if (State.ST && tmp > MAX32)
1405 State.a[OP[0]] = MAX32;
1406 else
1407 State.a[OP[0]] = tmp & MASK40;
1408 trace_output (OP_ACCUM);
1409 }
1410
1411 /* mulxsu */
1412 void
1413 OP_1C00 ()
1414 {
1415 int64 tmp;
1416
1417 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1418 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1419
1420 if (State.FX)
1421 tmp <<= 1;
1422
1423 State.a[OP[0]] = tmp & MASK40;
1424 trace_output (OP_ACCUM);
1425 }
1426
1427 /* mulxu */
1428 void
1429 OP_3C00 ()
1430 {
1431 int64 tmp;
1432
1433 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1434 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1435
1436 if (State.FX)
1437 tmp <<= 1;
1438
1439 State.a[OP[0]] = tmp & MASK40;
1440 trace_output (OP_ACCUM);
1441 }
1442
1443 /* mv */
1444 void
1445 OP_4000 ()
1446 {
1447 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1448 State.regs[OP[0]] = State.regs[OP[1]];
1449 trace_output (OP_REG);
1450 }
1451
1452 /* mv2w */
1453 void
1454 OP_5000 ()
1455 {
1456 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1457 State.regs[OP[0]] = State.regs[OP[1]];
1458 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1459 trace_output (OP_DREG);
1460 }
1461
1462 /* mv2wfac */
1463 void
1464 OP_3E00 ()
1465 {
1466 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1467 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1468 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1469 trace_output (OP_DREG);
1470 }
1471
1472 /* mv2wtac */
1473 void
1474 OP_3E01 ()
1475 {
1476 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
1477 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1478 trace_output (OP_ACCUM);
1479 }
1480
1481 /* mvac */
1482 void
1483 OP_3E03 ()
1484 {
1485 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1486 State.a[OP[0]] = State.a[OP[1]];
1487 trace_output (OP_ACCUM);
1488 }
1489
1490 /* mvb */
1491 void
1492 OP_5400 ()
1493 {
1494 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1495 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1496 trace_output (OP_REG);
1497 }
1498
1499 /* mvf0f */
1500 void
1501 OP_4400 ()
1502 {
1503 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1504 if (State.F0 == 0)
1505 State.regs[OP[0]] = State.regs[OP[1]];
1506 trace_output (OP_REG);
1507 }
1508
1509 /* mvf0t */
1510 void
1511 OP_4401 ()
1512 {
1513 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1514 if (State.F0)
1515 State.regs[OP[0]] = State.regs[OP[1]];
1516 trace_output (OP_REG);
1517 }
1518
1519 /* mvfacg */
1520 void
1521 OP_1E04 ()
1522 {
1523 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1524 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1525 trace_output (OP_ACCUM);
1526 }
1527
1528 /* mvfachi */
1529 void
1530 OP_1E00 ()
1531 {
1532 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1533 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1534 trace_output (OP_REG);
1535 }
1536
1537 /* mvfaclo */
1538 void
1539 OP_1E02 ()
1540 {
1541 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1542 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1543 trace_output (OP_REG);
1544 }
1545
1546 /* mvfc */
1547 void
1548 OP_5200 ()
1549 {
1550 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1551 if (OP[1] == 0)
1552 {
1553 /* PSW is treated specially */
1554 PSW = 0;
1555 if (State.SM) PSW |= 0x8000;
1556 if (State.EA) PSW |= 0x2000;
1557 if (State.DB) PSW |= 0x1000;
1558 if (State.IE) PSW |= 0x400;
1559 if (State.RP) PSW |= 0x200;
1560 if (State.MD) PSW |= 0x100;
1561 if (State.FX) PSW |= 0x80;
1562 if (State.ST) PSW |= 0x40;
1563 if (State.F0) PSW |= 8;
1564 if (State.F1) PSW |= 4;
1565 if (State.C) PSW |= 1;
1566 }
1567 State.regs[OP[0]] = State.cregs[OP[1]];
1568 trace_output (OP_REG);
1569 }
1570
1571 /* mvtacg */
1572 void
1573 OP_1E41 ()
1574 {
1575 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1576 State.a[OP[1]] &= MASK32;
1577 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1578 trace_output (OP_ACCUM_REVERSE);
1579 }
1580
1581 /* mvtachi */
1582 void
1583 OP_1E01 ()
1584 {
1585 uint16 tmp;
1586
1587 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1588 tmp = State.a[OP[1]] & 0xffff;
1589 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1590 trace_output (OP_ACCUM_REVERSE);
1591 }
1592
1593 /* mvtaclo */
1594 void
1595 OP_1E21 ()
1596 {
1597 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1598 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1599 trace_output (OP_ACCUM_REVERSE);
1600 }
1601
1602 /* mvtc */
1603 void
1604 OP_5600 ()
1605 {
1606 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1607 State.cregs[OP[1]] = State.regs[OP[0]];
1608 if (OP[1] == 0)
1609 {
1610 /* PSW is treated specially */
1611 State.SM = (PSW & 0x8000) ? 1 : 0;
1612 State.EA = (PSW & 0x2000) ? 1 : 0;
1613 State.DB = (PSW & 0x1000) ? 1 : 0;
1614 State.IE = (PSW & 0x400) ? 1 : 0;
1615 State.RP = (PSW & 0x200) ? 1 : 0;
1616 State.MD = (PSW & 0x100) ? 1 : 0;
1617 State.FX = (PSW & 0x80) ? 1 : 0;
1618 State.ST = (PSW & 0x40) ? 1 : 0;
1619 State.F0 = (PSW & 8) ? 1 : 0;
1620 State.F1 = (PSW & 4) ? 1 : 0;
1621 State.C = PSW & 1;
1622 if (State.ST && !State.FX)
1623 {
1624 (*d10v_callback->printf_filtered) (d10v_callback,
1625 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1626 PC<<2);
1627 State.exception = SIGILL;
1628 }
1629 }
1630 trace_output (OP_CR_REVERSE);
1631 }
1632
1633 /* mvub */
1634 void
1635 OP_5401 ()
1636 {
1637 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1638 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1639 trace_output (OP_REG);
1640 }
1641
1642 /* neg */
1643 void
1644 OP_4605 ()
1645 {
1646 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1647 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1648 trace_output (OP_REG);
1649 }
1650
1651 /* neg */
1652 void
1653 OP_5605 ()
1654 {
1655 int64 tmp;
1656
1657 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1658 tmp = -SEXT40(State.a[OP[0]]);
1659 if (State.ST)
1660 {
1661 if ( tmp > MAX32)
1662 State.a[OP[0]] = MAX32;
1663 else if (tmp < MIN32)
1664 State.a[OP[0]] = MIN32;
1665 else
1666 State.a[OP[0]] = tmp & MASK40;
1667 }
1668 else
1669 State.a[OP[0]] = tmp & MASK40;
1670 trace_output (OP_ACCUM);
1671 }
1672
1673
1674 /* nop */
1675 void
1676 OP_5E00 ()
1677 {
1678 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1679 trace_output (OP_VOID);
1680
1681 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1682 left_nops++;
1683 else
1684 right_nops++;
1685 }
1686
1687 /* not */
1688 void
1689 OP_4603 ()
1690 {
1691 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1692 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1693 trace_output (OP_REG);
1694 }
1695
1696 /* or */
1697 void
1698 OP_800 ()
1699 {
1700 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1701 State.regs[OP[0]] |= State.regs[OP[1]];
1702 trace_output (OP_REG);
1703 }
1704
1705 /* or3 */
1706 void
1707 OP_4000000 ()
1708 {
1709 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1710 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1711 trace_output (OP_REG);
1712 }
1713
1714 /* rac */
1715 void
1716 OP_5201 ()
1717 {
1718 int64 tmp;
1719 int shift = SEXT3 (OP[2]);
1720
1721 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1722 if (OP[1] != 0)
1723 {
1724 (*d10v_callback->printf_filtered) (d10v_callback,
1725 "ERROR at PC 0x%x: instruction only valid for A0\n",
1726 PC<<2);
1727 State.exception = SIGILL;
1728 }
1729
1730 State.F1 = State.F0;
1731 if (shift >=0)
1732 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1733 else
1734 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1735 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1736 if (tmp > MAX32)
1737 {
1738 State.regs[OP[0]] = 0x7fff;
1739 State.regs[OP[0]+1] = 0xffff;
1740 State.F0 = 1;
1741 }
1742 else if (tmp < MIN32)
1743 {
1744 State.regs[OP[0]] = 0x8000;
1745 State.regs[OP[0]+1] = 0;
1746 State.F0 = 1;
1747 }
1748 else
1749 {
1750 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1751 State.regs[OP[0]+1] = tmp & 0xffff;
1752 State.F0 = 0;
1753 }
1754 trace_output (OP_DREG);
1755 }
1756
1757 /* rachi */
1758 void
1759 OP_4201 ()
1760 {
1761 int64 tmp;
1762 int shift = SEXT3 (OP[2]);
1763
1764 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1765 State.F1 = State.F0;
1766 if (shift >=0)
1767 tmp = SEXT44 (State.a[1]) << shift;
1768 else
1769 tmp = SEXT44 (State.a[1]) >> -shift;
1770 tmp += 0x8000;
1771
1772 if (tmp > MAX32)
1773 {
1774 State.regs[OP[0]] = 0x7fff;
1775 State.F0 = 1;
1776 }
1777 else if (tmp < 0xfff80000000LL)
1778 {
1779 State.regs[OP[0]] = 0x8000;
1780 State.F0 = 1;
1781 }
1782 else
1783 {
1784 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1785 State.F0 = 0;
1786 }
1787 trace_output (OP_REG);
1788 }
1789
1790 /* rep */
1791 void
1792 OP_27000000 ()
1793 {
1794 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1795 RPT_S = PC + 1;
1796 RPT_E = PC + OP[1];
1797 RPT_C = State.regs[OP[0]];
1798 State.RP = 1;
1799 if (RPT_C == 0)
1800 {
1801 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1802 State.exception = SIGILL;
1803 }
1804 if (OP[1] < 4)
1805 {
1806 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1807 State.exception = SIGILL;
1808 }
1809 trace_output (OP_VOID);
1810 }
1811
1812 /* repi */
1813 void
1814 OP_2F000000 ()
1815 {
1816 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1817 RPT_S = PC + 1;
1818 RPT_E = PC + OP[1];
1819 RPT_C = OP[0];
1820 State.RP = 1;
1821 if (RPT_C == 0)
1822 {
1823 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
1824 State.exception = SIGILL;
1825 }
1826 if (OP[1] < 4)
1827 {
1828 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
1829 State.exception = SIGILL;
1830 }
1831 trace_output (OP_VOID);
1832 }
1833
1834 /* rtd */
1835 void
1836 OP_5F60 ()
1837 {
1838 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
1839 State.exception = SIGILL;
1840 }
1841
1842 /* rte */
1843 void
1844 OP_5F40 ()
1845 {
1846 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
1847 PC = BPC;
1848 PSW = BPSW;
1849 trace_output (OP_VOID);
1850 }
1851
1852 /* sadd */
1853 void
1854 OP_1223 ()
1855 {
1856 int64 tmp;
1857
1858 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
1859 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1860 if (State.ST)
1861 {
1862 if (tmp > MAX32)
1863 State.a[OP[0]] = MAX32;
1864 else if (tmp < MIN32)
1865 State.a[OP[0]] = MIN32;
1866 else
1867 State.a[OP[0]] = tmp & MASK40;
1868 }
1869 else
1870 State.a[OP[0]] = tmp & MASK40;
1871 trace_output (OP_ACCUM);
1872 }
1873
1874 /* setf0f */
1875 void
1876 OP_4611 ()
1877 {
1878 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1879 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1880 trace_output (OP_REG);
1881 }
1882
1883 /* setf0t */
1884 void
1885 OP_4613 ()
1886 {
1887 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1888 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1889 trace_output (OP_REG);
1890 }
1891
1892 /* sleep */
1893 void
1894 OP_5FC0 ()
1895 {
1896 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
1897 State.IE = 1;
1898 trace_output (OP_VOID);
1899 }
1900
1901 /* sll */
1902 void
1903 OP_2200 ()
1904 {
1905 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
1906 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1907 trace_output (OP_REG);
1908 }
1909
1910 /* sll */
1911 void
1912 OP_3200 ()
1913 {
1914 int64 tmp;
1915 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
1916 if ((State.regs[OP[1]] & 31) <= 16)
1917 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1918 else
1919 {
1920 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
1921 State.exception = SIGILL;
1922 return;
1923 }
1924
1925 if (State.ST)
1926 {
1927 if (tmp > MAX32)
1928 State.a[OP[0]] = MAX32;
1929 else if (tmp < 0xffffff80000000LL)
1930 State.a[OP[0]] = MIN32;
1931 else
1932 State.a[OP[0]] = tmp & MASK40;
1933 }
1934 else
1935 State.a[OP[0]] = tmp & MASK40;
1936 trace_output (OP_ACCUM);
1937 }
1938
1939 /* slli */
1940 void
1941 OP_2201 ()
1942 {
1943 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
1944 State.regs[OP[0]] <<= OP[1];
1945 trace_output (OP_REG);
1946 }
1947
1948 /* slli */
1949 void
1950 OP_3201 ()
1951 {
1952 int64 tmp;
1953
1954 if (OP[1] == 0)
1955 OP[1] = 16;
1956
1957 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
1958 tmp = SEXT40(State.a[OP[0]]) << OP[1];
1959
1960 if (State.ST)
1961 {
1962 if (tmp > MAX32)
1963 State.a[OP[0]] = MAX32;
1964 else if (tmp < 0xffffff80000000LL)
1965 State.a[OP[0]] = MIN32;
1966 else
1967 State.a[OP[0]] = tmp & MASK40;
1968 }
1969 else
1970 State.a[OP[0]] = tmp & MASK40;
1971 trace_output (OP_ACCUM);
1972 }
1973
1974 /* slx */
1975 void
1976 OP_460B ()
1977 {
1978 uint16 tmp;
1979
1980 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
1981 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1982 trace_output (OP_REG);
1983 }
1984
1985 /* sra */
1986 void
1987 OP_2400 ()
1988 {
1989 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
1990 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1991 trace_output (OP_REG);
1992 }
1993
1994 /* sra */
1995 void
1996 OP_3400 ()
1997 {
1998 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
1999 if ((State.regs[OP[1]] & 31) <= 16)
2000 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2001 else
2002 {
2003 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2004 State.exception = SIGILL;
2005 return;
2006 }
2007
2008 trace_output (OP_ACCUM);
2009 }
2010
2011 /* srai */
2012 void
2013 OP_2401 ()
2014 {
2015 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2016 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2017 trace_output (OP_REG);
2018 }
2019
2020 /* srai */
2021 void
2022 OP_3401 ()
2023 {
2024 if (OP[1] == 0)
2025 OP[1] = 16;
2026
2027 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2028 State.a[OP[0]] >>= OP[1];
2029 trace_output (OP_ACCUM);
2030 }
2031
2032 /* srl */
2033 void
2034 OP_2000 ()
2035 {
2036 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2037 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2038 trace_output (OP_REG);
2039 }
2040
2041 /* srl */
2042 void
2043 OP_3000 ()
2044 {
2045 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2046 if ((State.regs[OP[1]] & 31) <= 16)
2047 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2048 else
2049 {
2050 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2051 State.exception = SIGILL;
2052 return;
2053 }
2054
2055 trace_output (OP_ACCUM);
2056 }
2057
2058 /* srli */
2059 void
2060 OP_2001 ()
2061 {
2062 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2063 State.regs[OP[0]] >>= OP[1];
2064 trace_output (OP_REG);
2065 }
2066
2067 /* srli */
2068 void
2069 OP_3001 ()
2070 {
2071 if (OP[1] == 0)
2072 OP[1] = 16;
2073
2074 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2075 State.a[OP[0]] >>= OP[1];
2076 trace_output (OP_ACCUM);
2077 }
2078
2079 /* srx */
2080 void
2081 OP_4609 ()
2082 {
2083 uint16 tmp;
2084
2085 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2086 tmp = State.F0 << 15;
2087 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2088 trace_output (OP_REG);
2089 }
2090
2091 /* st */
2092 void
2093 OP_34000000 ()
2094 {
2095 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2096 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2097 trace_output (OP_VOID);
2098 }
2099
2100 /* st */
2101 void
2102 OP_6800 ()
2103 {
2104 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2105 SW (State.regs[OP[1]], State.regs[OP[0]]);
2106 trace_output (OP_VOID);
2107 }
2108
2109 /* st */
2110 void
2111 OP_6C1F ()
2112 {
2113 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2114 if ( OP[1] != 15 )
2115 {
2116 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2117 State.exception = SIGILL;
2118 return;
2119 }
2120 State.regs[OP[1]] -= 2;
2121 SW (State.regs[OP[1]], State.regs[OP[0]]);
2122 trace_output (OP_VOID);
2123 }
2124
2125 /* st */
2126 void
2127 OP_6801 ()
2128 {
2129 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2130 SW (State.regs[OP[1]], State.regs[OP[0]]);
2131 INC_ADDR (State.regs[OP[1]],2);
2132 trace_output (OP_VOID);
2133 }
2134
2135 /* st */
2136 void
2137 OP_6C01 ()
2138 {
2139 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2140 SW (State.regs[OP[1]], State.regs[OP[0]]);
2141 INC_ADDR (State.regs[OP[1]],-2);
2142 trace_output (OP_VOID);
2143 }
2144
2145 /* st2w */
2146 void
2147 OP_35000000 ()
2148 {
2149 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2150 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2151 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2152 trace_output (OP_VOID);
2153 }
2154
2155 /* st2w */
2156 void
2157 OP_6A00 ()
2158 {
2159 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
2160 SW (State.regs[OP[1]], State.regs[OP[0]]);
2161 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2162 trace_output (OP_VOID);
2163 }
2164
2165 /* st2w */
2166 void
2167 OP_6E1F ()
2168 {
2169 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
2170 if ( OP[1] != 15 )
2171 {
2172 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2173 State.exception = SIGILL;
2174 return;
2175 }
2176 State.regs[OP[1]] -= 4;
2177 SW (State.regs[OP[1]], State.regs[OP[0]]);
2178 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2179 trace_output (OP_VOID);
2180 }
2181
2182 /* st2w */
2183 void
2184 OP_6A01 ()
2185 {
2186 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
2187 SW (State.regs[OP[1]], State.regs[OP[0]]);
2188 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2189 INC_ADDR (State.regs[OP[1]],4);
2190 trace_output (OP_VOID);
2191 }
2192
2193 /* st2w */
2194 void
2195 OP_6E01 ()
2196 {
2197 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
2198 SW (State.regs[OP[1]], State.regs[OP[0]]);
2199 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2200 INC_ADDR (State.regs[OP[1]],-4);
2201 trace_output (OP_VOID);
2202 }
2203
2204 /* stb */
2205 void
2206 OP_3C000000 ()
2207 {
2208 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2209 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2210 trace_output (OP_VOID);
2211 }
2212
2213 /* stb */
2214 void
2215 OP_7800 ()
2216 {
2217 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2218 SB (State.regs[OP[1]], State.regs[OP[0]]);
2219 trace_output (OP_VOID);
2220 }
2221
2222 /* stop */
2223 void
2224 OP_5FE0 ()
2225 {
2226 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2227 State.exception = SIGQUIT;
2228 trace_output (OP_VOID);
2229 }
2230
2231 /* sub */
2232 void
2233 OP_0 ()
2234 {
2235 int32 tmp;
2236
2237 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2238 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2239 State.C = (tmp & 0xffff0000) ? 1 : 0;
2240 State.regs[OP[0]] = tmp & 0xffff;
2241 trace_output (OP_REG);
2242 }
2243
2244 /* sub */
2245 void
2246 OP_1001 ()
2247 {
2248 int64 tmp;
2249
2250 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2251 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2252 if (State.ST)
2253 {
2254 if ( tmp > MAX32)
2255 State.a[OP[0]] = MAX32;
2256 else if ( tmp < MIN32)
2257 State.a[OP[0]] = MIN32;
2258 else
2259 State.a[OP[0]] = tmp & MASK40;
2260 }
2261 else
2262 State.a[OP[0]] = tmp & MASK40;
2263
2264 trace_output (OP_ACCUM);
2265 }
2266
2267 /* sub */
2268
2269 void
2270 OP_1003 ()
2271 {
2272 int64 tmp;
2273
2274 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2275 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2276 if (State.ST)
2277 {
2278 if (tmp > MAX32)
2279 State.a[OP[0]] = MAX32;
2280 else if ( tmp < MIN32)
2281 State.a[OP[0]] = MIN32;
2282 else
2283 State.a[OP[0]] = tmp & MASK40;
2284 }
2285 else
2286 State.a[OP[0]] = tmp & MASK40;
2287
2288 trace_output (OP_ACCUM);
2289 }
2290
2291 /* sub2w */
2292 void
2293 OP_1000 ()
2294 {
2295 int64 tmp;
2296 int32 a,b;
2297
2298 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2299 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2300 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2301 tmp = a-b;
2302 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2303 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2304 State.regs[OP[0]+1] = tmp & 0xffff;
2305 trace_output (OP_DREG);
2306 }
2307
2308 /* subac3 */
2309 void
2310 OP_17000000 ()
2311 {
2312 int64 tmp;
2313
2314 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2315 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2316 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2317 State.regs[OP[0]+1] = tmp & 0xffff;
2318 trace_output (OP_DREG);
2319 }
2320
2321 /* subac3 */
2322 void
2323 OP_17000002 ()
2324 {
2325 int64 tmp;
2326
2327 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2328 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2329 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2330 State.regs[OP[0]+1] = tmp & 0xffff;
2331 trace_output (OP_DREG);
2332 }
2333
2334 /* subac3s */
2335 void
2336 OP_17001000 ()
2337 {
2338 int64 tmp;
2339
2340 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2341 State.F1 = State.F0;
2342 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2343 if ( tmp > MAX32)
2344 {
2345 State.regs[OP[0]] = 0x7fff;
2346 State.regs[OP[0]+1] = 0xffff;
2347 State.F0 = 1;
2348 }
2349 else if (tmp < MIN32)
2350 {
2351 State.regs[OP[0]] = 0x8000;
2352 State.regs[OP[0]+1] = 0;
2353 State.F0 = 1;
2354 }
2355 else
2356 {
2357 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2358 State.regs[OP[0]+1] = tmp & 0xffff;
2359 State.F0 = 0;
2360 }
2361 trace_output (OP_DREG);
2362 }
2363
2364 /* subac3s */
2365 void
2366 OP_17001002 ()
2367 {
2368 int64 tmp;
2369
2370 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2371 State.F1 = State.F0;
2372 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2373 if ( tmp > MAX32)
2374 {
2375 State.regs[OP[0]] = 0x7fff;
2376 State.regs[OP[0]+1] = 0xffff;
2377 State.F0 = 1;
2378 }
2379 else if (tmp < MIN32)
2380 {
2381 State.regs[OP[0]] = 0x8000;
2382 State.regs[OP[0]+1] = 0;
2383 State.F0 = 1;
2384 }
2385 else
2386 {
2387 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2388 State.regs[OP[0]+1] = tmp & 0xffff;
2389 State.F0 = 0;
2390 }
2391 trace_output (OP_DREG);
2392 }
2393
2394 /* subi */
2395 void
2396 OP_1 ()
2397 {
2398 int32 tmp;
2399 if (OP[1] == 0)
2400 OP[1] = 16;
2401
2402 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2403 tmp = (int16)State.regs[OP[0]] - OP[1];
2404 State.C = (tmp & 0xffff0000) ? 1 : 0;
2405 State.regs[OP[0]] = tmp & 0xffff;
2406 trace_output (OP_REG);
2407 }
2408
2409 /* trap */
2410 void
2411 OP_5F00 ()
2412 {
2413 trace_input ("trap", OP_CONSTANT16, OP_REG, OP_VOID);
2414 trace_output (OP_VOID);
2415
2416 switch (OP[0])
2417 {
2418 default:
2419 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2420 State.exception = SIGILL;
2421
2422 case 0:
2423 /* Trap 0 is used for simulating low-level I/O */
2424 {
2425 int save_errno = errno;
2426 errno = 0;
2427
2428 /* Registers passed to trap 0 */
2429
2430 #define FUNC State.regs[2] /* function number, return value */
2431 #define PARM1 State.regs[3] /* optional parm 1 */
2432 #define PARM2 State.regs[4] /* optional parm 2 */
2433 #define PARM3 State.regs[5] /* optional parm 3 */
2434
2435 /* Registers set by trap 0 */
2436
2437 #define RETVAL State.regs[2] /* return value */
2438 #define RETERR State.regs[3] /* return error code */
2439
2440 /* Turn a pointer in a register into a pointer into real memory. */
2441
2442 #define MEMPTR(x) ((char *)((x) + State.imem))
2443
2444 switch (FUNC)
2445 {
2446 #if !defined(__GO32__) && !defined(_WIN32)
2447 #ifdef SYS_fork
2448 case SYS_fork:
2449 RETVAL = fork ();
2450 break;
2451 #endif
2452 #ifdef SYS_execve
2453 case SYS_execve:
2454 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2455 (char **)MEMPTR (PARM3));
2456 break;
2457 #endif
2458 #ifdef SYS_execv
2459 case SYS_execv:
2460 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2461 break;
2462 #endif
2463 #ifdef SYS_pipe
2464 case SYS_pipe:
2465 {
2466 reg_t buf;
2467 int host_fd[2];
2468
2469 buf = PARM1;
2470 RETVAL = pipe (host_fd);
2471 SW (buf, host_fd[0]);
2472 buf += sizeof(uint16);
2473 SW (buf, host_fd[1]);
2474 }
2475 break;
2476 #endif
2477 #ifdef SYS_wait
2478 case SYS_wait:
2479 {
2480 int status;
2481
2482 RETVAL = wait (&status);
2483 SW (PARM1, status);
2484 }
2485 break;
2486 #endif
2487 #endif
2488
2489 #ifdef SYS_read
2490 case SYS_read:
2491 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2492 PARM3);
2493 break;
2494 #endif
2495 #ifdef SYS_write
2496 case SYS_write:
2497 if (PARM1 == 1)
2498 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2499 MEMPTR (PARM2), PARM3);
2500 else
2501 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2502 MEMPTR (PARM2), PARM3);
2503 break;
2504 #endif
2505 #ifdef SYS_lseek
2506 case SYS_lseek:
2507 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2508 break;
2509 #endif
2510 #ifdef SYS_close
2511 case SYS_close:
2512 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2513 break;
2514 #endif
2515 #ifdef SYS_open
2516 case SYS_open:
2517 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2518 break;
2519 #endif
2520 #ifdef SYS_exit
2521 case SYS_exit:
2522 /* EXIT - caller can look in PARM1 to work out the
2523 reason */
2524 State.exception = SIGQUIT;
2525 break;
2526 #endif
2527
2528 #ifdef SYS_stat
2529 case SYS_stat:
2530 /* stat system call */
2531 {
2532 struct stat host_stat;
2533 reg_t buf;
2534
2535 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2536
2537 buf = PARM2;
2538
2539 /* The hard-coded offsets and sizes were determined by using
2540 * the D10V compiler on a test program that used struct stat.
2541 */
2542 SW (buf, host_stat.st_dev);
2543 SW (buf+2, host_stat.st_ino);
2544 SW (buf+4, host_stat.st_mode);
2545 SW (buf+6, host_stat.st_nlink);
2546 SW (buf+8, host_stat.st_uid);
2547 SW (buf+10, host_stat.st_gid);
2548 SW (buf+12, host_stat.st_rdev);
2549 SLW (buf+16, host_stat.st_size);
2550 SLW (buf+20, host_stat.st_atime);
2551 SLW (buf+28, host_stat.st_mtime);
2552 SLW (buf+36, host_stat.st_ctime);
2553 }
2554 break;
2555 #endif
2556
2557 #ifdef SYS_chown
2558 case SYS_chown:
2559 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2560 break;
2561 #endif
2562 #ifdef SYS_chmod
2563 case SYS_chmod:
2564 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2565 break;
2566 #endif
2567 #ifdef SYS_utime
2568 case SYS_utime:
2569 /* Cast the second argument to void *, to avoid type mismatch
2570 if a prototype is present. */
2571 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2572 break;
2573 #endif
2574 default:
2575 abort ();
2576 }
2577 RETERR = errno;
2578 errno = save_errno;
2579 break;
2580 }
2581
2582 case 1:
2583 /* Trap 1 prints a string */
2584 {
2585 char *fstr = State.regs[2] + State.imem;
2586 fputs (fstr, stdout);
2587 break;
2588 }
2589
2590 case 2:
2591 /* Trap 2 calls printf */
2592 {
2593 char *fstr = State.regs[2] + State.imem;
2594 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2595 (int16)State.regs[3],
2596 (int16)State.regs[4],
2597 (int16)State.regs[5]);
2598 break;
2599 }
2600
2601 case 3:
2602 /* Trap 3 writes a character */
2603 putchar (State.regs[2]);
2604 break;
2605 }
2606 }
2607
2608 /* tst0i */
2609 void
2610 OP_7000000 ()
2611 {
2612 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2613 State.F1 = State.F0;
2614 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2615 trace_output (OP_FLAG);
2616 }
2617
2618 /* tst1i */
2619 void
2620 OP_F000000 ()
2621 {
2622 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
2623 State.F1 = State.F0;
2624 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2625 trace_output (OP_FLAG);
2626 }
2627
2628 /* wait */
2629 void
2630 OP_5F80 ()
2631 {
2632 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
2633 State.IE = 1;
2634 trace_output (OP_VOID);
2635 }
2636
2637 /* xor */
2638 void
2639 OP_A00 ()
2640 {
2641 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
2642 State.regs[OP[0]] ^= State.regs[OP[1]];
2643 trace_output (OP_REG);
2644 }
2645
2646 /* xor3 */
2647 void
2648 OP_5000000 ()
2649 {
2650 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2651 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2652 trace_output (OP_REG);
2653 }
2654
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