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[thirdparty/binutils-gdb.git] / sim / d10v / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #include <errno.h>
5 #include <sys/types.h>
6 #include <sys/stat.h>
7 #ifdef HAVE_UNISTD_H
8 #include <unistd.h>
9 #endif
10
11 #include "d10v_sim.h"
12 #include "simops.h"
13 #include "sys/syscall.h"
14
15 extern char *strrchr ();
16
17 enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
30 OP_FLAG_OUTPUT,
31 OP_CONSTANT16,
32 OP_CONSTANT8,
33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
39 OP_PREDEC,
40 OP_R2,
41 OP_R3,
42 OP_R4,
43 OP_R2R3
44 };
45
46 #ifdef DEBUG
47 static void trace_input_func PARAMS ((char *name,
48 enum op_types in1,
49 enum op_types in2,
50 enum op_types in3));
51
52 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
53
54 static void trace_output_func PARAMS ((enum op_types result));
55
56 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
57
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 8
60 #endif
61
62 #ifndef SIZE_OPERANDS
63 #define SIZE_OPERANDS 18
64 #endif
65
66 #ifndef SIZE_VALUES
67 #define SIZE_VALUES 13
68 #endif
69
70 #ifndef SIZE_LOCATION
71 #define SIZE_LOCATION 20
72 #endif
73
74 #ifndef SIZE_PC
75 #define SIZE_PC 6
76 #endif
77
78 #ifndef SIZE_LINE_NUMBER
79 #define SIZE_LINE_NUMBER 4
80 #endif
81
82 static void
83 trace_input_func (name, in1, in2, in3)
84 char *name;
85 enum op_types in1;
86 enum op_types in2;
87 enum op_types in3;
88 {
89 char *comma;
90 enum op_types in[3];
91 int i;
92 char buf[1024];
93 char *p;
94 long tmp;
95 char *type;
96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
100
101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
116 case INS_LONG: type = " B"; break;
117 }
118
119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
121 "0x%.*x %s: %-*s ",
122 SIZE_PC, (unsigned)PC,
123 type,
124 SIZE_INSTRUCTION, name);
125
126 else
127 {
128 buf[0] = '\0';
129 byte_pc = decode_pc ();
130 if (text && byte_pc >= text_start && byte_pc < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
135 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
142 p += strlen (p);
143 }
144 else
145 {
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
148 }
149
150 if (functionname)
151 {
152 sprintf (p, "%s ", functionname);
153 p += strlen (p);
154 }
155 else if (filename)
156 {
157 char *q = strrchr (filename, '/');
158 sprintf (p, "%s ", (q) ? q+1 : filename);
159 p += strlen (p);
160 }
161
162 if (*p == ' ')
163 *p = '\0';
164 }
165 }
166
167 (*d10v_callback->printf_filtered) (d10v_callback,
168 "0x%.*x %s: %-*.*s %-*s ",
169 SIZE_PC, (unsigned)PC,
170 type,
171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
173 }
174
175 in[0] = in1;
176 in[1] = in2;
177 in[2] = in3;
178 comma = "";
179 p = buf;
180 for (i = 0; i < 3; i++)
181 {
182 switch (in[i])
183 {
184 case OP_VOID:
185 case OP_R2:
186 case OP_R3:
187 case OP_R4:
188 case OP_R2R3:
189 break;
190
191 case OP_REG:
192 case OP_REG_OUTPUT:
193 case OP_DREG:
194 case OP_DREG_OUTPUT:
195 sprintf (p, "%sr%d", comma, OP[i]);
196 p += strlen (p);
197 comma = ",";
198 break;
199
200 case OP_CR:
201 case OP_CR_OUTPUT:
202 case OP_CR_REVERSE:
203 sprintf (p, "%scr%d", comma, OP[i]);
204 p += strlen (p);
205 comma = ",";
206 break;
207
208 case OP_ACCUM:
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
212 p += strlen (p);
213 comma = ",";
214 break;
215
216 case OP_CONSTANT16:
217 sprintf (p, "%s%d", comma, OP[i]);
218 p += strlen (p);
219 comma = ",";
220 break;
221
222 case OP_CONSTANT8:
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
224 p += strlen (p);
225 comma = ",";
226 break;
227
228 case OP_CONSTANT4:
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
230 p += strlen (p);
231 comma = ",";
232 break;
233
234 case OP_CONSTANT3:
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
236 p += strlen (p);
237 comma = ",";
238 break;
239
240 case OP_MEMREF:
241 sprintf (p, "%s@r%d", comma, OP[i]);
242 p += strlen (p);
243 comma = ",";
244 break;
245
246 case OP_MEMREF2:
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
248 p += strlen (p);
249 comma = ",";
250 break;
251
252 case OP_POSTINC:
253 sprintf (p, "%s@r%d+", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_POSTDEC:
259 sprintf (p, "%s@r%d-", comma, OP[i]);
260 p += strlen (p);
261 comma = ",";
262 break;
263
264 case OP_PREDEC:
265 sprintf (p, "%s@-r%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_FLAG:
271 case OP_FLAG_OUTPUT:
272 if (OP[i] == 0)
273 sprintf (p, "%sf0", comma);
274
275 else if (OP[i] == 1)
276 sprintf (p, "%sf1", comma);
277
278 else
279 sprintf (p, "%sc", comma);
280
281 p += strlen (p);
282 comma = ",";
283 break;
284 }
285 }
286
287 if ((d10v_debug & DEBUG_VALUES) == 0)
288 {
289 *p++ = '\n';
290 *p = '\0';
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
292 }
293 else
294 {
295 *p = '\0';
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
297
298 p = buf;
299 for (i = 0; i < 3; i++)
300 {
301 buf[0] = '\0';
302 switch (in[i])
303 {
304 case OP_VOID:
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
306 break;
307
308 case OP_REG_OUTPUT:
309 case OP_DREG_OUTPUT:
310 case OP_CR_OUTPUT:
311 case OP_ACCUM_OUTPUT:
312 case OP_FLAG_OUTPUT:
313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
314 break;
315
316 case OP_REG:
317 case OP_MEMREF:
318 case OP_POSTDEC:
319 case OP_POSTINC:
320 case OP_PREDEC:
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
323 break;
324
325 case OP_DREG:
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
328 break;
329
330 case OP_CR:
331 case OP_CR_REVERSE:
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
334 break;
335
336 case OP_ACCUM:
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
341 break;
342
343 case OP_CONSTANT16:
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
345 (uint16)OP[i]);
346 break;
347
348 case OP_CONSTANT4:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
351 break;
352
353 case OP_CONSTANT8:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
356 break;
357
358 case OP_CONSTANT3:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
361 break;
362
363 case OP_FLAG:
364 if (OP[i] == 0)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
366 State.F0 != 0);
367
368 else if (OP[i] == 1)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
370 State.F1 != 0);
371
372 else
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
374 State.C != 0);
375
376 break;
377
378 case OP_MEMREF2:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16)OP[i]);
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
383 break;
384
385 case OP_R2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
388 break;
389
390 case OP_R3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
393 break;
394
395 case OP_R4:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
398 break;
399
400 case OP_R2R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
405 i++;
406 break;
407 }
408 }
409 }
410
411 (*d10v_callback->flush_stdout) (d10v_callback);
412 }
413
414 static void
415 trace_output_func (result)
416 enum op_types result;
417 {
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
419 {
420 long tmp;
421
422 switch (result)
423 {
424 default:
425 putchar ('\n');
426 break;
427
428 case OP_REG:
429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
433 break;
434
435 case OP_DREG:
436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
440 break;
441
442 case OP_CR:
443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
447 break;
448
449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
453 break;
454
455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
461 break;
462
463 case OP_ACCUM_REVERSE:
464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
468 break;
469
470 case OP_FLAG:
471 case OP_FLAG_OUTPUT:
472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
474 break;
475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
487 }
488 }
489
490 (*d10v_callback->flush_stdout) (d10v_callback);
491 }
492
493 #else
494 #define trace_input(NAME, IN1, IN2, IN3)
495 #define trace_output(RESULT)
496 #endif
497
498 /* abs */
499 void
500 OP_4607 ()
501 {
502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
503 State.F1 = State.F0;
504 if ((int16)(State.regs[OP[0]]) < 0)
505 {
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
507 State.F0 = 1;
508 }
509 else
510 State.F0 = 0;
511 trace_output (OP_REG);
512 }
513
514 /* abs */
515 void
516 OP_5607 ()
517 {
518 int64 tmp;
519
520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
521 State.F1 = State.F0;
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
523
524 if (State.a[OP[0]] < 0 )
525 {
526 tmp = -State.a[OP[0]];
527 if (State.ST)
528 {
529 if (tmp > MAX32)
530 State.a[OP[0]] = MAX32;
531 else if (tmp < MIN32)
532 State.a[OP[0]] = MIN32;
533 else
534 State.a[OP[0]] = tmp & MASK40;
535 }
536 else
537 State.a[OP[0]] = tmp & MASK40;
538 State.F0 = 1;
539 }
540 else
541 State.F0 = 0;
542 trace_output (OP_ACCUM);
543 }
544
545 /* add */
546 void
547 OP_200 ()
548 {
549 uint16 tmp = State.regs[OP[0]];
550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
553 State.C = 1;
554 else
555 State.C = 0;
556 trace_output (OP_REG);
557 }
558
559 /* add */
560 void
561 OP_1201 ()
562 {
563 int64 tmp;
564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
565
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
567 if (State.ST)
568 {
569 if ( tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
574 State.a[OP[0]] = tmp & MASK40;
575 }
576 else
577 State.a[OP[0]] = tmp & MASK40;
578 trace_output (OP_ACCUM);
579 }
580
581 /* add */
582 void
583 OP_1203 ()
584 {
585 int64 tmp;
586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
587
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
589 if (State.ST)
590 {
591 if (tmp > MAX32)
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
595 else
596 State.a[OP[0]] = tmp & MASK40;
597 }
598 else
599 State.a[OP[0]] = tmp & MASK40;
600 trace_output (OP_ACCUM);
601 }
602
603 /* add2w */
604 void
605 OP_1200 ()
606 {
607 uint32 tmp;
608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
610
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
612 tmp = a + b;
613 State.C = (tmp < a);
614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
616 trace_output (OP_DREG);
617 }
618
619 /* add3 */
620 void
621 OP_1000000 ()
622 {
623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
625
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
627 State.C = (State.regs[OP[0]] < tmp);
628 trace_output (OP_REG);
629 }
630
631 /* addac3 */
632 void
633 OP_17000200 ()
634 {
635 int64 tmp;
636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
637
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
641 trace_output (OP_DREG);
642 }
643
644 /* addac3 */
645 void
646 OP_17000202 ()
647 {
648 int64 tmp;
649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
650
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
654 trace_output (OP_DREG);
655 }
656
657 /* addac3s */
658 void
659 OP_17001200 ()
660 {
661 int64 tmp;
662 State.F1 = State.F0;
663
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
666 if ( tmp > MAX32)
667 {
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
670 State.F0 = 1;
671 }
672 else if (tmp < MIN32)
673 {
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
676 State.F0 = 1;
677 }
678 else
679 {
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
682 State.F0 = 0;
683 }
684 trace_output (OP_DREG);
685 }
686
687 /* addac3s */
688 void
689 OP_17001202 ()
690 {
691 int64 tmp;
692 State.F1 = State.F0;
693
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
696 if ( tmp > MAX32)
697 {
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
700 State.F0 = 1;
701 }
702 else if (tmp < MIN32)
703 {
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
706 State.F0 = 1;
707 }
708 else
709 {
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
712 State.F0 = 0;
713 }
714 trace_output (OP_DREG);
715 }
716
717 /* addi */
718 void
719 OP_201 ()
720 {
721 uint tmp = State.regs[OP[0]];
722 if (OP[1] == 0)
723 OP[1] = 16;
724
725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
726 State.regs[OP[0]] += OP[1];
727 State.C = (State.regs[OP[0]] < tmp);
728 trace_output (OP_REG);
729 }
730
731 /* and */
732 void
733 OP_C00 ()
734 {
735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
736 State.regs[OP[0]] &= State.regs[OP[1]];
737 trace_output (OP_REG);
738 }
739
740 /* and3 */
741 void
742 OP_6000000 ()
743 {
744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
746 trace_output (OP_REG);
747 }
748
749 /* bclri */
750 void
751 OP_C01 ()
752 {
753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
755 trace_output (OP_REG);
756 }
757
758 /* bl.s */
759 void
760 OP_4900 ()
761 {
762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
763 State.regs[13] = PC+1;
764 JMP( PC + SEXT8 (OP[0]));
765 trace_output (OP_VOID);
766 }
767
768 /* bl.l */
769 void
770 OP_24800000 ()
771 {
772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
773 State.regs[13] = PC+1;
774 JMP (PC + OP[0]);
775 trace_output (OP_VOID);
776 }
777
778 /* bnoti */
779 void
780 OP_A01 ()
781 {
782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
784 trace_output (OP_REG);
785 }
786
787 /* bra.s */
788 void
789 OP_4800 ()
790 {
791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
792 JMP (PC + SEXT8 (OP[0]));
793 trace_output (OP_VOID);
794 }
795
796 /* bra.l */
797 void
798 OP_24000000 ()
799 {
800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
801 JMP (PC + OP[0]);
802 trace_output (OP_VOID);
803 }
804
805 /* brf0f.s */
806 void
807 OP_4A00 ()
808 {
809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
810 if (State.F0 == 0)
811 JMP (PC + SEXT8 (OP[0]));
812 trace_output (OP_FLAG);
813 }
814
815 /* brf0f.l */
816 void
817 OP_25000000 ()
818 {
819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
820 if (State.F0 == 0)
821 JMP (PC + OP[0]);
822 trace_output (OP_FLAG);
823 }
824
825 /* brf0t.s */
826 void
827 OP_4B00 ()
828 {
829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
830 if (State.F0)
831 JMP (PC + SEXT8 (OP[0]));
832 trace_output (OP_FLAG);
833 }
834
835 /* brf0t.l */
836 void
837 OP_25800000 ()
838 {
839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
840 if (State.F0)
841 JMP (PC + OP[0]);
842 trace_output (OP_FLAG);
843 }
844
845 /* bseti */
846 void
847 OP_801 ()
848 {
849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
850 State.regs[OP[0]] |= 0x8000 >> OP[1];
851 trace_output (OP_REG);
852 }
853
854 /* btsti */
855 void
856 OP_E01 ()
857 {
858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
861 trace_output (OP_FLAG);
862 }
863
864 /* clrac */
865 void
866 OP_5601 ()
867 {
868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
869 State.a[OP[0]] = 0;
870 trace_output (OP_ACCUM);
871 }
872
873 /* cmp */
874 void
875 OP_600 ()
876 {
877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
880 trace_output (OP_FLAG);
881 }
882
883 /* cmp */
884 void
885 OP_1603 ()
886 {
887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
888 State.F1 = State.F0;
889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
890 trace_output (OP_FLAG);
891 }
892
893 /* cmpeq */
894 void
895 OP_400 ()
896 {
897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
900 trace_output (OP_FLAG);
901 }
902
903 /* cmpeq */
904 void
905 OP_1403 ()
906 {
907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
908 State.F1 = State.F0;
909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
910 trace_output (OP_FLAG);
911 }
912
913 /* cmpeqi.s */
914 void
915 OP_401 ()
916 {
917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
918 State.F1 = State.F0;
919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
920 trace_output (OP_FLAG);
921 }
922
923 /* cmpeqi.l */
924 void
925 OP_2000000 ()
926 {
927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
928 State.F1 = State.F0;
929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
930 trace_output (OP_FLAG);
931 }
932
933 /* cmpi.s */
934 void
935 OP_601 ()
936 {
937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
938 State.F1 = State.F0;
939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
940 trace_output (OP_FLAG);
941 }
942
943 /* cmpi.l */
944 void
945 OP_3000000 ()
946 {
947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
950 trace_output (OP_FLAG);
951 }
952
953 /* cmpu */
954 void
955 OP_4600 ()
956 {
957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
960 trace_output (OP_FLAG);
961 }
962
963 /* cmpui */
964 void
965 OP_23000000 ()
966 {
967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
968 State.F1 = State.F0;
969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
970 trace_output (OP_FLAG);
971 }
972
973 /* cpfg */
974 void
975 OP_4E09 ()
976 {
977 uint8 *src, *dst;
978
979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
993 trace_output (OP_FLAG);
994 }
995
996 /* dbt */
997 void
998 OP_5F20 ()
999 {
1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1001 State.exception = SIGTRAP;
1002 }
1003
1004 /* divs */
1005 void
1006 OP_14002800 ()
1007 {
1008 uint16 foo, tmp, tmpf;
1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
1016 trace_output (OP_DREG);
1017 }
1018
1019 /* exef0f */
1020 void
1021 OP_4E04 ()
1022 {
1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1024 State.exe = (State.F0 == 0);
1025 trace_output (OP_FLAG);
1026 }
1027
1028 /* exef0t */
1029 void
1030 OP_4E24 ()
1031 {
1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1033 State.exe = (State.F0 != 0);
1034 trace_output (OP_FLAG);
1035 }
1036
1037 /* exef1f */
1038 void
1039 OP_4E40 ()
1040 {
1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1042 State.exe = (State.F1 == 0);
1043 trace_output (OP_FLAG);
1044 }
1045
1046 /* exef1t */
1047 void
1048 OP_4E42 ()
1049 {
1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1051 State.exe = (State.F1 != 0);
1052 trace_output (OP_FLAG);
1053 }
1054
1055 /* exefaf */
1056 void
1057 OP_4E00 ()
1058 {
1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
1061 trace_output (OP_FLAG);
1062 }
1063
1064 /* exefat */
1065 void
1066 OP_4E02 ()
1067 {
1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
1070 trace_output (OP_FLAG);
1071 }
1072
1073 /* exetaf */
1074 void
1075 OP_4E20 ()
1076 {
1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
1079 trace_output (OP_FLAG);
1080 }
1081
1082 /* exetat */
1083 void
1084 OP_4E22 ()
1085 {
1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
1088 trace_output (OP_FLAG);
1089 }
1090
1091 /* exp */
1092 void
1093 OP_15002A00 ()
1094 {
1095 uint32 tmp, foo;
1096 int i;
1097
1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1101 else
1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1103
1104 foo = 0x40000000;
1105 for (i=1;i<17;i++)
1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
1110 trace_output (OP_REG);
1111 return;
1112 }
1113 foo >>= 1;
1114 }
1115 State.regs[OP[0]] = 16;
1116 trace_output (OP_REG);
1117 }
1118
1119 /* exp */
1120 void
1121 OP_15002A02 ()
1122 {
1123 int64 tmp, foo;
1124 int i;
1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1127 tmp = SEXT40(State.a[OP[1]]);
1128 if (tmp < 0)
1129 tmp = ~tmp & MASK40;
1130
1131 foo = 0x4000000000LL;
1132 for (i=1;i<25;i++)
1133 {
1134 if (tmp & foo)
1135 {
1136 State.regs[OP[0]] = i-9;
1137 trace_output (OP_REG);
1138 return;
1139 }
1140 foo >>= 1;
1141 }
1142 State.regs[OP[0]] = 16;
1143 trace_output (OP_REG);
1144 }
1145
1146 /* jl */
1147 void
1148 OP_4D00 ()
1149 {
1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
1151 State.regs[13] = PC+1;
1152 JMP (State.regs[OP[0]]);
1153 trace_output (OP_VOID);
1154 }
1155
1156 /* jmp */
1157 void
1158 OP_4C00 ()
1159 {
1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1163
1164 JMP (State.regs[OP[0]]);
1165 trace_output (OP_VOID);
1166 }
1167
1168 /* ld */
1169 void
1170 OP_30000000 ()
1171 {
1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1174 trace_output (OP_REG);
1175 }
1176
1177 /* ld */
1178 void
1179 OP_6401 ()
1180 {
1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1182 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1183 INC_ADDR(State.regs[OP[1]],-2);
1184 trace_output (OP_REG);
1185 }
1186
1187 /* ld */
1188 void
1189 OP_6001 ()
1190 {
1191 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1192 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1193 INC_ADDR(State.regs[OP[1]],2);
1194 trace_output (OP_REG);
1195 }
1196
1197 /* ld */
1198 void
1199 OP_6000 ()
1200 {
1201 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1202 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1203 trace_output (OP_REG);
1204 }
1205
1206 /* ld2w */
1207 void
1208 OP_31000000 ()
1209 {
1210 uint16 addr = State.regs[OP[2]];
1211 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1212 State.regs[OP[0]] = RW (OP[1] + addr);
1213 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
1214 trace_output (OP_DREG);
1215 }
1216
1217 /* ld2w */
1218 void
1219 OP_6601 ()
1220 {
1221 uint16 addr = State.regs[OP[1]];
1222 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1223 State.regs[OP[0]] = RW (addr);
1224 State.regs[OP[0]+1] = RW (addr+2);
1225 INC_ADDR(State.regs[OP[1]],-4);
1226 trace_output (OP_DREG);
1227 }
1228
1229 /* ld2w */
1230 void
1231 OP_6201 ()
1232 {
1233 uint16 addr = State.regs[OP[1]];
1234 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
1237 INC_ADDR(State.regs[OP[1]],4);
1238 trace_output (OP_DREG);
1239 }
1240
1241 /* ld2w */
1242 void
1243 OP_6200 ()
1244 {
1245 uint16 addr = State.regs[OP[1]];
1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
1249 trace_output (OP_DREG);
1250 }
1251
1252 /* ldb */
1253 void
1254 OP_38000000 ()
1255 {
1256 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1257 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
1258 trace_output (OP_REG);
1259 }
1260
1261 /* ldb */
1262 void
1263 OP_7000 ()
1264 {
1265 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1266 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
1267 trace_output (OP_REG);
1268 }
1269
1270 /* ldi.s */
1271 void
1272 OP_4001 ()
1273 {
1274 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1275 State.regs[OP[0]] = SEXT4(OP[1]);
1276 trace_output (OP_REG);
1277 }
1278
1279 /* ldi.l */
1280 void
1281 OP_20000000 ()
1282 {
1283 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1284 State.regs[OP[0]] = OP[1];
1285 trace_output (OP_REG);
1286 }
1287
1288 /* ldub */
1289 void
1290 OP_39000000 ()
1291 {
1292 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1293 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1294 trace_output (OP_REG);
1295 }
1296
1297 /* ldub */
1298 void
1299 OP_7200 ()
1300 {
1301 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1302 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1303 trace_output (OP_REG);
1304 }
1305
1306 /* mac */
1307 void
1308 OP_2A00 ()
1309 {
1310 int64 tmp;
1311
1312 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1313 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1314
1315 if (State.FX)
1316 tmp = SEXT40( (tmp << 1) & MASK40);
1317
1318 if (State.ST && tmp > MAX32)
1319 tmp = MAX32;
1320
1321 tmp += SEXT40(State.a[OP[0]]);
1322 if (State.ST)
1323 {
1324 if (tmp > MAX32)
1325 State.a[OP[0]] = MAX32;
1326 else if (tmp < MIN32)
1327 State.a[OP[0]] = MIN32;
1328 else
1329 State.a[OP[0]] = tmp & MASK40;
1330 }
1331 else
1332 State.a[OP[0]] = tmp & MASK40;
1333 trace_output (OP_ACCUM);
1334 }
1335
1336 /* macsu */
1337 void
1338 OP_1A00 ()
1339 {
1340 int64 tmp;
1341
1342 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1343 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1344 if (State.FX)
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1346
1347 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1348 trace_output (OP_ACCUM);
1349 }
1350
1351 /* macu */
1352 void
1353 OP_3A00 ()
1354 {
1355 uint64 tmp;
1356 uint32 src1;
1357 uint32 src2;
1358
1359 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1360 src1 = (uint16) State.regs[OP[1]];
1361 src2 = (uint16) State.regs[OP[2]];
1362 tmp = src1 * src2;
1363 if (State.FX)
1364 tmp = (tmp << 1);
1365 State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
1366 trace_output (OP_ACCUM);
1367 }
1368
1369 /* max */
1370 void
1371 OP_2600 ()
1372 {
1373 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1374 State.F1 = State.F0;
1375 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1376 {
1377 State.regs[OP[0]] = State.regs[OP[1]];
1378 State.F0 = 1;
1379 }
1380 else
1381 State.F0 = 0;
1382 trace_output (OP_REG);
1383 }
1384
1385 /* max */
1386 void
1387 OP_3600 ()
1388 {
1389 int64 tmp;
1390
1391 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1392 State.F1 = State.F0;
1393 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1394 if (tmp > SEXT40(State.a[OP[0]]))
1395 {
1396 State.a[OP[0]] = tmp & MASK40;
1397 State.F0 = 1;
1398 }
1399 else
1400 State.F0 = 0;
1401 trace_output (OP_ACCUM);
1402 }
1403
1404 /* max */
1405 void
1406 OP_3602 ()
1407 {
1408 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1409 State.F1 = State.F0;
1410 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1411 {
1412 State.a[OP[0]] = State.a[OP[1]];
1413 State.F0 = 1;
1414 }
1415 else
1416 State.F0 = 0;
1417 trace_output (OP_ACCUM);
1418 }
1419
1420
1421 /* min */
1422 void
1423 OP_2601 ()
1424 {
1425 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1426 State.F1 = State.F0;
1427 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1428 {
1429 State.regs[OP[0]] = State.regs[OP[1]];
1430 State.F0 = 1;
1431 }
1432 else
1433 State.F0 = 0;
1434 trace_output (OP_REG);
1435 }
1436
1437 /* min */
1438 void
1439 OP_3601 ()
1440 {
1441 int64 tmp;
1442
1443 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1444 State.F1 = State.F0;
1445 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1446 if (tmp < SEXT40(State.a[OP[0]]))
1447 {
1448 State.a[OP[0]] = tmp & MASK40;
1449 State.F0 = 1;
1450 }
1451 else
1452 State.F0 = 0;
1453 trace_output (OP_ACCUM);
1454 }
1455
1456 /* min */
1457 void
1458 OP_3603 ()
1459 {
1460 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1461 State.F1 = State.F0;
1462 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1463 {
1464 State.a[OP[0]] = State.a[OP[1]];
1465 State.F0 = 1;
1466 }
1467 else
1468 State.F0 = 0;
1469 trace_output (OP_ACCUM);
1470 }
1471
1472 /* msb */
1473 void
1474 OP_2800 ()
1475 {
1476 int64 tmp;
1477
1478 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1479 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1480
1481 if (State.FX)
1482 tmp = SEXT40 ((tmp << 1) & MASK40);
1483
1484 if (State.ST && tmp > MAX32)
1485 tmp = MAX32;
1486
1487 tmp = SEXT40(State.a[OP[0]]) - tmp;
1488 if (State.ST)
1489 {
1490 if (tmp > MAX32)
1491 State.a[OP[0]] = MAX32;
1492 else if (tmp < MIN32)
1493 State.a[OP[0]] = MIN32;
1494 else
1495 State.a[OP[0]] = tmp & MASK40;
1496 }
1497 else
1498 State.a[OP[0]] = tmp & MASK40;
1499 trace_output (OP_ACCUM);
1500 }
1501
1502 /* msbsu */
1503 void
1504 OP_1800 ()
1505 {
1506 int64 tmp;
1507
1508 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1509 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1510 if (State.FX)
1511 tmp = SEXT40( (tmp << 1) & MASK40);
1512
1513 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1514 trace_output (OP_ACCUM);
1515 }
1516
1517 /* msbu */
1518 void
1519 OP_3800 ()
1520 {
1521 int64 tmp;
1522
1523 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1524 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1525 if (State.FX)
1526 tmp = SEXT40( (tmp << 1) & MASK40);
1527
1528 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1529 trace_output (OP_ACCUM);
1530 }
1531
1532 /* mul */
1533 void
1534 OP_2E00 ()
1535 {
1536 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1537 State.regs[OP[0]] *= State.regs[OP[1]];
1538 trace_output (OP_REG);
1539 }
1540
1541 /* mulx */
1542 void
1543 OP_2C00 ()
1544 {
1545 int64 tmp;
1546
1547 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1548 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1549
1550 if (State.FX)
1551 tmp = SEXT40 ((tmp << 1) & MASK40);
1552
1553 if (State.ST && tmp > MAX32)
1554 State.a[OP[0]] = MAX32;
1555 else
1556 State.a[OP[0]] = tmp & MASK40;
1557 trace_output (OP_ACCUM);
1558 }
1559
1560 /* mulxsu */
1561 void
1562 OP_1C00 ()
1563 {
1564 int64 tmp;
1565
1566 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1567 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1568
1569 if (State.FX)
1570 tmp <<= 1;
1571
1572 State.a[OP[0]] = tmp & MASK40;
1573 trace_output (OP_ACCUM);
1574 }
1575
1576 /* mulxu */
1577 void
1578 OP_3C00 ()
1579 {
1580 int64 tmp;
1581
1582 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1583 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1584
1585 if (State.FX)
1586 tmp <<= 1;
1587
1588 State.a[OP[0]] = tmp & MASK40;
1589 trace_output (OP_ACCUM);
1590 }
1591
1592 /* mv */
1593 void
1594 OP_4000 ()
1595 {
1596 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1597 State.regs[OP[0]] = State.regs[OP[1]];
1598 trace_output (OP_REG);
1599 }
1600
1601 /* mv2w */
1602 void
1603 OP_5000 ()
1604 {
1605 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1606 State.regs[OP[0]] = State.regs[OP[1]];
1607 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1608 trace_output (OP_DREG);
1609 }
1610
1611 /* mv2wfac */
1612 void
1613 OP_3E00 ()
1614 {
1615 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1616 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1617 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1618 trace_output (OP_DREG);
1619 }
1620
1621 /* mv2wtac */
1622 void
1623 OP_3E01 ()
1624 {
1625 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1626 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1627 trace_output (OP_ACCUM_REVERSE);
1628 }
1629
1630 /* mvac */
1631 void
1632 OP_3E03 ()
1633 {
1634 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1635 State.a[OP[0]] = State.a[OP[1]];
1636 trace_output (OP_ACCUM);
1637 }
1638
1639 /* mvb */
1640 void
1641 OP_5400 ()
1642 {
1643 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1644 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1645 trace_output (OP_REG);
1646 }
1647
1648 /* mvf0f */
1649 void
1650 OP_4400 ()
1651 {
1652 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1653 if (State.F0 == 0)
1654 State.regs[OP[0]] = State.regs[OP[1]];
1655 trace_output (OP_REG);
1656 }
1657
1658 /* mvf0t */
1659 void
1660 OP_4401 ()
1661 {
1662 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1663 if (State.F0)
1664 State.regs[OP[0]] = State.regs[OP[1]];
1665 trace_output (OP_REG);
1666 }
1667
1668 /* mvfacg */
1669 void
1670 OP_1E04 ()
1671 {
1672 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1673 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1674 trace_output (OP_ACCUM);
1675 }
1676
1677 /* mvfachi */
1678 void
1679 OP_1E00 ()
1680 {
1681 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1682 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1683 trace_output (OP_REG);
1684 }
1685
1686 /* mvfaclo */
1687 void
1688 OP_1E02 ()
1689 {
1690 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1691 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1692 trace_output (OP_REG);
1693 }
1694
1695 /* mvfc */
1696 void
1697 OP_5200 ()
1698 {
1699 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1700 if (OP[1] == 0)
1701 {
1702 /* PSW is treated specially */
1703 PSW = 0;
1704 if (State.SM) PSW |= 0x8000;
1705 if (State.EA) PSW |= 0x2000;
1706 if (State.DB) PSW |= 0x1000;
1707 if (State.IE) PSW |= 0x400;
1708 if (State.RP) PSW |= 0x200;
1709 if (State.MD) PSW |= 0x100;
1710 if (State.FX) PSW |= 0x80;
1711 if (State.ST) PSW |= 0x40;
1712 if (State.F0) PSW |= 8;
1713 if (State.F1) PSW |= 4;
1714 if (State.C) PSW |= 1;
1715 }
1716 State.regs[OP[0]] = State.cregs[OP[1]];
1717 trace_output (OP_REG);
1718 }
1719
1720 /* mvtacg */
1721 void
1722 OP_1E41 ()
1723 {
1724 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1725 State.a[OP[1]] &= MASK32;
1726 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1727 trace_output (OP_ACCUM_REVERSE);
1728 }
1729
1730 /* mvtachi */
1731 void
1732 OP_1E01 ()
1733 {
1734 uint16 tmp;
1735
1736 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1737 tmp = State.a[OP[1]] & 0xffff;
1738 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1739 trace_output (OP_ACCUM_REVERSE);
1740 }
1741
1742 /* mvtaclo */
1743 void
1744 OP_1E21 ()
1745 {
1746 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1747 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1748 trace_output (OP_ACCUM_REVERSE);
1749 }
1750
1751 /* mvtc */
1752 void
1753 OP_5600 ()
1754 {
1755 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1756 State.cregs[OP[1]] = State.regs[OP[0]];
1757 if (OP[1] == 0)
1758 {
1759 /* PSW is treated specially */
1760 State.SM = (PSW & 0x8000) ? 1 : 0;
1761 State.EA = (PSW & 0x2000) ? 1 : 0;
1762 State.DB = (PSW & 0x1000) ? 1 : 0;
1763 State.IE = (PSW & 0x400) ? 1 : 0;
1764 State.RP = (PSW & 0x200) ? 1 : 0;
1765 State.MD = (PSW & 0x100) ? 1 : 0;
1766 State.FX = (PSW & 0x80) ? 1 : 0;
1767 State.ST = (PSW & 0x40) ? 1 : 0;
1768 State.F0 = (PSW & 8) ? 1 : 0;
1769 State.F1 = (PSW & 4) ? 1 : 0;
1770 State.C = PSW & 1;
1771 if (State.ST && !State.FX)
1772 {
1773 (*d10v_callback->printf_filtered) (d10v_callback,
1774 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1775 PC<<2);
1776 State.exception = SIGILL;
1777 }
1778 }
1779 trace_output (OP_CR_REVERSE);
1780 }
1781
1782 /* mvub */
1783 void
1784 OP_5401 ()
1785 {
1786 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1787 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1788 trace_output (OP_REG);
1789 }
1790
1791 /* neg */
1792 void
1793 OP_4605 ()
1794 {
1795 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1796 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1797 trace_output (OP_REG);
1798 }
1799
1800 /* neg */
1801 void
1802 OP_5605 ()
1803 {
1804 int64 tmp;
1805
1806 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1807 tmp = -SEXT40(State.a[OP[0]]);
1808 if (State.ST)
1809 {
1810 if ( tmp > MAX32)
1811 State.a[OP[0]] = MAX32;
1812 else if (tmp < MIN32)
1813 State.a[OP[0]] = MIN32;
1814 else
1815 State.a[OP[0]] = tmp & MASK40;
1816 }
1817 else
1818 State.a[OP[0]] = tmp & MASK40;
1819 trace_output (OP_ACCUM);
1820 }
1821
1822
1823 /* nop */
1824 void
1825 OP_5E00 ()
1826 {
1827 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1828
1829 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1830 switch (State.ins_type)
1831 {
1832 default:
1833 ins_type_counters[ (int)INS_UNKNOWN ]++;
1834 break;
1835
1836 case INS_LEFT_PARALLEL:
1837 /* Don't count a parallel op that includes a NOP as a true parallel op */
1838 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1839 ins_type_counters[ (int)INS_RIGHT ]++;
1840 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1841 break;
1842
1843 case INS_LEFT:
1844 case INS_LEFT_COND_EXE:
1845 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1846 break;
1847
1848 case INS_RIGHT_PARALLEL:
1849 /* Don't count a parallel op that includes a NOP as a true parallel op */
1850 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1851 ins_type_counters[ (int)INS_LEFT ]++;
1852 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1853 break;
1854
1855 case INS_RIGHT:
1856 case INS_RIGHT_COND_EXE:
1857 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1858 break;
1859 }
1860
1861 trace_output (OP_VOID);
1862 }
1863
1864 /* not */
1865 void
1866 OP_4603 ()
1867 {
1868 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1869 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1870 trace_output (OP_REG);
1871 }
1872
1873 /* or */
1874 void
1875 OP_800 ()
1876 {
1877 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1878 State.regs[OP[0]] |= State.regs[OP[1]];
1879 trace_output (OP_REG);
1880 }
1881
1882 /* or3 */
1883 void
1884 OP_4000000 ()
1885 {
1886 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1887 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1888 trace_output (OP_REG);
1889 }
1890
1891 /* rac */
1892 void
1893 OP_5201 ()
1894 {
1895 int64 tmp;
1896 int shift = SEXT3 (OP[2]);
1897
1898 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1899 if (OP[1] != 0)
1900 {
1901 (*d10v_callback->printf_filtered) (d10v_callback,
1902 "ERROR at PC 0x%x: instruction only valid for A0\n",
1903 PC<<2);
1904 State.exception = SIGILL;
1905 }
1906
1907 State.F1 = State.F0;
1908 if (shift >=0)
1909 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1910 else
1911 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1912 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1913 if (tmp > MAX32)
1914 {
1915 State.regs[OP[0]] = 0x7fff;
1916 State.regs[OP[0]+1] = 0xffff;
1917 State.F0 = 1;
1918 }
1919 else if (tmp < MIN32)
1920 {
1921 State.regs[OP[0]] = 0x8000;
1922 State.regs[OP[0]+1] = 0;
1923 State.F0 = 1;
1924 }
1925 else
1926 {
1927 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1928 State.regs[OP[0]+1] = tmp & 0xffff;
1929 State.F0 = 0;
1930 }
1931 trace_output (OP_DREG);
1932 }
1933
1934 /* rachi */
1935 void
1936 OP_4201 ()
1937 {
1938 signed64 tmp;
1939 int shift = SEXT3 (OP[2]);
1940
1941 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1942 State.F1 = State.F0;
1943 if (shift >=0)
1944 tmp = SEXT40 (State.a[OP[1]]) << shift;
1945 else
1946 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
1947 tmp += 0x8000;
1948
1949 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
1950 {
1951 State.regs[OP[0]] = 0x7fff;
1952 State.F0 = 1;
1953 }
1954 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
1955 {
1956 State.regs[OP[0]] = 0x8000;
1957 State.F0 = 1;
1958 }
1959 else
1960 {
1961 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1962 State.F0 = 0;
1963 }
1964 trace_output (OP_REG);
1965 }
1966
1967 /* rep */
1968 void
1969 OP_27000000 ()
1970 {
1971 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1972 RPT_S = PC + 1;
1973 RPT_E = PC + OP[1];
1974 RPT_C = State.regs[OP[0]];
1975 State.RP = 1;
1976 if (RPT_C == 0)
1977 {
1978 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1979 State.exception = SIGILL;
1980 }
1981 if (OP[1] < 4)
1982 {
1983 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1984 State.exception = SIGILL;
1985 }
1986 trace_output (OP_VOID);
1987 }
1988
1989 /* repi */
1990 void
1991 OP_2F000000 ()
1992 {
1993 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1994 RPT_S = PC + 1;
1995 RPT_E = PC + OP[1];
1996 RPT_C = OP[0];
1997 State.RP = 1;
1998 if (RPT_C == 0)
1999 {
2000 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2001 State.exception = SIGILL;
2002 }
2003 if (OP[1] < 4)
2004 {
2005 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2006 State.exception = SIGILL;
2007 }
2008 trace_output (OP_VOID);
2009 }
2010
2011 /* rtd */
2012 void
2013 OP_5F60 ()
2014 {
2015 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
2016 State.exception = SIGILL;
2017 }
2018
2019 /* rte */
2020 void
2021 OP_5F40 ()
2022 {
2023 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2024 PC = BPC;
2025 PSW = BPSW;
2026 trace_output (OP_VOID);
2027 }
2028
2029 /* sadd */
2030 void
2031 OP_1223 ()
2032 {
2033 int64 tmp;
2034
2035 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2036 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
2037 if (State.ST)
2038 {
2039 if (tmp > MAX32)
2040 State.a[OP[0]] = MAX32;
2041 else if (tmp < MIN32)
2042 State.a[OP[0]] = MIN32;
2043 else
2044 State.a[OP[0]] = tmp & MASK40;
2045 }
2046 else
2047 State.a[OP[0]] = tmp & MASK40;
2048 trace_output (OP_ACCUM);
2049 }
2050
2051 /* setf0f */
2052 void
2053 OP_4611 ()
2054 {
2055 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2056 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2057 trace_output (OP_REG);
2058 }
2059
2060 /* setf0t */
2061 void
2062 OP_4613 ()
2063 {
2064 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2065 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2066 trace_output (OP_REG);
2067 }
2068
2069 /* sleep */
2070 void
2071 OP_5FC0 ()
2072 {
2073 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2074 State.IE = 1;
2075 trace_output (OP_VOID);
2076 }
2077
2078 /* sll */
2079 void
2080 OP_2200 ()
2081 {
2082 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2083 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2084 trace_output (OP_REG);
2085 }
2086
2087 /* sll */
2088 void
2089 OP_3200 ()
2090 {
2091 int64 tmp;
2092 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2093 if ((State.regs[OP[1]] & 31) <= 16)
2094 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2095 else
2096 {
2097 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2098 State.exception = SIGILL;
2099 return;
2100 }
2101
2102 if (State.ST)
2103 {
2104 if (tmp > MAX32)
2105 State.a[OP[0]] = MAX32;
2106 else if (tmp < 0xffffff80000000LL)
2107 State.a[OP[0]] = MIN32;
2108 else
2109 State.a[OP[0]] = tmp & MASK40;
2110 }
2111 else
2112 State.a[OP[0]] = tmp & MASK40;
2113 trace_output (OP_ACCUM);
2114 }
2115
2116 /* slli */
2117 void
2118 OP_2201 ()
2119 {
2120 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2121 State.regs[OP[0]] <<= OP[1];
2122 trace_output (OP_REG);
2123 }
2124
2125 /* slli */
2126 void
2127 OP_3201 ()
2128 {
2129 int64 tmp;
2130
2131 if (OP[1] == 0)
2132 OP[1] = 16;
2133
2134 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2135 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2136
2137 if (State.ST)
2138 {
2139 if (tmp > MAX32)
2140 State.a[OP[0]] = MAX32;
2141 else if (tmp < 0xffffff80000000LL)
2142 State.a[OP[0]] = MIN32;
2143 else
2144 State.a[OP[0]] = tmp & MASK40;
2145 }
2146 else
2147 State.a[OP[0]] = tmp & MASK40;
2148 trace_output (OP_ACCUM);
2149 }
2150
2151 /* slx */
2152 void
2153 OP_460B ()
2154 {
2155 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2156 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2157 trace_output (OP_REG);
2158 }
2159
2160 /* sra */
2161 void
2162 OP_2400 ()
2163 {
2164 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2165 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2166 trace_output (OP_REG);
2167 }
2168
2169 /* sra */
2170 void
2171 OP_3400 ()
2172 {
2173 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2174 if ((State.regs[OP[1]] & 31) <= 16)
2175 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
2176 else
2177 {
2178 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2179 State.exception = SIGILL;
2180 return;
2181 }
2182
2183 trace_output (OP_ACCUM);
2184 }
2185
2186 /* srai */
2187 void
2188 OP_2401 ()
2189 {
2190 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2191 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2192 trace_output (OP_REG);
2193 }
2194
2195 /* srai */
2196 void
2197 OP_3401 ()
2198 {
2199 if (OP[1] == 0)
2200 OP[1] = 16;
2201
2202 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2203 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
2204 trace_output (OP_ACCUM);
2205 }
2206
2207 /* srl */
2208 void
2209 OP_2000 ()
2210 {
2211 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2212 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2213 trace_output (OP_REG);
2214 }
2215
2216 /* srl */
2217 void
2218 OP_3000 ()
2219 {
2220 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2221 if ((State.regs[OP[1]] & 31) <= 16)
2222 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
2223 else
2224 {
2225 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2226 State.exception = SIGILL;
2227 return;
2228 }
2229
2230 trace_output (OP_ACCUM);
2231 }
2232
2233 /* srli */
2234 void
2235 OP_2001 ()
2236 {
2237 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2238 State.regs[OP[0]] >>= OP[1];
2239 trace_output (OP_REG);
2240 }
2241
2242 /* srli */
2243 void
2244 OP_3001 ()
2245 {
2246 if (OP[1] == 0)
2247 OP[1] = 16;
2248
2249 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2250 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
2251 trace_output (OP_ACCUM);
2252 }
2253
2254 /* srx */
2255 void
2256 OP_4609 ()
2257 {
2258 uint16 tmp;
2259
2260 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2261 tmp = State.F0 << 15;
2262 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2263 trace_output (OP_REG);
2264 }
2265
2266 /* st */
2267 void
2268 OP_34000000 ()
2269 {
2270 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2271 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2272 trace_output (OP_VOID);
2273 }
2274
2275 /* st */
2276 void
2277 OP_6800 ()
2278 {
2279 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2280 SW (State.regs[OP[1]], State.regs[OP[0]]);
2281 trace_output (OP_VOID);
2282 }
2283
2284 /* st */
2285 void
2286 OP_6C1F ()
2287 {
2288 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2289 if ( OP[1] != 15 )
2290 {
2291 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2292 State.exception = SIGILL;
2293 return;
2294 }
2295 State.regs[OP[1]] -= 2;
2296 SW (State.regs[OP[1]], State.regs[OP[0]]);
2297 trace_output (OP_VOID);
2298 }
2299
2300 /* st */
2301 void
2302 OP_6801 ()
2303 {
2304 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2305 SW (State.regs[OP[1]], State.regs[OP[0]]);
2306 INC_ADDR (State.regs[OP[1]],2);
2307 trace_output (OP_VOID);
2308 }
2309
2310 /* st */
2311 void
2312 OP_6C01 ()
2313 {
2314 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2315 if ( OP[1] == 15 )
2316 {
2317 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2318 State.exception = SIGILL;
2319 return;
2320 }
2321 SW (State.regs[OP[1]], State.regs[OP[0]]);
2322 INC_ADDR (State.regs[OP[1]],-2);
2323 trace_output (OP_VOID);
2324 }
2325
2326 /* st2w */
2327 void
2328 OP_35000000 ()
2329 {
2330 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2331 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2332 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2333 trace_output (OP_VOID);
2334 }
2335
2336 /* st2w */
2337 void
2338 OP_6A00 ()
2339 {
2340 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2341 SW (State.regs[OP[1]], State.regs[OP[0]]);
2342 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2343 trace_output (OP_VOID);
2344 }
2345
2346 /* st2w */
2347 void
2348 OP_6E1F ()
2349 {
2350 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2351 if ( OP[1] != 15 )
2352 {
2353 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2354 State.exception = SIGILL;
2355 return;
2356 }
2357 State.regs[OP[1]] -= 4;
2358 SW (State.regs[OP[1]], State.regs[OP[0]]);
2359 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2360 trace_output (OP_VOID);
2361 }
2362
2363 /* st2w */
2364 void
2365 OP_6A01 ()
2366 {
2367 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2368 SW (State.regs[OP[1]], State.regs[OP[0]]);
2369 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2370 INC_ADDR (State.regs[OP[1]],4);
2371 trace_output (OP_VOID);
2372 }
2373
2374 /* st2w */
2375 void
2376 OP_6E01 ()
2377 {
2378 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2379 if ( OP[1] == 15 )
2380 {
2381 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2382 State.exception = SIGILL;
2383 return;
2384 }
2385 SW (State.regs[OP[1]], State.regs[OP[0]]);
2386 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2387 INC_ADDR (State.regs[OP[1]],-4);
2388 trace_output (OP_VOID);
2389 }
2390
2391 /* stb */
2392 void
2393 OP_3C000000 ()
2394 {
2395 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2396 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2397 trace_output (OP_VOID);
2398 }
2399
2400 /* stb */
2401 void
2402 OP_7800 ()
2403 {
2404 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2405 SB (State.regs[OP[1]], State.regs[OP[0]]);
2406 trace_output (OP_VOID);
2407 }
2408
2409 /* stop */
2410 void
2411 OP_5FE0 ()
2412 {
2413 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2414 State.exception = SIG_D10V_STOP;
2415 trace_output (OP_VOID);
2416 }
2417
2418 /* sub */
2419 void
2420 OP_0 ()
2421 {
2422 uint16 tmp;
2423
2424 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2425 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2426 State.C = (tmp > State.regs[OP[0]]);
2427 State.regs[OP[0]] = tmp;
2428 trace_output (OP_REG);
2429 }
2430
2431 /* sub */
2432 void
2433 OP_1001 ()
2434 {
2435 int64 tmp;
2436
2437 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2438 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2439 if (State.ST)
2440 {
2441 if ( tmp > MAX32)
2442 State.a[OP[0]] = MAX32;
2443 else if ( tmp < MIN32)
2444 State.a[OP[0]] = MIN32;
2445 else
2446 State.a[OP[0]] = tmp & MASK40;
2447 }
2448 else
2449 State.a[OP[0]] = tmp & MASK40;
2450
2451 trace_output (OP_ACCUM);
2452 }
2453
2454 /* sub */
2455
2456 void
2457 OP_1003 ()
2458 {
2459 int64 tmp;
2460
2461 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2462 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2463 if (State.ST)
2464 {
2465 if (tmp > MAX32)
2466 State.a[OP[0]] = MAX32;
2467 else if ( tmp < MIN32)
2468 State.a[OP[0]] = MIN32;
2469 else
2470 State.a[OP[0]] = tmp & MASK40;
2471 }
2472 else
2473 State.a[OP[0]] = tmp & MASK40;
2474
2475 trace_output (OP_ACCUM);
2476 }
2477
2478 /* sub2w */
2479 void
2480 OP_1000 ()
2481 {
2482 uint32 tmp,a,b;
2483
2484 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2485 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2486 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2487 /* see ../common/sim-alu.h for a more extensive discussion on how to
2488 compute the carry/overflow bits */
2489 tmp = a - b;
2490 State.C = (a >= b);
2491 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2492 State.regs[OP[0]+1] = tmp & 0xffff;
2493 trace_output (OP_DREG);
2494 }
2495
2496 /* subac3 */
2497 void
2498 OP_17000000 ()
2499 {
2500 int64 tmp;
2501
2502 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2503 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2504 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2505 State.regs[OP[0]+1] = tmp & 0xffff;
2506 trace_output (OP_DREG);
2507 }
2508
2509 /* subac3 */
2510 void
2511 OP_17000002 ()
2512 {
2513 int64 tmp;
2514
2515 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2516 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2517 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2518 State.regs[OP[0]+1] = tmp & 0xffff;
2519 trace_output (OP_DREG);
2520 }
2521
2522 /* subac3s */
2523 void
2524 OP_17001000 ()
2525 {
2526 int64 tmp;
2527
2528 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2529 State.F1 = State.F0;
2530 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2531 if ( tmp > MAX32)
2532 {
2533 State.regs[OP[0]] = 0x7fff;
2534 State.regs[OP[0]+1] = 0xffff;
2535 State.F0 = 1;
2536 }
2537 else if (tmp < MIN32)
2538 {
2539 State.regs[OP[0]] = 0x8000;
2540 State.regs[OP[0]+1] = 0;
2541 State.F0 = 1;
2542 }
2543 else
2544 {
2545 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2546 State.regs[OP[0]+1] = tmp & 0xffff;
2547 State.F0 = 0;
2548 }
2549 trace_output (OP_DREG);
2550 }
2551
2552 /* subac3s */
2553 void
2554 OP_17001002 ()
2555 {
2556 int64 tmp;
2557
2558 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2559 State.F1 = State.F0;
2560 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2561 if ( tmp > MAX32)
2562 {
2563 State.regs[OP[0]] = 0x7fff;
2564 State.regs[OP[0]+1] = 0xffff;
2565 State.F0 = 1;
2566 }
2567 else if (tmp < MIN32)
2568 {
2569 State.regs[OP[0]] = 0x8000;
2570 State.regs[OP[0]+1] = 0;
2571 State.F0 = 1;
2572 }
2573 else
2574 {
2575 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2576 State.regs[OP[0]+1] = tmp & 0xffff;
2577 State.F0 = 0;
2578 }
2579 trace_output (OP_DREG);
2580 }
2581
2582 /* subi */
2583 void
2584 OP_1 ()
2585 {
2586 unsigned tmp;
2587 if (OP[1] == 0)
2588 OP[1] = 16;
2589
2590 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2591 /* see ../common/sim-alu.h for a more extensive discussion on how to
2592 compute the carry/overflow bits. */
2593 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2594 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2595 + (unsigned)(unsigned16) ( - OP[1]));
2596 State.C = (tmp >= (1 << 16));
2597 State.regs[OP[0]] = tmp;
2598 trace_output (OP_REG);
2599 }
2600
2601 /* trap */
2602 void
2603 OP_5F00 ()
2604 {
2605 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2606 trace_output (OP_VOID);
2607
2608 switch (OP[0])
2609 {
2610 default:
2611 #if 0
2612 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2613 State.exception = SIGILL;
2614 #else
2615 /* Use any other traps for batch debugging. */
2616 {
2617 int i;
2618 static int first_time = 1;
2619
2620 if (first_time)
2621 {
2622 first_time = 0;
2623 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2624 for (i = 0; i < 16; i++)
2625 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2626 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2627 }
2628
2629 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2630
2631 for (i = 0; i < 16; i++)
2632 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2633
2634 for (i = 0; i < 2; i++)
2635 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2636 ((int)(State.a[i] >> 32) & 0xff),
2637 ((unsigned long)State.a[i]) & 0xffffffff);
2638
2639 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2640 State.F0 != 0, State.F1 != 0, State.C != 0);
2641 (*d10v_callback->flush_stdout) (d10v_callback);
2642 break;
2643 }
2644 #endif
2645
2646 case 0: /* old system call trap, to be deleted */
2647 case 15: /* new system call trap */
2648 /* Trap 15 is used for simulating low-level I/O */
2649 {
2650 errno = 0;
2651
2652 /* Registers passed to trap 0 */
2653
2654 #define FUNC State.regs[6] /* function number */
2655 #define PARM1 State.regs[2] /* optional parm 1 */
2656 #define PARM2 State.regs[3] /* optional parm 2 */
2657 #define PARM3 State.regs[4] /* optional parm 3 */
2658 #define PARM4 State.regs[5] /* optional parm 3 */
2659
2660 /* Registers set by trap 0 */
2661
2662 #define RETVAL State.regs[2] /* return value */
2663 #define RETVAL_HIGH State.regs[2] /* return value */
2664 #define RETVAL_LOW State.regs[3] /* return value */
2665 #define RETERR State.regs[4] /* return error code */
2666
2667 /* Turn a pointer in a register into a pointer into real memory. */
2668
2669 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2670
2671 switch (FUNC)
2672 {
2673 #if !defined(__GO32__) && !defined(_WIN32)
2674 case SYS_fork:
2675 RETVAL = fork ();
2676 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2677 trace_output (OP_R2);
2678 break;
2679
2680 case SYS_getpid:
2681 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2682 RETVAL = getpid ();
2683 trace_output (OP_R2);
2684 break;
2685
2686 case SYS_kill:
2687 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2688 if (PARM1 == getpid ())
2689 {
2690 trace_output (OP_VOID);
2691 State.exception = PARM2;
2692 }
2693 else
2694 {
2695 int os_sig = -1;
2696 switch (PARM2)
2697 {
2698 #ifdef SIGHUP
2699 case 1: os_sig = SIGHUP; break;
2700 #endif
2701 #ifdef SIGINT
2702 case 2: os_sig = SIGINT; break;
2703 #endif
2704 #ifdef SIGQUIT
2705 case 3: os_sig = SIGQUIT; break;
2706 #endif
2707 #ifdef SIGILL
2708 case 4: os_sig = SIGILL; break;
2709 #endif
2710 #ifdef SIGTRAP
2711 case 5: os_sig = SIGTRAP; break;
2712 #endif
2713 #ifdef SIGABRT
2714 case 6: os_sig = SIGABRT; break;
2715 #elif defined(SIGIOT)
2716 case 6: os_sig = SIGIOT; break;
2717 #endif
2718 #ifdef SIGEMT
2719 case 7: os_sig = SIGEMT; break;
2720 #endif
2721 #ifdef SIGFPE
2722 case 8: os_sig = SIGFPE; break;
2723 #endif
2724 #ifdef SIGKILL
2725 case 9: os_sig = SIGKILL; break;
2726 #endif
2727 #ifdef SIGBUS
2728 case 10: os_sig = SIGBUS; break;
2729 #endif
2730 #ifdef SIGSEGV
2731 case 11: os_sig = SIGSEGV; break;
2732 #endif
2733 #ifdef SIGSYS
2734 case 12: os_sig = SIGSYS; break;
2735 #endif
2736 #ifdef SIGPIPE
2737 case 13: os_sig = SIGPIPE; break;
2738 #endif
2739 #ifdef SIGALRM
2740 case 14: os_sig = SIGALRM; break;
2741 #endif
2742 #ifdef SIGTERM
2743 case 15: os_sig = SIGTERM; break;
2744 #endif
2745 #ifdef SIGURG
2746 case 16: os_sig = SIGURG; break;
2747 #endif
2748 #ifdef SIGSTOP
2749 case 17: os_sig = SIGSTOP; break;
2750 #endif
2751 #ifdef SIGTSTP
2752 case 18: os_sig = SIGTSTP; break;
2753 #endif
2754 #ifdef SIGCONT
2755 case 19: os_sig = SIGCONT; break;
2756 #endif
2757 #ifdef SIGCHLD
2758 case 20: os_sig = SIGCHLD; break;
2759 #elif defined(SIGCLD)
2760 case 20: os_sig = SIGCLD; break;
2761 #endif
2762 #ifdef SIGTTIN
2763 case 21: os_sig = SIGTTIN; break;
2764 #endif
2765 #ifdef SIGTTOU
2766 case 22: os_sig = SIGTTOU; break;
2767 #endif
2768 #ifdef SIGIO
2769 case 23: os_sig = SIGIO; break;
2770 #elif defined (SIGPOLL)
2771 case 23: os_sig = SIGPOLL; break;
2772 #endif
2773 #ifdef SIGXCPU
2774 case 24: os_sig = SIGXCPU; break;
2775 #endif
2776 #ifdef SIGXFSZ
2777 case 25: os_sig = SIGXFSZ; break;
2778 #endif
2779 #ifdef SIGVTALRM
2780 case 26: os_sig = SIGVTALRM; break;
2781 #endif
2782 #ifdef SIGPROF
2783 case 27: os_sig = SIGPROF; break;
2784 #endif
2785 #ifdef SIGWINCH
2786 case 28: os_sig = SIGWINCH; break;
2787 #endif
2788 #ifdef SIGLOST
2789 case 29: os_sig = SIGLOST; break;
2790 #endif
2791 #ifdef SIGUSR1
2792 case 30: os_sig = SIGUSR1; break;
2793 #endif
2794 #ifdef SIGUSR2
2795 case 31: os_sig = SIGUSR2; break;
2796 #endif
2797 }
2798
2799 if (os_sig == -1)
2800 {
2801 trace_output (OP_VOID);
2802 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2803 (*d10v_callback->flush_stdout) (d10v_callback);
2804 State.exception = SIGILL;
2805 }
2806 else
2807 {
2808 RETVAL = kill (PARM1, PARM2);
2809 trace_output (OP_R2);
2810 }
2811 }
2812 break;
2813
2814 case SYS_execve:
2815 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2816 (char **)MEMPTR (PARM3));
2817 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2818 trace_output (OP_R2);
2819 break;
2820
2821 #ifdef SYS_execv
2822 case SYS_execv:
2823 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2824 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2825 trace_output (OP_R2);
2826 break;
2827 #endif
2828
2829 case SYS_pipe:
2830 {
2831 reg_t buf;
2832 int host_fd[2];
2833
2834 buf = PARM1;
2835 RETVAL = pipe (host_fd);
2836 SW (buf, host_fd[0]);
2837 buf += sizeof(uint16);
2838 SW (buf, host_fd[1]);
2839 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2840 trace_output (OP_R2);
2841 }
2842 break;
2843
2844 #ifdef SYS_wait
2845 case SYS_wait:
2846 {
2847 int status;
2848
2849 RETVAL = wait (&status);
2850 if (PARM1)
2851 SW (PARM1, status);
2852 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2853 trace_output (OP_R2);
2854 }
2855 break;
2856 #endif
2857 #else
2858 case SYS_getpid:
2859 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2860 RETVAL = 1;
2861 trace_output (OP_R2);
2862 break;
2863
2864 case SYS_kill:
2865 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2866 trace_output (OP_VOID);
2867 State.exception = PARM2;
2868 break;
2869 #endif
2870
2871 case SYS_read:
2872 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2873 PARM3);
2874 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2875 trace_output (OP_R2);
2876 break;
2877
2878 case SYS_write:
2879 if (PARM1 == 1)
2880 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2881 MEMPTR (PARM2), PARM3);
2882 else
2883 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2884 MEMPTR (PARM2), PARM3);
2885 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2886 trace_output (OP_R2);
2887 break;
2888
2889 case SYS_lseek:
2890 {
2891 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2892 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2893 PARM4);
2894 RETVAL_HIGH = ret >> 16;
2895 RETVAL_LOW = ret & 0xffff;
2896 }
2897 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2898 trace_output (OP_R2R3);
2899 break;
2900
2901 case SYS_close:
2902 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2903 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2904 trace_output (OP_R2);
2905 break;
2906
2907 case SYS_open:
2908 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2909 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2910 trace_output (OP_R2);
2911 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2912 trace_output (OP_R2);
2913 break;
2914
2915 case SYS_exit:
2916 State.exception = SIG_D10V_EXIT;
2917 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2918 trace_output (OP_VOID);
2919 break;
2920
2921 case SYS_stat:
2922 /* stat system call */
2923 {
2924 struct stat host_stat;
2925 reg_t buf;
2926
2927 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2928
2929 buf = PARM2;
2930
2931 /* The hard-coded offsets and sizes were determined by using
2932 * the D10V compiler on a test program that used struct stat.
2933 */
2934 SW (buf, host_stat.st_dev);
2935 SW (buf+2, host_stat.st_ino);
2936 SW (buf+4, host_stat.st_mode);
2937 SW (buf+6, host_stat.st_nlink);
2938 SW (buf+8, host_stat.st_uid);
2939 SW (buf+10, host_stat.st_gid);
2940 SW (buf+12, host_stat.st_rdev);
2941 SLW (buf+16, host_stat.st_size);
2942 SLW (buf+20, host_stat.st_atime);
2943 SLW (buf+28, host_stat.st_mtime);
2944 SLW (buf+36, host_stat.st_ctime);
2945 }
2946 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2947 trace_output (OP_R2);
2948 break;
2949
2950 case SYS_chown:
2951 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2952 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2953 trace_output (OP_R2);
2954 break;
2955
2956 case SYS_chmod:
2957 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2958 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2959 trace_output (OP_R2);
2960 break;
2961
2962 #ifdef SYS_utime
2963 case SYS_utime:
2964 /* Cast the second argument to void *, to avoid type mismatch
2965 if a prototype is present. */
2966 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2967 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2968 trace_output (OP_R2);
2969 break;
2970 #endif
2971
2972 #ifdef SYS_time
2973 case SYS_time:
2974 {
2975 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2976 RETVAL_HIGH = ret >> 16;
2977 RETVAL_LOW = ret & 0xffff;
2978 }
2979 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2980 trace_output (OP_R2R3);
2981 break;
2982 #endif
2983
2984 default:
2985 abort ();
2986 }
2987 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
2988 break;
2989 }
2990 }
2991 }
2992
2993 /* tst0i */
2994 void
2995 OP_7000000 ()
2996 {
2997 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2998 State.F1 = State.F0;
2999 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
3000 trace_output (OP_FLAG);
3001 }
3002
3003 /* tst1i */
3004 void
3005 OP_F000000 ()
3006 {
3007 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3008 State.F1 = State.F0;
3009 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
3010 trace_output (OP_FLAG);
3011 }
3012
3013 /* wait */
3014 void
3015 OP_5F80 ()
3016 {
3017 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3018 State.IE = 1;
3019 trace_output (OP_VOID);
3020 }
3021
3022 /* xor */
3023 void
3024 OP_A00 ()
3025 {
3026 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3027 State.regs[OP[0]] ^= State.regs[OP[1]];
3028 trace_output (OP_REG);
3029 }
3030
3031 /* xor3 */
3032 void
3033 OP_5000000 ()
3034 {
3035 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3036 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
3037 trace_output (OP_REG);
3038 }
3039
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